High apaci Single-Chip ASIC Alternative 3,000 54,000 System Gates
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40MX 42MX FPGA Families
High apaci
Single-Chip ASIC Alternative 3,000 54,000 System Gates kbits Configurable Dual-Port SRAM Fast Wide-Decode Circuitry User-Programmable Pins Clock-to-Out Performance Dual-Port SRAM Access FIFOs 35-Bit Address Decode
Commercial, Military Temperature, MIL-STD-883 Ceramic Packages Certification Ceramic Devices Available DSCC
High ance
Mixed-Voltage Operation (5.0V 3.3V core I/Os), with PCI-Compliant I/Os 100% Resource Utilization 100% Locking Deterministic, User-Controllable Timing Unique In-System Diagnostic Verification Capability with Silicon Explorer Power Consumption IEEE Standard 1149.1 (JTAG) Boundary Scan Testing
Feat
Commercial, Industrial, Automotive, Military Temperature Plastic Packages
Device Capacity System Gates SRAM Bits Logic Modules Sequential Combinatorial Decode Clock-to-Out SRAM Modules (64x4 32x8) Dedicated Flip-Flops Maximum Flip-Flops Clocks User (maximum) Boundary Scan Test (BST) Packages count)) PLCC PQFP VQFP TQFP CQFP PBGA A40MX02 3,000 A40MX04 6,000 A42MX09 14,000 100, A42MX16 24,000 100, 160, A42MX24 36,000 1,410 160, A42MX36 54,000 2,560 1,230 1,184 1,230 1,822 208, 208,
2004 Actel Corporation
40MX 42MX FPGA Families
A42MX16 Application (Temperature Range) Blank Commercial +70°C) Industrial (-40 +85°C) Automotive (-40 +125°C) Military (-55 +125°C) MIL-STD-883 Package Lead Count Package Type Plastic Leaded Chip Carrier Plastic Quad Flat Pack Thin (1.4 Quad Flat Pack Very Thin (1.0 Quad Flat Pack Plastic Ball Grid Array Ceramic Quad Flat Pack Speed Grade Blank Standard Speed Approximately Faster than Standard Approximately Faster than Standard Approximately Faster than Standard Approximately Slower than Standard Part Number A40MX02 A40MX04 A42MX09 A42MX16 A42MX24 A42MX36 3,000 System Gates 6,000 System Gates 14,000 System Gates 24,000 System Gates 36,000 System Gates 54,000 System Gates
User I/Os Device A40MX02 A40MX04 A42MX09 A42MX16 A42MX24 A42MX36 PLCC 44-Pin PLCC 68-Pin PLCC 84-Pin PQFP PQFP PQFP PQFP 100-Pin 160-Pin 208-Pin 240-Pin VQFP 80-Pin VQFP TQFP PBGA 100-Pin 176-Pin 272-Pin
Package Definitions PLCC Plastic Leaded Chip Carrier, PQFP Plastic Quad Flat Pack, TQFP Thin Quad Flat Pack, VQFP Very Thin Quad Flat Pack, PBGA Plastic Ball Grid Array
User I/Os Device A42MX36 CQFP 208-Pin CQFP 256-Pin
Package Definitions CQFP Ceramic Quad Flat Pack
Package PLCC PLCC PLCC PQFP PQFP PQFP PQFP VQFP VQFP TQFP PBGA CQFP CQFP Notes: Commercial Industrial Automotive Military MIL-STD-883 Class A40MX02 A40MX04 A42MX09 A42MX16 A42MX24 A42MX36
Note:
Refer 40MX 42MX Automotive Family FPGAs datasheet details automotive-grade offerings.
Contact your local Actel representative device availability.
40MX 42MX FPGA Families
Actel's 40MX 42MX families offer cost-effective design solution devices single-chip solutions provide high performance while shortening system design development cycle. devices integrate consolidate logic implemented multiple PALs, CPLDs, FPGAs. Example applications include high-speed controllers address decoding, peripheral interfaces, DSP, co-processor functions. device architecture based Actel's patented antifuse technology implemented 0.45µm triple-metal CMOS process. With capacities ranging from 3,000 54,000 system gates, devices provide performance MHz, live power-up have one-fifth standby power consumption comparable FPGAs. Actel's FPGAs provide user I/Os available wide variety packages speed grades. Actel's A42MX24 A42MX36 devices also feature MultiPlex I/Os, which support mixed-voltage systems, enable programmable PCI, deliver high-performance operation both 5.0V 3.3V, provide low-power mode. devices fully compliant with Local Specification (version 2.1). They deliver on-chip operation clock-to-output performance. 42MX24 42MX36 devices include system-level features such IEEE Standard 1149.1 (JTAG) Boundary Scan Testing fast wide-decode modules. addition, A42MX36 device offers dual-port SRAM implementing fast FIFOs, LIFOs, temporary data storage. storage elements efficiently address applications requiring wide datapath manipulation perform transformation functions such those required telecommunications, networking, DSP. devices fully tested over automotive military temperature ranges. addition, largest member family, A42MX36, available both CQ208 CQ256 ceramic packages screened MIL-STD-883 levels. easy prototyping conversion from plastic ceramic, CQ208 PQ208 devices pin-compatible.
devices composed fine-grained building blocks that enable fast, efficient logic designs. devices within these families composed logic modules, modules, routing resources clock networks, which building blocks fast logic designs. addition, A42MX36 device contains embedded dual-port SRAM modules, which optimized high-speed datapath functions such FIFOs, LIFOs scratchpad memory. A42MX24 A42MX36 also contain wide-decode modules.
40MX logic module eight-input, one-output logic circuit designed implement wide range logic functions with efficient interconnect routing resources (Figure logic module implement four basic logic functions (NAND, AND, NOR) gates two, three, four inputs. logic module also implement variety D-latches, exclusivity functions, AND-ORs OR-ANDs. dedicated hard-wired latches flip-flops required array; latches flip-flops constructed from logic modules whenever required application.
Figure 40MX Logic Module
42MX devices contain three types logic modules: combinatorial (C-modules), sequential (S-modules) decode (D-modules). Figure illustrates combinatorial logic module. S-module, shown Figure implements same combinatorial logic function C-module while adding sequential element. sequential element configured either D-flip-flop transparent latch. S-module register bypassed that implements purely combinatorial logic.
Figure 42MX C-Module Implementation
GATE
7-Input Function Plus D-Type Flip-Flop with Clear
7-Input Function Plus Latch
GATE
4-Input Function Plus Latch with Clear
8-Input Function (Same C-Module)
Figure 42MX S-Module Implementation
40MX 42MX FPGA Families
A42MX24 A42MX36 devices contain D-modules, which arranged around periphery device. D-modules contain wide-decode circuitry, providing fast, wide-input function similar that found CPLD architectures (Figure D-module allows A42MX24 A42MX36 devices perform wide-decode functions speeds comparable CPLDs PALs. output D-module programmable inverter active HIGH assertion. D-module output hardwired output pin, also back into array incorporated into other logic.
ules
offering active HIGH implementation. SRAM block contains eight data inputs (WD[7:0]), eight outputs (RD[7:0]), which connected segmented vertical routing tracks. A42MX36 dual-port SRAM blocks provide optimal solution high-speed buffered applications requiring FIFO LIFO queues. ACTgen Macro Builder within Actel's Designer software provides capability quickly design memory functions with SRAM blocks. Unused SRAM blocks used implement registers other user logic within design.
A42MX36 device contains dual-port SRAM modules that have been optimized synchronous asynchronous applications. SRAM modules arranged 256-bit blocks that configured 32x8 64x4. SRAM modules cascaded together form memory spaces user-definable width depth. block diagram A42MX36 dual-port SRAM block shown Figure A42MX36 SRAM modules true dual-port structures containing independent read write ports. Each SRAM module contains bits read write addressing (RDAD[5:0] WRAD[5:0], respectively) 64x4-bit blocks. When configured byte mode, highest order address bits (RDAD5 WRAD5) used. read write ports SRAM block contain independent clocks (RCLK WCLK) with programmable polarities
Inputs
Hard-Wire Programmable Inverter
Feedback Array
Figure A42MX24 A42MX36 D-Module Implementation
WD[7:0]
Latches [7:0]
[5:0] Write Port Logic SRAM Module (256 Bits) Read Port Logic Latches
RDAD[5:0]
WRAD[5:0] Latches
[5:0]
Read Logic
RCLK
MODE BLKEN WCLK Write Logic RD[7:0]
Routing Tracks
Figure A42MX36 Dual-Port SRAM Block
architecture uses vertical horizontal routing tracks interconnect various logic modules. These routing tracks metal interconnects that continuous split into segments. Varying segment lengths allow interconnect over design tracks occur with only antifuse connections. Segments joined together ends using antifuses increase their lengths full length track. interconnects accomplished with maximum four antifuses.
Horizontal Routing
Segmented Horizontal Routing Tracks
Logic Modules
Antifuses
Horizontal routing tracks span whole length divided into multiple segments located between rows modules. segment that spans more than one-third length considered long horizontal segment. typical channel shown Figure Within horizontal routing, dedicated routing tracks used global clock networks power ground tie-off tracks. Non-dedicated tracks used signal nets.
Vertical Routing
Vertical Routing Tracks
Figure Routing Structure
40MX devices have global clock distribution network (CLK). signal network being routed through CLKBUF buffer. 42MX devices, there low-skew, high-fanout clock distribution networks, referred CLKA CLKB. Each network clock module (CLKMOD) that select source clock signal from following (Figure page Externally from CLKA pad, using CLKBUF buffer Externally from CLKB pad, using CLKBUF buffer Internally from CLKINTA input, using CLKINT buffer Internally from CLKINTB input, using CLKINT buffer clock modules located modules. Clock drivers dedicated horizontal clock track located each horizontal routing channel. Clock input pads both 40MX 42MX devices also used normal I/Os, bypassing clock networks. A42MX36 device four additional register control resources, called quadrant clock networks (Figure page Each quadrant clock provides local, high-fanout resource contiguous logic modules within quadrant device. Quadrant clock signals originate from specific pins from internal array used secondary register clock, register clear, output enable.
Another routing tracks vertically through module. There three types vertical tracks: input, output, long. Long tracks span column length module, divided into multiple segments. Each segment input track dedicated input particular module; each segment output track dedicated output particular module. Long segments uncommitted assigned during routing. Each output segment spans four channels (two above below), except near bottom array, where edge effects occur. Long vertical tracks contain either segments. example vertical routing tracks segments shown Figure
Antifuse Structures
antifuse "normally open" structure. antifuses implement programmable logic device results highly testable structures well efficient programming algorithms. There pre-existing connections; temporary connections made using pass transistors. These temporary connections isolate individual antifuses programmed individual circuit structures tested, which done before after programming. instance, metal tracks tested continuity shorts between adjacent tracks, functionality logic modules verified.
40MX 42MX FPGA Families
CLKB CLKA From Pads CLKMOD
CLKINB CLKINA Internal Signal CLKO(17)
Clock Drivers
CLKO(16) CLKO(15)
CLKO(2) CLKO(1)
Clock Tracks
Figure Clock Networks 42MX Devices
QCLKA Quad Clock Module Quad Clock Module
QCLKC
QCLKB *QCLK1IN
QCLK1
QCLK3
QCLKD *QCLK3IN
Quad Clock Module *QCLK2IN
QCLK2
QCLK4
Quad Clock Module *QCLK4IN
*QCLK1IN, QCLK2IN, QCLK3IN, QCLK4IN internally-generated signals.
Figure Quadrant Clock Network A42MX36 Devices
odul
42MX devices feature Multiplex I/Os support 5.0V, 3.3V, mixed 3.3V/5.0V operations. MultiPlex modules provide interface between device pins logic array. Figure block diagram 42MX module. variety user functions, determined library macro selection, implemented module. (Refer Antifuse Macro Library Guide more information.) 42MX modules contain tristate buffers, with input output latches that configured input, output, bidirectional operation. 42MX devices contain flexible structures, where each output dedicated output-enable control (Figure module used latch input output data, both, providing fast set-up time. addition, Actel Designer software tools build D-type flip-flop using C-module combined with module register input output signals. Refer Antifuse Macro Library Guide more details. A42MX24 A42MX36 devices also offer selectable output drives, enabling 100% compliance with version specification. low-power systems, inputs outputs turned reduce current consumption below 500µA. achieve 5.0V 3.3V PCI-compliant output drives A42MX24 A42MX36 devices, chip-wide fuse programmed Device Selection Wizard Designer software (Figure 10). When fuse programmed, output drive standard. Actel's Designer software development tools provide design library macro functions that implement configurations supported FPGAs.
Signal
Output Drive Enable Fuse
Figure Output Structure A42MX24 A42MX36 Devices
devices operate with internal clock frequencies MHz, enabling fast execution complex logic functions. devices live power-up require auxiliary configuration devices thus optimal platform integrate functionality contained multiple programmable logic devices. addition, designs that previously would have required gate array meet performance integrated into device with improvements cost time-to-market. Using timing-driven place-and-route (TDPR) tools, designers achieve highly deterministic device performance.
Actel FuseLock provides robust security against design theft. Special security fuses hidden fabric device prevent unauthorized users from accessing programming and/or probe interfaces. virtually impossible identify bypass these fuses without damaging device, making Actel antifuse FPGAs immune both invasive noninvasive attacks. Special security fuses 40MX devices include Probe Fuse Program Fuse. former disables probing circuitry while latter prohibits further programming fuses, including Probe Fuse. 42MX devices, there Security Fuse which, when programmed, both disables probing circuitry prohibits further programming device. Look this symbol ensure your valuable secure. more information, refer Actel's Implementation Security Actel Antifuse FPGAs application note.
From Array
G/CLK*
Array
G/CLK* Configured Latch Flip-Flop (Using C-Module)
Figure 42MX Module
FuseLock
40MX 42MX FPGA Families
Load .AFM file Select device programmed Begin programming
Device programming supported through Silicon Sculptor series programmers. Silicon Sculptor compact, robust, single-site multi-site device programmer With standalone software, Silicon Sculptor designed allow concurrent programming multiple units from same Silicon Sculptor programs devices independently achieve fastest programming times possible. After being programmed, each fuse verified insure that been programmed correctly. Furthermore, programming, there integrity tests that ensure extra fuses have been programmed. only does test fuses (both programmed nonprogrammed), Silicon Sculptor also allows self-test verify hardware extensively. procedure programming device using Silicon Sculptor follows: Table Voltage Support Devices
Device 40MX 5.0V 3.3V 42MX VCCA 5.0V 3.3V 5.0V VCCI 5.0V 3.3V 3.3V
When design ready production, Actel offers device volume-programming services either through distribution partners In-House Programming from factory. more details programming devices, please refer Programming Actel Devices Silicon Sculptor user's guides.
uppl
devices designed operate both 5.0V 3.3V environments. particular, 42MX devices operate mixed 5.0V/3.3V systems. Table describes voltage support devices.
Maximum Input Tolerance 5.5V 3.6V 5.5V 3.6V 5.5V
Nominal Output Voltage 5.0V 3.3V 5.0V 3.3V 3.3V
ower ixed
When powering 42MX mixed voltage mode (VCCA 5.0V VCCI 3.3V), VCCA must greater than equal VCCI throughout power-up sequence. VCCI exceeds VCCA during power either I/Os' input protection junction I/Os will forward-biased I/Os will logical HIGH, rises high levels. power-down, sequence with VCCA VCCI implemented.
42MX devices have been designed with Power Mode. This feature, activated with setting special HIGH period longer than particularly useful battery-operated systems where battery life primary concern. this mode, core device turned device consumes minimal power with standby current. addition, input buffers turned off, outputs bidirectional buffers tristated. Since core device turned off, states registers lost. device must re-initialized when exiting Power Mode. I/Os driven during mode, clock pins should driven HIGH should float avoid drawing current. exit mode, must pulled over allow charge pumps power device initialization will begin.
general power consumption devices made static dynamic power expressed with following equation:
Gener quat
VCCA Power supply volts Switching frequency megahertz (MHz)
apac ance
[ICCstandby ICCactive] VCCI IOL* VOL* (VCCI VOH) where: ICCstandby current flowing when inputs outputs changing. ICCactive current flowing CMOS switching. IOL, sink/source currents. VOL, level output voltages. equals number outputs driving loads VOL. equals number outputs driving loads VOH. Accurate values difficult determine because they depend family type, design details, system I/O. power divided into components: static active.
ponen
Equivalent capacitance calculated measuring ICCactive specified frequency voltage each circuit component interest. Measurements have been made over range frequencies fixed value VCC. Equivalent capacitance frequency-independent, results used over wide range operating conditions. Equivalent capacitance values shown below.
Valu
Modules (CEQM) Input Buffers (CEQI) Output Buffers (CEQO) Routed Array Clock Buffer Loads (CEQCR)
18.2
calculate active power dissipated from complete design, switching frequency each part logic must known. equation below shows piece-wise linear summation over components. Power VCCA2 CEQM fm)Modules CEQI fn)Inputs (CEQO fp)outputs CEQCR fq1)routed_Clk1 fq1)routed_Clk1 CEQCR fq2)routed_Clk2 fq2)routed_Clk2 where: CEQM CEQI CEQO
static power standby current typically small component overall power consumption. Standby power calculated commercial, worst-case conditions. static power dissipation loads depends number outputs driving, load current. instance, 32-bit sinking 0.33V will generate 42mW with outputs driving LOW, 140mW with outputs driving HIGH. actual dissipation will average somewhere between, I/Os switch states with time.
ower nent
Power dissipation CMOS devices usually dominated dynamic power dissipation. Dynamic power consumption frequency-dependent function logic external I/O. Active power dissipation results from charging internal chip capacitances interconnect, unprogrammed antifuses, module inputs, module outputs, plus external capacitances board traces load device inputs. additional component active power dissipation totem pole current CMOS transistor pairs. effect associated with equivalent capacitance that combined with frequency voltage represent active power dissipation. power dissipated CMOS circuit expressed equation: Power (µW) VCCA2 where: Equivalent capacitance expressed picofarads (pF)
Number logic modules switching frequency Number input buffers switching frequency Number output buffers switching frequency Number clock loads first routed array clock Number clock loads second routed array clock Fixed capacitance first routed array clock Fixed capacitance second routed array clock Equivalent capacitance logic modules Equivalent capacitance input buffers Equivalent capacitance output buffers
CEQCR Equivalent capacitance routed array clock Output load capacitance Average logic module switching rate Average input buffer switching rate Average output buffer switching rate Average first routed array clock rate Average second routed array clock rate
40MX 42MX FPGA Families
Device Type A40MX02 A40MX04 A42MX09 A42MX16 A42MX24 A42MX36
routed_Clk1 41.4 68.6
routed_Clk2
functional 18-channel logic analyzer. Silicon Explorer allows designers complete design verification process their desks reduces verification time from several hours cycle seconds. Silicon Explorer used control MODE, DCLK, pins devices select desired nets debugging. user simply assigns selected internal nets Silicon Explorer software PRA/PRB output pins observation. Probing functionality activated when MODE held HIGH. Figure illustrates interconnection between Silicon Explorer 40MX devices, while Figure page illustrates interconnection between Silicon Explorer 42MX devices allow probing capabilities, security fuses must programmed. (Refer "User Security" section page security fuses 40MX 42MX devices). Table page summarizes possible device configurations probing. pins dual-purpose pins. When "Reserve Probe Pin" checked Designer software, pins reserved dedicated outputs probing. pins required user I/Os achieve successful layout "Reserve Probe Pin" checked, layout tool will override option place user I/Os pins.
xplo
devices contain probing circuitry that provides built-in access every node design, Silicon Explorer Silicon Explorer integrated hardware software solution that, conjunction with Designer software, allow users examine internal nets device while operating prototyping production system. user probe into device without changing placement routing design without using additional resources. Silicon Explorer II's noninvasive method does alter timing loading effects, thus shortening debug cycle providing true representation device under actual functional situations. Silicon Explorer samples data (asynchronous) (synchronous). Silicon Explorer attaches PC's standard port, turning into fully
Logic Analyzer Channels
Serial Connection Windows
40MX Silicon Explorer
MODE DCLK
Figure Silicon Explorer Setup with 40MX
Logic Analyzer Channels
Serial Connection Windows
42MX Silicon Explorer
MODE DCLK
Figure Silicon Explorer Setup with 42MX Table Device Configuration Options Probe Capability
Security Fuse(s) Programmed MODE HIGH PRA, PRB1 User I/Os2 Probe Circuit Outputs Probe Circuit Secured SDI, SDO, DCLK1 User I/Os2 Probe Circuit Inputs Probe Circuit Secured
Notes: Avoid using SDI, SDO, DCLK, pins input bidirectional ports. Since these pins active during probing, input signals will pass through these pins cause contention. user signal assigned these pins, they will behave unused I/Os this mode. "Pin Descriptions" section page information unused pins.
recommended series termination resistor every probe connector (SDI, SDO, MODE, DCLK, PRB). series termination used prevent data transmission corruption during probing reading back checksum.
149.
rising edge given state transition occur. indicate that instruction register data register operating that state. controller receives control inputs (TMS TCK) generates control clock signals rest test logic architecture. power-up, controller enters Test-Logic-Reset state. guarantee reset controller from possible states, must remain high five cycles. 42MX24 42MX36 devices support three types test data registers: bypass, device identification, boundary scan. bypass register selected when other register needs accessed device. This speeds test data transfer other devices test data path. 32-bit device identification register shift register with four fields (lowest significant byte (LSB), number, part number version). boundary-scan register observes controls state each pin. Each cell three boundary-scan register cells, each with serial-in, serial-out, parallel-in, parallel-out pin. serial pins used serially connect boundary-scan register cells device into boundary-scan register chain, which starts ends pin. parallel ports connected internal core logic tile input, output control ports buffer capture load data into register control observe logic state each I/O.
42MX24 42MX36 devices compatible with IEEE Standard 1149.1 (informally known Joint Testing Action Group Standard JTAG), which defines hardware architecture mechanisms cost-effective board-level testing. basic boundary-scan logic circuit composed (test access port), controller, test data registers instruction register (Figure page 14). This circuit supports mandatory IEEE 1149.1 instructions (EXTEST, SAMPLE/PRELOAD BYPASS) some optional instructions. Table page describes ports that control JTAG testing, while Table page describes test instructions supported these devices. Each test section accessed through TAP, which four associated pins: (test clock input), (test data input output), (test mode selector). controller four-bit state machine. '1's '0's represent values that must present
40MX 42MX FPGA Families
Boundary Scan Register Bypass Register Control Logic JTAG JTAG Instruction Register Controller Instruction Decode
Output
Figure 42MX IEEE 1149.1 Boundary Scan Circuitry Table Test Access Port Descriptions
Port (Test Mode Select) Description Serial input test logic control bits. Data captured rising edge test logic clock (TCK). Dedicated test logic clock used serially shift test instruction, test data, control inputs rising edge clock, serially shift output data falling edge clock. maximum clock frequency MHz. Serial input instruction test data. Data captured rising edge test logic clock. Serial output test instruction data from test logic. Inactive Drive state (high impedance) when data scanning progress.
(Test Clock Input)
(Test Data Input) (Test Data Output)
Table Supported Public Instructions
Instruction EXTEST Code (IR2.IR0) Instruction Type Mandatory Description Allows external circuitry board-level interconnections tested forcing test pattern output pins capturing test results input pins. Allows snapshot signals device pins captured examined during operation Tristates I/Os allow external signals drive pins. Please refer IEEE Standard 1149.1 specification. Allows state signals driven from component pins determined from Boundary-Scan Register. Please refer IEEE Standard 1149.1 specification details. Enables bypass register between pins. test data passes through selected device adjacent devices test chain.
SAMPLE/PRELOAD HIGH
Mandatory Optional
CLAMP
Optional
BYPASS
Mandatory
Mode
JTAG test logic circuit activated Designer software selecting Tools Device Selection. This brings Device Selection dialog shown Figure JTAG test logic circuit enabled clicking "Reserve JTAG Pins" check box. Table explains pins' behavior either mode.
Figure Device Selection Wizard Table Boundary Scan Configuration Functionality
Reserve JTAG TDI, Checked input; must terminated logical HIGH avoid floating input; float tied HIGH output; float connected another device Unchecked User User User
active reset (TRST) supported; however, devices contain power-on circuitry that resets boundary scan circuitry upon power-up. Also, equipped with internal pull-up resistor. This allows controller remain return Test-Logic-Reset state when there input when logical pin. reset controller, must HIGH least five cycles.
ndar Lang uage
passing necessary design data among tools. Additionally, Libero allows users integrate both schematic synthesis into single flow verify entire design single environment. Libero includes Synplify® Actel from Synplicity®, ViewDraw Actel from Mentor Graphics, ModelSimHDL Simulator from Mentor Graphics®, WaveFormer Litefrom SynaptiCADTM, Designer software from Actel. Refer Libero flow (located Actel's website) diagram more information. Actel's Designer software place-and-route tool provides comprehensive suite backend support tools FPGA development. Designer software includes timing-driven place-and-route, world-class integrated static timing analyzer constraints editor. With Designer software, user lock his/her design pins before layout while minimally impacting results place-and-route. Additionally, back-annotation flow compatible with major simulators simulation results cross-probed with Silicon Explorer Actel's integrated verification logic analysis tool. Another tool included Designer software ACTgen macro builder, which easily creates popular commonly used logic functions implementation into your schematic design. Actel's Designer software compatible with most popular FPGA design entry verification tools from companies such Mentor Graphics, Synplicity, Synopsys, Cadence Design Systems. Designer software available both Windows UNIX operating systems. Actel's Designer software compatible with most popular FPGA design entry verification tools from companies such Mentor Graphics, Synplicity, Synopsys, Cadence Design Systems. Designer software available both Windows UNIX operating systems.
Conforming IEEE Standard 1149.1 requires that operation various JTAG components documented. BSDL file provides standard format describe JTAG components that used automatic test equipment software. file includes instructions that supported, instruction pattern, boundary-scan chain order. in-depth discussion BSDL files, please refer Actel BSDL Files Format Description application note. Actel BSDL files grouped into categories generic device-specific. generic files assign user I/Os inouts. Device-specific files assign user I/Os inputs, outputs inouts. Generic files devices available Actel's website
family FPGAs fully supported both Actel's LiberoIntegrated Design Environment Designer FPGA Development software. Actel Libero design management environment that streamlines design flow. Libero provides integrated design manager that seamlessly integrates design tools while guiding user through design flow, managing design files,
40MX 42MX FPGA Families
Actel BSDL Files Format Description Programming Actel Devices
anua
Antifuse Macro Library Guide Actel's Implementation Security Actel Antifuse FPGAs Silicon Sculptor
neous
Libero Flow Diagram
axim 40MX ices
Symbol tSTG Note: Supply Voltage Input Voltage Output Voltage
Parameter
Limits -0.5 +7.0 -0.5 VCC+0.5 -0.5 VCC+0.5 +150
Units
Storage Temperature
*Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. Exposure absolute maximum rated conditions extended periods affect device reliability. Devices should operated outside Recommended Operating Conditions.
axim 42MX ices
Symbol VCCI VCCA tSTG Note:
Parameter Supply Voltage I/Os Supply Voltage Array Input Voltage Output Voltage Storage Temperature
Limits -0.5 +7.0 -0.5 +7.0 -0.5 VCCI+0.5 -0.5 VCCI+0.5 +150
Units
*Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. Exposure absolute maximum rated conditions extended periods affect device reliability. Devices should operated outside Recommended Operating Conditions.
ende
Parameter Temperature Range* (40MX) VCCA (42MX) VCCI (42MX) Note:
Commercial 4.75 5.25 4.75 5.25 4.75 5.25
Industrial
Military +125
Units
*Ambient temperature (TA) used commercial industrial grades; case temperature (TC) used military grades.
40MX 42MX FPGA Families
Commercial Symbol VOH1 VOL1 (40MX) (42MX) Input Transition Time, Capacitance A40MX02, A40MX04 Standby Current, ICC2 A42MX09 A42MX16 A42MX24, A42MX36 Low-Power Mode Standby Current 42MX devices only 0.5V 2.7V Parameter -10mA -4mA 10mA -0.3 VCC+0.3 VCCI+0.3 -0.3 VCC+0.3 VCCI+0.3 -0.3 VCC+0.3 VCCI+0.3 -0.3 VCC+0.3 VCCI+0.3 Min. Commercial Min. 'Industrial Min. Military Units
IIO, source sink current derived from IBIS model Notes: Only output tested time. VCC/VCCI min. outputs unloaded. inputs VCC/VCCI GND.
axim 40MX ices
Symbol tSTG Note:
Parameter Supply Voltage Input Voltage Output Voltage Storage Temperature
Limits -0.5 +7.0 -0.5 VCC+0.5 -0.5 VCC+0.5 +150
Units
*Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. Exposure absolute maximum rated conditions extended periods affect device reliability. Devices should operated outside Recommended Operating Conditions.
axim 42MX ices
Symbol VCCI VCCA tSTG Note:
Parameter Supply Voltage I/Os Supply Voltage Array Input Voltage Output Voltage Storage Temperature
Limits -0.5 +7.0 -0.5 +7.0 -0.5 VCCI+0.5 -0.5 VCCI+0.5 +150
Units
*Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. Exposure absolute maximum rated conditions extended periods affect device reliability. Devices should operated outside Recommended Operating Conditions.
ende
Parameter Temperature Range* (40MX) VCCA (42MX) VCCI (42MX) Note:
Commercial
Industrial
Military +125
Units
*Ambient temperature (TA) used commercial industrial grades; case temperature (TC) used military grades.
40MX 42MX FPGA Families
Commercial Symbol (40MX) (42MX) Input Transition Time, Capacitance A40MX02, A40MX04 Standby Current, ICC2 A42MX09 A42MX16 A42MX24, A42MX36 Low-Power Mode Standby Current IIO, source sink current 42MX devices only
Commercial Min. 2.15
Industrial Min.
Military Min. Units 0.48 -0.3 VCC+0.3 VCCI+0.3
Parameter -4mA
Min. 2.15
VOL1
-0.3 VCC+0.3 VCCI+0.3 -0.3
VCC+0.3 VCCI+0.3 -0.3
0.48 VCC+0.3 VCCI+0.3
derived from IBIS model
Notes: Only output tested time. VCC/VCCI min. outputs unloaded. inputs VCC/VCCI GND.
axim
Symbol VCCI VCCA tSTG Note:
Parameter Supply Voltage I/Os Supply Voltage Array Input Voltage Output Voltage Storage Temperature
Limits -0.5 +7.0 -0.5 +7.0 -0.5 VCCI+0.5 -0.5 VCCI+0.5 +150
Units
*Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. Exposure absolute maximum rated conditions extended periods affect device reliability. Devices should operated outside Recommended Operating Conditions.
ende
Parameter Temperature Range* VCCA VCCI Note:
Commercial 4.75 5.25 3.14 3.47
Industrial
Military +125
Units
*Ambient temperature (TA) used commercial industrial grades; case temperature (TC) used military grades.
Commercial Symbol VOH1 VOL1 Input Transition Time, Capacitance A42MX09 Standby Current, ICC2 A42MX16 A42MX24, A42MX36 Low-Power Mode Standby Current source sink current 0.5V 2.7V Parameter -10mA -4mA 10mA -0.3 VCCI+0.3 -0.3 VCCI+0.3 -0.3 VCCI+0.3 -0.3 VCCI+0.3 Min. Commercial Min. 'Industrial Min. Military Min. Units
derived from IBIS model
Notes: Only output tested time. VCCI min. outputs unloaded. inputs VCCI GND.
40MX 42MX FPGA Families
device drivers were designed specifically high-performance systems. Figure page shows typical output drive characteristics devices. output drivers compliant with Local Specification.
igna
Symbol VCCI CCLK LPIN Parameter Supply Voltage I/Os Input High Voltage Input Voltage Input High Leakage Current Input Leakage Current Output High Voltage Output Voltage Input Capacitance Capacitance Inductance 2.7V VIN=0.5V IOUT IOUT IOUT 0.55 3.84 Condition Min. 4.75 -0.5 5.25 Min. 4.75 -0.3
5.252 VCCI Units 0.33
Notes: Local Specification, Version 2.1, Section 4.2.1.1. Maximum rating VCCI -0.5V 7.0V. Dependent upon chosen package. recommends packaging reduce inductance capacitance.
(5.0 gnal
Symbol Slew Slew Note: Parameter Clamp Current Output Rise Slew Rate Output Fall Slew Rate Condition 0.4V 2.4V load 2.4V 0.4V load Min. (VIN /0.015 Min.
Units V/ns V/ns
*PCI Local Specification, Version 2.1, Section 4.2.1.2.
igna
Symbol VCCI CCLK LPIN Parameter Supply Voltage I/Os Input High Voltage Input Voltage Input High Leakage Current Input Leakage Current Output High Voltage Output Voltage Input Capacitance Capacitance Inductance IOUT IOUT 2.7V Condition Min. -0.5 Min. -0.3
VCCI Units VCCI
Notes: Local Specification, Version 2.1, Section 4.2.2.1. Maximum rating VCCI -0.5V 7.0V. Dependent upon chosen package. recommends packaging reduce inductance capacitance.
igna ng)*
Symbol Slew Slew Note: Parameter Clamp Current Output Rise Slew Rate Output Fall Slew Rate Condition 0.2V 0.6V load 0.6V 0.2V load Min. (VIN /0.015 Min.
Units V/ns V/ns
*PCI Local Specification, Version 2.1, Section 4.2.2.2.
40MX 42MX FPGA Families
0.50 0.45 0.40 0.35 0.30 0.25 0.20 Current 0.15 0.10
Maximum
Minimum
0.05 0.00
-0.05 -0.10 -0.15 -0.20
Maximum
Minimum
Voltage
Figure Typical Output Drive Characteristics (based upon measured data)
temperature variable Designer software refers junction temperature, ambient temperature. This important distinction because heat generated from dynamic power consumption usually hotter than ambient temperature. Equation shown below, used calculate junction temperature. Junction Temperature Where: Ambient Temperature Temperature gradient between junction (silicon) ambient Power
Junction ambient package. numbers located Package Thermal Characteristics table below.
device junction-to-case thermal characteristic junction-to-ambient characteristic thermal characteristics shown with different flow rates. maximum junction temperature 150°C. Maximum power dissipation commercialindustrial-grade devices function
sample calculation absolute maximum power dissipation allowed TQFP 176-pin package commercial temperature still follows:
Max. junction temp. (°C) Max. ambient temp. (°C) 150°C 70°C Maximum Power Allowed 2.86W (°C/W) 28°C/W
maximum power dissipation military-grade devices function sample calculation absolute maximum power dissipation allowed CQFP 208-pin package military temperature still follows:
Max. junction temp. (°C) Max. ambient temp. (°C) 150°C 125°C Maximum Power Allowed 3.97W (°C/W) 6.3°C/W
Plastic Packages Plastic Quad Flat Pack Plastic Quad Flat Pack Plastic Quad Flat Pack Plastic Quad Flat Pack Plastic Leaded Chip Carrier Plastic Leaded Chip Carrier Plastic Leaded Chip Carrier Thin Plastic Quad Flat Pack Very Thin Plastic Quad Flat Pack Very Thin Plastic Quad Flat Pack Plastic Ball Grid Array Count
12.0 10.0 16.0 13.0 12.0 11.0 12.0 10.0
Still 27.8 26.2 26.1 25.6 20.0 25.0 22.5 24.7 38.2 35.3 18.3
ft/min 23.4 22.8 22.5 22.3 24.5 21.0 18.9 19.9 31.9 29.4 14.9
ft/min 21.2 21.1 20.8 20.8 22.0 19.4 17.6 18.0 29.4 27.1 13.9
Units °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W
Ceramic Packages Ceramic Quad Flat Pack Ceramic Quad Flat Pack Count
Still 22.0 20.0
ft/min 19.8 16.5
ft/min 18.0 15.0
Units °C/W °C/W
40MX 42MX FPGA Families
Input Delay Module tINYL 0.62 IRD2 2.59 Logic Module tDLH 3.32 tIRD1 2.09 tIRD4 3.64 tIRD8 5.73 1.24 1.24 tRD1 1.28 tRD2 1.80 tRD4 2.33 tRD8 4.93 tENHZ 7.92 Internal Delays Predicted Routing Delays Output Delay Module
Array Clock
tCKH 4.55 FMAX
Note:
Values shown 40MX `-3' speed devices 5.0V worst-case commercial conditions.
Input Delays Module tINYL Internal Delays tIRD1 Combinatorial Logic Module tRD1 tRD2 tRD4 tRD8 Predicted Routing Delays Output Delays Module
tDLH
tINH tINSU tINGL Sequential Logic Module
Combinatorial Logic included tSUD
Module tDLH
tRD1 0.70
tENHZ
tOUTH 0.00 tOUTSU tGLH
Array Clocks
tCKH 2.70 FMAX
tSUD 0.00
tLCO (light loads, pad-to-pad)
Notes: *Values shown A42MX09 `-3' 5.0V worst-case commercial conditions. Input module predicted routing delay.
40MX 42MX FPGA Families
Input Delays Module tINPY IRD1 Combinatorial Module tRD1 tRD2 tRD4 Internal Delays Predicted Routing Delays Output Delays Module
tDLH
tINH tINSU tINGO Decode Module tPDD Module tDLH
tRDD
Sequential Logic Module
Combinatorial Logic included tSUD
tRD1
tENHZ
0.00 tLSU tGHL=
tSUD Quadrant Clocks tCKH 3.03 ns** FMAX
Notes: Values shown A42MX36 `-3' 5.0V worst-case commercial conditions. Load-dependent
Input Delays Module tINPY IRD1
tINSU tINH tINGO
Predicted Routing Delays [7:0] WRAD [5:0] BLKEN WCLK tADSU tADH tWENSU tBENS [7:0] RDAD [5:0] tRD1
Module tDLH
RCLK tADSU tADH tRENSU tRCO
tGHL= tLSU
Array Clocks FMAX Note:
*Values shown A42MX36 5.0V worst-case commercial conditions.
TRIBUFF test loads (shown below)
1.5V 1.5V
VCCI
1.5V tENLZ
1.5V tENHZ
tDLH
tDHL
tENZL
tENZH
40MX 42MX FPGA Families
Load (Used measure propagation delay)
Load (Used measure rising/falling edges) VCCI
output under test
output under test
VCCI tPLZ/tPZL tPHZ/tPZH
Modu
INBUF
tINYH 1.5V 1.5V VCCI tINYL
tPLH tPHL tPLH
tPHL
(Positive Edge-Triggered)
tSUD tSUENA tHENA PRE, tWASYN Note: represents data functions involving multiplexed flip-flops. tWCLKI tWCLKA
40MX 42MX FPGA Families
(continued)
Inpu Buffer
DATA
IBDL
CLKBUF
DATA tINH tINSU tHEXT tSUEXT
uffer ches
OBDLHS
tOUTSU tOUTH
A-G,
tPHL tPLH
Write Port WRAD [5:0] BLKEN WCLK [7:0] Array 32x8 64x4 (256 Bits)
Read Port RDAD [5:0] RCLK [7:0]
40MX 42MX FPGA Families
42MX
tRCKHL WCLK tADSU WD[7:0] WRAD[5:0] Valid tWENSU tBENSU BLKEN Valid tBENH tWENH tADH
tRCKHL
Note:
Identical timing falling edge clock.
42MX hronou
tCKHL RCLK
tRCKHL
tRENSU tADSU RDAD[5:0] Valid
tRENH
tADH
tRCO tDOH RD[7:0] Data Data
Note:
Identical timing falling edge clock.
42MX chrono
(Read Address Controlled)
tRDADV RDAD[5:0] ADDR1 tDOH RD[7:0] Data ADDR2 tRPD Data
42MX chrono
(Write Address Controlled)
tWENSU
tWENH
WD[7:0] WRAD[5:0] BLKEN
Valid tADSU tADH tRPD tDOH
WCLK
RD[7:0]
Data
Data
40MX 42MX FPGA Families
Propagation delay between logic modules depends resistive capacitive loading routing tracks, interconnect elements, module inputs being driven. Propagation delay increases length routing tracks, number interconnect elements, number inputs increases. From design perspective, propagation delay statistically correlated modeled fanout (number loads) driven module. Higher fanout usually requires some paths have longer routing tracks. FPGAs deliver tight fanout delay distribution, which achieved ways: decreasing delay interconnect elements decreasing number interconnect elements path. Actel's patented antifuse offers very resistive/capacitive interconnect. antifuses, fabricated 0.45 lithography, offer nominal levels resistance 7.0fF capacitance antifuse. fanout distribution also tight number antifuses required each interconnect path. proprietary architecture limits number antifuses path maximum four, with percent interconnects using only antifuses.
Device timing characteristics fall into three categories: family-dependent, device-dependent, design-dependent. input output buffer characteristics common devices. Internal routing delays device-dependent; actual delays determined until after place-and-route user's design complete. Delay values then determined using Designer software utility performing simulation with post-layout delays.
ical
Propagation delays expressed only typical nets, which used initial design performance evaluation. Critical delays then applied most timing critical paths. Critical nets determined property assignment Actel's Designer software prior placement routing. nets design designated critical.
Some nets design long tracks, which special routing resources that span multiple rows, columns, modules. Long tracks employ three sometimes four antifuse connections, which increase capacitance resistance, resulting longer delays macros connected long tracks. Typically, percent nets fully utilized device require long tracks. Long tracks approximately delay, which represented statistically higher fanout (FO=8) routing delays data sheet specifications section, beginning page
devices manufactured with CMOS process. Therefore, device performance varies according temperature, voltage, process changes. Minimum timing parameters reflect maximum operating voltage, minimum operating temperature best-case processing. Maximum timing parameters reflect minimum operating voltage, maximum operating temperature worst-case processing.
(Normalized 25°C, 5.0V)
Temperature 42MX Voltage -55°C 4.50 4.75 5.00 5.25 5.50 0.93 0.88 0.85 0.84 0.83 -40°C 0.95 0.90 0.87 0.86 0.85 1.05 1.00 0.96 0.95 0.94 25°C 1.09 1.03 1.00 0.97 0.96 70°C 1.25 1.18 1.15 1.12 1.10 85°C 1.29 1.22 1.18 1.14 1.13 125°C 1.41 1.34 1.29 1.28 1.26
42MX Junction Temperature Voltage Derating Curves (Normalized 25°C, VCCA 5.0V)
1.50 1.40
Derating Factor
1.30 -55°C 1.20 -40°C 1.10 1.00 0.90 0.80 0.70 0.60 4.50 4.75 5.00 5.25 5.50 25°C 70°C 85°C 125°C
Voltage
Note: This derating factor applies routing propagation delays.
40MX 42MX FPGA Families
(Normalized 25°C, 5.0V)
Temperature 40MX Voltage -55°C 4.50 4.75 5.00 5.25 5.50 0.89 0.84 0.82 0.80 0.79 -40°C 0.93 0.88 0.85 0.82 0.82 1.02 0.97 0.94 0.91 0.90 25°C 1.09 1.03 1.00 0.97 0.96 70°C 1.25 1.18 1.15 1.12 1.10 85°C 1.31 1.24 1.20 1.16 1.15 125°C 1.45 1.37 1.33 1.29 1.28
40MX Junction Temperature Voltage Derating Curves (Normalized 25°C, 5.0V)
1.50 1.40
Derating Factor
1.30 1.20 1.10 1.00 0.90 0.80 0.70 0.60 4.50 4.75 5.00 5.25 5.50 -55°C -40°C 25°C 70°C 85°C 125°C
Voltage
Note: This derating factor applies routing propagation delays.
(Normalized 25°C, 3.3V)
Temperature 42MX Voltage 3.00 3.30 3.60 -55°C 0.97 0.84 0.81 -40°C 1.00 0.87 0.84 1.10 0.96 0.92 25°C 1.15 1.00 0.96 70°C 1.32 1.15 1.10 85°C 1.36 1.18 1.13 125°C 1.45 1.26 1.21
42MX Junction Temperature Voltage Derating Curves (Normalized 25°C, VCCA 3.3V)
1.60 1.50 1.40 1.30 1.20 1.10 1.00 0.90 0.80 0.70 0.60 0.50 0.40 3.00 3.30 Voltage 3.60
55°C 40°C 25°C 70°C 85°C 125°C
Note:
Derating Factor
This derating factor applies routing propagation delays.
40MX 42MX FPGA Families
(Normalized 25°C, 3.3V)
Temperature 40MX Voltage 3.00 3.30 3.60 -55°C 1.08 0.86 0.83 -40°C 1.12 0.89 0.85 1.21 0.96 0.92 25°C 1.26 1.00 0.96 70°C 1.50 1.19 1.14 85°C 1.64 1.30 1.25 125°C 2.00 1.59 1.53
40MX Junction Temperature Voltage Derating Curves (Normalized 25°C, 3.3V)
2.20 2.00 1.80 Derating Factor 1.60 1.40 1.20 1.00 0.80 0.60 3.00 3.30 Voltage 3.60 55°C -55°C 40°C -40C °0°C 25°C 25°C 70°C 70°C 85°C 85°C 125°C 125°
Note:
This derating factor applies routing propagation delays.
Table Table list critical timing parameters corresponding timing parameters PCI-compliant devices. Table Clock Specification
Actel provides synthesizable VHDL Verilog-HDL models Target interface, Target Target+DMA Master interface. Contact your Actel sales representative more details.
Symbol tCYC tHIGH tLOW Parameter Cycle Time High Time Time Min. Max.
A42MX24 Min. Max.
A42MX36 Min. Max. Units
Table Timing Parameters
Symbol tVAL tVAL(PTP) tOFF tSU(PTP) Parameter Signal Valid-Bused Signals Signal Valid-Point-to-Point Float Active Active Float Input Set-Up Time CLK-Bused Signals Input Set-Up Time CLK-Point-to-Point Input Hold Min.
A42MX24 Max. Min. Max. 8.31
A42MX36 Min. Max. 8.31 Units
Notes: TOFF system dependent. devices have turn-off time, reflection typically additional REQ# GNT# point-to-point signals have different output valid delay input setup times than bussed signals. GNT# setup REW# setup
40MX 42MX FPGA Families
(Worst-Case Commercial Conditions, 4.75V, 70°C)
`-3' Speed Parameter Description Logic Module Propagation Delays tPD1 tPD2 Single Module Dual-Module Macros Sequential Clock-to-Q Latch G-to-Q Flip-Flop (Latch) Reset-to-Q
`-2' Speed Min. Max.
`-1' Speed Min. Max.
`Std' Speed Min. Max.
`-F' Speed Min. Max. Units
Min.
Max.
Logic Module Predicted Routing Delays tRD1 tRD2 tRD3 tRD4 tRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay Timing2
10.6
Logic Module Sequential tSUD
Flip-Flop (Latch) Data Input Set-Up Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Flip-Flop (Latch) Clock Frequency 128)
10.4
tSUENA tHENA tWCLKA tWASYN fMAX
Notes: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Set-up times assume fanout Further testing information obtained from Timer utility. hold time DFME1A macro greater than Timer tool from Designer software check hold time this macro.
(continued)
(Wor erci ndit 4.75V, 70°C)
`-3' Speed Parameter Description Input Module Propagation Delays tINYH tINYL Pad-to-Y HIGH Pad-to-Y Delays1 12.4 Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Input Module Predicted Routing tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Global Clock Network tCKH tCKL tPWH tPWL tCKSW fMAX Input HIGH Input High 3.01 10.0 10.4 10.4 10.4
Minimum Pulse Width HIGH Minimum Pulse Width Maximum Skew Minimum Period Maximum Frequency
Note: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance.
40MX 42MX FPGA Families
(continued)
(Wor erci ndit 4.75V, 70°C)
`-3' Speed Parameter Description Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable Delta HIGH Delta HIGH Timing1 0.03 0.02 0.04 0.02 10.4 0.04 0.03 6.05 12.2 0.05 0.03 10.5 17.0 12.6 0.07 0.04 ns/pF ns/pF 0.02 0.03 0.02 0.03 10.4 0.03 0.03 12.2 0.03 0.04 10.1 17.1 12.6 0.04 0.06 ns/pF ns/pF Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
CMOS Output Module tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL
Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable Delta HIGH Delta HIGH
Note: Delays based loading.
(Worst-Case Commercial Conditions, 3.0V, 70°C)
`-3' Speed Parameter Description Logic Module Propagation Delays tPD1 tPD2 Single Module Dual-Module Macros Sequential Clock-to-Q Latch G-to-Q Flip-Flop (Latch) Reset-to-Q
`-2' Speed Min. Max.
`-1' Speed Min. Max.
`Std' Speed Min. Max.
`-F' Speed Min. Max. Units
Min.
Max.
Logic Module Predicted Routing Delays tRD1 tRD2 tRD3 tRD4 tRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay Timing2
10.9
15.2
Logic Module Sequential tSUD
Flip-Flop (Latch) Data Input Set-Up Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Flip-Flop (Latch) Clock Frequency 128)
10.4
14.6
tSUENA tHENA tWCLKA tWASYN fMAX
Notes: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Set-up times assume fanout Further testing information obtained from Timer utility. hold time DFME1A macro greater than Timer tool from Designer software check hold time this macro.
40MX 42MX FPGA Families
(continued)
(Wor erci ndit 3.0V, 70°C)
`-3' Speed Parameter Description Input Module Propagation Delays tINYH tINYL Pad-to-Y HIGH Pad-to-Y Delays1 9.26 10.5 12.6 11.0 17.3 Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Input Module Predicted Routing tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Global Clock Network tCKH tCKL tPWH tPWL tCKSW fMAX Input HIGH Input HIGH Minimum Pulse Width HIGH Minimum Pulse Width Maximum Skew Minimum Period Maximum Frequency 10.1 10.4 14.1 14.6 10.4 10.4 13.7 13.7 14.5 14.5
Note: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance.
(continued)
(Wor erci ndit 3.0V, 70°C)
`-3' Speed Parameter Description Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable Delta HIGH Delta HIGH Timing1 11.1 0.05 0.03 12.8 0.05 0.03 14.5 10.7 0.06 0.04 10.5 17.1 12.6 0.07 0.04 11.9 10.2 10.2 14.7 23.9 17.7 0.10 0.06 ns/pF ns/pF 11.1 0.03 0.04 12.8 0.03 0.04 14.5 10.7 0.04 0.05 10.1 17.1 12.6 0.04 0.06 10.0 12.0 11.3 14.1 23.9 17.7 0.06 0.08 ns/pF ns/pF Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
CMOS Output Module tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL
Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable Delta HIGH Delta HIGH
Note: Delays based loading.
40MX 42MX FPGA Families
(Worst-Case Commercial Conditions, 4.75V, 70°C)
`-3' Speed Parameter Description Logic Module Propagation Delays tPD1 tPD2 Single Module Dual-Module Macros Sequential Clock-to-Q Latch G-to-Q Flip-Flop (Latch) Reset-to-Q
`-2' Speed Min. Max.
`-1' Speed Min. Max.
`Std' Speed Min. Max.
`-F' Speed Min. Max. Units
Min.
Max.
Logic Module Predicted Routing Delays tRD1 tRD2 tRD3 tRD4 tRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay Timing2
10.9
Logic Module Sequential tSUD
Flip-Flop (Latch) Data Input Set-Up Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Flip-Flop (Latch) Clock Frequency 128)
10.4
tSUENA tHENA tWCLKA tWASYN fMAX
Notes: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Set-up times assume fanout Further testing information obtained from Timer utility. hold time DFME1A macro greater than Timer utility from Designer software check hold time this macro.
(continued)
(Wor erci ndit 4.75V, 70°C)
`-3' Speed Parameter Description Input Module Propagation Delays tINYH tINYL Pad-to-Y HIGH Pad-to-Y Delays1 12.4 Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Input Module Predicted Routing tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Global Clock Network tCKH tCKL tPWH tPWL tCKSW fMAX Input HIGH Input HIGH 10.1 10.4 10.4 10.4
Minimum Pulse Width HIGH Minimum Pulse Width Maximum Skew Minimum Period Maximum Frequency
Note: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance.
40MX 42MX FPGA Families
(continued)
(Wor erci ndit 4.75V, 70°C)
`-3' Speed Parameter Description Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable Delta HIGH Delta HIGH Timing1 0.03 0.02 0.04 0.02 10.4 0.04 0.03 12.2 0.05 0.03 10.5 17.1 12.6 0.07 0.04 ns/pF ns/pF 0.02 0.02 0.02 0.03 10.4 0.03 0.03 12.2 0.03 0.04 10.1 17.1 12.6 0.04 0.06 ns/pF ns/pF Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
CMOS Output Module tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL
Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable Delta HIGH Delta HIGH
Note: Delays based loading.
(Worst-Case Commercial Conditions, 3.0V, 70°C)
`-3' Speed Parameter Description Logic Module Propagation Delays tPD1 tPD2 Single Module Dual-Module Macros Sequential Clock-to-Q Latch G-to-Q Flip-Flop (Latch) Reset-to-Q
`-2' Speed Min. Max.
`-1' Speed Min. Max.
`Std' Speed Min. Max.
`-F' Speed Min. Max. Units
Min.
Max.
Logic Module Predicted Routing Delays tRD1 tRD2 tRD3 tRD4 tRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay Timing2
10.9
15.2
Logic Module Sequential tSUD
Flip-Flop (Latch) Data Input Set-Up Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Flip-Flop (Latch) Clock Frequency 128)
10.4
14.6
tSUENA tHENA tWCLKA tWASYN fMAX
Notes: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Set-up times assume fanout Further testing information obtained from Timer utility. hold time DFME1A macro greater than Timer tool from Designer software check hold time this macro.
40MX 42MX FPGA Families
(continued)
(Wor erci ndit 3.0V, 70°C)
`-3' Speed Parameter Description Input Module Propagation Delays tINYH tINYL Pad-to-Y HIGH Pad-to-Y Delays1 10.5 12.4 11.0 17.2 Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Input Module Predicted Routing tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Global Clock Network tCKH tCKL tPWH tPWL tCKSW fMAX Input HIGH Input HIGH Minimum Pulse Width HIGH Minimum Pulse Width Maximum Skew Minimum Period Maximum Frequency 10.1 10.4 14.1 14.6 10.4 10.4 13.8 13.8 14.6 14.6
Note: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance.
(continued)
(Wor erci ndit 3.0V, 70°C)
`-3' Speed Parameter Description Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable Delta HIGH Delta HIGH Timing1 11.1 0.05 0.03 12.8 0.05 0.03 14.5 10.7 0.06 0.04 10.5 17.1 12.6 0.07 0.04 11.9 10.2 10.2 14.7 23.9 17.7 0.10 0.06 ns/pF ns/pF 11.1 0.03 0.04 12.8 0.03 0.04 14.5 10.7 0.04 0.05 10.1 17.1 12.6 0.04 0.06 10.0 12.0 11.3 14.1 23.9 17.7 0.06 0.08 ns/pF ns/pF Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
CMOS Output Module tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL
Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable Delta HIGH Delta HIGH
Note: Delays based loading.
40MX 42MX FPGA Families
(Worst-Case Commercial Conditions, 4.75V, 70°C)
`-3' Speed Parameter Description Logic Module Propagation Delays1 tPD1 Single Module Sequential Clock-to-Q Latch G-to-Q Flip-Flop (Latch) Reset-to-Q Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Logic Module Predicted Routing Delays2 tRD1 tRD2 tRD3 tRD4 tRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Logic Module Sequential Timing tSUD tSUENA tHENA tWCLKA tWASYN tINH tINSU tOUTH tOUTSU fMAX
Flip-Flop (Latch) Data Input Set-Up Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Input Buffer Latch Hold Input Buffer Latch Set-Up Output Buffer Latch Hold Output Buffer Latch Set-Up Flip-Flop (Latch) Clock Frequency
Notes: dual-module macros, tPD1 tRD1 tPDn, tRD1 tPDn, tPD1 tRD1 tSUD, whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from Timer utility. Set-up hold timing parameters input buffer latch defined with respect input. External setup/hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time.
(continued)
(Worst-Case Commercial Conditions, 4.75V, 70°C)
`-3' Speed Parameter Description Input Module Propagation Delays tINYH tINYL tINGH tINGL Pad-to-Y HIGH Pad-to-Y HIGH Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Input Module Predicted Routing Delays1 tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT fMAX Input HIGH Input HIGH Minimum Pulse Width HIGH Minimum Pulse Width Maximum Skew Input Latch External Set-Up Input Latch External Hold Minimum Period Maximum Frequency
Note: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance.
40MX 42MX FPGA Families
(continued)
(Worst-Case Commercial Conditions, 4.75V, 70°C)
`-3' Speed Parameter Description Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLCO tACO dTLH dTHL Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable G-to-Pad HIGH G-to-Pad Latch Set-Up Latch Hold Latch Clock-to-Out (Pad-to-Pad), Clock Loading Array Clock-to-Out (Pad-to-Pad), Clock Loading Capacity Loading, HIGH Capacity Loading, HIGH
`-2' Speed Min. Max.
`-1' Speed Min. Max.
`Std' Speed Min. Max.
`-F' Speed Min. Max. Units
Min.
Max.
0.03 0.04
0.03 0.04
0.03 0.04
10.9 0.04 0.05
10.2 11.1
10.8 15.3 0.06 0.07
ns/pF ns/pF
CMOS Output Module Timing tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLCO tACO dTLH dTHL Data-to-Pad HIGH Data-to-Pad
0.03 0.04
0.03 0.04
0.03 0.04
10.9 0.04 0.05
10.2 11.1
Enable HIGH Enable Enable HIGH Enable G-to-Pad HIGH G-to-Pad Latch Set-Up Latch Hold Latch Clock-to-Out (Pad-to-Pad), Clock Loading Array Clock-to-Out (Pad-to-Pad), Clock Loading Capacity Loading, HIGH Capacity Loading, HIGH
10.8 15.3 0.06 0.07
ns/pF ns/pF
Note: Delays based loading.
(Wor erci ndit
`-3' Speed Parameter Description Logic Module Propagation Delays tPD1 Single Module Sequential Clock-to-Q Latch G-to-Q Flip-Flop (Latch) Reset-to-Q Delays2
`-2' Speed Min. Max.
`-1' Speed Min. Max.
`Std' Speed Min. Max.
`-F' Speed Min. Max. Units
Min.
Max.
Logic Module Predicted Routing tRD1 tRD2 tRD3 tRD4 tRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Logic Module Sequential Timing tSUD tSUENA tHENA tWCLKA tWASYN tINH tINSU tOUTH tOUTSU fMAX Flip-Flop (Latch) Data Input Set-Up Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Input Buffer Latch Hold Input Buffer Latch Set-Up Output Buffer Latch Hold Output Buffer Latch Set-Up Flip-Flop (Latch) Clock Frequency 12.9
Notes: dual-module macros, tPD1 tRD1 tPDn, tRD1 tPDn, tPD1 tRD1 tSUD, whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from Timer utility. Set-up hold timing parameters input buffer latch defined with respect input. External setup/hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time.
40MX 42MX FPGA Families
(continued)
(Worst-Case Commercial Conditions, 3.0V, 70°C)
`-3' Speed Parameter Description Input Module Propagation Delays tINYH tINYL tINGH tINGL Pad-to-Y HIGH Pad-to-Y HIGH 2.17 Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Input Module Predicted Routing Delays1 tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 10.8
Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT fMAX Input HIGH Input HIGH Minimum Pulse Width HIGH Minimum Pulse Width Maximum Skew Input Latch External Set-Up Input Latch External Hold Minimum Period Maximum Frequency 12.9 14.2 10.2 11.2
Note: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance.
(continued)
(Worst-Case Commercial Conditions, 3.0V, 70°C)
`-3' Speed Parameter Description Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLCO tACO dTLH dTHL Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable G-to-Pad HIGH G-to-Pad Latch Set-Up Latch Hold Latch Clock-to-Out (Pad-to-Pad), Clock Loading Array Clock-to-Out (Pad-to-Pad), Clock Loading Capacity Loading, HIGH Capacity Loading, HIGH
`-2' Speed Min. Max.
`-1' Speed Min. Max.
`Std' Speed Min. Max.
`-F' Speed Min. Max. Units
Min.
Max.
12.2 0.00 0.09
13.5 0.00 0.10
10.9 15.4 0.00 0.10
10.2 11.1 12.9 18.1 0.10 0.10
14.2 15.5 12.0 12.0
18.0 25.3 0.01 0.10
ns/pF ns/pF
CMOS Output Module Timing tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLCO tACO dTLH dTHL Data-to-Pad HIGH Data-to-Pad
12.2 0.04 0.05
13.5 0.04 0.05
10.9 15.4 0.05 0.06
10.2 11.1 12.9 18.1 0.06 0.07
14.2 15.5 12.0 12.0
Enable HIGH Enable Enable HIGH Enable G-to-Pad HIGH G-to-Pad Latch Set-Up Latch Hold Latch Clock-to-Out (Pad-to-Pad), Clock Loading Array Clock-to-Out (Pad-to-Pad), Clock Loading Capacity Loading, HIGH Capacity Loading, HIGH
18.0 25.3 0.08 0.10
ns/pF ns/pF
Note: Delays based loading.
40MX 42MX FPGA Families
(Wor erci ndit 75V,
`-3' Speed Parameter Description Logic Module Propagation Delays tPD1 Single Module Sequential Clock-to-Q Latch G-to-Q Flip-Flop (Latch) Reset-to-Q Delays2
`-2' Speed Min. Max.
`-1' Speed Min. Max.
`Std' Speed Min. Max.
`-F' Speed Min. Max. Units
Min.
Max.
Logic Module Predicted Routing tRD1 tRD2 tRD3 tRD4 tRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Logic Module Sequential Timing3,4 tSUD tSUENA tHENA tWCLKA tWASYN tINH tINSU tOUTH tOUTSU fMAX Flip-Flop (Latch) Data Input Set-Up Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Input Buffer Latch Hold Input Buffer Latch Set-Up Output Buffer Latch Hold Output Buffer Latch Set-Up Flip-Flop (Latch) Clock Frequency 10.1 14.1
Notes: dual-module macros, tPD1 tRD1 tPDn, tRD1 tPDn, tPD1 tRD1 tSUD, point position whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from Timer utility. Set-up hold timing parameters input buffer latch defined with respect input. External setup/hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time.
(continued)
(Worst-Case Commercial Conditions, 4.75V, 70°C)
`-3' Speed Parameter Description Input Module Propagation Delays tINYH tINYL tINGH tINGL Pad-to-Y HIGH Pad-to-Y HIGH Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Input Module Predicted Routing Delays1 tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT fMAX Input HIGH Input HIGH Minimum Pulse Width HIGH 4.67 10.7
Minimum Pulse Width Maximum Skew
Input Latch External Set-Up Input Latch External Hold Minimum Period Maximum Frequency
Note: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance.
40MX 42MX FPGA Families
(continued)
(Worst-Case Commercial Conditions, 4.75V, 70°C)
`-3' Speed Parameter Description Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLCO tACO dTLH dTHL Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable G-to-Pad HIGH G-to-Pad Latch Clock-to-Out (Pad-to-Pad), Clock Loading Array Clock-to-Out (Pad-to-Pad), Clock Loading Capacitive Loading, HIGH Capacitive Loading, HIGH 0.03 0.04 0.03 0.04 10.1 0.03 0.04 11.9 0.04 0.05 11.2 10.4 11.9 16.7 0.06 0.07 ns/pF ns/pF Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
CMOS Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLCO tACO dTLH dTHL Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable G-to-Pad HIGH G-to-Pad Latch Clock-to-Out (Pad-to-Pad), Clock Loading Array Clock-to-Out (Pad-to-Pad), Clock Loading Capacitive Loading, HIGH Capacitive Loading, HIGH 0.03 0.04 0.03 0.04 10.1 0.03 0.04 11.9 0.04 0.05 11.2 10.4 10.5 10.5 11.9 16.7 0.06 0.07 ns/pF ns/pF
Note: Delays based loading.
(Wor erci ndit
`-3' Speed Parameter Description Logic Module Propagation Delays tPD1 Single Module Sequential Clock-to-Q Latch G-to-Q Flip-Flop (Latch) Reset-to-Q Delays2
`-2' Speed Min. Max.
`-1' Speed Min. Max.
`Std' Speed Min. Max.
`-F' Speed Min. Max. Units
Min.
Max.
Logic Module Predicted Routing tRD1 tRD2 tRD3 tRD4 tRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Logic Module Sequential Timing3, tSUD tSUENA tHENA tWCLKA tWASYN tINH tINSU tOUTH tOUTSU fMAX Flip-Flop (Latch) Data Input Set-Up Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Input Buffer Latch Hold Input Buffer Latch Set-Up Output Buffer Latch Hold Output Buffer Latch Set-Up Flip-Flop (Latch) Clock Frequency 10.6 12.0 0.89 14.1 1.01 1.01 12.9 19.8
Notes: dual-module macros tPD1 tRD1 taped, tRD1 taped, tPD1 tRD1 tusk, whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from Timer utility. Set-up hold timing parameters input buffer latch defined with respect input. External setup/hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time.
40MX 42MX FPGA Families
(continued)
(Worst-Case Commercial Conditions, 3.0V, 70°C)
`-3' Speed Parameter Description Input Module Propagation Delays tINYH tINYL tINGH tINGL Pad-to-Y HIGH Pad-to-Y HIGH Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Input Module Predicted Routing Delays1 tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 10.5
Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT fMAX Input HIGH Input HIGH Minimum Pulse Width HIGH Minimum Pulse Width Maximum Skew Input Latch External Set-Up 10.7 16.2 17.8 11.8 13.7 11.0 12.9 11.0 12.9
Input Latch External Hold Minimum Period Maximum Frequency
Note: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance.
(continued)
(Worst-Case Commercial Conditions, 3.0V, 70°C)
`-3' Speed Parameter Description Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLCO tACO dTLH dTHL Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable G-to-Pad HIGH G-to-Pad Latch Clock-to-Out (Pad-to-Pad), Clock Loading Array Clock-to-Out (Pad-to-Pad), Clock Loading Capacitive Loading, HIGH Capacitive Loading, HIGH 10.1 14.2 0.05 0.06 11.2 10.4 11.9 16.7 0.06 0.07 15.7 14.5 10.0 10.0 16.7 23.3 0.08 0.10 ns/pF ns/pF Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
11.3 0.04 0.05
12.5 0.04 0.05
CMOS Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLCO tACO dTLH dTHL Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable G-to-Pad HIGH G-to-Pad Latch Clock-to-Out (Pad-to-Pad), Clock Loading Array Clock-to-Out (Pad-to-Pad), Clock Loading Capacitive Loading, HIGH Capacitive Loading, HIGH 11.3 0.04 0.05 12.5 0.04 0.05 10.1 14.2 0.05 0.06 11.2 10.4 10.5 10.5 11.9 16.7 0.06 0.07 15.7 14.5 14.7 14.7 16.7 23.3 0.08 0.10 ns/pF ns/pF
Note: Delays based loading.
40MX 42MX FPGA Families
(Wor erci ndit 75V,
`-3' Speed Parameter Description Logic Module Combinatorial Functions tPDD Internal Array Module Delay Internal Decode Module Delay
`-2'Speed Min. Max.
`-1' Speed Min. Max.
`Std' Speed Min. Max.
`-F' Speed Min. Max. Units
Min.
Max.
Logic Module Predicted Routing Delays2 tRD1 tRD2 tRD3 tRD4 tRD5 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Logic Module Sequential Timing tSUD tSUENA tHENA tWCLKA tWASYN
Flip-Flop Clock-to-Output Latch Gate-to-Output Flip-Flop (Latch) Set-Up Time Flip-Flop (Latch) Hold Time Flip-Flop (Latch) Reset-to-Output Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width
Notes: dual-module macros, tPD1 tRD1 tPDn, tRD1 tPDn, tPD1 tRD1 tSUD, whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from Timer utility. Set-up hold timing parameters Input Buffer Latch defined with respect input. External setup/hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time.
A42MX24 Timing Characteristics (Nominal 5.0V Operation) (continued)
(Worst-Case Commercial Conditions, 4.75V, 70°C)
`-3' Speed Parameter Description Input Module Propagation Delays tINPY tINGO tINH tINSU tILA Input Data Pad-to-Y Input Latch Gate-to-Output Input Latch Hold Input Latch Set-Up Latch Active Pulse Width Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Input Module Predicted Routing Delays1 tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT fMAX Input HIGH Input HIGH FO=32 FO=486 FO=32 FO=486 10.9 11.9
Minimum Pulse Width HIGH FO=32 FO=486 Minimum Pulse Width FO=32 FO=486 Maximum Skew FO=32 FO=486
Input Latch External Set-Up FO=32 FO=486 Input Latch External Hold Minimum Period (1/fMAX) Maximum Datapath Frequency FO=32 FO=486 FO=32 FO=486 FO=32 FO=486
Note: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance.
40MX 42MX FPGA Families
A42MX24 Timing Characteristics (Nominal 5.0V Operation) (continued)
(Worst-Case Commercial Conditions, 4.75V, 70°C)
`-3' Speed Parameter Description Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLCO tACO Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable G-to-Pad HIGH G-to-Pad Latch Output Set-Up Latch Output Hold Latch Clock-to-Out (Pad-to-Pad) Array Latch Clock-to-Out (Pad-to-Pad) Capacitive Loading, HIGH Capacitive Loading, HIGH 11.4 10.7 Min. Max. `-2'Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
10.6 0.04 0.03
11.8 0.04 0.03
13.4 0.04 0.03
15.7 0.05 0.04
22.0 0.07 0.06
ns/pF ns/pF
dTLH dTHL
CMOS Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLCO tACO Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable G-to-Pad HIGH G-to-Pad Latch Set-Up Latch Hold Latch Clock-to-Out (Pad-to-Pad) Array Latch Clock-to-Out (Pad-to-Pad) Capacitive Loading, HIGH Capacitive Loading, HIGH 11.3 10.7 10.1 10.1
10.6 0.04 0.03
11.8 0.04 0.03
13.4 0.04 0.03
15.7 0.05 0.04
22.0 0.07 0.06
ns/pF ns/pF
dTLH dTHL
Note: Delays based loading.
(Wor erci ndit
`-3' Speed Parameter Description Logic Module Combinatorial Functions tPDD Internal Array Module Delay Internal Decode Module Delay
`-2'Speed Min. Max.
`-1' Speed Min. Max.
`Std' Speed Min. Max.
`-F' Speed Min. Max. Units
Min.
Max.
Logic Module Predicted Routing Delays2 tRD1 tRD2 tRD3 tRD4 tRD5 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Logic Module Sequential Timing tSUD tSUENA tHENA tWCLKA tWASYN
Flip-Flop Clock-to-Output Latch Gate-to-Output Flip-Flop (Latch) Set-Up Time Flip-Flop (Latch) Hold Time Flip-Flop (Latch) Reset-to-Output Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width
12.6
Notes: dual-module macros, tPD1 tRD1 tPDn, tRD1 tPDn, tPD1 tRD1 tSUD, whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from Timer utility. Set-up hold timing parameters Input Buffer Latch defined with respect input. External setup/hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time.
40MX 42MX FPGA Families
A42MX24 Timing Characteristics (Nominal 3.3V Operation) (continued)
(Worst-Case Commercial Conditions, 3.0V, 70°C)
`-3' Speed Parameter Description Input Module Propagation Delays tINPY tINGO tINH tINSU tILA Input Data Pad-to-Y Input Latch Gate-to-Output Input Latch Hold Input Latch Set-Up Latch Active Pulse Width 13.5 Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Input Module Predicted Routing Delays1 tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 10.0
Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT fMAX Input HIGH Input HIGH FO=32 FO=486 FO=32 FO=486 10.4 10.8 11.9 18.2 19.9 10.0 10.6 12.4
Minimum Pulse Width HIGH FO=32 FO=486 Minimum Pulse Width FO=32 FO=486 Maximum Skew FO=32 FO=486
Input Latch External Set-Up FO=32 FO=486 Input Latch External Hold Minimum Period (1/fMAX) Maximum Datapath Frequency FO=32 FO=486 FO=32 FO=486 FO=32 FO=486
Note: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance.
A42MX24 Timing Characteristics (Nominal 3.3V Operation) (continued)
(Worst-Case Commercial Conditions, 3.0V, 70°C)
Speed Parameter Description Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLCO Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable G-to-Pad HIGH G-to-Pad Latch Output Set-Up Latch Output Hold Latch Clock-to-Out (Pad-to-Pad) Array Latch Clock-to-Out (Pad-to-Pad) Capacitive Loading, HIGH Capacitive Loading, HIGH 11.3 10.7 15.9 14.9 13.9 10.0 10.0 Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
tACO
14.8 0.05 0.04
16.5 0.05 0.04
18.7 0.06 0.05
22.0 0.07 0.06
30.8 0.10 0.08
ns/pF ns/pF
dTLH dTHL
CMOS Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLCO Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable G-to-Pad HIGH G-to-Pad Latch Set-Up Latch Hold Latch Clock-to-Out (Pad-to-Pad) Array Latch Clock-to-Out (Pad-to-Pad) Capacitive Loading, HIGH Capacitive Loading, HIGH 11.3 10.7 10.1 10.1 15.9 14.9 13.9 14.2 14.2
tACO
14.8 0.05 0.04
16.5 0.05 0.04
18.7 0.06 0.05
22.0 0.07 0.06
30.8 0.10 0.08
ns/pF ns/pF
dTLH dTHL
Note: Delays based loading.
40MX 42MX FPGA Families
(Wor erci ndit 75V,
`-3' Speed Parameter Description Logic Module Combinatorial Functions tPDD Internal Array Module Delay Internal Decode Module Delay
`-2' Speed Min. Max.
`-1' Speed Min. Max.
`Std' Speed Min. Max.
`-F' Speed Min. Max. Units
Min.
Max.
Logic Module Predicted Routing Delays2 tRD1 tRD2 tRD3 tRD4 tRD5 tRDD FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay Decode-to-Output Routing Delay
Logic Module Sequential Timing tSUD tSUENA tHENA tWCLKA tWASYN
Flip-Flop Clock-to-Output Latch Gate-to-Output Flip-Flop (Latch) Set-Up Time Flip-Flop (Latch) Hold Time Flip-Flop (Latch) Reset-to-Output Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width
Notes: dual-module macros, tPD1 tRD1 tPDn, tRD1 tPDn, tPD1 tRD1 tSUD, whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from Timer utility. Set-up hold timing parameters Input Buffer Latch defined with respect input. External setup/hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time.
(continued)
(Worst-Case Commercial Conditions, 4.75V, 70°C)
Logic Module Timing Parameter Description Synchronous SRAM Operations tRCKHL tRCO tADSU tADH tRENSU tRENH tWENSU tWENH tBENS tBENH Read Cycle Time Write Cycle Time Clock HIGH/LOW Time Data Valid After Clock HIGH/LOW Address/Data Set-Up Time Address/Data Hold Time Read Enable Set-Up Read Enable Hold Write Enable Set-Up Write Enable Hold Block Enable Set-Up Block Enable Hold 10.0 10.0 14.0 14.0 `-3' Speed Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Asynchronous SRAM Operations tRPD tRDADV tADSU tADH tRENSUA tRENHA tWENSU tWENH tDOH Asynchronous Access Time Read Address Valid Address/Data Set-Up Time Address/Data Hold Time Read Enable Set-Up Address Valid Read Enable Hold Write Enable Set-Up Write Enable Hold Data Hold Time 11.1 10.2 13.0 12.0 18.2 16.8
40MX 42MX FPGA Families
(continued)
(Worst-Case Commercial Conditions, 4.75V, 70°C)
`-3' Speed Parameter Description Input Module Propagation Delays tINPY tINGO tINH tINSU tILA Input Data Pad-to-Y Input Latch Gate-to-Output Input Latch Hold Input Latch Set-Up Latch Active Pulse Width Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Input Module Predicted Routing Delays1 tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT fMAX Input HIGH Input HIGH FO=32 FO=635 FO=32 FO=635 12.7 13.8 10.1
Minimum Pulse Width HIGH FO=32 FO=635 Minimum Pulse Width FO=32 FO=635 Maximum Skew FO=32 FO=635
Input Latch External Set-Up FO=32 FO=635 Input Latch External Hold Minimum Period (1/fMAX) Maximum Datapath Frequency FO=32 FO=635 FO=32 FO=635 FO=32 FO=635
Note: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance.
(continued)
(Worst-Case Commercial Conditions, 4.75V, 70°C)
`-3' Speed Parameter Description Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLCO Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable G-to-Pad HIGH G-to-Pad Latch Output Set-Up Latch Output Hold Latch Clock-to-Out (Pad-to-Pad) Array Latch Clock-to-Out (Pad-to-Pad) Capacitive Loading, HIGH Capacitive Loading, HIGH 11.8 10.9 10.2 Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
tACO
0.07 0.07
0.08 0.08
0.09 0.09
11.5 0.10 0.10
16.1 0.14 0.14
ns/pF ns/pF
dTLH dTHL
CMOS Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLCO Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable G-to-Pad HIGH G-to-Pad Latch Set-Up Latch Hold Latch Clock-to-Out (Pad-to-Pad) Array Latch Clock-to-Out (Pad-to-Pad) Capacitive Loading, HIGH Capacitive Loading, HIGH 11.8 10.9 10.2 10.4 10.4
tACO
0.07 0.07
0.08 0.08
0.09 0.09
11.5 0.10 0.10
16.1 0.14 0.14
ns/pF ns/pF
dTLH dTHL
Note: Delays based loading.
40MX 42MX FPGA Families
(Wor erci ndit
`-3' Speed Parameter Description Logic Module Combinatorial Functions tPDD Internal Array Module Delay Internal Decode Module Delay
`-2' Speed Min. Max.
`-1' Speed Min. Max.
`Std' Speed Min. Max.
`-F' Speed Min. Max. Units
Min.
Max.
Logic Module Predicted Routing Delays2 tRD1 tRD2 tRD3 tRD4 tRD5 tRDD FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay Decode-to-Output Routing Delay
Logic Module Sequential Timing tSUD tSUENA tHENA tWCLKA tWASYN
Flip-Flop Clock-to-Output Latch Gate-to-Output Flip-Flop (Latch) Set-Up Time Flip-Flop (Latch) Hold Time Flip-Flop (Latch) Reset-to-Output Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width
12.6
Notes: dual-module macros, tPD1 tRD1 tPDn, tRD1 tPDn, tPD1 tRD1 tSUD, whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from Timer utility. Set-up hold timing parameters Input Buffer Latch defined with respect input. External setup/hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time.
(continued)
(Worst-Case Commercial Conditions, 3.0V, 70°C)
Logic Module Timing Parameter Description Synchronous SRAM Operations tRCKHL tRCO tADSU tADH tRENSU tRENH tWENSU tWENH tBENS tBENH Read Cycle Time Write Cycle Time Clock HIGH/LOW Time Data Valid After Clock HIGH/LOW Address/Data Set-Up Time Address/Data Hold Time Read Enable Set-Up Read Enable Hold Write Enable Set-Up Write Enable Hold Block Enable Set-Up Block Enable Hold 10.5 10.5 11.9 11.9 14.0 14.0 19.6 19.6 `-3' Speed Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Asynchronous SRAM Operations tRPD tRDADV tADSU tADH tRENSUA tRENHA tWENSU tWENH tDOH Asynchronous Access Time Read Address Valid Address/Data Set-Up Time Address/Data Hold Time Read Enable Set-Up Address Valid Read Enable Hold Write Enable Set-Up Write Enable Hold Data Hold Time 12.3 11.3 13.7 12.6 15.5 14.3 18.2 16.8 25.5 23.5
40MX 42MX FPGA Families
(continued)
(Worst-Case Commercial Conditions, 3.0V, 70°C)
`-3' Speed Parameter Description Input Module Propagation Delays tINPY tINGO tINH tINSU tILA Input Data Pad-to-Y Input Latch Gate-to-Output Input Latch Hold Input Latch Set-Up Latch Active Pulse Width 13.5 Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
Input Module Predicted Routing Delays1 tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 12.6
Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT fMAX Input HIGH Input HIGH FO=32 FO=635 FO=32 FO=635 10.2 11.0 11.1 12.0 12.7 13.8 21.2 23.0 10.1 10.3 11.0 14.1
Minimum Pulse Width HIGH FO=32 FO=635 Minimum Pulse Width FO=32 FO=635 Maximum Skew FO=32 FO=635
Input Latch External Set-Up FO=32 FO=635 Input Latch External Hold Minimum Period (1/fMAX) Maximum Datapath Frequency FO=32 FO=635 FO=32 FO=635 FO=32 FO=635
Note: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance.
(continued)
(Worst-Case Commercial Conditions, 3.0V, 70°C)
`-3' Speed Parameter Description Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLCO Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable G-to-Pad HIGH G-to-Pad Latch Output Set-Up Latch Output Hold Latch Clock-to-Out (Pad-to-Pad) Array Latch Clock-to-Out (Pad-to-Pad) Capacitive Loading, HIGH Capacitive Loading, HIGH 7.34 10.0 11.8 10.9 10.2 16.5 15.3 14.3 10.2 10.2 Min. Max. `-2' Speed Min. Max. `-1' Speed Min. Max. `Std' Speed Min. Max. `-F' Speed Min. Max. Units
tACO
10.9 0.10 0.10
12.1 0.11 0.11
13.7 0.12 0.12
16.1 0.14 0.14
22.5 0.20 0.20
ns/pF ns/pF
dTLH dTHL
CMOS Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLCO Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable G-to-Pad HIGH G-to-Pad Latch Set-Up Latch Hold Latch Clock-to-Out (Pad-to-Pad) Array Latch Clock-to-Out (Pad-to-Pad) Capacitive Loading, HIGH Capacitive Loading, HIGH 10.0 11.8 10.9 10.2 10.4 10.4 16.5 10.3 15.3 14.3 14.6 14.6
tACO
10.9 0.10 0.10
12.1 0.11 0.11
13.7 0.12 0.12
16.1 0.14 0.14
22.5 0.20 0.20
ns/pF ns/pF
dTLH dTHL
Note: Delays based loading.
40MX 42MX FPGA Families
CLK/A/B, Global Clock
Clock inputs clock distribution networks. 40MX while CLKA CLKB 42MX devices. clock input buffered prior clocking logic modules. This also used I/O.
DCLK, Diagnostic Clock
PRA, PRB,
Probe
Clock input diagnostic probe device programming. DCLK active when MODE HIGH. This functions when MODE LOW.
Ground
Input supply voltage.
Input/Output
Probe used output data from user-defined design node within device. Each diagnostic used conjunction with other probe allow real-time diagnostic output signal path within device. Probe used user-defined when verification been completed. pin's probe capabilities permanently disabled protect programmed design confidentiality. Probe accessible when MODE HIGH. This functions when MODE LOW.
QCLKA/B/C/D, Quadrant Clock
Input, output, tristate bi-directional buffer. Input output levels compatible with standard CMOS specifications. Unused I/Os pins configured Designer software shown Table Table Configuration Unused I/Os
Device A40MX02, A40MX04 A42MX09, A42MX16 A42MX24, A42MX36 Configuration Pulled Pulled Tristated
Quadrant clock inputs A42MX36 devices. When used register control signal, these pins function user I/Os.
SDI, Serial Data Input
Serial data input diagnostic probe device programming. active when MODE HIGH. This functions when MODE LOW.
SDO, Serial Data Output
cases, recommended unused pins board. This applies dual-purpose pins when configured I/Os well.
Power Mode
Serial data output diagnostic probe device programming. active when MODE HIGH. This functions when MODE LOW. available 42MX devices only. When Silicon Explorer being used, will output while "checksum" command run. will return user when "checksum" complete.
TCK, Test Clock
Controls power mode 42MX devices. device placed power mode connecting logic HIGH. power mode, I/Os tristated, input buffers turned OFF, core device turned OFF. exit power mode, must LOW. device enters power mode 800ns after driven logic HIGH. will resume normal operation 200µs after driven logic LOW.
MODE Mode
Clock signal shift Boundary Scan Test (BST) data into device. This functions when "Reserve JTAG" checked Designer Software. pins only available A42MX24 A42MX36 devices.
TDI, Test Data
Controls multifunction pins (DCLK, PRA, PRB, SDI, TDO). MODE held HIGH provide verification capability. MODE should terminated through resistor that MODE pulled HIGH when required.
Connection
Serial data input instructions data. Data shifted rising edge TCK. This functions when "Reserve JTAG" checked Designer Software. pins only available A42MX24 A42MX36 devices.
TDO, Test Data
This connected circuitry within device. These pins driven voltage left floating with effect operation device.
Serial data output instructions test data. This functions when "Reserve JTAG" checked Designer Software. pins only available A42MX24 A42MX36 devices.
TMS,
Test Mode Select
Supply Voltage
controls IEEE 1149.1 Boundary Scan pins (TCK, TDI, TDO). flexible mode when LOW, TCK, pins boundary scan pins. Once boundary scan pins test mode, they will remain that mode until internal boundary scan state machine reaches "logic reset" state. this point, boundary scan pins will released will function regular pins. "logic reset" state reached cycles after HIGH. dedicated test mode, functions specified IEEE 1149.1 specifications. IEEE JTAG specification recommends pull-up resistor pin. pins only available A42MX24 A42MX36 devices.
Supply Voltage
Supply voltage I/Os 42MX devices
Wide Decode Output
When wide decode module used 42MX device this used dedicated output from wide decode module. This direct connection eliminates additional interconnect delays associated with regular logic modules. implement direct connection, connect output buffer type output wide decode macro place this output reserved pins.
Input supply voltage 40MX devices
Supply Voltage
Supply voltage array 42MX devices
44-Pin PLCC
44-Pin PLCC
Number
A40MX02 Function
A40MX04 Function
Number
A40MX02 Function CLK, MODE SDI, DCLK, PRA, PRB,
A40MX04 Function CLK, MODE SDI, DCLK, PRA, PRB,
68-Pin PLCC
68-Pin PLCC
Number
A40MX02 Function
A40MX04 Function
Number
A40MX02 Function
A40MX04 Function
Number
A40MX02 Function CLK, MODE SDI, DCLK, PRA, PRB,
A40MX04 Function CLK, MODE SDI, DCLK, PRA, PRB,
(continued)
84-Pin PLCC
84-Pin PLCC
A40MX04 A42MX09 A42MX16 A42MX24 Number Function Function Function Function PRB, MODE VCCA VCCI PRB, MODE VCCI VCCA PRB, MODE VCCI VCCA TMS, TDI,
A40MX04 A42MX09 A42MX16 Number Function Function Function CLK, MODE SDI, DCLK, PRA, PRB, VCCA SDO, VCCA VCCI SDI, PRA, VCCA VCCA SDO, VCCA VCCI SDI, PRA, VCCA
A42MX24 Function VCCA SDO, TDO, TCK, VCCA VCCI SDI, PRA, CLKA, VCCA
CLKB, CLKB, CLKB,
DCLK, DCLK, DCLK,
CLKA, CLKA,
(continued)
100-Pin PQFP Package (Top View)
100-Pin PQFP
100-
Number
A40MX02 A40MX04 A42MX09 A42MX16 Function Function Function Function PRB, PRB,
Number
A40MX02 A40MX04 A42MX09 A42MX16 Function Function Function Function VCCA SDO, VCCA VCCI VCCA VCCA SDO, VCCA VCCI VCCA
DCLK, DCLK, MODE VCCA VCCI MODE VCCA VCCA
100-
Number
A40MX02 A40MX04 A42MX09 A42MX16 Function Function Function Function SDI, PRA, SDI, PRA,
Number
A40MX02 A40MX04 A42MX09 A42MX16 Function Function Function Function CLK, MODE SDI, CLK, MODE SDI, VCCA VCCA
CLKB, CLKB, PRB, PRB,
DCLK, DCLK, PRA, PRA,
CLKA, CLKA,
(continued)
160-Pin PQFP Package (Top View)
160-Pin PQFP
160-
Number
A42MX09 Function DCLK, PRB, CLKB, VCCA CLKA, PRA, SDI,
A42MX16 Function DCLK, VCCI PRB, CLKB, VCCA CLKA, PRA, VCCI SDI,
A42MX24 Function DCLK, VCCI PRB, CLKB, VCCA CLKA, PRA, VCCI SDI,
Number
A42MX09 Function VCCA VCCI VCCA
A42MX16 Function VCCA VCCA VCCI VCCA
A42MX24 Function VCCA VCCA VCCI VCCA TCK,
160-
Number
A42MX09 Function SDO, VCCA
A42MX16 Function SDO, VCCI VCCA VCCI
A42MX24 Function SDO, TDO, VCCI VCCA VCCI TDI, TMS,
Number
A42MX09 Function VCCI MODE
A42MX16 Function VCCA VCCA VCCI VCCA MODE
A42MX24 Function VCCA VCCA VCCI VCCA MODE
(continued)
208-Pin PQFP Package (Top View)
208-Pin PQFP
208-
Number
A42MX16 Function MODE VCCA VCCI VCCA VCCA
A42MX24 Function VCCA MODE VCCA VCCI VCCA VCCA
A42MX36 Function VCCA MODE VCCA VCCI VCCA VCCA
Number
A42MX16 Function VCCI VCCA
A42MX24 Function TMS, TDI, VCCI VCCA VCCI
A42MX36 Function TMS, TDI, VCCI QCLKA, VCCA VCCI
208-
Number
A42MX16 Function VCCI SDO,
A42MX24 Function VCCI VCCA
A42MX36 Function QCLKB, VCCI VCCA
Number
A42MX16 Function VCCA VCCI VCCA VCCA SDI, VCCI
A42MX24 Function TCK, VCCA VCCI VCCA VCCA SDI, VCCI
A42MX36 Function TCK, VCCA VCCI VCCA VCCA SDI, VCCI
SDO, TDO, SDO, TDO,
208-
Number
A42MX16 Function PRA, CLKA, VCCA CLKB, PRB,
A42MX24 Function PRA, CLKA, VCCI VCCA CLKB, PRB,
A42MX36 Function QCLKD, PRA, CLKA, VCCI VCCA CLKB, PRB,
Number
A42MX16 Function VCCI DCLK,
A42MX24 Function VCCI DCLK,
A42MX36 Function QCLKC, VCCI DCLK,
(continued)
240-Pin PQFP Package (Top View)
240-Pin PQFP
240-
Number
A42MX36 Function DCLK, VCCI QCLKC, PRB, CLKB, VCCA VCCI CLKA, PRA,
Number
A42MX36 Function QCLKD, VCCI SDI, VCCA VCCI
Number
A42MX36 Function VCCA VCCA VCCI VCCA TCK, VCCI VCCA
Number
A42MX36 Function SDO, TDO, VCCI QCLKB, VCCI VCCA
240-
Number
A42MX36 Function QCLKA, VCCI TDI, TMS,
Number
A42MX36 Function VCCA VCCI
Number
A42MX36 Function VCCA VCCA VCCI VCCA
Number
A42MX36 Function VCCI MODE VCCA
(continued)
80-Pin VQFP
80-Pin VQFP
VQFP
Number
A40MX02 Function
A40MX04 Function
Number
A40MX02 Function CLK, MODE SDI, DCLK, PRA, PRB,
A40MX04 Function CLK, MODE SDI, DCLK, PRA, PRB,
(continued)
100- ackag
100-Pin VQFP
100-Pin VQFP Package
Number
A42MX09 Function MODE VCCA VCCI VCCA SDO,
A42MX16 Function MODE VCCI VCCA SDO,
Number
A42MX09 Function VCCA VCCI VCCA SDI, PRA, CLKA, VCCA CLKB, PRB, DCLK,
A42MX16 Function VCCA VCCI VCCA SDI, PRA, CLKA, VCCA CLKB, PRB, DCLK,
(continued)
176-Pin TQFP Package (Top View)
176-Pin TQFP
176-
Number
A42MX09 Function MODE VCCA VCCI
A42MX16 Function MODE VCCA VCCI VCCA VCCA
A42MX24 Function MODE VCCA VCCI VCCA VCCA
Number
A42MX09 Function VCCA SDO,
A42MX16 Function VCCI VCCA VCCI SDO,
A42MX24 Function TMS, TDI, VCCI VCCA VCCI SDO, TDO,
176-
Number
A42MX09 Function VCCA VCCI VCCA
A42MX16 Function VCCA VCCI VCCA VCCA
A42MX24 Function TCK, VCCA VCCI VCCA VCCA
Number
A42MX09 Function SDI, PRA, CLKA, VCCA CLKB, PRB, DCLK,
A42MX16 Function SDI, VCCI PRA, CLKA, VCCA CLKB, PRB, VCCI DCLK,
A42MX24 Function SDI, VCCI PRA, CLKA, VCCA CLKB, PRB, VCCI DCLK,
208-Pin CQFP (Top View)
Index
A42MX36 208-Pin CQFP
208-Pin CQFP
Number
A42MX36 Function VCCA MODE VCCA VCCI VCCA VCCA
Number
A42MX36 Function TMS, TDI, VCCI QCLKA,
Number
A42MX36 Function VCCA VCCI QCLKB, VCCI TDO, VCCA
Number
A42MX36 Function TCK, VCCA VCCI VCCA VCCA
208-Pin CQFP (Continued)
Number
A42MX36 Function SDI, VCCI
Number
A42MX36 Function QCLKD, PRA, CLKA, VCCI
Number
A42MX36 Function VCCA CLKB, PRB,
Number
A42MX36 Function QCLKC, VCCI DCLK,
(continued)
256-Pin CQFP (Top View)
Index
A42MX36 256-Pin CQFP
256-Pin CQFP
Number
A42MX36 Function VCCA VCCA VCCI VCCA TCK,
Number
A42MX36 Function VCCA SDO, TDO, VCCI QCLKB,
Number
A42MX36 Function VCCI VCCA QCLKA, VCCI
Number
A42MX36 Function VCCA VCCA VCCI VCCA
256-Pin CQFP (Continued)
Number
A42MX36 Function MODE VCCA
Number
A42MX36 Function DCLK, VCCI QCLKC,
Number
A42MX36 Function PRB, CLKB, VCCA VCCI CLKA, PRA,
Number
A42MX36 Function QCLKD, VCCI SDI,
(continued)
272-
272-Pin PBGA
272-Pin PBGA
Number
A42MX36 Function CLKA DCLK, PRB, MODE
Ball
A42MX36 Function QCLKC, CLKB PRA, QCLKD, SDI, VCCI VCCA VCCI VCCI VCCI VCCA VCCA VCCI
Ball
A42MX36 Function VCCI VCCI VCCI VCCA VCCI VCCA VCCI
Ball
A42MX36 Function VCCA VCCA VCCA VCCA VCCI TCK, VCCI VCCI VCCI VCCA
272-Pin PBGA (Continued)
Number
A42MX36 Function VCCI VCCI VCCA VCCI
Ball
A42MX36 Function VCCA VCCI QCLKB, VCCI
Ball
A42MX36 Function SDO, TDO, TMS,
Ball
A42MX36 Function TDI, QCLKA,
following table lists critical changes that were made current version document.
Previous version Changes current version (v6.0) "Ease Integration" section page updated. "Temperature Grade Offerings" table page new. "Speed Grade Offerings" table page new. "General Description" section page updated. "MultiPlex Modules" section page updated. "User Security" section page updated. Table page updated. "Power Dissipation" section page updated. "Static Power Component" section page updated. "Equivalent Capacitance" section page updated. Figure page updated. Table page updated. Figure page updated. Table page updated. "Development Tool Support" section page updated. "Absolute Maximum Ratings 42MX Devices*" table page "Absolute Maximum Ratings 40MX Devices*" table page were updated. Electrical Specifications" table page updated. "3.3V LVTTL Electrical Specifications" table page updated. "Mixed 5.0V/3.3V Operating Conditions (for 42MX devices only)" section page "Absolute Maximum Ratings*" table "Recommended Operating Conditions" table "Mixed 5.0V/3.3V Electrical Specifications" table were updated. Specification (5.0V Signaling)1" table page updated. Specification (3.3V Signaling)1" table page updated. Junction Temperature (TJ) section, "Package Thermal Characteristics" section page tables were updated. "40MX Timing Model*" page updated. "42MX Timing Model (Logic Functions using Quadrant Clocks)*" page "42MX Timing Model (SRAM Functions)*" page updated. "Output Buffer Latches" figure page updated. "42MX Temperature Voltage Derating Factors" section page new. "40MX Temperature Voltage Derating Factors" section page new. "Pin Descriptions" section page updated. "100-Pin PQFP" table page following pins changed: (42MX09 42MX16) changed "160-Pin PQFP" table page following pins changed: (42MX09, 42MX16, 42MX64) changed "208-Pin PQFP" table page following pins changed: (42MX09, 42MX16, 42MX64) changed (42MX09) changed "240-Pin PQFP" table page following pins changed: (42MX36) changed "100-Pin VQFP Package" table page 102, following pins changed: (42MX09 42MX16) changed "176-Pin TQFP" table page 104, following pins changed: (42MX09 42MX16) changed "272-Pin PBGA" table page 113, following pins changed: (42MX36) changed Page page page page page page page page page page page page page page page page page page page page
v5.1
page page page page page page page page page page page page page
page page page page
v5.0
v4.0.1
"Low Power Mode" page updated. Footnote "Electrical Specifications" table page updated. Footnote "Electrical Specifications" table page updated. Because changes this data sheet extensive technical nature, this should viewed document. Please read would data sheet that published first time. Note that "Package Characteristics Mechanical Drawings" section been eliminated from data sheet. mechanical drawings contained separate document, "Package Characteristics Mechanical Drawings," available Actel site.
page page page
order provide latest information designers, some datasheets published before data been fully characterized. Datasheets designated "Product Brief," "Advanced," "Production," "Datasheet Supplement." definition these categories follows:
Product Brief
product brief summarized version datasheet (advanced production) containing general product information. This brief gives overview specific device family information.
Advanced
This datasheet version contains initial estimated information based simulation, other products, devices, speed grades. This information used estimates, production.
Unmarked (production)
This datasheet version contains information that considered final.
Datasheet Supplement
datasheet supplement gives specific device information derivative family that differs from general family datasheet. supplement used conjunction with datasheet obtain more detailed information specifications that differ between families.
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Dunlop House, Riverside Camberley, Surrey GU15 United Kingdom Tel: (0)1276 401450 Fax: (0)1276 401490
Actel Japan
EXOS Ebisu Bldg. 1-24-14 Ebisu Shibuya-ku Tokyo Japan Tel: 03-3445-7671 Fax: 03-3445-7668
Actel Hong Kong
39th Floor Pacific Place Queensway Admiralty, Hong Kong Tel: 852-22735712 5172136-8/1.04
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