2.4GHz Transmitter module specification MD7301 _A01 Oct

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2.4GHz Transmitter module specification MD7301 _A01 Oct

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MODULE MD7301_A01
2.4GHz Transmitter
module specification
MD7301 _A01
Oct, 2003, Version
AMIC Technology, Corp.
MODULE MD7301_A01 General Description
transmitter module designed 2.4GHz band wireless applications using AMIC A7301 transmitter. This module features fully programmable frequency synthesizer, which base 2MHz reference frequency 300uA charge pump output current. maximum data rate 64Kbps.
Electrical specification
Item
Supply voltage
Specification
6uA(typical) @sleep mode 1.3mA(typical) @stand-by mode 14mA(typical) mode, power 17mA(typical) mode, high power 2416 2478 power, 2.5V high power, 2.5V meters (typical) header 22(L) 20(W) 10(H)
Remark
Current consumption
Frequency Transmit output power Modulation Channel spacing Channel number Transmission distance Interface Dimension Operating temperature
Oct, 2003, Version
AMIC Technology, Corp.
MODULE MD7301_A01 Interface
Number Name
EN_REG SPI_LATCH SPI_CLOCK SPI_DATA LVOUT TXDATAIN
Description
Supply voltage. Voltage regulator enable input, active high (VIN). Latch interface. Clock interface. Data interface. Ground. Battery-low indicator output, active low. Transmitter data input.
Note
Option.
Option.
Oct, 2003, Version
AMIC Technology, Corp.
MODULE MD7301_A01 Serial Parallel Interface (SPI)
consists three signals: SPI_DATA, SPI_CLOCK, SPI_LATCH. This interface used external baseband controller communicate with internal registers. contents registers shown following register description sections. After setting SPI_LATCH signal "Low" state, data SPI_DATA shifted into internal shift register rising edge SPI_CLOCK with going first. SPI_LATCH should asserted latch data packet into register according address bits, through each registers. registers only written into except Status Register, which only read. When content Status Register need fetched external controller, external baseband controller need make sure that address bits pointing address location proper read operation. After address bits shifted into interface latched asserting SPI_LATCH, interface will Read Mode content Status Register will shifted SPI_DATA pin. When status bits have been shifted out, will back Write Mode automatically. Register Description
Note: Convention used: Logic level "ONE". Logic level "ZERO". Don't care. Synthesizer Configuration Register (Write only Address 0xf) Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2
Synthesizer Configuration Register (Write only Address 0x7) Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2
Synthesizer Configuration Register Synthesizer Configuration Register control synthesizer frequency settings where MA[4:0]: counter[4:0] Valid range from MB[9:0]: counter[9:0] Valid range from 1023. R[7:0]: counter[7:0] Valid range from 255, this module must proper operation. content registers unsigned binary format (i.e., 111112 3110). equation setting synthesizer frequency fvco fcrystal (32*B
example:
fvco 2450MHz, fcrysta 12MHz, freference 2MHz. Then fcrysta freference =000001102, 00001001102 010012.
Oct, 2003, Version
AMIC Technology, Corp.
MODULE MD7301_A01
Crystal Control Register (Write only Address 0xb) Bit12 Bit11 Bit10 TXH2 TXH1 TXH0 TXL2 Bit9 TXL1 Bit8 TXL0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2
Data Polarity. This control sets data output polarity. Data inverted. Normal. TXH[2:0]: Must proper operation. TXL[2:0]: Must proper operation. FX[3:0]: Must proper operation. Control Register (Write only Address 0x3) VTH2 VTH1 VTH0 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2
VTH[2:0]: tuning voltage range, this module must proper operation. VDD-0.3V VDD-0.5V VDD-0.7V VDD-0.9V VDD-0.4V VDD-0.6V VDD-0.8V VDD-1.0V
T[1:0]: Reserved. Must proper operation. HP0: output power level control. power output (-13 dBm). High power output dBm). CP[2]: Reserved. Must proper operation. CP[1:0]: Charge pump output current control, this module must (300uA) proper operation. 100uA 500uA 300uA 700uA
VC[2:0]: Reserved. Must proper operation. Test Control Register (Write only Address 0xd) Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2
T[2:0]: Reserved. Must proper operation.
Oct, 2003, Version
AMIC Technology, Corp.
MODULE MD7301_A01
Mode Select Register (Write only Address 0x5) Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 EXTB Bit5 Bit4 Bit3 Bit2
SC[1:0]: Status Register control. Depends setting SC[1:0], Status Register represent system error flag, Battery-low detect lock detect. [1:0] System Error. [1:0] Battery-low detect. [1:0] lock detect. Reserved. Must proper operation. EXTB: Operating mode selection. external mode. Operation mode determined external MODSEL0 MODSEL1. internal mode. Operation mode determined setting MD[1:0]. MD[1:0]: Internal mode selection. [1:0] Sleep mode. Transceiver circuit turned off. [1:0] Stand-by mode. X'TAL oscillator turned [1:0] Transmit mode. [1:0] Receive mode. Status Register (Read only Address 0x0) SR15 SR14 SR13 SR12 SR11 SR10 S/B/P
S/B/P: Depends setting SC[1:0] Mode Select Register, this used reflect status System Error, Battery-low detect System Error: Normal; Error. Battery-low detect: Battery supply voltage below threshold. Normal. lock detect: Unlock. Lock. SR[3:0]: Address bits.
Oct, 2003, Version
AMIC Technology, Corp.
MODULE MD7301_A01
Timing Diagram
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9
Bit5 Bit4
Bit3
Bit2 Bit1 Bit0
SPI_DATA
SPI_CLOCK
tCWH tCWL
SPI_LATCH
Figure WRITE mode timing diagram After reading bits, write mode
SR11 SR12 SR13 SR14 SR15 Bit15 Bit14
SPI_DATA
SPI_CLOCK
SPI_LATCH Figure READ mode timing diagram
Oct, 2003, Version
AMIC Technology, Corp.
MODULE MD7301_A01
Timing Specification Parameter High level voltage level voltage SPI_DATA SPI_CLOCK setup time SPI_CLOCK SPI_DATA hold time SPI_CLOCK pulse width high SPI_CLOCK pulse width SPI_CLOCK SPI_LATCH setup time SPI_LATCH pulse width Conditions Three wire SPI_CLOCK, SPI_DATA, SPI_LATCH timing diagram Three wire SPI_CLOCK, SPI_DATA, SPI_LATCH timing diagram Three wire SPI_CLOCK, SPI_DATA, SPI_LATCH timing diagram Three wire SPI_CLOCK, SPI_DATA, SPI_LATCH timing diagram Three wire SPI_CLOCK, SPI_DATA, SPI_LATCH timing diagram Three wire SPI_CLOCK, SPI_DATA, SPI_LATCH timing diagram Three wire SPI_CLOCK, SPI_DATA, SPI_LATCH timing diagram Three wire SPI_CLOCK, SPI_DATA, SPI_LATCH timing diagram Table Value VCC-0.4 Units
Symbol tCWH tCWL
Module setup procedure:
Step Supply voltage VIN. Step Reset setting SPI_CLOCK _LATCH logic high simultaneously more than Step Setup IC's internal control registers configuring followings: Synthesizer Configuration Register Synthesizer Configuration Register Crystal Control Register, Crystal Control Register. registers should written order specified above. Synthesizer Configuration Register center frequency. Crystal Control Register: TXDATA polarity. Control Register: tuning range charge pump output current. Step Stand-by mode. internal mode operation, Mode Select Register 0x05D5, then wait about 10mS. Step mode. internal mode operation, Mode Select Register 0x05E5. Whenever frequency changed, system error been detected reading from Status Register) must reset repeating step 3-a, 4and
Oct, 2003, Version
AMIC Technology, Corp.
MODULE MD7301_A01
Module dimension layout drawings
Figure Dimension Drawing
Figure Component side layout
Oct, 2003, Version
AMIC Technology, Corp.
MODULE MD7301_A01
Figure Ground side layout
Figure Component side placement
AMIC Technology, Corp.
Oct, 2003, Version

2.4GHz Transmitter module specification MD7301 _A01 Oct

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