FlexQTMII Volt Synchronous First-In/First-Out Queue Memory C
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FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
FlexQTMII
Volt Synchronous First-In/First-Out Queue
Memory Configuration
524,288 262,144 131,072 65,536 32,768 16,384
Part Number
FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
Features
Industry leading First-In/First-Out Queues 133MHz) Write cycle time 7.5ns independent Read cycle time Read cycle time 7.5ns independent Write cycle time User selectable input output port bus-sizing Endian/Little Endian user selectable byte representation 3.3V power supply input tolerant control data input pins output tolerant flags data output pins Master Reset clears previously programmed configurations including Write Read pointers. Partial Reset clears Write Read pointers maintains previously programmed configurations. First Word Fall Through (FWFT) Standard Timing modes Preset Almost Full PRAF Almost Empty PRAE offsets values Parallel/Serial programming PRAF PRAE offset values Full, Empty, Almost Full, Almost Empty Half Full indicators Asynchronous output enable tri-state data output drivers Data retransmission Available package: Plastic Thin Quad Flat Pack (TQFP), Slim Thin Quad Flat Pack (STQFP) (0°C 70°C) Commercial operating temperature available cycle time 7.5ns above (-40°C 85°C) Industrial operating temperature available cycle time 7.5ns above
Product Description
HBA's FlexQII offers industry leading FIFO queuing bandwidth Gbps) with wide range memory configurations (from 16,384 524,288 System designer full flexibility implementing deeper wider queues using FWFT mode width expansion features. Full, Empty, Half-Full indicators allow easy handshaking between transmitters receivers. User programmable Almost Full Almost Empty (Parallel/Serial) indicators allow implementation virtual queue depths. tolerant input output pins allow easy interfacing with devices operating higher voltage levels. Asynchronous Output Enable configures tri-state data output drivers. Independent Write Read controls provide rate-matching capability. Master Reset clears previously programmed configurations providing pulse MRST pin. addition, Write Read pointers queue initialized zero. Partial Reset will alter previously programmed configurations will initialize Write Read pointers zero. FWFT mode, first data written into queue appears output data after specified latency period high transition RCLK. Subsequent reads from queue will require asserting This feature useful when implementing depth expansion functions. this mode, DRDY QRDY used instead FULL EMPTY respectively. Standard mode, always assert read operation. FULL EMPTY used instead DRDY QRDY respectively.
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FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
FlexQTMII Product Description (Continued)
PRAF PRAE HALF available either FWFT Standard mode. PRAF PRAE operate either synchronous asynchronous modes.
time, data previously read from queue retransmitted asserting high transition RCLK retransmit operation. Retransmit initializes Read pointer zero. Hence, re-reads will always start from physical (Read pointer zero), location queue. These FlexQII devices have power consumption, hence minimizing system power requirements. addition, industry standard Plastic TQFP STQFP offered save system board space. These queues ideal applications such data communication, telecommunication, graphics, multiprocessing, test equipment, network switching, etc.
Block Diagram Single Synchronous Queue 524,288 262,144 131,072 65,536 32,768 16,384
PARTIAL RESET (PRST
MASTER RESET (MRST)
WRITE CLOCK (WCLK) WRITE ENABLE (WEN) LOAD LOAD) DATA SERIAL DATA ENABLE (SDEN) FIRST WORD FALL THROUGH/ SERIAL DATA INPUT (FWFT/SDI) FULL FLAG INPUT READY FULL DRDY) PROGRAMMABLE ALMOST-FULL (PRAF FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
READ CLOCK (RCLK) READ ENABLE (REN) OUTPUT ENABLE (OE) DATA RETRANSMIT EMPTY FLAG OUTPUT READY EMPTY QRDY PROGRAMMABLE ALMOSTEMPTY PRAE HALF-FULL FLAG HALF
Figure Single Device Configuration Signal Flow Diagram
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FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
FlexQTMII
WCLK
LOAD SDEN FWFT/SDI Write Control Logic
FULL DRDY PRAF EMPTY/ QRDY
Offset Register
Flag Logic
Write Pointer
PRAE HALF FWFT/SDI
Input Register
SRAM
Output Register
Output Buffer
Read Pointer
Read Control Logic
Reset
RCLK
MRST PRST
Figure Device Architecture
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FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
FlexQTMII
EMPTY/QRDY
FULL/DRDY
WCLK
LOAD
FWFT/SDI
MRST
RCLK
HALF
PRAE
PRAF
PRST
SDEN DC(1)
DNC(2) DNC(2) DNC(2) DNC(2) DNC(2) DNC(2) DNC(2) DNC(2) DNC(2)
TQFP (Drw PF-01A; Order code: STQFP (Drw TF-01A; Order code: View NOTES:
Don't Care. Must tied Vcc, cannot left open. Connect.
Figure Device
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FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
FlexQTMII
Name Symbol Input/Output Description
Master Reset required initialize Write Read pointers first position queue setting MRST low. Standard mode, FULL PRAF will high; EMPTY PRAE will low. FWFT mode, DRDY will QRDY will high. PRAF PRAE will same state Standard mode. both modes, data outputs will low. Previous programmed configurations will maintained. Partial Reset required initialize Write Read pointers first position queue setting PRST low. Standard mode, FULL PRAF will high; EMPTY PRAE will low. FWFT mode, DRDY will QRDY will high. PRAF PRAE will same state Standard mode. both modes, data outputs will low. Previous programmed configurations will maintained. Writes data into queue during high transitions WCLK low. Controls write operation into queue offset registers during high transition WCLK. During Master Reset, LOAD select parallel programming default offset value 127. LOAD high select serial programming default offset value 1023. After Master Reset, LOAD controls write/read, to/from offset registers during high transition WCLK/RCLK respectively. conjunction with wide input data bus. Reads data from queue during high transitions RCLK low. Controls read operation from queue offset registers during high transition RCLK. Setting activates data output drivers. Setting high deactivates data output drivers (High-Z). wide output data bus. Selects FWFT timing Standard timing mode during Master Reset. After Master Reset, serial programming selected LOAD high), FWFT/SDI used serial data input offset registers. Serial data written during high transition WCLK. conjunction with SDEN
Master Reset
MRST
Input
Partial Reset
PRST
Input
Write Clock Write Enable
WCLK
Input Input
Load Enable
LOAD
Input
15,16,17, 18,19,20, 21,22,23 36,35,34, 32,31,29, 28,26,25
Data Inputs Read Clock Read Enable Output Enable
RCLK
Input Input Input Input
Data Outputs
Output
First Word Fall Through/Serial Data Input
FWFT/SDI
Input
Table Descriptions
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FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
FlexQTMII
Name
Serial Data Input Enable
Symbol
SDEN
Input/Output
Input
Description
serial programming selected, setting SDEN LOAD enables serial data input written into offset registers during high transition WCLK. Data previously read from queue retransmitted asserting high transition RCLK retransmit operation. Retransmit initializes Read pointer zero. Hence, re-reads will always start from physical (Read pointer zero) location queue. Queue full when FULL goes during high transition WCLK. This prohibits further writes into queue. FWFT mode, queue full when DRDY goes high during high transition WCLK. This prohibits further writes into queue. Queue empty when EMPTY goes during high transition RCLK. This prohibits further reads from queue. FWFT mode, queue empty when QRDY goes high during high transition RCLK. This prohibits further reads form queue. Queue almost full when PRAF goes during high transition WCLK. Default (Full-offset) programmed offset values determine status PRAF Queue almost empty when PRAE goes during high transition RCLK. Default (Empty+offset) programmed offset values determine status PRAE Queue more than half full when HALF goes low. Triggered both WCLK RCLK. This tied high low, cannot left open. 3.3V power supply. Ground. connect.
Retransmit
Input
Full Data Input Ready Flag
FULL DRDY
Output
Empty Data Output Ready Flag
EMPTY QRDY
Output
Almost Full
PRAF
Output
Almost Empty
PRAE
Output
Half Full Don't Care Power Ground Connect
HALF
Output
Table Descriptions (Continued)
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FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
FlexQTMII
Symbol
VTERM
Rating
Terminal Voltage with respect Storage Temperature
Com'l Ind'l
-0.5
Unit
NOTES:
Absolute Ratings reference only. Permanent damage device occur extended period operation outside this range. Standard operation should fall within Recommended Operating Conditions.
TSTG
+125
IOUT
Output Current
Table Absolute Maximum Ratings
FQV2111, FQV2101, FQV291, FQV281, FQV271, FQV261 Commercial Clock 7.5ns, 10ns, 15ns, 20ns Industrial Clock 7.5ns, 10ns, 15ns, 20ns
Symbol
Parameter
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
Recommended Operating Conditions
Supply Voltage Com'l Ind'l Supply Voltage Input High Voltage Com'l Ind'l Input Voltage Com'l Ind'l Operating Temperature Commercial Operating Temperature Industrial Input Leakage Current (any input) Output Leakage Current Output Logic Voltage, IOH=-2mA Output Logic Voltage,
Electrical Characteristics
ILI(1)
Power Consumption
Icc1(2,3) Icc2(4) Active Power Supply Current Standby Current
Table Specifications
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FlexQTMII
Capacitance 100MHz Ambient Temperature (25°C) Symbol
CIN(2) COUT(2,4)
NOTES:
Measurement with 0.4<=VIN<=Vcc With output tri-stated High) Icc(1,2) measured with WCLK RCLK Design simulated, tested.
Parameter
Input Capacitance Output Capacitance
Conditions
VIN= VOUT=
Max.
Unit
Table Specifications (Continued)
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FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
FlexQTMII
Commercial Industrial
FQV2111-7.5 FQV2101-7.5 FQV291-7.5 FQV281-7.5 FQV271-7.5 FQV261-7.5 FQV2111-10 FQV2101-10 FQV291-10 FQV281-10 FQV271-10 FQV261-10 FQV2111-15 FQV2101-15 FQV291-15 FQV281-15 FQV271-15 FQV261-15 FQV2111-20 FQV2101-20 FQV291-20 FQV281-20 FQV271-20 FQV261-20
Symbol
tWCLK tWCLKH tWCLKL tRCLK tRCLKH tRCLKL tENS tENH tRST tRSTS tRSTR tRSTF tOLZ tOHZ tFULL tEMPTY tPRAFS tPRAES tSKEW1 tSKEW2 tSKEW3
Parameter
Clock Cycle Frequency Data Access Time Write Clock Cycle Time Write Clock High Time Write Clock Time Read Clock Cycle Time Read Clock High Time Read Clock Time Data Set-up Time Data Hold Time Enable Set-up Time Enable Hold Time Reset Pulse Width
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Reset Set-up Time Reset Recovery Time Reset Flag Output Time Output Enable Output Low-Z Output Enable Output Valid Output Enable Output High-Z Write Clock Full Flag Read Clock Empty Flag Write Clock Almost-Full Flag Read Clock Almost-Empty Flag Skew time between Read Clock Write Clock Full Flag Empty Flag Skew time between Read Clock Write Clock PRAF PRAE Skew time between Read Clock Write Clock EMPTY QRDY
Table Electrical Characteristics
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FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
FlexQTMII
Commercial Industrial
FQV2111-7.5 FQV2101-7.5 FQV291-7.5 FQV281-7.5 FQV271-7.5 FQV261-7.5 FQV2111-10 FQV2101-10 FQV291-10 FQV281-10 FQV271-10 FQV261-10 FQV2111-15 FQV2101-15 FQV291-15 FQV281-15 FQV271-15 FQV261-15 FQV2111-20 FQV2101-20 FQV291-20 FQV281-20 FQV271-20 FQV261-20
Symbol
tLOADS tLOADH tRTS
Parameter
Load Setup Time Load Hold Time Retransmit Setup Time Clock HALF
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
NOTES:
Design simulated, tested.
Table Electrical Characteristics (Continued)
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FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
FlexQTMII
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load, clock Output Load*, clock 10ns, 15ns, 20ns
3.0V 1.5V 1.5V Refer Figure Refer Figure
Include scope capacitances
Table Test Condition
Vcc/2
3.3V
D.U.T. 30pF*
Figure Test Load clock 7.5ns
Figure Output Load clock 10ns, 15ns, 20ns *Includes scope capacitances.
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FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
FlexQTMII Functions
MRST
Master Reset required initialize Write Read pointers first position queue setting MRST low. Standard mode, FULL PRAF will high; EMPTY PRAE will low. FWFT mode, DRDY will QRDY will high. PRAF PRAE will same state Standard mode. both modes, data outputs will low. Previous programmed configurations will maintained. Partial Reset required initialize Write Read pointers first position queue setting PRST low. Standard mode, FULL PRAF will high; EMPTY PRAE will low. FWFT mode, DRDY will QRDY will high. PRAF PRAE will same state Standard mode. both modes, data outputs will low. Previous programmed configurations will maintained. Writes data into queue during high transitions WCLK activated. Synchronizes FULL DRDY PRAF flags. WCLK RCLK independent each other. Controls write operation into queue offset registers during high transition WCLK. During Master Reset, LOAD select parallel programming default offset value 127. LOAD high select serial programming default offset value 1023. After Master Reset, LOAD controls write/read, to/from offset registers during high transition WCLK/RCLK respectively parallel programming. conjunction with During programming offset registers, PRAF PRAE flag status invalid. Serial programming, LOAD used enable serial loading offset registers together with SDEN Refer Figure details. wide input data bus. Reads data from queue during high transitions RCLK low. Synchronizes EMPTY QRDY PRAE flags. RCLK WCLK independent each other. Reads data from queue during high transitions RCLK low. This also advances Read pointer queue. Setting activates data output drivers. Setting high deactivates data output drivers (High-Z). does control advancement Read pointer. wide output data bus. Selects FWFT timing Standard timing mode during Master Reset. After Master Reset, serial programming selected LOAD high), FWFT/SDI used serial data input offset registers. Serial data written during high transition WCLK. conjunction with SDEN FWFT mode, DRDY QRDY used instead FULL EMPTY Standard mode, FULL EMPTY used instead DRDY QRDY Refer Table flags status. serial programming selected, setting SDEN LOAD enables serial data written into offset registers during high transition WCLK. During serial programming, PRAF PRAE flags status invalid. Refer Figure details. Data previously read from queue retransmitted asserting high transition RCLK retransmit operation. Retransmit initializes Read pointer zero. Hence, re-reads will always start from physical (Read pointer zero) location queue. Refer Diagram details.
PRST
WCLK
LOAD
D8-0 RCLK
Q8-0 FWFT/SDI
SDEN
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FlexQTMII Functions (Continued)
FULL DRDY
Standard mode, queue full when FULL goes during high transition WCLK. This prohibits further writes into queue prevents advancement Write pointer. FWFT mode, queue full when DRDY goes high during high transition WCLK. This prohibits further writes into queue prevents advancement Write pointer. Refer Table behavior FULL DRDY Standard mode, queue empty when EMPTY goes during high transition RCLK. This prohibits further reads from queue prevents advancement Read pointer. FWFT mode, queue empty when QRDY goes during high transition RCLK. This prohibits further reads from queue prevents advancement Read pointer. Refer Table behavior EMPTY QRDY Synchronous mode, queue almost full when PRAF goes during high transition WCLK. Default (Full-offset) programmed offset values determine status PRAF Asynchronous timing mode, PRAF triggered both WCLK RCLK. Refer Table behavior PRAF Synchronous mode, queue almost empty when PRAE goes during high transition RCLK. Default (Empty+offset) programmed offset values determine status PRAE Asynchronous timing mode, PRAE triggered both WCLK RCLK. Refer Table behavior PRAE Queue more than half full when HALF goes during high transition WCLK. HALF goes high during high transition RCLK when queue less than half full. Refer Table details.
EMPTY QRDY
PRAF
PRAE
HALF
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FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
FlexQTMII
FQV281 FQV271 FQV261 Selection Sequence
Parallel write offset registers: Empty Offset (Low Byte) Empty Offset (High Byte) Full Offset (Low Byte) Full Offset (High Byte) Parallel read from offset registers: Empty Offset (Low Byte) Empty Offset (High Byte) Full Offset (Low Byte) Full Offset (High Byte) Parallel write registers: PRAE Byte PRAE High Byte PRAF Byte PRAF High Byte Parallel read from registers: PRAE Byte PRAE High Byte PRAF Byte PRAF High Byte
LOAD
SDEN
WCLK
RCLK
Serial shift into registers: bits FQV281 bits FQV271 bits FQV261 each rising WCLK edge Starting with Empty Offset (Low Byte) Ending with Full Offset (High Byte) Operation Write Memory
Read Memory Operation
Figure Programmable Flag Offset Programming Sequence (FQV281, FQV271 FQV261)
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FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
FlexQTMII
FQV2111 FQV2101 FQV291 Selection Sequence
Parallel write offset registers: Empty Offset (Low Byte) Empty Offset (Mid Byte) Empty Offset (High Byte) Full Offset (Low Byte) Full Offset (Mid Byte) Full Offset (High Byte) Parallel read from offset registers: Empty Offset (Low Byte) Empty Offset (High Byte) Empty Offset (Mid Byte) Full Offset (Low Byte) Full Offset (Mid Byte) Full Offset (High Byte) Parallel write registers: PRAE Byte PRAE Byte PRAE High Byte PRAF Byte PRAF Byte PRAF High Byte Parallel read from registers: PRAE Byte PRAE Byte PRAE High Byte PRAF Byte PRAF Byte PRAF High Byte
LOAD
SDEN
WCLK
RCLK
Serial shift into registers: bits FQV2111 bits FQV2101 bits FQV291 each rising WCLK edge Starting with Empty Offset (Low Byte) Ending with Full Offset (High Byte) Operation Write Memory
Read Memory Operation
Figure Programmable Flag Offset Programming Sequence (FQV291, FQV2101, FQV2111)
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FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
FlexQTMII
Device
FQV2111
PRAF Programming (bits)
D/Q7 D/Q7 D/Q7 D/Q7 D/Q7 D/Q7 D/Q7 D/Q7 D/Q7 D/Q6 D/Q7 D/Q5 Byte Byte High Byte Byte Byte High Byte Byte Byte High Byte Byte High Byte Byte High Byte Byte High Byte
PRAE Programming (bits)
D/Q7 D/Q7 D/Q7 D/Q7 D/Q7 D/Q7 D/Q7 D/Q7 D/Q7 D/Q6 D/Q7 D/Q5 Byte Byte High Byte Byte Byte High Byte Byte Byte High Byte Byte High Byte Byte High Byte Byte High Byte
FQV2101
FQV291 FQV281 FQV271 FQV261
FQV2111 FQV2101 FQV291
Byte Byte 7FH, LOAD FFH, LOAD 00H, LOAD 03H, LOAD
FQV281 FQV271 FQV261
7FH, LOAD FFH, LOAD 00H, LOAD 03H, LOAD
High Byte
Table Parallel Offset Register Data Mapping Default Values
Device
FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
Standard Mode
524,288 262,144 131,072 65,536 32,768 16,384
FWFT Mode
524,289 262,145 131,073 65,537 32,769 16,385
Table Maximum Depth Queue Standard FWFT Mode
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FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
FlexQTMII
Data Width Cycle PRAE (Low Byte) Cycle PRAE (Mid Byte) Cycle PRAE (High Byte)
D/Q8 D/Q7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0
Cycle PRAF (Low Byte) Cycle PRAF (Mid Byte) Cycle PRAF (High Byte)
FQV2111, FQV2101, FQV291
Data Width Cycle PRAE (Low Byte) Cycle PRAE (High Byte)
D/Q8 D/Q7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0
Cycle PRAF (Low Byte) Cycle PRAF (High Byte)
FQV281 FQV271 FQV261
Bits Offset Registers bits FQV2111 bits FQV2101 bits FQV291 bits FQV281 bits FQV271 bits FQV261 Note: Don't Care applies unused bits both High Byte Byte
Figure Parallel Offset Write/Read Cycle Diagram
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FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
FlexQTMII
FQV2111
y(1) (y+1) 262,144 262,145 [524,288-(x+1)] (524,288-x(2))to 524,287 524,288
FULL
PRAF
HALF
PRAE
EMPTY
FQV2101
y(1) (y+1) 131,072 131,073 [262,144-(x+1)] (262,144-x(2))to 262,143 262,144
FULL
PRAF
HALF
PRAE
EMPTY
FQV291
y(1) (y+1) 65,536 65,537 [131,072-(x+1)] (131,072-x(2))to 131,071 131,072
FULL
PRAF
HALF
PRAE
EMPTY
FQV281
y(1) (y+1) 32,768 32,769 [65,536-(x+1)] (65,536-x(2))to 65,535 65,536
FULL
PRAF
HALF
PRAE
EMPTY
FQV271
y(1) (y+1) 16,384 16,385 [32,768-(x+1)] (32,768-x(2)) 32,767 32,768
FULL
PRAF
HALF
PRAE
EMPTY
FQV261
y(1) (y+1) 8,192 8,193 [16,384-(x+1)] (16,384 -x(2))t 16,383 16,384
NOTES:
FULL
PRAF
HALF
PRAE
EMPTY
PRAE offset; Default Values: when parallel offset loading selected 1,023 when serial offset loading selected.
PRAF offset; Default Values: when parallel offset loading selected 1,023 when serial offset loading selected.
Table Status Flags (Standard Mode)
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FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
FlexQTMII
FQV2111
y+1(1) (y+2) 262,145 262,146 [524,289-(x+1)] (524,289-x(2))to 524,288 524,289
DRDY
PRAF
HALF
PRAE
QRDY
FQV2101
y+1(1) (y+2) 131,073 131,074 [262,145-(x+1)] (262,145-x(2))to 262,144 262,145
DRDY
PRAF
HALF
PRAE
QRDY
FQV291
y+1(1) (y+2) 65,537 65,538 [131,073-(x+1)] (131,073-x(2)) 131,072 131,073
DRDY
PRAF
HALF
PRAE
QRDY
FQV281
y+1(1) (y+2) 32,769 32,770 [65,537-(x+1)] (65,537-x(2)) 65,536 65,537
DRDY
PRAF
HALF
PRAE
QRDY
FQV271
y+1(1) (y+2) 16,385 16,386 [32,769-(x+1)] (32,769-x(2)) 32,768 32,769
DRDY
PRAF
HALF
PRAE
QRDY
FQV261
y(1) (y+2) 8,193 8,194 [16,385-(x+1)] (16,385 -x(2)) 16,384 16,385
NOTES:
DRDY
PRAF
HALF
PRAE
QRDY
PRAE offset; Default Values: when parallel offset loading selected 1,023 when serial offset loading selected. PRAF offset; Default Values: when parallel offset loading selected 1,023 when serial offset loading selected.
Table Status Flags (FWFT Mode)
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FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
FlexQTMII Timing Diagrams
tRST MRST tRSTS tRSTS tRSTS FWFT/SDI tRSTS tRSTR tRSTR tRSTR tRSTR
LOAD
tRSTS
tRSTS SDEN tRSTF FWFT 1,QRDY EMPTY QRDY tRSTF FWFT FULL FULL DRDY tRSTF PRAE tRSTF PRAF HALF tRSTF FWFT DRDY FWFT EMPTY
Diagram Master Reset Timing
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FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
FlexQTMII
tRST PRST tRSTS tRSTS tRSTS tRSTS SDEN FWFT 1,QRDY
EMPTY QRDY
tRSTR
tRSTR
FWFT EMPTY tRSTF FWFT FULL
FULL DRDY tRSTF
PRAE
FWFT DRDY
tRSTF
PRAF HALF
tRSTF
Diagram Partial Reset Timing
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3F209C
tWCLK tWCLKH
Write tWCLKL
Write
Write
WCLK
tFULL tFULL tFULL
tSKEW1
tFULL
FULL
RCLK
tENH tENS tENH
tENS
2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
Data Read Next Data Read
Output Register Data
NOTES:
time between rising edge RCLK rising edge WCLK greater than equal tSKEW1, FULL will high (after WCLK cycle plus tFULL). tSKEW1 met, then FULL will assert more WCLK cycles. LOAD High, Low.
FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
Diagram Write Cycle Full Flag Timing (Standard Mode)
FlexQTMII
OCTOBER 2002
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3F209C
tRCLK tRCLKH
tRCLKL
RCLK tENH tENS tENH tENS
tENS
tENH
tEMPTY tEMPTY tEMPTY
EMPTY Last Word tOLZ tOHZ tOEN tOLZ Last Word
tSKEW1
WCLK tENS tENH tENS tENH
2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
NOTES:
time between rising edge WCLK rising edge RCLK greater than equal tSKEW1, EMPTY will high (after RCLK cycle plus tEMPTY). tSKEW1 met, then EMPTY will assert more RCLK cycles. LOAD High. First word latency: tSKEW1 tEMPTY tRCLK.
FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
Diagram Read Cycle, Empty Flag First Data Word Latency Timing (Standard Mode)
FlexQTMII
OCTOBER 2002
Page
3F209C
tENH tSKEW2 DW[y+2] DW[y+3] DW[y+4] DW[(D-1)/2+1] DW[(D-1)/2+2] DW[(D-1)/2+3] DW[D-x-1] DW[D-x] DW[D-x+1] DW[D-x+2] DW[D-x+3] DW[D-1] tEMPTY tPRAES tHALF tPRAFS tFULL
WCLK
tENS
tSKEW1
RCLK
Output Register Data
QRDY
PRAE
2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
HALF
PRAF
DRDY
NOTES:
time between rising edge WCLK rising edge RCLK greater than equal tSKEW1, QRDY will (after RCLK cycle plus tEMPTY). tSKEW1 met, then QRDY will assert more RCLK cycles. time between rising edge WCLK rising edge RCLK greater than equal tSKEW2, PRAE will high (after RCLK cycle plus tPRAES). tSKEW2 met, then PRAE will assert more RCLK cycles. LOAD High, Low. PRAE offset, PRAF offset. maximum queue depth. Please refer Table Depth. First word latency: tSKEW1 tEMPTY tRCLK
FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
Diagram Write Timing (FWFT Mode)
FlexQTMII
OCTOBER 2002
Page
3F209C
tSKEW2
WCLK
tENS
tENH
tSKEW1
RCLK
tENS
tENS
DWx+2 DW[(D-1)/2+2]
tOHZ DWx+1 DWx+3 DW[(D-1)/2+1] DW[D-y-1] DW[D-y] DW[D-y+1] DW[D-y+2]
DW[D-1]
tEMPTY
QRDY tPRAES
PRAE tHALF
HALF tPRAFS
2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
tFULL
PRAF
tFULL
DRDY
NOTES:
time between rising edge WCLK rising edge RCLK greater than equal tSKEW1, QRDY will (after RCLK cycle plus tEMPTY). tSKEW1 met, then QRDY will assert more RCLK cycles. time between rising edge WCLK rising edge RCLK greater than equal tSKEW2, PRAE will high (after RCLK cycle plus tPRAES). tSKEW2 met, then PRAE will assert more RCLK cycles. LOAD High, Low. PRAE offset, PRAF offset. maximum queue depth. Please refer Table Depth. First word latency: tSKEW1 tEMPTY tRCLK
FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
Diagram Read Timing (FWFT Mode)
FlexQTMII
OCTOBER 2002
Page
FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
FlexQTMII
RCLK
tENS
tENH
tRETS
tENS
tENH
DWi+1 tSKEW2
WCLK
tRETS tENS
tENH
tEMPTY
EMPTY
tEMPTY
tPRAES
PRAE
tHALF
HALF
tPRAFS
PRAF
NOTES:
Upon completion retransmit setup, read operation begin only after EMPTY returns high. Low. Words written queue after MRST Where 1,2,3. depth. Upon reset completion, there must more than words written queue retransmit setup valid.
Diagram Retransmit Timing (Standard Mode)
3F209C 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
OCTOBER 2002
Page
FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
FlexQTMII
RCLK RETS
SKEW2
RETS
PRAES
PRAE
HALF
HALF
PRAFS PRAF
NOTES:
Upon completion retransmit setup, read operation begin only after QRDY returns low. Low. Words written queue after MRST Where 1,2,3. depth. Upon reset completion, there must more than words written queue retransmit setup valid.
Diagram Retransmit Timing (FWFT Mode)
3F209C 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
OCTOBER 2002
Page
FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
FlexQTMII
WCLK tENS SDEN tLOADS LOAD tLOADH tLOADH tENH tENH
PRAE offset
PRAF offset
*Refer Table
Diagram Serial Loading Programmable Flag Registers (Standard FWFT Mode)
FQV2111
FQV2101
FQV291
FQV281
FQV271
FQV261
Table Reference Table Diagram
3F209C 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
OCTOBER 2002
Page
FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
FlexQTMII
tWCLK tWCLKH WCLK tLOADS LOAD tENS
PRAE offset (Low Byte) PRAE offset (High Byte)
tWCLKL
tLOADH
tLOADH
tENH
tENH
PRAF offset (Low Byte)
PRAF offset (High Byte)
Diagram Parallel Loading Programmable Flag Registers FQV281, FQV271 FQV261 (Standard FWFT Mode)
tWCLK tWCLKH WCLK tLOADS
LOAD
tWCLKL
tLOADH
tLOADH
tENS
PRAE offset (Low Byte)
tENH
tENH
PRAE offset (Mid Byte)
PRAE offset (High Byte)
PRAF offset (Low Byte)
PRAF offset (Mid Byte)
PRAF offset (High Byte)
Diagram Parallel Loading Programmable Flag Registers FQV291 (Standard FWFT Mode)
3F209C 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
OCTOBER 2002
Page
FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
FlexQTMII
tRCLK tRCLKH RCLK tLOADS LOAD tENS
tRCLKL
tLOADH
tLOADH
tENH
tENH
Output Register Data PRAE offset (Low Byte) PRAE offset (High Byte) PRAF offset (Low Byte)
PRAF offset (High Byte)
Diagram Parallel Read Programmable Flag Registers FQV281, FQV271 FQV261 (Standard FWFT Mode)
tRCLK tRCLKH RCLK tLOADS LOAD tENS Output Register Data
PRAE offset (Low Byte) PRAE offset (Mid Byte) PRAE offset (High Byte)
tRCLKL
tLOADH
tLOADH
tENH
tENH
PRAF offset (Low Byte) PRAF offset (Mid Byte)
PRAF offset (High Byte)
Diagram Parallel Read Programmable Flag Registers FQV291 (Standard FWFT Mode)
3F209C 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
OCTOBER 2002
Page
FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
FlexQTMII
tWCLKH WCLK tENS
PRAF
tWCLKL tENH tPRAFS words Queue tSKEW2 words Queue tPRAFS D-(x+1) words Queue
RCLK tENS tENH
NOTES:_
PRAF offset. maximum queue depth. Please refer Table Depth. time between rising edge RCLK rising edge WCLK greater than equal tSKEW2, PRAF will high (after WCLK cycle plus tPRAFS). tSKEW2 met, then PRAF will assert more WCLK cycles. PRAF synchronizes rising edge WCLK only.
Diagram Synchronous Programmable Almost-Full Flag Timing (Standard FWFT Mode)
tWCLKH WCLK tWCLKH PRAE
tWCLKL
tWCLKL
words Queue(2) words Queue(3) tSKEW2 tPRAES
words Queue(2) words Queue(3) tPRAES tENS tENH
words Queue(2) words Queue(3)
RCLK
NOTES:
PRAE offset. Standard Mode. FWFT Mode. time between rising edge WCLK rising edge RCLK greater than equal tSKEW2, PRAE will high (after RCLK cycle plus tPRAES). tSKEW2 met, then PRAE will assert more RCLK cycles. PRAE synchronizes rising edge RCLK only.
Diagram Synchronous Programmable Almost-Empty Flag Timing (Standard FWFT Mode)
3F209C 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
OCTOBER 2002
Page
FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
FlexQTMII
tWCLKH WCLK tENS
tWCLKL
tENH
tHALF
HALF
words Queue(1); [(D+1)/2] words Queue(2)
words Queue(1); [(D+1)/2 words Queue(2) tHALF
words Queue(1); [(D+1)/2] words Queue(2)
RCLK tENS
NOTES:
Standard Mode. FWFT Mode. Refer Table Depth.
Diagram Half-Full Flag Timing (Standard FWFT Mode)
3F209C 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
OCTOBER 2002
Page
FQV2111 FQV2101 FQV291 FQV281 FQV271 FQV261
FlexQTMII
Order Information:
Device Family Device Type XXXXX V2111 (524,288 V2101 (262,144 V291 (131,072 V281 (65,536 V271 (32,768 V261 (16,384 *Speed Slower speeds available upon request. **Package Plastic Thin Quad Flat Pack (TQFP), Slim Thin Quad Flat Pack (STQFP) Example: FQV281L7-5PF FQV271L10PFI (64k 7.5ns, Commercial temp) (32k 10ns, Industrial temp) Power Speed (ns) Package** Temperature Range Blank Commercial (0°C 70°C) Industrial (-40° 85°C)
2107 North First Street, Suite Jose, 95131, www.hba.com
Tel: 408.453.8885 Fax: 408.453.8886
Taiwan Suite 8F-9, Shui-Lee Hsinchu, Taiwan, R.O.C. www.hba.com
Tel: 886.3.516.9118 Fax: 886.3.516.9181
3F209C 2001 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
OCTOBER 2002
Page
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