Volt Synchronous x9/x18 First-In/First-Out Queue Memory Organizat
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FQV2113 FQV2103 FQV293 FQV283 FQV273 FQV263 FQV243 FlexQTMIII
Volt Synchronous x9/x18 First-In/First-Out Queue
Memory Organization
262,144 524,288 131,072 262,144 65,536 131,072 32,768 65,536
Device
FQV2113 FQV2103 FQV293 FQV283
Memory Organization
16,384 32,768 8,192 16,384 4,096 8,192 2,048 4,096
Device
FQV273 FQV263 FQV253 FQV243
Features
Industry leading First-In/First-Out Queues 166MHz) Write cycle time 6.0ns independent Read cycle time (Data Setup time 2.0ns) Read cycle time 6.0ns independent Write cycle time (Data Access time 4.0ns) User selectable input output port bus-sizing Endian/Little Endian user selectable byte representation 3.3V power supply input tolerant control data input pins output tolerant flags data output pins Master Reset clears previously programmed configurations including Write Read pointers Partial Reset clears Write Read pointers maintains previously programmed configurations First Word Fall Through (FWFT) Standard Timing modes Presets eight different Almost Full Almost Empty offset values Parallel/Serial programming PRAF PRAE offset values Programmable 8-bit 9-bit parallel programming modes offset values Full, Empty, Almost Full, Almost Empty, Half Full indicators PRAF PRAE operates either synchronous asynchronous modes Asynchronous output enable tri-state data output drivers Data retransmission with programmable zero normal latency modes Available package: Plastic Thin Quad Flat Pack (TQFP) (0°C 70°C) Commercial operating temperature available cycle time 6.0ns above (-40°C 85°C) Industrial operating temperature available cycle time 7.5ns above
Product Description
HBA's FlexQIII offers industry leading FIFO queuing bandwidth Gbps), with wide range memory configurations (from 2,048 262,144 4,096 524,286 System designer full flexibility implementing deeper wider queues using FWFT mode width expansion features. Full, Empty, Half-Full indicators allow easy handshaking between transmitters receivers. User programmable Almost Full Almost Empty (Parallel/Serial) indicators allow implementation virtual queue depths. tolerant input output pins allows easy interfacing with devices operating higher voltage levels. Asynchronous Output Enable configures tri-state data output drivers. Independent Write Read controls provide rate-matching capability. Master Reset clears previously programmed configurations providing pulse MRST pin. addition, Write Read pointers queue initialized zero. Partial Reset will alter previously programmed configurations will initialize Write Read pointers zero.
FWFT mode, first data written into queue appears output data after specified latency period high transition RCLK. Subsequent reads from queue will require asserting This feature useful when implementing depth expansion functions. this mode, DRDY QRDY used instead FULL EMPTY respectively.
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FQV2113 FQV2103 FQV293 FQV283 FQV273 FQV263 FQV243 FlexQTMIII
Product Description (Continued)
Standard mode, always assert whenever read operation. FULL EMPTY used instead DRDY QRDY respectively. matching feature available with following configurations: Input Width Output Width
addition, Endian Select available implementing byte re-ordering data outputs. Eight different default offset values available Almost Full PRAF Almost Empty PRAE flags. Parallel Serial programming these offset values provide total flexibility other than pre-defined default values. Both 8-bit 9-bit parallel programming modes offset values selected convenience. PRAF PRAE HALF available either FWFT Standard mode. PRAF PRAE operate either synchronous asynchronous modes. time, data previously read from queue retransmitted asserting high transition RCLK retransmit operation. Retransmit initializes Read pointer zero. Hence, re-reads will always start from physical (Read pointer zero) location queue. Both zero normal latency timing modes available retransmit operation. These FlexQIII devices have power consumption, hence minimizing system power requirements. addition, industry standard Plastic TQFP offered save system board space. These queues ideal applications such data communication, telecommunication, graphics, multiprocessing, test equipment, network switching, etc.
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FQV2113 FQV2103 FQV293 FQV283 FQV273 FQV263 FQV243 FlexQTMIII
Block Diagram Single Synchronous Queue 262,144 131,072 65,536 32,768 16,384 8,192 4,096 2,048 524,288 262,144 131,072 65,536 32,768 16,384 8,192 4,096
PARTIAL RESET PRST
MASTER RESET MRST)
READ CLOCK (RCLK) WRTIE CLOCK (WCLK) WRITE ENABLE WEN) LOAD LOAD) DATA SERIAL DATA ENABLE SDEN FIRST WORD FALL THROUGH/ SERIAL DATA INPUT (FWFT/SDI) FULL FLAG INPUT READY FULL DRDY PROGRAMMABLE ALMOST-FULL (PRAF) FQV2113 FQV2103 FQV293 FQV283 FQV273 FQV263 FQV253 FQV243 READ ENABLE OUTPUT ENABLE DATA RETRANSMIT RET) EMPTY FLAG OUTPUT READY (EMPTY QRDY PROGRAMMABLE ALMOSTEMPTY PRAE HALF-FULL FLAG HALF BIG-ENDIAN LITTLE-ENDIAN INTERSPERSED NON-INTERSPERSED PARITY (IPAR)
MATCHING (BM1)
MATCHING (BM0)
Figure Single Device Configuration Signal Flow Diagram
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FQV2113 FQV2103 FQV293 FQV283 FQV273 FQV263 FQV243 FlexQTMIII
WCLK IPAR LOAD SDEN FWFT/SDI
Write Control Logic
FULL DRDY PRAF EMPTY/ QRDY
Offset Register
PRAE
Flag Logic HALF FWFT/SDI PFS1 PFS0
Write Pointer
17-0 x18,
Input Register
SRAM
Output Register
Output Buffer
17-0 x18,
Read Pointer
Read Control Logic
Reset
Configuration
RETZL RCLK
MRST PRST
Figure Device Architecture
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FQV2113 FQV2103 FQV293 FQV283 FQV273 FQV263 FQV243 FlexQTMIII
EMPTY/QRDY
FULL/DRDY
FWFT/SDI
WCLK
RETZL
MRST
LOAD
RCLK
HALF
IPAR
PFS0
PFS1
PRAE
PRAF
PRST
Index
SDEN
DNC1
TQFP (Drw PF-01A; Order code: View NOTES:
Connect.
Figure Device
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FQV2113 FQV2103 FQV293 FQV283 FQV273 FQV263 FQV243 FlexQTMIII
Name
Symbol
Input/Output
Description
Master Reset required initialize Write Read pointers first position queue setting MRST low. Standard mode, FULL PRAF will high; EMPTY PRAE will low. FWFT mode, DRDY will QRDY will high. PRAF PRAE will same state Standard mode. both modes, data outputs will low. Previous programmed configurations will maintained. Partial Reset required initialize Write Read pointers first position queue setting PRST low. Standard mode, FULL PRAF will high; EMPTY PRAE will low. FWFT mode, DRDY will QRDY will high. PRAF PRAE will same state Standard mode. both modes, data outputs will low. Previous programmed configurations will maintained. Writes data into queue during high transitions WCLK low. Controls write operation into queue offset registers during high transition WCLK. During Master Reset, LOAD select parallel programming eight default-offset values. LOAD high select serial programming eight default offset values. After Master Reset, LOAD controls write/read, to/from offset registers during high transition WCLK/RCLK respectively. conjunction with During Master Reset, select eight default-offset values. conjunction with LOAD PFS0. During Master Reset, select eight default-offset values. conjunction with LOAD PFS1.
Master Reset
MRST
Input
Partial Reset
PRST
Input
Write Clock Write Enable
WCLK
Input Input
Load Enable
LOAD
Input
08,10,11, 12,13,15, 16,17,18 19,21,22, 24,25,26, 27,28,29
Default Programming Default Programming
PFS1 PFS0
Input Input
Data Inputs
D17-0
Input
wide input data bus.
Read Clock Read Enable
RCLK
Input Input
Reads data from queue during high transitions RCLK low. Controls read operation from queue offset registers during high transition RCLK. Setting activates data output drivers. Setting high deactivates data output drivers (High-Z).
Output Enable
Input
Table Descriptions
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FQV2113 FQV2103 FQV293 FQV283 FQV273 FQV263 FQV243 FlexQTMIII
57,56,53, 52,50,49, 47,45,43, 42,41,40, 38,37,35, 34,32,31
Name
Symbol
Input/Output
Description
Data Outputs
Q17-0
Output
wide output data bus.
First Word Fall Through/Serial Data Input
FWFT/SDI
Input
Selects FWFT timing Standard timing mode during Master Reset. After Master Reset, serial programming selected LOAD high), FWFT/SDI used serial data input offset registers. Serial data written during high transition WCLK. conjunction with SDEN serial programming selected, setting SDEN LOAD enables serial data input written into offset registers during high transition WCLK. During Master Reset, select input width high select input width. During Master Reset, select output width high select output width. During Master Reset, high select byte reordering data outputs select byte re-ordering data outputs. Data previously read from queue retransmitted asserting high transition RCLK retransmit operation. Retransmit initializes Read pointer zero. Hence, re-reads will always start from physical (Read pointer zero) location queue. During Master Reset, RETZL select zero latency retransmit RETZL high select normal latency retransmit. Queue full when FULL goes during high transition WCLK. This prohibits further writes into queue. FWFT mode, queue full when DRDY goes high during high transition WCLK. This prohibits further writes into queue. Queue empty when EMPTY goes during high transition RCLK. This prohibits further reads from queue. FWFT mode, queue empty when QRDY goes high during high transition RCLK. This prohibits further reads from queue. During Master Reset, IPAR select 9-bit parallel programming mode IPAR high select 8bit parallel programming mode.
Serial Data Input Enable Matching Matching Endian Select
SDEN
Input
Input
Input
Input
Retransmit
Input
Zero Latency Retransmit
RETZL
Input
Full/Data Input Ready Flag
FULL DRDY
Output
Empty/Data Output Ready Flag
EMPTY QRDY
Output
Interspersed Parity
IPAR
Input
Table Descriptions (Continued)
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FQV2113 FQV2103 FQV293 FQV283 FQV273 FQV263 FQV243 FlexQTMIII
Name
Synchronous Partial Flag Mode
Symbol
Input/Output
Input
Description
During Master Reset, high select Synchronous Partial Flag mode select Asynchronous Partial Flag mode. Queue almost full when PRAF goes during high transition WCLK. Default (Full-offset) programmed offset values determine status PRAF Queue almost empty when PRAE goes during high transition RCLK. Default (Empty +offset) programmed offset values determine status PRAE Queue more than half full when HALF goes low. Triggered both WCLK RCLK. connect. 3.3V power supply.
Almost Full
PRAF
Output
Almost Empty
PRAE
Output
04,09,20 36,44,51, 58,67 07,14,23, 30,33,39, 46,48,54,55,
Half Full Connect Power
HALF
Output
Ground
Ground.
Table Descriptions (Continued)
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FQV2113 FQV2103 FQV293 FQV283 FQV273 FQV263 FQV243 FlexQTMIII
Symbol VTERM TSTG IOUT
Rating Terminal Voltage with respect Storage Temperature Output Current
Com'l Ind'l -0.5 +125
Unit
NOTES:
Absolute Ratings reference only. Permanent damage device occur extended period operation outside this range. Standard operation should fall within Recommended Operating Conditions.
Table Absolute Maximum Ratings
FQV2113, FQV2103FQV293, FQV283 FQV273, FQV263, FQV253, FQV243 Commercial Clock 6ns, 7.5ns, 10ns, 15ns Industrial Clock 7.5ns, 10ns, 15ns
Symbol Parameter Recommended Operating Conditions
Supply Voltage Com'l Ind'l Supply Voltage Input High Voltage Com'l Ind'l Input Voltage Com'l Ind'l Operating Temperature Commercial Operating Temperature Industrial Input Leakage Current (any input) Output Leakage Current Output Logic Voltage, IOH=-2mA Output Logic Voltage, Active Power Supply Current Input Output) Active Power Supply Current (x18 Input Output) Standby Current
Min.
Typ.
Max.
Min.
Typ.
Max.
Unit
3.15
3.45
3.15
3.45
Electrical Characteristics
ILI(1)
Power Consumption
ICC1(2,3) ICC1(2,3) ICC2(4)
Table Specifications
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FQV2113 FQV2103 FQV293 FQV283 FQV273 FQV263 FQV243 FlexQTMIII
Capacitance 1.0MHz Ambient Temperature (25°C) Symbol Parameter
CIN(2) COUT(2,4)
NOTES:
Measurement with 0.4<=VIN<=Vcc. With output tri-stated High). Icc(1,2) measured with WCLK RCLK MHz. Design simulated, tested.
Conditions
VIN= VOUT=
Max.
Unit
Input Capacitance Output Capacitance
Table Specifications (Continued)
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FQV2113 FQV2103 FQV293 FQV283 FQV273 FQV263 FQV243 FlexQTMIII
Commercial FQV2113-6 FQV2103-6 FQV293-6 FQV283-6 FQV273-6 FQV263-6 FQV253-6 FQV243-6 Symbol tWCLK tWCLKH tWCLKL tRCLK tRCLKH tRCLKL tENS tENH tRST tRSTS tRSTR tRSTF tOLZ tOHZ tFULL tEMPTY tPRAFS tPRAES tSKEW1 tSKEW2 tLOADS tLOADH Parameter Clock Cycle Frequency Data Access Time Write Clock Cycle Time Write Clock High Time Write Clock Time Read Clock Cycle Time Read Clock High Time Read Clock Time Data Set-up Time Data Hold Time Enable Set-up Time Enable Hold Time Reset Pulse Width(1) Reset Set-up Time Reset Recovery Time Reset Flag Output Time Output Enable Output Low-Z(1) Output Enable Output Valid Output Enable Output High-Z Write Clock Full Flag Read Clock Empty Flag Write Clock Synchronous Almost-Full Flag Read Clock Synchronous Almost-Empty Flag Skew time between Read Clock Write Clock Full Flag Empty Flag Skew time between Read Clock Write Clock PRAE PRAF Load Setup Time Load Hold Time
Commercial Industrial FQV2113-7.5 FQV2103-7.5 FQV293-7.5 FQV283-7.5 FQV273-7.5 FQV263-7.5 FQV253-7.5 FQV243-7.5 Min. Max. FQV2113-10 FQV2103-10 FQV293-10 FQV283-10 FQV273-10 FQV263-10 FQV253-10 FQV243-10 Min. Max. FQV2113-15 FQV2103-15 FQV293-15 FQV283-15 FQV273-15 FQV263-15 FQV253-15 FQV243-15 Min. Max. Unit
Min.
Max.
Table Electrical Characteristics
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FQV2113 FQV2103 FQV293 FQV283 FQV273 FQV263 FQV243 FlexQTMIII
Commercial FQV2113-6 FQV2103-6 FQV293-6 FQV283-6 FQV273-6 FQV263-6 FQV253-6 FQV243-6 Symbol tRETS tHALF tPRAFA tPRAEA Parameter Retransmit Setup Time Clock HALF Write Clock Asynchronous Programmable Almost-Full Flag Read Clock Asynchronous Programmable Almost-Empty Flag
NOTES: Design simulated, tested. Table Electrical Characteristics (Continued)
Commercial Industrial FQV2113-7.5 FQV2103-7.5 FQV293-7.5 FQV283-7.5 FQV273-7.5 FQV263-7.5 FQV253-7.5 FQV243-7.5 Min. Max. 12.5 12.5 12.5 FQV2113-10 FQV2103-10 FQV293-10 FQV283-10 FQV273-10 FQV263-10 FQV253-10 FQV243-10 Min. Max. FQV2113-15 FQV2103-15 FQV293-15 FQV283-15 FQV273-15 FQV263-15 FQV253-15 FQV243-15 Min. Max. Unit
Min.
Max.
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FQV2113 FQV2103 FQV293 FQV283 FQV273 FQV263 FQV243 FlexQTMIII
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load, clock 6ns, 7.5ns Output Load clock 10ns,
3.0V 1.5V 1.5V Refer Figure Refer Figure
Include scope capacitances Table Test Condition
Vcc/2
3.3V
D.U.T. 30pF*
Figure Test Load clock 6ns, 7.5ns
Figure Output Load clock 10ns, 15ns *Includes scope capacitances.
(Typical,
Capacitance (pF)
Figure Lumped Capacitive Load
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FQV2113 FQV2103 FQV293 FQV283 FQV273 FQV263 FQV243 FlexQTMIII
Functions
MRST Master Reset required initialize Write Read pointers first position queue setting MRST low. Standard mode, FULL PRAF will high; EMPTY PRAE will low. FWFT mode, DRDY will QRDY will high. PRAF PRAE will same state Standard mode. both modes, data outputs will low. Previous programmed configurations will maintained. Partial Reset required initialize Write Read pointers first position queue setting PRST low. Standard mode, FULL PRAF will high; EMPTY PRAE will low. FWFT mode, DRDY will QRDY will high. PRAF PRAE will same state Standard mode. both modes, data outputs will low. Previous programmed configurations will maintained. Writes data into queue during high transitions WCLK activated. Synchronizes FULL DRDY PRAF flags. WCLK RCLK independent each other. Controls write operation into queue offset registers during high transition WCLK. During Master Reset, LOAD select parallel programming eight default offset values. LOAD high select serial programming eight default offset values. After Master Reset, LOAD controls write/read, to/from offset registers during high transition WCLK/RCLK respectively parallel programming. conjunction with During programming offset registers, PRAF PRAE flag status invalid. Serial programming, LOAD used enable serial loading offset registers together with SDEN Refer Figure Table details. During Master Reset, select eight default-offset values. conjunction with LOAD PFS0. Refer Table details. During Master Reset, select eight default-offset values. conjunction with LOAD PFS1. Refer Table details. wide input data bus. Reads data from queue during high transitions RCLK low. Synchronizes EMPTY QRDY PRAE flags. RCLK WCLK independent each other. Reads data from queue offset registers during high transitions RCLK low. This also advances Read pointer queue. Setting activates data output drivers. Setting high deactivates data output drivers (High-Z). does control advancement Read pointer. wide output data bus. Selects FWFT timing Standard timing mode during Master Reset. After Master Reset, serial programming selected LOAD high), FWFT/SDI used serial data input offset registers. Serial data written during high transition WCLK. conjunction with SDEN FWFT mode, DRDY QRDY used instead FULL EMPTY Refer Table flags status. Standard mode, FULL EMPTY used instead DRDY QRDY Refer Table flags status. serial programming selected, setting SDEN LOAD enables serial data written into offset registers during high transition WCLK. During serial programming, PRAF PRAE flags status invalid. Refer Figure details.
PRST
WCLK
LOAD
PFS1
PFS0 D17-0 RCLK
Q17-0 FWFT/SDI
SDEN
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FQV2113 FQV2103 FQV293 FQV283 FQV273 FQV263 FQV243 FlexQTMIII
Functions (Continued)
During Master Reset, setting selects input width. high selects input width. Refer Table details. During Master Reset, select output width. high select output width. Refer Table details. During Master Reset, high select byte re-ordering data outputs select byte re-ordering data outputs. must static throughout device operation. Refer Table details. Data previously read from queue retransmitted asserting high transition RCLK retransmit operation. Retransmit initializes Read pointer zero. Hence, re-reads will always start from physical (Read pointer zero), location queue. Refer Diagram details. During Master Reset, RETZL select zero latency retransmit RETZL high select normal latency retransmit. Standard mode, queue full when FULL goes during high transition WCLK. This prohibits further writes into queue prevents advancement Write pointer. FWFT mode, queue full when DRDY goes high during high transition WCLK. This prohibits further writes into queue prevents advancement Write pointer. Refer Table behavior FULL DRDY Standard mode, queue empty when EMPTY goes during high transition RCLK. This prohibits further reads from queue prevents advancement Read pointer. FWFT mode, queue empty when QRDY goes high during high transition RCLK. This prohibits further reads from queue prevents advancement Read pointer. Refer Table behavior EMPTY QRDY During Master Reset, IPAR select 9-bit parallel programming mode IPAR high select 8-bit parallel programming mode. 9-bit mode, 9-bit wide data input/output width used storing/fetching offset values. 8-bit mode, 8-bit wide data input/output used storing/fetching offset values. During Master Reset, high select Synchronous Partial Flag mode select Asynchronous Partial Flag mode. Synchronous mode, PRAF PRAE synchronous WCLK RCLK respectively. Asynchronous mode, WCLK synchronizes assertion PRAF deassertion PRAE RCLK synchronizes assertion PRAE de-assertion PRAF Synchronous mode, queue almost full when PRAF goes during high transition WCLK. Default (Full-offset) programmed offset values determine status PRAF Asynchronous mode, PRAF triggered both WCLK RCLK. Refer Table behavior PRAF Synchronous mode, queue almost empty when PRAE goes during high transition RCLK. Default (Empty+offset) programmed offset values determine status PRAE Asynchronous timing mode, PRAE triggered both WCLK RCLK. Refer Table behavior PRAE Queue more than half full when HALF goes during high transition WCLK. HALF goes high during high transition RCLK when queue less than half full. Refer Table details.
RETZL FULL DRDY
EMPTY QRDY
IPAR
PRAF
PRAE
HALF
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FQV2113 FQV2103 FQV293 FQV283 FQV273 FQV263 FQV243 FlexQTMIII
LOAD
SDEN
WCLK
RCLK
FQV283 FQV273 FQV263 FQV253 FQV243 Selection Sequence Parallel write offset registers: Empty Offset (Low Byte) Empty Offset (High Byte) Full Offset (Low Byte) Full Offset (High Byte) Parallel read from offset registers: Empty Offset (Low Byte) Empty Offset (High Byte) Full Offset (Low Byte) Full Offset (High Byte) Mode Serial shift into registers: bits FQV283 bits FQV273 bits FQV263 bits FQV253 bits FQV243 each rising WCLK edge Starting with Empty Offset (Low Byte) Ending with Full Offset (High Byte) Operation Write Memory Parallel write registers: PRAE Byte PRAE High Byte PRAF Byte PRAF High Byte Parallel read from registers: PRAE Byte PRAE High Byte PRAF Byte PRAF High Byte Other Modes Serial shift into registers: bits FQV283 bits FQV273 bits FQV263 bits FQV253 bits FQV243 each rising WCLK edge Starting with Empty Offset (Low Byte) Ending with Full Offset (High Byte)
Read Memory Operation
Figure Programmable Flag Offset Programming Sequence (FQV283, FQV273, FQV263, FQV253 FQV243)
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FQV2113 FQV2103 FQV293 FQV283 FQV273 FQV263 FQV243 FlexQTMIII
LOAD
SDEN
WCLK
RCLK
FQV2113 FQV2103 FQV293 Selection Sequence Parallel write offset registers: Empty Offset (Low Byte) Empty Offset (Mid Byte) Empty Offset (High Byte) Full Offset (Low Byte) Full Offset (Mid Byte) Full Offset (High Byte) Parallel read from offset registers: Empty Offset (Low Byte) Empty Offset (Mid Byte) Empty Offset (High Byte) Full Offset (Low Byte) Full Offset (Mid Byte) Full Offset (High Byte) Mode Serial shift into registers: bits FQV2113 bits FQV2103 bits FQV293 each rising WCLK edge Starting with Empty Offset (Low Byte) Ending with Full Offset (High Byte) Operation Write Memory Parallel write registers: PRAE Byte PRAE Byte PRAE High Byte PRAF Byte PRAF Byte PRAF High Byte Parallel read from registers: PRAE Byte PRAE Byte PRAE High Byte PRAF Byte PRAF Byte PRAF High Byte Other Modes Serial shift into registers: bits FQV2113 bits FQV2103 bits FQV293 each rising WCLK edge Starting with Empty Offset (Low Byte) Ending with Full Offset (High Byte)
Read Memory Operation
Figure Programmable Flag Offset Programming Sequence (FQV2113, FQV2103, FQV293)
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FQV2113 FQV2103 FQV293 FQV283 FQV273 FQV263 FQV243 FlexQTMIII
Device FQV2113 FQV2103 FQV293 FQV283 FQV273 FQV263 FQV253 FQV243 D/Q15
PRAF Programming (bits)
Non-IPAR IPAR Non-IPAR IPAR Non-IPAR IPAR Non-IPAR IPAR Non-IPAR IPAR Non-IPAR IPAR Non-IPAR IPAR Non-IPAR IPAR D/Q15 D/Q16 D/Q7 D/Q15 D/Q16 D/Q7 D/Q15 D/Q16 D/Q7 D/Q14 D/Q15 D/Q7 D/Q13 D/Q14 D/Q7 D/Q12 D/Q13 D/Q7 D/Q11 D/Q12 D/Q7 D/Q10 D/Q11 D/Q7
PRAE Programming (bits)
Non-IPAR IPAR Non-IPAR IPAR Non-IPAR IPAR Non-IPAR IPAR Non-IPAR IPAR Non-IPAR IPAR Non-IPAR IPAR Non-IPAR IPAR D/Q16 D/Q7 D/Q15 D/Q16 D/Q7 D/Q15 D/Q16 D/Q7 D/Q14 D/Q15 D/Q7 D/Q13 D/Q14 D/Q7 D/Q12 D/Q13 D/Q7 D/Q11 D/Q12 D/Q7 D/Q10 D/Q11 D/Q7
Condition Applies Write Cycle with input Width and/or Read Cycle with output Width
Device FQV2113
PRAF Programming (bits)
D/Q7 D/Q7 D/Q1 D/Q7 Byte Byte High Byte Byte Byte High Byte Byte High Byte Byte High Byte Byte High Byte Byte High Byte Byte High Byte Byte High Byte
PRAE Programming (bits)
D/Q7 D/Q7 D/Q1 D/Q7 D/Q7 D/Q7 D/Q7 D/Q7 D/Q6 D/Q7 D/Q5 D/Q7 D/Q4 D/Q7 D/Q3 D/Q7 D/Q2 Byte Byte High Byte Byte Byte High Byte Byte High Byte Byte High Byte Byte High Byte Byte High Byte Byte High Byte Byte High Byte
FQV2103
D/Q7 D/Q0 D/Q7 D/Q7 D/Q7 D/Q6 D/Q7 D/Q5 D/Q7 D/Q4 D/Q7 D/Q3 D/Q7 D/Q2
FQV293 FQV283 FQV273 FQV263 FQV253 FQV243
Condition Applies Write Cycle with input Width Read Cycle with output Width (except mode)
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FQV2113 FQV2103 FQV293 FQV283 FQV273 FQV263 FQV243 FlexQTMIII
Device FQV2113
PRAF Programming (bits)
D/Q7 D/Q7 D/Q2 D/Q7 Byte Byte High Byte Byte Byte High Byte Byte Byte High Byte Byte High Byte Byte High Byte Byte High Byte Byte High Byte Byte High Byte
PRAE Programming (bits)
D/Q7 D/Q7 D/Q2 D/Q7 D/Q7 D/Q1 D/Q7 D/Q7 D/Q0 D/Q7 D/Q7 D/Q7 D/Q6 D/Q7 D/Q5 D/Q7 D/Q4 D/Q7 D/Q3 Byte Byte High Byte Byte Byte High Byte Byte Byte High Byte Byte High Byte Byte High Byte Byte High Byte Byte High Byte Byte High Byte
FQV2103
D/Q7 D/Q1 D/Q7
FQV293
D/Q7 D/Q0 D/Q7 D/Q7 D/Q7 D/Q6 D/Q7 D/Q5 D/Q7 D/Q4 D/Q7 D/Q3
FQV283 FQV273 FQV263 FQV253 FQV243
Condition Applies Write Cycle with input Width Read Cycle with output Width (only mode) Table Parallel Offset Write/Read Cycle Register Location
Device
FQV2113 FQV2103 FQV293 FQV283 FQV273 FQV263 FQV253 FQV243
Standard Mode
262,144 524,288 131,072 262,144 65,536 131,072 32,768 65,536 16,384 32,768 8,192 16,384 4,096 8,192 2,048 4,096
FWFT Mode
262,145 524,289 131,073 262,145 65,537,x 131,073 32,769 65,537 16,385 32,769 8,193 16,385 4,097 8,193 2,049 4,097
Table Maximum Depth Queue Standard FWFT Mode
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FQV2113 FQV2103 FQV293 FQV283 FQV273 FQV263 FQV243 FlexQTMIII
Data Width Cycle PRAE Byte Cycle PRAE High Byte
D/Q8 D/Q7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0
Cycle PRAF Byte Cycle PRAF High Byte
FQV293, FQV283, FQV273, FQV263, FQV253, FQV243 Parallel Offset Write/Read Cycles Width Condtion Applies Write Cycle with input Width and/or Read Cycle output with Width (except FQV293 mode)
Data Width Cycle PRAE Byte Cycle PRAE Byte Cycle PRAE High Byte
D/Q8 D/Q7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0
Cycle PRAF Byte Cycle PRAF Byte Cycle PRAF High Byte
FQV2113, FQV2103, FQV293 Parallel Offset Write/Read Cycles Width Condtion Applies FQV293 mode FQV2113, FQV2103 modes
Mode Bits Offset Registers bits FQV2113 bits FQV2103 bits FQV293 bits FQV283 bits FQV273 bits FQV263 bits FQV253 bits FQV243 Note: Don't Care applies unused bits
Other Modes Bits Offset Registers bits FQV2113 bits FQV2103 bits FQV293 bits FQV283 bits FQV273 bits FQV263 bits FQV253 bits FQV243 Note: Don't Care applies unused bits
Figure Parallel Offset Write/Read Cycle Diagram
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FQV2113 FQV2103 FQV293 FQV283 FQV273 FQV263 FQV243 FlexQTMIII
Data Width Cycle PRAE Non-Interspersed Parity Interspersed Parity
D/Q17 D/Q16 D/Q15 D/Q14 D/Q13 D/Q12 D/Q11 D/Q10
D/Q9
D/Q8
D/Q7
D/Q6
D/Q5
D/Q4
D/Q3
D/Q2
D/Q1
D/Q0
Data Width Cycle PRAF Non-Interspersed Parity Interspersed Parity
D/Q17 D/Q16 D/Q15 D/Q14 D/Q13 D/Q12 D/Q11 D/Q10
D/Q9
D/Q8
D/Q7
D/Q6
D/Q5
D/Q4
D/Q3
D/Q2
D/Q1
D/Q0
FQV293, FQV283, FQV273, FQV263, FQV253, FQV243 Parallel Offset Write/Read Cycles Width Condtion Applies Write Cycle with input Width and/or Read Cycle output Width
Data Width Cycle PRAE Non-Interspersed Parity Interspersed Parity Cycle PRAE Non-Interspersed Parity Interspersed Parity Cycle PRAF Non-Interspersed Parity Interspersed Parity Cycle PRAF Non-Interspersed Parity Interspersed Parity
D/Q17 D/Q16 D/Q15 D/Q14 D/Q13 D/Q12 D/Q11 D/Q10
D/Q9
D/Q8
D/Q7
D/Q6
D/Q5
D/Q4
D/Q3
D/Q2
D/Q1
D/Q0
FQV2113, FQV2103 Parallel Offset Write/Read Cycles Width Condtion Applies Write Cycle with input Width and/or Read Cycle output Width
Figure Parallel Offset Write/Read Cycles Diagram (Continued)
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FQV2113 FQV2103 FQV293 FQV283 FQV273 FQV263 FQV243 FlexQTMIII
FQV2113
y(1) (y+1) 262,144 262,145 [524,288-(x+1)] (524,288 -x(1)) 524,287 524,288
FULL
PRAF
HALF
PRAE
EMPTY
FQV2103
FQV2113
(y+1) 131,072 131,073 [262,144-(x+1)] (262,144 262,143 262,144
FULL
PRAF
HALF
PRAE
EMPTY
FQV293
FQV2103
(y+1) 65,536 65,537 [131,072-(x+1)] (131,072 131,071 131,072
FULL
PRAF
HALF
PRAE
EMPTY
FQV283
FQV293
(y+1) 32,768 32,769 [65,536-(x+1)] (65,536 65,535 65,536
FULL
PRAF
HALF
PRAE
EMPTY
FQV273
FQV283
(y+1) 16,384 16,385 [32,768-(x+1)] (32,768 32,767 32,768
FULL
PRAF
HALF
PRAE
EMPTY
NOTES:
Table values
Table Status Flags (Standard Mode)
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FQV2113 FQV2103 FQV293 FQV283 FQV273 FQV263 FQV243 FlexQTMIII FQV263
FQV273
(y+1) 8,192 8,193 [16,384-(x+1)] (16,384 16,383 16,384
FULL
PRAF
HALF
PRAE
EMPTY
FQV253
FQV263
(y+1) 4,096 4,097 [8,192-(x+1)] (8,192 8,191 8,192
FULL
PRAF
HALF
PRAE
EMPTY
FQV243
FQV253
(y+1) 2,048 2,049 [4,096-(x+1)] (4,096 4,095 4,096
FULL
PRAF
HALF
PRAE
EMPTY
FQV243 (y+1) 1,024 1,025 [2,048-(x+1)] (2,048-x) 2,047 2,048
NOTES:
Table values
FULL
PRAF
HALF
PRAE
EMPTY
Table Status Flags (Standard Mode) (Continued)
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FQV2113 FQV2103 FQV293 FQV283 FQV273 FQV263 FQV243 FlexQTMIII
FQV2113
y+1(1) (y+2) 262,145 262,146 [524,289-(x+1)] (524,289-x(1)) 524,288 524,289
DRDY
PRAF
HALF
PRAE
QRDY
FQV2103
FQV2113
(y+2) 131,073 131,074 [262,145-(x+1)] (262,145-x) 262,144 262,145
DRDY
PRAF
HALF
PRAE
QRDY
FQV293
FQV2103
(y+2) 65,537 65,538 [131,073-(x+1)] (131,073-x) 131,072 131,073
DRDY
PRAF
HALF
PRAE
QRDY
FQV283
FQV293
(y+2) 32,769 32,770 [65,537-(x+1)] (65,537 65,536 65,537
DRDY
PRAF
HALF
PRAE
QRDY
FQV273
FQV283
(y+2) 16,385 16,386 [32,769-(x+1)] (32,769-x) 32,768 32,769
DRDY
PRAF
HALF
PRAE
QRDY
NOTES: Table values Table Status Flags (FWFT Mode)
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FQV2113 FQV2103 FQV293 FQV283 FQV273 FQV263 FQV243 FlexQTMIII FQV263
FQV273
(y+2) 8,193 8,194 [16,385-(x+1)] (16,385 16,384 16,385
DRDY
PRAF
HALF
PRAE
QRDY
FQV253
FQV263
(y+2) 4,097 4,098 [8,193-(x+1)] (8,193 8,192 8,193
DRDY
PRAF
HALF
PRAE
QRDY
FQV243
FQV253
(y+2) 2,049 2,050 [4,097-(x+1)] (4,097-x) 4,096 4,097
DRDY
PRAF
HALF
PRAE
QRDY
FQV243
(y+2) 1,025 1,026 [2,049 -(x+1)] (2,049 2,048 2,049
NOTES:
Table values
DRDY
PRAF
HALF
PRAE
QRDY
Table Status Flags (FWFT Mode) (Continued)
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FQV2113 FQV2103 FQV293 FQV283 FQV273 FQV263 FQV243 FlexQTMIII
Width
D/Q17
Byte Byte Byte
D/Q8
Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte
Sequence
Write Read Write Read Read Write Write Read Write Write Read Read Write Read Write Read Read Write Read Read
Byte
Byte Byte Byte
Byte
Table Bus-Matching Table
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FQV2113 FQV2103 FQV293 FQV283 FQV273 FQV263 FQV243 FlexQTMIII
LOAD
PFS0
PFS1
FQV243 Offsets Other Modes Mode
1,023 Serial Parallel
FQV273 FQV263 FQV253 Offsets
1,023
LOAD
PFS0
PFS1
FQV283 Offsets Other Modes Mode
16,383 8,191 4,095 1,023 2,047 Serial Parallel
FQV2113 FQV2103 FQV293 Offsets
16,383 8,191 4,095 1,023 2,047
NOTES:
1,023
PRAF offset, PRAE offset.
Table Default Programmable Flag Offsets
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FQV2113 FQV2103 FQV293 FQV283 FQV273 FQV263 FQV243 FlexQTMIII
Timing Diagrams
tRST MRST tRSTS tRSTS tRSTS FWFT/SDI tRSTS LOAD tRSTS PFS1/PFS0 tRSTS BM1/BM0 tRSTS tRSTS RETZL tRSTS tRSTS IPAR tRSTS
tRSTR
tRSTR
tRSTR
tRSTR
tRSTS SDEN tRSTF FWFT 1,QRDY EMPTY QRDY tRSTF FWFT FULL FULL DRDY tRSTF PRAE tRSTF PRAF HALF tRSTF Q17- FWFT DRDY FWFT EMPTY
Diagram Master Reset Timing
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FQV2113 FQV2103 FQV293 FQV283 FQV273 FQV263 FQV243 FlexQTMIII
tRST PRST tRSTS tRSTS tRSTS tRSTS SDEN tRSTF FWFT 1,QRDY
EMPTY QRDY
tRSTR
tRSTR
FWFT EMPTY tRSTF FWFT FULL
FULL DRDY tRSTF
PRAE
FWFT DRDY
tRSTF
PRAF HALF
tRSTF
Diagram Partial Reset Timing
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tWCLK tWCLKH tWCLKL Write
3F30918C
Write
Write
WCLK
tFULL tFULL tFULL tSKEW1
tSKEW1
tFULL
FULL
RCLK
tENH tENS tENH
tENS
Data Read Next Data Read
2003 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
Output Register Data
NOTES:
time between rising edge RCLK rising edge WCLK greater equal than tSKEW1, FULL will high (after WCLK cycle plus tFULL). tSKEW1 met, then FULL will assert more WCLK cycles.
LOAD High, Low.
Diagram Write Cycle Full Flag Timing (Standard Mode)
FQV2113 FQV2103 FQV293 FQV283 FQV273 FQV263 FQV243 FlexQTMIII
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3F30918C
tRCLK tRCLKH
tRCLKL
RCLK tENH tENS Operation Operation tENH tENS tENH
tENS
tEMPTY tEMPTY tEMPTY
EMPTY Last Word tOHZ tOLZ Last Word
tOLZ
tSKEW1
WCLK tENS tENH tENS tENH
2003 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
NOTES:
time between rising edge WCLK rising edge RCLK greater equal than tSKEW1, EMPTY will high (after RCLK cycle plus tEMPTY). tSKEW1 met, then EMPTY will assert more RCLK cycles.
LOAD High. First word latency: tSKEW1 tEMPTY tRCLK.
Diagram Read Cycle, Empty Flag First Data Word Latency Timing (Standard Mode)
FQV2113 FQV2103 FQV293 FQV283 FQV273 FQV263 FQV243 FlexQTMIII
JANUARY 2003
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3F30918C
tSKEW2 DW[y+2] DW[y+3] DW[y+4] DW[(D-1)/2+1] DW[(D-1)/2+2] DW[(D-1)/2+3] DW[D-x-1] DW[D-x] DW[D-x+1] DW[D-x+2] DW[D-x+3] DW[D-1] tENH tEMPTY tPRAES tHALF tPRAFS tFULL
WCLK
tENS
tSKEW1
RCLK
Output Register Data
QRDY
PRAE
HALF
2003 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
PRAF
DRDY
NOTES:
time between rising edge WCLK rising edge RCLK greater equal than tSKEW1, QRDY will (after RCLK cycle plus tEMPTY). tSKEW1 met, then QRDY will assert more RCLK cycles.
time between rising edge WCLK rising edge RCLK greater equal than tSKEW2, PRAE will high (after RCLK cycle plus tPRAES). tSKEW2 met, then PRAE will assert more RCLK cycles.
LOAD High, Low.
PRAE offset, PRAF offset. maximum queue depth. Please refer Table Depth. First word latency: tSKEW1 tEMPTY tRCLK
Diagram Write Timing (FWFT Mode)
FQV2113 FQV2103 FQV293 FQV283 FQV273 FQV263 FQV243 FlexQTMIII
JANUARY 2003
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3F30918C
tSKEW2 tENS
DWx+2 DW[(D-1)/2+2]
WCLK
tENS
tENH
tSKEW1
RCLK
tENS
DWx+1 DWx+3 DW[(D-1)/2+1] DW[D-y-1] DW[D-y] DW[D-y+1] DW[D-y+2] DW[D-1] tEMPTY
tOHZ
QRDY tPRAES
PRAE tHALF
HALF tPRAFS
2003 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
tFULL
PRAF
tFULL
DRDY
NOTES:
time between rising edge RCLK rising edge WCLK greater equal than tSKEW1, DRDY will (after WCLK cycle plus tFULL) tSKEW1 met, then DRDY will assert more WCLK cycles.
time between rising edge RCLK rising edge WCLK greater equal than tSKEW2, PRAF will high (after WCLK cycle plus tPRAFS) tSKEW2 met, then PRAF will assert more WCLK cycles.
LOAD High
PRAE Offset, PRAF offset. maximum queue depth. Please refer Table Depth.
FQV2113 FQV2103 FQV293 FQV283 FQV273 FQV263 FQV243
FlexQTMIII
JANUARY 2003
Page
Diagram Read Timing (FWFT Mode)
FQV2113 FQV2103 FQV293 FQV283 FQV273 FQV263 FQV243 FlexQTMIII
RCLK tENS
tENH tRETS tENS
tENH
tSKEW2 WCLK tRETS
DWi+1
tENS
tENH
tEMPTY
EMPTY
tEMPTY
tPRAES
PRAE
tHALF
HALF
tPRAFS
PRAF
NOTES:
Upon completion retransmit setup, read operation begin only after EMPTY returns high. Low. Words written queue after MRST Where 1,2,3. depth. Upon reset completion, there must more than words written queue retransmit setup valid.
Diagram Retransmit Timing (Standard Mode)
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FQV2113 FQV2103 FQV293 FQV283 FQV273 FQV263 FQV243 FlexQTMIII
RCLK tENS tENH tRETS
tENS
tENH
DWi+1 tSKEW2 WCLK tRETS tENS tEMPTY
QRDY
tENH
tEMPTY
tPRAES PRAE tHALF
HALF
tPRAFS PRAF
NOTES:
Upon completion retransmit setup, read operation begin only after QRDY returns low. Low. Words written queue after MRST Where 1,2,3. depth. Upon reset completion, there must more than words written queue retransmit setup valid. Please refer Table Depth.
Diagram Retransmit Timing (FWFT Mode)
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FQV2113 FQV2103 FQV293 FQV283 FQV273 FQV263 FQV243 FlexQTMIII
RCLK tENS DWi+1
tENH
tSKEW2
WCLK tRETS tENS
tENH
EMPTY
tPRAES
PRAE
tHALF
HALF
tPRAFS
PRAF
NOTES:
part empty point retransmit, Empty Flag EMPTY will updated based RCLK (Retransmit Clock cycle). Valid data will appear output. Low; enables data read outputs DW1= first word written queue after Master Reset; DW2= second word written queue after Master Reset. more than written queue between reset (Master Partial) retransmit setup. Therefore, FULL will high throughout retransmit setup procedure. Please refer Table Depth. There must least words written zero latency retransmit from queue before retransmit operation invoked. RETZL during MRST
Diagram Zero Latency Retransmit Timing (Standard Mode)
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FQV2113 FQV2103 FQV293 FQV283 FQV273 FQV263 FQV243 FlexQTMIII
RCLK tENS
tENH
tSKEW2
WCLK tRETS tENS
tENH
QRDY tPRAES PRAE tHALF
HALF
tPRAFS
PRAF
NOTES:
part empty point retransmit, output ready flag QRDY will updated based RCLK (Retransmit Clock cycle). Valid data will appear output. more than words written queue between reset (Master Partial) retransmit setup. Therefore, DRDY will throughout retransmit setup procedure. Please refer Table Depth. Low. DW1, DW2, first, second third words written queue after Master Reset. There must least words written queue before retransmit operation invoked. RETZL during MRST
Diagram Zero Latency Retransmit Timing (FWFT Mode)
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FQV2113 FQV2103 FQV293 FQV283 FQV273 FQV263 FQV243 FlexQTMIII
WCLK tENS SDEN tLOADS
LOAD
tENH
tENH
tLOADH
tLOADH
PRAE Offset
PRAF Offset
*Refer Table
Diagram Serial Loading Programmable Flag Registers (Standard FWFT Mode)
FQV21113 Other Modes
FQV2103
FQV293
FQV283
FQV273
FQV263
FQV253
FQV243
Table Reference Table Diagram
3F30918C 2003 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
JANUARY 2003
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FQV2113 FQV2103 FQV293 FQV283 FQV273 FQV263 FQV243 FlexQTMIII
tWCLK tWCLKH WCLK tLOADS
LOAD
tWCLKL
tLOADH
tLOADH
tENS
tENH
tENH
PRAE offset (Low Byte)
PRAE offset (High Byte)
PRAF offset (Low Byte)
PRAF offset (High Byte)
NOTES:
Based programming width. width, extra cycle both PRAE PRAF offsets.
Diagram Parallel Loading Programmable Flag Registers (Standard FWFT Mode)
tRCLK tRCLKH RCLK tLOADS
LOAD
tRCLKL
tLOADH
tLOADH
tENS
tENH
tENH
Data Output Register PRAE offset (Low Byte)
PRAE offset (High Byte)
PRAF offset (Low Byte)
PRAF offset (High Byte)
NOTES:
Based programming width. width, extra cycle both PRAE PRAF offsets.
Diagram Parallel Read Programmable Flag Registers (Standard FWFT Mode)
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FQV2113 FQV2103 FQV293 FQV283 FQV273 FQV263 FQV243 FlexQTMIII
tWCLKH
WCLK
tWCLKL tENS tENH tPRAFS
words Queue words Queue
tPRAFS
words Queue
PRAF
tSKEW2
RCLK
tENS
tENH
NOTES:_
PRAF offset. maximum queue depth. Please refer Table Depth. time between rising edge RCLK rising edge WCLK greater equal than tSKEW2, PRAF will high (after WCLK cycle plus tPRAFS). tSKEW2 met, then PRAF will assert more WCLK cycles. PRAF synchronizes rising edge WCLK only.
Diagram Synchronous Programmable Almost-Full Flag Timing (Standard FWFT Mode)
tWCLKH
WCLK
tWCLKL
tENS
tENH
PRAE
words Queue(2) words Queue(3) tSKEW2 tPRAES
words Queue(2) words Queue(3) tPRAES tENS tENH
words Queue(2) words Queue(3)
RCLK
NOTES:_
PRAE offset. Standard Mode. FWFT Mode. time between rising edge WCLK rising edge RCLK greater equal than tSKEW2, PRAE will high (after RCLK cycle plus tPRAES). tSKEW2 met, then PRAE will assert more RCLK cycles. PRAE synchronizes rising edge RCLK only.
Diagram Synchronous Programmable Almost-Empty Flag Timing (Standard FWFT Mode)
3F30918C 2003 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
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FQV2113 FQV2103 FQV293 FQV283 FQV273 FQV263 FQV243 FlexQTMIII
tWCLKH WCLK tENS
tWCLKL
tENH
tPRAFA PRAF words Queue words Queue tPRAFA RCLK tENS tENH words Queue
NOTES:_
PRAF offset. maximum queue depth. Please refer Table Depth. PRAF asserted WCLK transition reset high RCLK transition. Select this mode setting during Master Reset.
Diagram Asynchronous Programmable Almost-Full Flag Timing (Standard FWFT Mode)
tWCLKH WCLK tENS
tWCLKL
tENH
tPRAEA PRAE
words Queue(2); words Queue(3) words Queue(2); words Queue words Queue(2); words Queue(3)
tPRAEA
RCLK tENS tENH
NOTES:_
PRAE offset. Standard Mode. FWFT Mode. PRAE asserted RCLK transition reset high WCLK transition. Select this mode setting during Master Reset.
Diagram Asynchronous Programmable Almost-Empty Flag Timing (Standard FWFT Mode)
3F30918C 2003 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
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FQV2113 FQV2103 FQV293 FQV283 FQV273 FQV263 FQV243 FlexQTMIII
tWCLKH WCLK tENS
tWCLKL
tENH
tHALF HALF words Queue(1); [(D+1)/2] words Queue(2)
words Queue(1); [(D+1)/2 words Queue(2) tHALF
words Queue(1); [(D+1)/2] words Queue(2)
RCLK tENS tENH
NOTES:
Standard Mode. FWFT Mode. Please refer Table Depth.
Diagram Half-Full Flag Timing (Standard FWFT Mode)
3F30918C 2003 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
JANUARY 2003
Page
FQV2113 FQV2103 FQV293 FQV283 FQV273 FQV263 FQV243 FlexQTMIII
Order Information:
Device Family Device Type XXXXX V2113 (524,288 (262,144 V2103 (262,144 (131,072 V293 V283 V273 V263 V253 V243 (131,072 (65,536 (65,536 (32,768 (32,768 (16,384 (16,384 (8,192 (8,192 (4,096 (4,096 (2,048 *Speed available only Commercial temp (0°C 70°C). Slower speeds available upon request. **Package Plastic Thin Quad Flat Pack (TQFP) Example: FQV283L6PF FQV273L10PFI (64k 6ns, Commercial temp) (32k 10ns, Industrial temp) Power Speed (ns) Package** Temperature Range Blank Commercial (0°C 70°C) Industrial (-40° 85°C)
Document Revision History:
02/26/03
2107 North First Street, Suite Jose, 95131, www.hba.com
3F30918C
Tel: 408.453.8885 Fax: 408.453.8886
Taiwan Suite 8F-9, Shui-Lee Hsinchu, Taiwan, R.O.C. www.hba.com
Tel: 886.3.516.9118 Fax: 886.3.516.9181
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2003 High Bandwidth Access, Inc. rights reserved. Product specifications subject change without notice.
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