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Document Title CMOS DYNAMIC WITH PAGE MODE Revision History CMOS


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A42U0616 Series
Document Title CMOS DYNAMIC WITH PAGE MODE Revision History
CMOS DYNAMIC WITH PAGE MODE
History
Initial issue
Issue Date
June 2001
Remark
(June, 2001, Version 0.0)
AMIC Technology, Inc.
A42U0616 Series
Features
Organization: 1,048,576 words bits Part Identification A42U0616 Ref.) Single 2.5V power supply/built-in generator power consumption Operating: 120mA (-50 max) Standby: (TTL), 0.2mA (CMOS), 250µA (Self-refresh current) High speed 50/60/80 access time 25/30/40 column address access time 13/15/20 access time 20/25/35 Page Mode Cycle Time Separate UCAS LCAS byte selection Fast Page Mode with Extended Data Read-modify-write, -only, -before- Hidden refresh capability TTL-compatible, three-state JEDEC standard packages 400mil, 42-pin 400mil, 50/44 TSOP type package
CMOS DYNAMIC WITH PAGE MODE
General Description
A42U0616 generation randomly accessed memory graphics, organized 1,048,576 -word 16-bit configuration. This product execute Write Read operation pin. A42U0616 offers accelerated Fast Page Mode cycle with feature called Extended Data (EDO). This allow random access 1024(1K Ref.) words within 50/40/28 cycle, making A42U0616 ideally suited graphics, digital signal processing high performance computing systems.
Configuration TSOP Descriptions
LCAS UCAS
LCAS UCAS
Symbol I/O0 I/O15
Description Address Inputs product) Data Input/Output Address Strobe Column Address Strobe Lower Byte (I/O0 I/O7)
A42U0616S
A42U0616V
LCAS UCAS
Column Address Strobe Upper Byte (I/O8 I/O15) Write Enable Output Enable 2.5V Power Supply Ground Connection
PRELIMINARY
(June, 2001, Version 0.0)
AMIC Technology, Inc.
A42U0616 Series
Selection Guide
Symbol tRAC tCAC tOEA Description Maximum Access Time Maximum Column Address Access Time Maximum Access Time Maximum Output Enable Access Time Minimum Read Write Cycle Time Minimum Cycle Time Unit
Functional Description
A42U0616 reads writes data multiplexing 20-bit address into 10-bit 10-bit column address. used strobe address column address, respectively. A42U0616 inputs: LCAS controls I/O0I/O7, UCAS controls I/O8 I/O15, UCAS LCAS function identical manner that either will generate internal signal. function timing determined first UCAS LCAS transition last transition high. Byte Read Byte Write controlled using LCAS UCAS separately. Read cycle performed holding signal high during RAS/ operation. Write cycle executed holding signal during RAS/ operation; input data latched falling edge whichever occurs later. data inputs outputs routed through common pins, with RAS, controlling direction. Page Mode operation 1024(1K) columns within selected randomly accessed high data rate. Page Mode cycle initiated with address latched followed column address latched While holding low, toggled strobe changing column addresses, thus achieving shorter cycle times. A42U0616 offers accelerated Fast Page Mode cycle through feature called Extended Data Out, which keeps output drivers during precharge time (tcp). Since data output after goes high, user required wait valid data appear before starting next access cycle. Data-out will remain valid long low, high; this only characteristic which differentiates Extended Data operation from standard Read Fast Page Read. memory cycle terminated returning both high. Memory cell data will retain correct state maintaining power accessing 1024(1K) combinations 10-bit addresses, regardless sequence, least once every 16ms through cycle (Read, Write) Refresh cycle (RAS -only, CBR, Hidden). Refresh cycle automatically controls addresses invoking refresh counter controller.
Power-On
initial application supply requires wait followed minimum eight initialization cycles containing clock. During Power-On, current dependent input levels recommended that track with held valid during Power-On avoid current surges.
PRELIMINARY
(June, 2001, Version 0.0)
AMIC Technology, Inc.
A42U0616 Series
Block Diagram
UCAS LCAS
Control Clocks
Generator
Refresh Timer
Decoder
Lower Data Buffer
Refresh Counter
Memory Array 1,048,576 Cells
Sense Amps
Refresh control
Lower Data Buffer
Upper Data Buffer
A0~A9
Address Buffer Upper Data Buffer
A0~A9
Col. Address Buffer
Column Decoder
Recommended Operating Conditions
Symbol Description Power Supply Input High Voltage Input High Voltage Input Voltage
+70°C) Min. 2.25 -1.0 Typ. Max. 2.75 Unit
PRELIMINARY
(June, 2001, Version 0.0)
AMIC Technology, Inc.
A42U0616 Series
Truth Table
Function Standby Read: Word Read: Lower Byte
UCAS
LCAS
Address Row/Col. Row/Col.
I/Os High-Z Data I/O0-7 Data I/O8-15 High-Z
Notes
Read: Upper Byte
Row/Col.
I/O0-7 High-Z I/O8-15 Data
Write: Word Write: Lower Byte
Row/Col. Row/Col.
Data I/O0-7 Data I/O8-15
Write: Upper Byte
Row/Col.
I/O0-7 I/O8-15 Data Data Data Data Data Data Data Data Data Data Data Data Data High-Z High-Z High-Z High-Z
Read-Write EDO-Page-Mode Read: Hi-Z -First cycle -Subsequent Cycles EDO-Page-Mode Write -First cycle -Subsequent Cycles EDO-Page-Mode Read-Write -First cycle -Subsequent Cycles Hidden Refresh Read Hidden Refresh Write RAS-Only Refresh Refresh Self Refresh Note:
Row/Col. Row/Col. Col. Row/Col. Col. Row/Col. Col. Row/Col. Row/Col.
Byte Write executed with either UCAS LCAS active. Byte Read executed with either UCAS LCAS active. Only signal UCAS LCAS must active.
PRELIMINARY
(June, 2001, Version 0.0)
AMIC Technology, Inc.
A42U0616 Series
Absolute Maximum Ratings*
Input Voltage (Vin) -0.5V VCC+0.5V Output Voltage (Vout) -0.5V VCC+0.5V Power Supply Voltage (VCC) -0.5V VCC+0.5V Operating Temperature (TOPR +70°C Storage Temperature (TSTG) -55°C +150°C Soldering Temperature Time (TSOLDER 260°C 10sec Power Dissipation (PD) Short Circuit Output Current (Iout) 50mA Latch-up Current 200mA
*Comments
Stresses above thos listed under "Absolute Maximum Ratings" cause permanent damage this device. These stress ratings only. Functional operation this device these other conditions above those indicated operational sections these specification implied intended. Exposure absolute maximum rating conditions extended periods affect device reliability.
Electrical Characteristics (VCC 2.5V 10%, +70°C)
Symbol Parameter Min. Input Leakage Current Output Leakage Current Operating Power Supply Current Standby Power Supply Current Average Power Supply Current, Refresh Mode Page Mode Average Power Supply Current -before- Refresh Power Supply Current CMOS Standby Power Supply Current Self Refresh Mode Current Max. Min. Max. Min. Max. 0.2V Pins under Test DOUT disabled, Vout UCAS LCAS min. UCAS LCAS =VIH cycling, VIH, Unit Test Conditions Notes
ICC1
Address cycling;
ICC2 ICC3
UCAS LCAS
min.
ICC4
VIL, UCAS LCAS Address cycling; min. UCAS LCAS min.
ICC5
cycling;
ICC6
UCAS LCAS 0.2V VSS+0.2V other input high levels VCC-0.2V input levels +0.2V IOUT -2mA IOUT
ICC7
Output Voltage
PRELIMINARY
(June, 2001, Version 0.0)
AMIC Technology, Inc.
A42U0616 Series
Characteristics (VCC 2.5V ±10%, +70°C)
Test Conditions: Input timing reference level: VIH/VIL=1.8V/0.8V Output reference level: VOH/VOL=1.6V/0.8V Output Load: 1TTL gate (100pF) Assumed tT=2ns Symbol Parameter Min. tREF tRAS tCAS tRCD tRAD tRSH tCSH tCRP tASR tRAH tCLZ tRAC tCAC tRCS tRCH tRRH Transition Time (Rise Fall) Refresh Period Random Read Write Cycle Time Precharge Time Pulse Width Pulse Width Delay Time Column Address Delay Time Hold Time Hold Time Precharge Time Address Setup Time Address Hold Time Output Access Time from Access Time from Access Time from Column Address Column Address Hold Time from Read mand Setup Time Read Command Hold Time Read Command Hold Time Reference Max. Min. Max. Min. Max. Unit Notes
PRELIMINARY
(June, 2001, Version 0.0)
AMIC Technology, Inc.
A42U0616 Series
Characteristics (continued) (VCC 2.5V ±10%, +70°C)
Test Conditions: Input timing reference level: VIH/VIL=1.8V/0.8V Output reference level: VOH/VOL=1.6V/0.8V Output Load: 1TTL gate (100pF) Assumed tT=2ns Symbol Parameter Min. tRAL tCOH tODS tOFF tASC tCAH tOES tWCS tWCH tWCR tDHR Column Address Lead Time Output Hold After Output Disable Setup Time Output Buffer Turn-Off Delay Time Column Address Setup Time Column Address Hold Time
High
Min. Max.
Unit Notes Min. Max.
Max.
Write Command Setup Time Write Command Hold Time Write Command Hold Time Write Command Pulse Width Write Command Lead Time Write Command Lead Time Data-in setup Time Data-in Hold Time Data-in Hold Time Read-Modify-Write Cycle Time Delay Time (Read-ModifyWrite) Delay Time (Read-ModifyWrite) Column Address Delay Time (Read-Modify-Write)
tAWD
PRELIMINARY
(June, 2001, Version 0.0)
AMIC Technology, Inc.
A42U0616 Series
Characteristics (continued) (VCC 2.5V 10%, +70°C)
Test Conditions: Input timing reference level: VIH/VIL=1.8V/0.8V Output reference level: VOH/VOL=1.6V/0.8V Output Load: 1TTL gate (100pF) Assumed tT=2ns Symbol tOEH tOEP tCPA tPCM tCRW tRASP tCSR tCHR tRPC tROH tOEA tOED tOEZ tRASS tRPS tCHS Parameter Min. Hold Time from High Pulse Width Read Write Cycle Time (EDO Page) Access Time from Precharge (EDO Page) Precharge Time (EDO Page) Page Mode Cycle Time Page Mode Pulse Width (RMW) Pulse Width (EDO Page) Max. Min. Max. Min. Max. Unit Notes
Setup Time -before- RAS) Hold Time -before- RAS)
Precharge Time -before- RAS) Hold Time Reference Access Time Data Delay Output Buffer Turn-off Delay from pulse width self-refresh) precharge time self-refresh) hold time self-refresh)
PRELIMINARY
(June, 2001, Version 0.0)
AMIC Technology, Inc.
A42U0616 Series
Notes: ICC1, ICC3, ICC4, ICC5 depend cycle rate. ICC1 ICC4 depend output loading. Specified values obtained with outputs open. initial pause 200µs required after power-up followed cycles before proper device operation achieved. case internal refresh counter, minimum -before- initialization cycles instead cycles required. initialization cycles required after extended periods bias without clocks. Characteristics assume 2ns. parameters measured with load equivalent load 100pF, (min.) (max.) VCC. (min.) (max.) reference levels measuring timing input signals. Transition times measured between VIL. Operation within tRCD (max.) limit insures that tRAC (max.) met. tRCD (max.) specified reference point only. tRCD greater than specified tRCD (max.) limit, then access time controlled exclusively tCAC Operation within (max.) limit insures that tRAC (max.) met. tRAD (max.) specified reference point only. tRAD greater than specified tRAD (max.) limit, then access time controlled exclusively tAA. Assumes three state test load (5pF Thevenin equivalent). Either tRCH tRRH must satisfied read cycle. tOFF (max.) defines time which output achieves open circuit condition; referenced output voltage levels. tWCS, restrictive operating parameters. They included data sheet electrical characteristics only. tWCS (min.) tWCH (min.), cycle early write cycle data-out pins will remain open circuit, high impedance, throughout entire cycle. (min.) (min.) tAWD tAWD (min.), cycle read-modify-write cycle data will contain data read from selected cell. neither above conditions satisfied, condition data access time indeterminate. Access time determined longer tCAC tCPA. tASC achieve (min.) tCPA (max.) values.
PRELIMINARY
(June, 2001, Version 0.0)
AMIC Technology, Inc.
A42U0616 Series
Word Read Cycle
tRC(1) tRAS(3) tRP(2)
tCSH(8) tCRP(9) tRCD(5) tRSH(7) tCAS(4) tCRP(9)
UCAS LCAS
tRAD(6) tASR(10) tRAH(11) tASC(24)
tRAL(20) tCAH(25)
Address
Address
tAR(16)
Column Address
tRCH(18) tRRH(19)
tRCS(17)
tROH(51) tOEA(52)
tCAC(14) tAA(15) tRAC(13) tOFF(23) tOEZ(54)
I/O0
High-Z
tCLZ(12)
Valid Data-out
High
PRELIMINARY
(June, 2001, Version 0.0)
AMIC Technology, Inc.
A42U0616 Series
Word Write Cycle (Early Write)
tRC(1) tRAS(3) tRP(2)
tCSH(8) tCRP(9) tRCD(5) tRSH(7) tCAS(4) tCRP(9)
UCAS LCAS
tAR(16) tRAD(6) tASR(10) tRAH(11) tASC(24)
tRAL(20) tCAH(25)
Address
Address
Column Address
tWCR(29) tCWL(32) tRWL(31) tWP(30)
tWCS(27) tWCH(28)
tDHR(35) tDS(33) tDH(34)
I/O0 I/O15
Valid Data-in
High
PRELIMINARY
(June, 2001, Version 0.0)
AMIC Technology, Inc.
A42U0616 Series
Word Write Cycle (Late Write)
tRC(1) tRAS(3) tRP(2)
tCSH(8) tCRP(9) tRCD(5) tRSH(7) tCAS(4) tCRP(9)
UCAS LCAS
tAR(16) RAD(6) tASR(10) tRAH(11) tASC(24)
tRAL(20) tCAH(25)
Address
Address
Column Address
tCWL(32) tRWL(31) tWCR(29) tWP(30)
tOEH(40) tOED(53)
tDHR(35) tDS(33) tDH(34)
I/O0 I/O15
High-Z Vaild Data-in
High
PRELIMINARY
(June, 2001, Version 0.0)
AMIC Technology, Inc.
A42U0616 Series
Word Read-Modify-Write Cycle
tRWC(36) tRAS(3) tRP(2)
tCSH(8) tCRP(9) tRCD(5) tRSH(7) tCAS(4) tCRP(9)
UCAS LCAS
tAR(16) tRAD(6) tASR(10) tRAH(11) tASC(24) tCAH(25)
Address
Address
Column Address
tAWD(39) tRCS(17) tRWD(37) tCWD38) tCWL(32) tRWL(31)
tWP(30)
tOED(53) tOEA(52) tOEZ(54)
tCAC(14) tAA(15) tRAC(13) tDS(33) tOEH(40) tDH(34)
I/O0
High-Z Data-out
tCLZ(12)
Data-in
High
PRELIMINARY
(June, 2001, Version 0.0)
AMIC Technology, Inc.
A42U0616 Series
Page Mode Word Read Cycle
tRASP(47)
tRP(2)
tCSH(8) CRP(9) RCD(5) tCAS(4) tCP(44) tPC(42) tCAS(4) tRSH(7) tCRP(9) tCAS(4)
UCAS LCAS
tRAD(6) tRAH(11) tCSH(8) tAR(16) tASR(10) tASC(24) tCAH(25) tRAL(20) tCAH(25) tASC(24)
Address
Column
tCAH(25) tRCS(17)
Column
tRCS(17) tRCH(25)
Column
tRCS(17) tRCH(25)
tAA(15) tCPA(43) tOEA(52) tOEA(52) tOES(26) tCAC(14) tCAC(14) tCLZ(12) tCOH(21) tAA(15) tRRH(19)
tRAC(13)
tOEP(41) tCAC(14) tOEZ(54)
tOFF(23) tOEZ(54)
I/O0 I/O15
Data-out
Data-out
Data-out
tCLZ(12)
High
PRELIMINARY
(June, 2001, Version 0.0)
AMIC Technology, Inc.
A42U0616 Series
Page Mode Early Word Write Cycle
tRASP(47)
tRP(2)
tCSH(8) tCRP(9) tRCD(5) tCAS(4) tCP(44) tCAS(4) tCP(44) tCAS(4) tPC(42) tRSH(7) tCRP(9)
UCAS LCAS
tRAL(20) tRAD(6) tASR(10) tRAH(11) tASC(24) tCAH(25) tASC(24) tCAH(25) tASC(24) tCAH(25)
Address
Column
tCWL(32) tWCS(27) WCS(27) tWCH(28)
Column
tCWL(32) tWCS(27) tWCH(28)
Column
CWL(32) tRWL(31) WCH(28)
tWP(30) tWP(30) tWP(30)
tDH(34) tDS(33) tDS(33)
tDH(34) tDS(33)
tDH(34)
I/O0
Data-in
Data-in
Data-in
High
PRELIMINARY
(June, 2001, Version 0.0)
AMIC Technology, Inc.
A42U0616 Series
Page Mode Word Read-Modify-Write Cycle
tRASP(47)
tRP(2)
tCSH(8) tRCD(5) tCAS(4) tCP(44) tCAS(4) tCP(44) tCAS(4) tPCM(45) tRSH(7) tCRP(9)
tCRP(9)
UCAS LCAS
tRAD(6) tASR(10) tRAH(11) tCAH(25) tASC(24) tCAH(25) tASC(24) tRAL(20) tCAH(25) tASC(24)
Address
Column
Column
tCWL(32)
Column
tCWL(32) tCWL(32) tRWL(31)
tRWD(37) tRCS(17) tCWD(38) tCWD(38) tCWD(38)
tWP(30) tAWD(39) tAWD(39) tWP(30) tAWD(39) tROH(51) tOEA(52) tOEA(52) tOEH(40) tOED(53) tCAC(14) tAA(15) tOEZ(54) tRAC(13) tDH(34) tDS(33) tCPA(43) tAA(15) tOEZ(54) tDH(34) tDS(33) tOED(53) tCPA(43) tAA(15) tOEZ(54) tDH(34) tDS(33) tOED(53) tOEA(52) tWP(30)
High-Z
tCLZ(12) tCLZ(12) tCLZ(12)
Data-in Data-out Data-out
Data-in Data-out
Data-in
High
PRELIMINARY
(June, 2001, Version 0.0)
AMIC Technology, Inc.
A42U0616 Series
Only Refresh Cycle
tRC(1) tRAS(3) tRP(2)
tRPC(50)
tCRP(9)
UCAS LCAS
tASR(10) tRAH(11)
Address
Note: Don't care.
High
Before Refresh Cycle
tRC(1) RP(2) tRAS(3) tRP(2)
tRPC(50) tPC(42) tCSR(48) tCHR(49)
UCAS LCAS I/O0
OFF(23)
High-Z
Note: Address Don't care.
High
PRELIMINARY
(June, 2001, Version 0.0)
AMIC Technology, Inc.
A42U0616 Series
Hidden Refresh Cycle (Word Read)
tRC(1) tRAS(3) tRP(2) tRAS(3) tRC(1) tRP(2)
tAR(16) tCRP(9) tRCD(5) RSH(7) tCHR(49) tCRP(9)
UCAS LCAS
tASR(10) tRAD(6) tRAH(11) tASC(24) tRAL(20) tCAH(25)
Address
Column
tRCS(17)
tRRH(19)
tAA(15)
tCAC(14) tCLZ(12) tRAC(13) tOFF(23)
I/O0 I/O15
High-Z Valid Data-out
High
PRELIMINARY
(June, 2001, Version 0.0)
AMIC Technology, Inc.
A42U0616 Series
Hidden Refresh Cycle (Early Word Write)
tRC(1) tRAS(3) tRP(2) tRAS(3)
tRC(1) tRP(2)
tAR(16) tCRP(9) tRCD(5) tRSH(7) tCHR(49) tCRP(9)
UCAS LCAS
tRAD(6) tASR(10) tRAH(11) tASC(24) tRAL(20) tCAH(25)
Address
tWCS(27)
Column
tWCH(28) tWP(30)
tDS(33)
tDH(34)
I/O0 I/O15
Valid Data-in
High
PRELIMINARY
(June, 2001, Version 0.0)
AMIC Technology, Inc.
A42U0616 Series
Page Mode Read-Early-Write Cycle (Pseudo Read-Modify-Write)
tRASP(47)
tRP(2)
tCSH(8) tPC(42) tCRP(9) tRCD(5) tCAS(4) tCP(44) tCAS(4) tPC(42) tCP(44) tRSH(7) tCAS(4) tCPR(9)
UCAS LCAS
tRAD(6) tASR(10) tRAH(11) tASC(24) tCAH(25) tRAD(6) tASC(24) tCAH(25) tASC(24) tRAL(20) tCAH(25)
Address
Column
Column
tRCH(18)
Column
tRCS(17) tWCS(27) tWCH(28)
tAA(15) tRAC(13) tCAC(14) tOEA(52)
tAA(15) tCAP(43) tCAC(14) tDS(33) tDH(34)
tCOH(21)
Data-out
Data-out
Data-in
High
PRELIMINARY
(June, 2001, Version 0.0)
AMIC Technology, Inc.
A42U0616 Series
Self Refresh Mode
tRP(2)
tRASS(55)
tRPS(56)
tRPC(50)
tCSR(48)
tCHS(57)
tCRP(9)
UCAS LCAS
tCPN(42) tASR(10)
tOFF(23)
I/O0
High-Z
Note: Don't care.
High
Self Refresh Mode. Entering Self Refresh Mode: A42U0616 Self Refresh Mode entered using before cycle holding signal "low" longer than 100µs. Continuing Self Refresh Mode: Self Refresh Mode continued holding "low" after entering Self Refresh Mode. does depend being "high" "low" after entering Self Refresh Mode continue Self Refresh Mode. Exiting Self Refresh Mode: A42U0616 exits Self Refresh Mode when signal brought "high".
PRELIMINARY
(June, 2001, Version 0.0)
AMIC Technology, Inc.
A42U0616 Series
Capacitance Room Temperature, 2.5V 10%)
Symbol CIN1 CIN2 Signals I/O0 I/O15 Input Capacitance Parameter Max. Unit Test Conditions
CI/O
Capacitance
Vout
Ordering Codes
Package\ Access Time (400mil) 50(44)L TSOP type (400mil) 50ns A42U0616S-50 A42U0616V-50 60ns A42U0616S-60 A42U0616V-60 80ns A42U0616S-80 A42U0616V-80 Refresh Cycle SelfRefresh
PRELIMINARY
(June, 2001, Version 0.0)
AMIC Technology, Inc.
A42U0616 Series
Package Information
Outline Dimensions unit: inches/mm
Seating Plane
Symbol
Dimensions inches 0.128 0.025 0.105 0.026 0.015 0.007 1.075 0.395 0.435 0.082 0.138 0.110 0.028 0.018 0.008 1.080 0.400 0.050 0.370 0.440 0.148 0.115 0.032 0.020 0.013 1.085 0.405 0.445 0.045 0.003
Dimensions 3.25 0.64 2.67 0.66 0.38 0.18 27.31 10.03 11.05 2.08 3.51 2.79 0.71 0.46 0.20 27.43 10.16 1.27 11.18 3.76 2.92 0.81 0.51 0.33 27.56 10.29 11.30 1.14 0.075
Notes: maximum value dimension includes flash. Dimension does include resin fins. Dimension Board surface mount pitch design reference only. Dimension includes flash.
PRELIMINARY
(June, 2001, Version 0.0)
AMIC Technology, Inc.
A42U0616 Series
Package Information
TSOP 50/44L (Type Outline Dimensions unit: inches/mm
Detail
Detail
Seating Plane
Dimensions inches
Dimensions 0.05 0.95 0.30 0.12 20.82 10.03 1.00 20.95 10.16 0.80 1.20 0.15 1.05 0.45 0.21 21.08 10.29
Symbol
0.002 0.037 0.012 0.005 0.820 0.395
0.039 0.825 0.400 0.0315
0.048 0.006 0.042 0.018 0.008 0.830 0.405
0.455 0.016 0.005 0.005
0.463 0.020 0.0435
0.471 0.024 0.010
11.56 0.40 0.12 0.12
11.76 0.50 0.875
11.96 0.60 0.25
0.004
Notes: maximum value dimension includes flash. Dimension does include resin fins. Dimension includes flash.
PRELIMINARY
(June, 2001, Version 0.0)
AMIC Technology, Inc.

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