128K 3.3V HIGH SPEED CMOS SRAM Document Title 128K 3.3V HIGH SPEE

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128K 3.3V HIGH SPEED CMOS SRAM Document Title 128K 3.3V HIGH SPEE

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LP61L1024
128K 3.3V HIGH SPEED CMOS SRAM
Document Title 128K 3.3V HIGH SPEED CMOS SRAM Revision History
History
product family 32-pin TSSOP package ball package type
Issue Date
2002 August 2002
Remark
Final
(August, 2002, Version 2.1)
AMIC Technology, Inc.
LP61L1024
128K 3.3V HIGH SPEED CMOS SRAM
Features
Single +3.3V power supply Access times: 12/15 (max.) Current: Operating: 170mA (max.) Standby: 10mA (max.) Full static operation, clock refreshing required inputs outputs directly compatible Common using three-state output Output enable chip enable inputs easy application Data retention voltage: 2.0V (min.) Available 32-pin mil, 32-pin TSOP 32pin TSSOP 36-pin packages
General Description
LP61L1024 operating current 1,048,576-bit static random access memory organized 131,072 words bits operates single 3.3V power supply. Inputs three-state outputs compatible allow direct interfacing with common system structures. chip enable inputs provided POWER-DOWN device enable output enable input included easy interfacing. Data retention guaranteed power supply voltage 2.0V.
Product Family Product Family
Operating Temperature Range
Power Dissipation Speed
Data Retention (ICCDR, Typ.) Standby (ISB1, Typ.) Operating (ICC1, Typ.)
Package Type TSOP
LP61L1024
70°C
3.6V
12/15
0.4mA
0.5mA
130mA
TSSOP µBGA
Typical values measured 3.0V, 25°C 100% tested. Data retention current 2.0V.
(August, 2002, Version 2.1)
AMIC Technology, Inc.
LP61L1024
Configurations
TSOP TSSOP (Chip Size Package)
36-pin View
I/O1 I/O2 I/O3
I/O8 I/O7 I/O6 I/O5 I/O4
Name Name
I/O4 I/O5 I/O6 I/O7 I/O0 I/O1 I/O2 I/O3
LP61L1024V(X)
Block Diagram
LP61L1024S
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
Description
4096 DECODER MEMORY ARRAY
Symbol
Description Address Inputs
I/O1 I/O8
Write Enable Output Enable Chip Enable Chip Enable Connection Data Input/Outputs Power Supply Ground
I/O1 INPUT DATA CIRCUIT I/O8
COLUMN
CONTROL CIRCUIT
(August, 2002, Version 2.1)
AMIC Technology, Inc.
LP61L1024
Recommended Operating Conditions
70°C) Symbol Parameter Supply Voltage Ground Input High Voltage Input Voltage Output Load Output Load Min. -0.3 Typ. Max. +0.8 Unit
Absolute Maximum Ratings*
-0.5V +7.0V IN/OUT Volt .-0.5V +0.5V Operating Temperature, Topr +70°C Storage Temperature, Tstg. -55°C +125°C Temperature Under Bias, Tbias. -10°C +85°C Power Dissipation, Pt.1.0W Soldering Temp. Time .260°C,
*Comments
Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage this device. These stress ratings only. Functional operation this device these other conditions above those indicated operational sections this specification implied intended. Exposure absolute maximum rating conditions extended periods affect device reliability.
Electrical Characteristics
Symbol Parameter
70°C, 3.3V 10%, LP61L1024-12/15 Min. Max. VI/O VIL, II/O 0.2V, 0.2V, 0.2V 0.2V 0.2V, 0.2V 0.2V 0.2V Unit Conditions
Input Leakage Current Output Leakage Current
ICC1 ISB1
Dynamic Operating Current
Standby Power Supply Current ISB2 Output Voltage Output High Voltage
Note: ICC1 dependent output loading, cycle rates, Read/Write patterns
(August, 2002, Version 2.1)
AMIC Technology, Inc.
LP61L1024
Truth Table
Mode Standby Output Disable Read Write Note: Operation High High High DOUT Supply Current ISB, ISB1 ISB, ISB2 ICC1 ICC1 ICC1
Capacitance 25°C, 1.0MHz)
Symbol CIN* CI/O* Parameter Input Capacitance Input/Output Capacitance Min. Max. Unit Conditions VI/O
These parameters sampled 100% tested.
Characteristics +70°C, 3.3V
Symbol Parameter LP61L1024-12 Min. Read Cycle tACE1 tACE2 tCLZ1 tCLZ2 tOLZ tCHZ1 tCHZ2 tOHZ Output Disable Output High Output Hold from Address Change Output Enable Output Chip Disable Output High Output Enable Output Valid Chip Enable Output Read Cycle Time Address Access Time Chip Enable Access Time Max. LP61L1024-15 Min. Max. Unit
(August, 2002, Version 2.1)
AMIC Technology, Inc.
LP61L1024
Characteristics (continued)
Symbol Parameter LP61L1024-12 Min. Write Cycle tWHZ Write Cycle Time Chip Enable Write Address Setup Time Write Address Valid Write Write Pulse Width Write Recovery Time Write Output High Data Write Time Overlap Data Hold from Write Time Output Active from Write Max. LP61L1024-15 Min. Max. Unit
Notes: tCHZ1, tCHZ2, tOHZ, tWHZ defined time which outputs achieve open circuit condition referred output voltage levels.
Timing Waveforms
Read Cycle
Address
DOUT
(August, 2002, Version 2.1)
AMIC Technology, Inc.
LP61L1024
Read Cycle
tACE1 tCLZ15
tCHZ15
DOUT
Read Cycle
tACE2 tCLZ25 tCHZ25
DOUT
(August, 2002, Version 2.1)
AMIC Technology, Inc.
LP61L1024
Timing Waveforms (continued)
Read Cycle
Address
tOLZ5
tACE1 tCLZ25 tCHZ15
tACE2 tCLZ25 DOUT tOHZ5 tCHZ25
Notes:
high Read Cycle. Device continuously enabled VIH. Address valid prior coincident with transition low. VIL. Transition measured ±500mV from steady state. This parameter sampled 100% tested. high. low. Address valid prior coincident with transition high.
(August, 2002, Version 2.1)
AMIC Technology, Inc.
LP61L1024
Timing Waveforms (continued)
Write Cycle (Write Enable Controlled)
Address tCW5
tAS1
tWHZ
DOUT
(August, 2002, Version 2.1)
AMIC Technology, Inc.
LP61L1024
Timing Waveforms (continued)
Write Cycle (Chip Enable Controlled)
Address tCW5 tAS1
tCW5
tWHZ7
DOUT
Notes:
measured from address valid beginning Write. Write occurs during overlap (tWP) CE1, high measured from earliest going high going Write cycle. transition high transition occurs simultaneously with transition after transition, outputs remain high impedance state. measured from later going going high Write. continuously low. VIL) Transition measured ±500mV from steady state. This parameter sampled 100% tested.
(August, 2002, Version 2.1)
AMIC Technology, Inc.
LP61L1024
Test Conditions
Input Pulse Levels Input Rise Fall Time Input Output Timing Reference Levels Output Load 3.0V 1.5V Figures
+3.3V
+3.3V
30pF*
5pF*
Including scope jig.
Including scope jig.
Figure Output Load
Figure Output Load tCLZ1, tCLZ2, tOHZ, tOLZ, tCHZ1, tCHZ2, tWHZ,
Data Retention Characteristics 70°C)
Symbol VDR1 Data Retention Parameter Min. Max. Unit Conditions 0.2V 0.2V 0.2V 0.2V 0.2V 0.2V 3.0V 0.2V 0.2V 0.2V 0.2V 3.0V 0.2V 0.2V 0.2V 0.2V Retention Waveform Operation Recovery Time
VDR2
ICCDR1 Data Retention Current
ICCDR2
tCDR
Chip Disable Data Retention Time
(August, 2002, Version 2.1)
AMIC Technology, Inc.
LP61L1024
Data Retention Waveform Controlled)
DATA RETENTION MODE 3.0V tCDR 3.0V
0.2V
Data Retention Waveform (CE2 Controlled)
DATA RETENTION MODE 3.0V tCDR 3.0V
0.2V
Ordering Information
Part LP61L1024S-12 LP61L1024V-12 LP61L1024X-12 LP61L1024U-12 LP61L1024S-15 LP61L1024V-15 LP61L1024X-15 LP61L1024U-15 Access Time (ns) Operating Current Max. (mA) Standby Current Max. (mA) Package (300 mil) TSOP TSSOP (300 mil) TSOP TSSOP
(August, 2002, Version 2.1)
AMIC Technology, Inc.
LP61L1024
Package Information 32/32LD (300mil BODY) Outline Dimensions
unit: inches/mm
DETAIL BASE METAL WITH PLATING SECTION
DETAIL
SEATING PLANE
0.026"
0.004
Symbol
Dimensions inches Min. 0128 0.052 0.095 0.016 0.026 0.006 0.820 0.330 0.295 0.260 Nom. 0.132 0.100 0.018 0.028 0.008 0.825 0.335 0.300 0.267 0.050 Max. 0.140 0.105 0.020 0.032 0.012 0.830 0.340 0.305 0.274 0.048 0.004
Dimensions Min. 3.25 2.08 2.41 0.41 0.66 0.15 20.83 8.39 7.49 6.61 Nom. 3.35 2.54 0.46 0.71 0.20 20.96 8.51 7.62 6.78 1.27 Max. 3.56 2.67 0.51 0.81 0.30 21.08 8.63 7.75 6.96 1.22 0.10
Notes: maximum value dimension includes flash. Dimension doesn't include resin fins. Dimension Board surface mount pitch design reference only. Dimension includes flash.
(August, 2002, Version 2.1)
AMIC Technology, Inc.
LP61L1024
Package Information TSOP TYPE 20mm) Outline Dimensions
unit: inches/mm
12.0°
GAUGE PLANE
0.25
Detail Detail
0.10(0.004)
Symbol
Dimensions inches 0.047 Max. 0.004±0.002 0.039±0.002 0.008±0.001 0.006±0.001 0.724±0.004 0.315±0.004 0.020 TYP. 0.787±0.007 0.020±0.004 0.031 TYP. 0.0167 TYP. 0.004 Max.
Dimensions 1.20 Max. 0.10±0.05 1.00±0.05 0.20±0.03 0.15±0.02 18.40±0.10 8.00±0.10 0.50 TYP. 20.00±0.20 0.50±0.10 0.80 TYP. 0.425 TYP. 0.10 Max.
Notes: maximum value dimension includes flash. Dimension does include resin fins. Dimension Board surface mount pitch design reference only. Dimension includes flash.
(August, 2002, Version 2.1)
AMIC Technology, Inc.
LP61L1024
Package Information TSSOP TYPE 13.4mm) Outline Dimensions unit: inches/mm
Detail
Detail
0.076MM
SEATING PLANE
Dimensions inches Symbol 0.520 0.461 0.012 0.0275 0.002 0.037 0.007 0.0056 0.311 0.039 0.008 0.0059 0.315 0.020 0.528 0.465 0.020 0.0315 0.0109 0.535 0.469 0.028 0.0355 0.049 0.041 0.009 0.0062 0.319
Dimensions 0.05 0.95 0.17 0.142 7.90 1.00 0.20 0.150 8.00 0.50 13.20 11.70 0.30 0.700 13.40 11.80 0.50 0.800 0.278 13.60 11.90 0.70 0.900 1.25 1.05 0.23 0.158 8.10
Notes: maximum value dimension includes flash. Dimension does include resin fins. Dimension includes flash.
(August, 2002, Version 2.1)
AMIC Technology, Inc.
LP61L1024
Package Information 36LD Outline Dimensions
VIEW BOTTOM VIEW Ball#A1 CORNER 0.10 0.25 Ball*A1 CORNER (36X)
unit:
0.10 0.20(4X)
SIDE VIEW 0.25
(0.36)
SEATING PLANE
Symbol
Dimensions MIN. 1.00 0.16 0.48 5.80 7.80 -0.25 NOM. 1.10 0.21 0.53 6.00 8.00 3.75 5.25 0.75 0.30 MAX. 1.20 0.26 0.58 6.20 8.20 -0.35
Note: BALL DIAMETER, BALL PITCH, STAND-OFF PACKAGE THICKNESS DIFFERENT FROM JEDEC SPEC MO192 (LOW PROFILE FAMILY). PRIMARY DATUM SEATING PLANE DEFINED SPHERICAL CROWNS SOLDER BALLS. DIMENSION MEASURED MAXIMUM. THEERE SHALL MINIMUM CLEARANCE 0.25mm BETWEEN EDGE SOLDER BALL BODY EDGE.
(August, 2002, Version 2.1)
AMIC Technology, Inc.

128K 3.3V HIGH SPEED CMOS SRAM Document Title 128K 3.3V HIGH SPEE

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