128K CMOS SRAM Single power supply Access times: 55/70 (max.) Cur
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LP621024D-T Series
128K CMOS SRAM
Single power supply Access times: 55/70 (max.) Current: Very power version: Operating: 70mA (max.) Standby: 50µA (max.) Full static operation, clock refreshing required inputs outputs directly TTL-compatible Common using three-state output Output enable chip enable inputs easy application Data retention voltage: (min.) Available 32-pin DIP, TSOP TSSOP 13.4mm) packages
General Description
LP621024D-T operating current 1,048,576bit static random access memory organized 131,072 words bits operates single power supply. Inputs three-state outputs compatible allow direct interfacing with common system structures. chip enable inputs provided POWER-DOWN device enable output enable input included easy interfacing. Data retention guaranteed power supply voltage
Configurations
I/O1 I/O2 I/O3 I/O8 I/O7 I/O6 I/O5 I/O4
I/O1 I/O2 I/O3
TSOP/(TSSOP)
LP621024DM-T
LP621024DV-T (LP621024DX-T)
I/O8 I/O7 I/O6 I/O5 I/O4
Name Name I/O1 I/O2 I/O3
(August, 2001, Version 1.0)
LP621024D-T
I/O4
I/O5
I/O6
I/O7
I/O8
AMIC Technology, Inc.
LP621024D-T Series
Block Diagram
DECODER 2048 MEMORY ARRAY
I/O1
INPUT DATA CIRCUIT
COLUMN
I/O8
CONTROL CIRCUIT
Descriptions DIP/SOP
Symbol Description Connection Address Inputs
Description TSOP/TSSOP
Symbol I/O1 I/O8 Description Address Inputs Write Enable Chip Enable Power Supply Connection Data Input/Outputs Ground Chip Enable Output Enable
I/O1 I/O8
Data Input/Outputs Ground Chip Enable Output Enable Write Enable Chip Enable Power Supply (+5V)
(August, 2001, Version 1.0)
AMIC Technology, Inc.
LP621024D-T Series
Recommended Operating Conditions
-25°C 85°C) Symbol Parameter Supply Voltage Ground Input High Voltage Input Voltage Output Load Output Load Min. -0.3 Typ. Max. +0.8 Unit
Absolute Maximum Ratings*
-0.5V 7.0V IN/OUT Volt .-0.5V 0.5V Operating Temperature, Topr -25°C 85°C Storage Temperature, Tstg. -55°C 125°C Temperature Under Bias, Tbias. -10°C 85°C Power Dissipation, 0.7W Soldering Temp. Time .260°C,
*Comments
Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage this device. These stress ratings only. Functional operation this device these other conditions above those indicated operational sections this specification implied intended. Exposure absolute maximum rating conditions extended periods affect device reliability.
Electrical Characteristics
Symbol Parameter
-25°C 85°C, 10%, LP621024D-55LLT Min. Max. LP621024D-70LLT Min. Max. VI/O VIL, II/O Min. Cycle, Duty 100% VIL, II/O VIL, VCC, 1MHZ, II/O Unit Conditions
Input Leakage Current
Output Leakage Current Active Power Supply Current
ICC1
Dynamic Operating Current
ICC2
(August, 2001, Version 1.0)
AMIC Technology, Inc.
LP621024D-T Series
Electrical Characteristics (continued)
Symbol Parameter LP621024D-55LLT Min. Max. LP621024D-70LLT Min. Max. =VIL 0.2V 0.2V 0.2V 2.1mA Unit Conditions
ISB1
Standby Power Supply Current
ISB2 Output Voltage Output High Voltage
-1.0mA
Truth Table
Mode Standby Output Disable Read Write Note: Operation High High High DOUT Supply Current ISB, ISB1 ISB, ISB2 ICC, ICC1, ICC2 ICC, ICC1, ICC2 ICC, ICC1, ICC2
Capacitance 25°C, 1.0MHz)
Symbol CIN* CI/O* Parameter Input Capacitance Input/Output Capacitance Min. Max. Unit Conditions VI/O
These parameters sampled 100% tested.
(August, 2001, Version 1.0)
AMIC Technology, Inc.
LP621024D-T Series
Characteristics -25°C 85°C, 10%)
Symbol Parameter LP621024D-55LLT Min. Read Cycle tACE1 tACE2 tCLZ1 tCLZ2 tOLZ tCHZ1 tCHZ2 tOHZ Write Cycle tWHZ Write Cycle Time Chip Enable Write Address Setup Time Address Valid Write Write Pulse Width Write Recovery Time Write Output High Data Write Time Overlap Data Hold from Write Time Output Active from Write Output Disable Output High Output Hold from Address Change Output Enable Output Chip Disable Output High Output Enable Output Valid Chip Enable Output Read Cycle Time Address Access Time Chip Enable Access Time Max. LP621024D-70LLT Min. Max. Unit
Notes: tCHZ1, tCHZ2, tOHZ, tWHZ defined time which outputs achieve open circuit condition referred output voltage levels.
(August, 2001, Version 1.0)
AMIC Technology, Inc.
LP621024D-T Series
Timing Waveforms
Read Cycle
Address
DOUT
Read Cycle
tACE1 tCLZ15
tCHZ15
DOUT
Read Cycle
tACE2 tCLZ25 tCHZ25
DOUT
(August, 2001, Version 1.0)
AMIC Technology, Inc.
LP621024D-T Series
Timing Waveforms (continued)
Read Cycle
Address
tOLZ5
tACE1 tCLZ15 tACE2 tCLZ25 DOUT tCHZ25 tOHZ tCHZ15
Notes:
high Read Cycle. Device continuously enabled VIH. Address valid prior coincident with transition low. VIL. Transition measured ±500mV from steady state. This parameter sampled 100% tested. high. low. Address valid prior coincident with transition high.
(August, 2001, Version 1.0)
AMIC Technology, Inc.
LP621024D-T Series
Timing Waveforms (continued)
Write Cycle (Write Enable Controlled)
Address
tWR3
tAS1 tWP2
tWHZ DOUT
(August, 2001, Version 1.0)
AMIC Technology, Inc.
LP621024D-T Series
Timing Waveforms (continued)
Write Cycle (Chip Enable Controlled)
Address tCW5 tAS1 tWR3
tCW5 tWP2
tWHZ7
DOUT
Notes:
measured from address valid beginning Write. Write occurs during overlap (tWP) CE1, high measured from earliest going high going Write cycle. transition high transition occurs simultaneously with transition after transition, outputs remain high impedance state. measured from later going going high Write. continuously low. VIL) Transition measured ±500mV from steady state. This parameter sampled 100% tested.
(August, 2001, Version 1.0)
AMIC Technology, Inc.
LP621024D-T Series
Test Conditions
Input Pulse Levels Input Rise Fall Time Input Output Timing Reference Levels Output Load 3.0V 1.5V Figures
1800
1800
30pF*
5pF*
Including scope jig.
Including scope jig.
Figure Output Load
Figure Output Load tCLZ1, tCLZ2, tOHZ, tOLZ, tCHZ1, tCHZ2, tWHZ,
Data Retention Characteristics -25°C 85°C)
Symbol VDR1 VDR2 Data Retention Parameter Min. Max. Unit Conditions 0.2V 0.2V 0.2V 0.2V 3.0V, 0.2V 0.2V 3.0V 0.2V Retention Waveform
ICCDR1 Data Retention Current ICCDR2
LL-Version
20**
LL-Version
20**
tCDR
Chip Disable Data Retention Time Operation Recovery Time ICCDR: Max.
LP621024D-55LLT/70LLT
(August, 2001, Version 1.0)
AMIC Technology, Inc.
LP621024D-T Series
Data Retention Waveform Controlled)
DATA RETENTION MODE 4.5V tCDR 4.5V
0.2V
Data Retention Waveform (CE2 Controlled)
DATA RETENTION MODE 4.5V tCDR 4.5V
0.2V
(August, 2001, Version 1.0)
AMIC Technology, Inc.
LP621024D-T Series
Ordering Information
Part LP621024D-55LLT LP621024DM-55LLT LP621024DV-55LLT LP621024DX-55LLT LP621024D-70LLT LP621024DM-70LLT LP621024DV-70LLT LP621024DX-70LLT Access Time (ns) Operating Current Max. (mA) Standby Current Max. (µA) Package TSOP TSSOP TSOP TSSOP
(August, 2001, Version 1.0)
AMIC Technology, Inc.
LP621024D-T Series
Package Information P-DIP Outline Dimensions
unit: inches/mm
Base Plane
Seating Plane
Symbol
Dimensions inches 0.210 Max. 0.010 Min. 0.155±0.010 0.018 +0.004 -0.002 0.050 +0.004 -0.002 0.010 +0.004 -0.002 1.650 Typ. (1.670 Max.) 0.600±0.010 0.550 Typ. (0.562 Max.) 0.100±0.010 0.130±0.010 0.655±0.035 0.090 Max.
Dimensions 5.33 Max. 0.25 Min. 3.94±0.25 0.46 +0.10 -0.05 1.27 +0.10 -0.05 0.25 +0.11 -0.05 41.91 Typ. (42.42 Max.) 15.24±0.25 13.97 Typ. (14.27 Max.) 2.54±0.25 3.30±0.25 16.64±0.89 2.29 Max.
Notes: maximum value dimension includes flash. Dimension does include resin fins. Dimension includes flash.
(August, 2001, Version 1.0)
AMIC Technology, Inc.
LP621024D-T Series
Package Information (W.B.) Outline Dimensions
unit: inches/mm
Detail
Seating Plane
Detail
Symbol
Dimensions inches 0.118 Max. 0.004 Min. 0.106±0.005 0.016 +0.004 -0.002 0.008 +0.004 -0.002 0.805 Typ. (0.820 Max.) 0.445±0.010 0.050 ±0.006 0.525 NOM. 0.556±0.010 0.031±0.008 0.055±0.008 0.044 Max. 0.004 Max.
Dimensions 3.00 Max. 0.10 Min. 2.69±0.13 0.41 +0.10 -0.05 0.20 +0.10 -0.05 20.45 Typ. (20.83 Max.) 11.30±0.25 1.27±0.15 13.34 NOM. 14.12±0.25 0.79±0.20 1.40±0.20 1.12 Max. 0.10 Max.
Notes: maximum value dimension includes flash. Dimension does include resin fins. Dimension Board surface mount pitch design reference only. Dimension includes flash.
(August, 2001, Version 1.0)
AMIC Technology, Inc.
LP621024D-T Series
Package Information TSOP TYPE 20mm) Outline Dimensions
unit: inches/mm
12.0°
GAUGE PLANE
0.25
Detail Detail
0.10(0.004)
Symbol
Dimensions inches 0.047 Max. 0.004±0.002 0.039±0.002 0.008±0.001 0.006±0.001 0.724±0.004 0.315±0.004 0.020 TYP. 0.787±0.007 0.020±0.004 0.031 TYP. 0.0167 TYP. 0.004 Max.
Dimensions 1.20 Max. 0.10±0.05 1.00±0.05 0.20±0.03 0.15±0.02 18.40±0.10 8.00±0.10 0.50 TYP. 20.00±0.20 0.50±0.10 0.80 TYP. 0.425 TYP. 0.10 Max.
Notes: maximum value dimension includes flash. Dimension does include resin fins. Dimension Board surface mount pitch design reference only. Dimension includes flash.
(August, 2001, Version 1.0)
AMIC Technology, Inc.
LP621024D-T Series
Package Information TSSOP TYPE 13.4mm) Outline Dimensions
unit: inches/mm
12.0°
GAUGE PLANE
0.25
Detail
Detail
0.10MM
SEATING PLANE
Symbol
Dimensions inches 0.049 Max. 0.002 Min. 0.039±0.002 0.008±0.001 0.006±0.0003 0.315±0.004 0.020 TYP. 0.528±0.008 0.465±0.004 0.02±0.008 0.0266 Min. 0.0109 TYP. 0.004 Max.
Dimensions 1.25 Max. 0.05 Min. 1.00±0.05 0.20±0.03 0.15±0.008 8.00±0.10 0.50 TYP. 13.40±0.20 11.80±0.10 0.50±0.20 0.675 Min. 0.278 TYP. 0.10 Max.
Notes: maximum value dimension includes flash. Dimension does include resin fins. Dimension Board surface mount pitch design reference only. Dimension includes flash.
(August, 2001, Version 1.0)
AMIC Technology, Inc.
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