128K VOLTAGE CMOS SRAM Document Title 128K VOLTAGE CMOS SRAM Revi

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128K VOLTAGE CMOS SRAM Document Title 128K VOLTAGE CMOS SRAM Revi

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LP62S1024B-T Series
128K VOLTAGE CMOS SRAM
Document Title 128K VOLTAGE CMOS SRAM Revision History
History
Initial issue Pb-Free TSSOP package type Final version release
Issue Date
February 2002 October 2002 July 2003
Remark
Preliminary Final
(July, 2003, Version 1.0)
AMIC Technology, Corp.
LP62S1024B-T Series
128K VOLTAGE CMOS SRAM
Features
Power supply range: 2.7V 3.6V Access times: 55/70 (max.) Current: Very power version: Operating: 30mA(max.) Standby: (max.) Full static operation, clock refreshing required inputs outputs directly TTL-compatible Common using three-state output Output enable chip enable inputs easy application Data retention voltage: (min.) Available 32-pin SOP, TSOP, TSSOP 13.4mm) forward type 36-pin packages
General Description
LP62S1024B-T operating current 1,048,576bit static random access memory organized 131,072 words bits operates power voltage: 2.7V 3.6V. built using AMIC's high performance CMOS process. Inputs three-state outputs compatible allow direct interfacing with common system structures. chip enable inputs provided POWER-DOWN device enable output enable input included easy interfacing. Data retention guaranteed power supply voltage
Product Family
Product Family Operating Temperature Range Power Dissipation Speed Data Retention (ICCDR, Typ.) Standby (ISB1, Typ.) Operating (ICC2, Typ.) Package Type LP62S1024B -25°C +85°C 2.7V~3.6V 55ns 70ns 0.05µA 0.08µA 1.5mA TSOP TSSOP µBGA Typical values measured 3.0V, 25°C 100% tested. Data retention current 2.0V.
(July, 2003, Version 1.0)
AMIC Technology, Corp.
LP62S1024B-T Series
Configurations
TSOP/TSSOP (Chip Size Package) 36-pin View
I/O1 I/O2 I/O3 I/O5 I/O6 I/O7 I/O8 I/O1 I/O2 I/O3 I/O4
LP62S1024BV-T (LP62S1024BX-T)
LP62S1024BM-T
I/O8 I/O7 I/O6 I/O5 I/O4
Name Name
Block Diagram
DECODER
2048 MEMORY ARRAY
I/O1
INPUT DATA CIRCUIT
COLUMN
I/O8
CONTROL CIRCUIT
(July, 2003, Version 1.0)
AMIC Technology, Corp.
LP62S1024B-T Series
Descriptions
Symbol Description Connection Address Inputs
Description TSOP/TSSOP
Symbol I/O1 I/O8 Description Address Inputs Write Enable Chip Enable Power Supply Connection Data Input/Outputs Ground Chip Enable Output Enable
I/O1 I/O8
Data Input/Outputs Ground Chip Enable Output Enable Write Enable Chip Enable Power Supply
Description
Symbol Description Address Inputs Write Enable Output Enable Chip Enable Chip Enable Symbol I/O1 I/O8 -Description Connection Data Input/Output Power Supply Ground
(July, 2003, Version 1.0)
AMIC Technology, Corp.
LP62S1024B-T Series
Recommended Operating Conditions
-25°C +85°C) Symbol Parameter Supply Voltage Ground Input High Voltage Input Voltage Output Load Output Load Min. -0.3 Typ. Max. +0.6 Unit
Absolute Maximum Ratings*
-0.5V +4.6V IN/OUT Volt .-0.5V +0.5V Operating Temperature, Topr -25°C +85°C Storage Temperature, Tstg. -55°C +125°C Temperature Under Bias, Tbias. -10°C +85°C Power Dissipation, .0.7W
*Comments
Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage this device. These stress ratings only. Functional operation this device these other conditions above those indicated operational sections this specification implied intended. Exposure absolute maximum rating conditions extended periods affect device reliability.
Electrical Characteristics
Symbol
-25°C +85°C, 2.7V 3.6V, LP62S1024B-55LLT/70LLT Min. Max. VI/O VIL, II/O Min. Cycle, Duty 100% VIL, II/O VIL, VCC, MHZ, II/O Unit Conditions
Parameter
Input Leakage Current
Output Leakage Current
Active Power Supply Current
ICC1 Dynamic Operating Current ICC2
(July, 2003, Version 1.0)
AMIC Technology, Corp.
LP62S1024B-T Series
Electrical Characteristics (continued)
Symbol Parameter LP62S1024B-55LLT/70LLT Min. Standby Power Supply Current ISB1 Max. 3.3V =VIL 3.3V 0.2V 0.2V 2.1mA -1.0mA Unit Conditions
Output Voltage Output High Voltage
Truth Table
Mode Standby Output Disable Read Write Note: Operation High High High DOUT Supply Current ISB, ISB1 ISB, ISB2 ICC, ICC1, ICC2 ICC, ICC1, ICC2 ICC, ICC1, ICC2
Capacitance 25°C, 1.0MHz)
Symbol CIN* CI/O* Parameter Input Capacitance Input/Output Capacitance Min. Max. Unit Conditions VI/O
These parameters sampled 100% tested.
(July, 2003, Version 1.0)
AMIC Technology, Corp.
LP62S1024B-T Series
Characteristics
Symbol -25°C +85°C, 2.7V 3.6V) Parameter LP62S1024B-55LLT Min. Read Cycle tACE1 tACE2 tCLZ1 tCLZ2 tOLZ tCHZ1 tCHZ2 tOHZ Write Cycle tWHZ Write Cycle Time Chip Enable Write Address Setup Time Address Valid Write Write Pulse Width Write Recovery Time Write Output High Data Write Time Overlap Data Hold from Write Time Output Active from Write Output Disable Output High Output Hold from Address Change Output Enable Output Chip Disable Output High Output Enable Output Valid Chip Enable Output Read Cycle Time Address Access Time Chip Enable Access Time Max. LP62S1024B-70LLT Min. Max. Unit
Notes: tCHZ1, tCHZ2, tOHZ, tWHZ defined time which outputs achieve open circuit condition referred output voltage levels.
(July, 2003, Version 1.0)
AMIC Technology, Corp.
LP62S1024B-T Series
Timing Waveforms
Read Cycle
Address
DOUT
Read Cycle
tACE1 tCLZ15
tCHZ15
DOUT
Read Cycle
tACE2 tCLZ25 tCHZ25
DOUT
(July, 2003, Version 1.0)
AMIC Technology, Corp.
LP62S1024B-T Series
Timing Waveforms (continued)
Read Cycle
Address
tOLZ5
tACE1 tCLZ15 tACE2 tCLZ25 DOUT tCHZ25 tOHZ tCHZ15
Notes:
high Read Cycle. Device continuously enabled VIH. Address valid prior coincident with transition low. VIL. Transition measured ±500mV from steady state. This parameter sampled 100% tested. high. low. Address valid prior coincident with transition high.
(July, 2003, Version 1.0)
AMIC Technology, Corp.
LP62S1024B-T Series
Timing Waveforms (continued)
Write Cycle (Write Enable Controlled)
Address
tWR3
tAS1 tWP2
tWHZ DOUT
(July, 2003, Version 1.0)
AMIC Technology, Corp.
LP62S1024B-T Series
Timing Waveforms (continued)
Write Cycle (Chip Enable Controlled)
Address tCW5 tAS1 tWR3
tCW5 tWP2
tWHZ7
DOUT
Notes:
measured from address valid beginning Write. Write occurs during overlap (tWP) CE1, high measured from earliest going high going Write cycle. transition high transition occurs simultaneously with transition after transition, outputs remain high impedance state. measured from later going going high Write. continuously low. VIL) Transition measured ±500mV from steady state. This parameter sampled 100% tested.
(July, 2003, Version 1.0)
AMIC Technology, Corp.
LP62S1024B-T Series
Test Conditions
Input Pulse Levels Input Rise Fall Time Input Output Timing Reference Levels Output Load 0.4V 2.4V 1.5V Figures
30pF
Including scope jig.
Including scope jig.
Figure Output Load
Figure Output Load tCLZ1, tCLZ2, tOHZ, tOLZ, tCHZ1, tCHZ2, tWHZ,
Data Retention Characteristics -25°C 85°C)
Symbol VDR1 Data Retention VDR2 0.2V, 0.2V, 0.2V, Retention Waveform Parameter Min. Max. Unit Conditions 0.2V
ICCDR1 Data Retention Current
ICCDR2 tCDR Chip Disable Data Retention Time Operation Recovery Time ICCDR: max.
LP62S1024B-55LLT/70LLT
40°C
(July, 2003, Version 1.0)
AMIC Technology, Corp.
LP62S1024B-T Series
Data Retention Waveform Controlled)
DATA RETENTION MODE 3.0V tCDR 3.0V
0.2V
Data Retention Waveform (CE2 Controlled)
DATA RETENTION MODE 3.0V tCDR 3.0V
0.2V
(July, 2003, Version 1.0)
AMIC Technology, Corp.
LP62S1024B-T Series
Ordering Information
Part LP62S1024BM-55LLT LP62S1024BV-55LLT LP62S1024BX-55LLT LP62S1024BX-55LLTF LP62S1024BU-55LLT LP62S1024BM-70LLT LP62S1024BV-70LLT LP62S1024BX-70LLT LP62S1024BX-70LLTF LP62S1024BU-70LLT Access Time (ns) Operating Current Max. (mA) Standby Current Max. (µA) Package TSOP TSSOP Pb-Free TSSOP TSOP TSSOP Pb-Free TSSOP
(July, 2003, Version 1.0)
AMIC Technology, Corp.
LP62S1024B-T Series
Package Information (W.B.) Outline Dimensions
unit: inches/mm
Detail
Seating Plane
Detail
Symbol
Dimensions inches 0.118 Max. 0.004 Min. 0.106±0.005 0.016 +0.004 -0.002 0.008 +0.004 -0.002 0.805 Typ. (0.820 Max.) 0.445±0.010 0.050 ±0.006 0.525 NOM. 0.556±0.010 0.031±0.008 0.055±0.008 0.044 Max. 0.004 Max.
Dimensions 3.00 Max. 0.10 Min. 2.69±0.13 0.41 +0.10 -0.05 0.20 +0.10 -0.05 20.45 Typ. (20.83 Max.) 11.30±0.25 1.27±0.15 13.34 NOM. 14.12±0.25 0.79±0.20 1.40±0.20 1.12 Max. 0.10 Max.
Notes: maximum value dimension includes flash. Dimension does include resin fins. Dimension Board surface mount pitch design reference only. Dimension includes flash.
(July, 2003, Version 1.0)
AMIC Technology, Corp.
LP62S1024B-T Series
Package Information TSOP TYPE 20mm) Outline Dimensions
unit: inches/mm
12.0°
GAUGE PLANE
0.25
Detail Detail
0.10(0.004)
Symbol
Dimensions inches 0.047 Max. 0.004±0.002 0.039±0.002 0.008±0.001 0.006±0.001 0.724±0.004 0.315±0.004 0.020 TYP. 0.787±0.007 0.020±0.004 0.031 TYP. 0.0167 TYP. 0.004 Max.
Dimensions 1.20 Max. 0.10±0.05 1.00±0.05 0.20±0.03 0.15±0.02 18.40±0.10 8.00±0.10 0.50 TYP. 20.00±0.20 0.50±0.10 0.80 TYP. 0.425 TYP. 0.10 Max.
Notes: maximum value dimension includes flash. Dimension does include resin fins. Dimension Board surface mount pitch design reference only. Dimension includes flash.
(July, 2003, Version 1.0)
AMIC Technology, Corp.
LP62S1024B-T Series
Package Information TSSOP TYPE 13.4mm) Outline Dimensions
unit: inches/mm
12.0°
GAUGE PLANE
0.25
Detail
Detail
0.10MM
SEATING PLANE
Symbol
Dimensions inches 0.049 Max. 0.002 Min. 0.039±0.002 0.008±0.001 0.006±0.0003 0.315±0.004 0.020 TYP. 0.528±0.008 0.465±0.004 0.02±0.008 0.0266 Min. 0.0109 TYP. 0.004 Max.
Dimensions 1.25 Max. 0.05 Min. 1.00±0.05 0.20±0.03 0.15±0.008 8.00±0.10 0.50 TYP. 13.40±0.20 11.80±0.10 0.50±0.20 0.675 Min. 0.278 TYP. 0.10 Max.
Notes: maximum value dimension includes flash. Dimension does include resin fins. Dimension Board surface mount pitch design reference only. Dimension includes flash.
(July, 2003, Version 1.0)
AMIC Technology, Corp.
LP62S1024B-T Series
Package Information 36LD Outline Dimensions
VIEW BOTTOM VIEW Ball#A1 CORNER 0.10 0.25 Ball*A1 CORNER (36X)
unit:
0.10 0.20(4X)
SIDE VIEW 0.25
(0.36)
SEATING PLANE
Symbol
Dimensions MIN. 1.00 0.16 0.48 5.80 7.80 -0.25 NOM. 1.10 0.21 0.53 6.00 8.00 3.75 5.25 0.75 0.30 MAX. 1.20 0.26 0.58 6.20 8.20 -0.35
Note: BALL DIAMETER, BALL PITCH, STAND-OFF PACKAGE THICKNESS DIFFERENT FROM JEDEC SPEC MO192 (LOW PROFILE FAMILY). PRIMARY DATUM SEATING PLANE DEFINED SPHERICAL CROWNS SOLDER BALLS. DIMENSION MEASURED MAXIMUM. THEERE SHALL MINIMUM CLEARANCE 0.25mm BETWEEN EDGE SOLDER BALL BODY EDGE.
(July, 2003, Version 1.0)
AMIC Technology, Corp.

128K VOLTAGE CMOS SRAM Document Title 128K VOLTAGE CMOS SRAM Revi

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