256K VOLTAGE CMOS SRAM Document Title 256K VOLTAGE CMOS SRAM Revi

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256K VOLTAGE CMOS SRAM Document Title 256K VOLTAGE CMOS SRAM Revi

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LP62E16256E-T Series
256K VOLTAGE CMOS SRAM
Document Title 256K VOLTAGE CMOS SRAM Revision History
History
Initial issue Final version release
Issue Date
July 2002 July 2003
Remark
Preliminary Final
(July, 2003, Version 1.0)
AMIC Technology, Corp.
LP62E16256E-T Series
256K VOLTAGE CMOS SRAM
Features
Operating voltage: 1.65V 2.2V Access times: 70ns (max.) Current: Very power version: Operating: 30mA (max.) Standby: 10µA (max.) Full static operation, clock refreshing required inputs outputs directly TTL-compatible Common using three-state output Data retention voltage: 1.2V (min.) Available 44-pin TSOP 48-ball packages
General Description
LP62E16256E-T operating current 4,194,304-bit static random access memory organized 262,144 words bits operates power voltage from 1.65V 2.2V. built using AMIC's high performance CMOS process. Inputs three-state outputs compatible allow direct interfacing with common system structures. chip enable input provided POWER-DOWN, device enable. byte enable inputs output enable input included easy interfacing. Data retention guaranteed power supply voltage 1.2V.
Product Family
Product Family Operating Temperature -25°C +85°C Power Dissipation Range Speed Data Retention (ICCDR, Typ.) 0.2µA Standby (ISB1, Typ.) 1.4µA Operating (ICC2, Typ.) Package Type TSOP
LP62E16256E
1.65V~2.2V
70ns
Typical values measured 2.0V, 25°C 100% tested. Data retention current 1.2V.
Configurations
TSOP (Chip Size Package) 48-pin View
I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8
I/O16 I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9
I/O9 I/O10 I/O15 I/O16
I/O11 I/O12 I/O13 I/O14
I/O2 I/O4 I/O5 I/O6
I/O1 I/O3 I/O7 I/O8
LP62E16256EV-T
(July, 2003, Version 1.0)
AMIC Technology, Corp.
LP62E16256E-T Series
Block Diagram
DECODER 8192 MEMORY ARRAY
I/O1 COLUMN INPUT DATA CIRCUIT
I/O9
INPUT DATA CIRCUIT
I/O8
I/O16
CONTROL CIRCUIT
Descriptions TSOP
Symbol I/O1 I/O16 Description Address Inputs Chip Enable Input
Data Inputs/Outputs Write Enable Input Lower Byte Enable Input (I/O1 I/O8) Higher Byte Enable Input (I/O9 I/O16) Output Enable Input Power Ground Connection
(July, 2003, Version 1.0)
AMIC Technology, Corp.
LP62E16256E-T Series
Description
Symbol Description Address Inputs Symbol Description Higher Byte Enable Input (I/O9 I/O16) Output Enable Power Supply Ground Connection
I/O1 I/O16
Chip Enable Data Input/Output Write Enable Input Byte Enable Input (I/O1 I/O8)
Recommended Operating Conditions
-25°C 85°C) Symbol Parameter Supply Voltage Ground Input High Voltage Input Voltage Output Load Output Load Min. 1.65 -0.2 Typ. Max. +0.4 Unit
(July, 2003, Version 1.0)
AMIC Technology, Corp.
LP62E16256E-T Series
Absolute Maximum Ratings*
.-0.5V +3.0V IN/OUT Volt -0.5V 0.5V Operating Temperature, Topr .-25°C +85°C Storage Temperature, Tstg.-55°C +125°C Power Dissipation, 0.7W
*Comments
Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage this device. These stress ratings only. Functional operation this device these other conditions above those indicated operational sections this specification implied intended. Exposure absolute maximum rating conditions extended periods affect device reliability.
Electrical Characteristics -25°C 85°C, 1.65V 2.2V,
Symbol Parameter LP62E16256E-70LLT Min. Input Leakage Current Max. VI/O VIL, II/O Min. Cycle, Duty 100% II/O VIL, VCC, 1MHz, II/O 0.2V, -0.1 Unit Conditions
Output Leakage Current
ICC1
Active Power Supply Current
Dynamic Operating Current ICC2
ISB1 Standby Current
Output Voltage Output High Voltage
(July, 2003, Version 1.0)
AMIC Technology, Corp.
LP62E16256E-T Series
Truth Table
I/O1 I/O8 Mode selected High Read Read High Write Write High High High I/O9 I/O16 Mode selected High Read High Read Write High Write High High Current ISB1, ISB1, ICC1, ICC2, ICC1, ICC2, ICC1, ICC2, ICC1, ICC2, ICC1, ICC2, ICC1, ICC2, ICC1, ICC2, ICC1, ICC2,
Note:
Capacitance 25°C, 1.0MHz)
Symbol CIN* CI/O* Parameter Input Capacitance Input/Output Capacitance Min. Max. Unit Conditions VI/O
These parameters sampled 100% tested.
(July, 2003, Version 1.0)
AMIC Technology, Corp.
LP62E16256E-T Series
Characteristics -25°C +85°C, 1.65V 2.2V)
Symbol Parameter LP62E16256E-70LLT Min. Read Cycle tACE tCLZ tBLZ tOLZ tCHZ tBHZ tOHZ Write Cycle tWHZ Write Cycle Time Chip Enable Write Byte Enable Write Address Setup Time Address Valid Write Write Pulse Width Write Recovery Time Write Output High Data Write Time Overlap Data Hold from Write Time Output Active from Write Read Cycle Time Address Access Time Chip Enable Access Time Byte Enable Access Time Output Enable Output Valid Chip Enable Output Byte Enable Output Output Enable Output Chip Disable Output High Byte Disable Output High Output Disable Output High Output Hold from Address Change Max. Unit
Note: tCHZ, tBHZ tOHZ tWHZ defined time which outputs achieve open circuit condition referred output voltage levels.
(July, 2003, Version 1.0)
AMIC Technology, Corp.
LP62E16256E-T Series
Timing Waveforms
Read Cycle
Address
DOUT
Read Cycle
Address
tACE tCLZ
tCHZ
tBLZ
tBHZ
tOHZ
tOLZ DOUT
Notes:
high Read Cycle. Device continuously enabled VIL, and, VIL. Address valid prior coincident with and, transition low. VIL. Transition measured ±200mV from steady state. This parameter sampled 100% tested.
(July, 2003, Version 1.0)
AMIC Technology, Corp.
LP62E16256E-T Series
Timing Waveforms (continued)
Write Cycle (Write Enable Controlled)
Address tWR3
tAS1
tWP2
DATA tWHZ
DATA
(July, 2003, Version 1.0)
AMIC Technology, Corp.
LP62E16256E-T Series
Timing Waveforms (continued)
Write Cycle (Chip Enable Controlled)
Address tAS1 tCW2 tWR3
DATA tWHZ
DATA
(July, 2003, Version 1.0)
AMIC Technology, Corp.
LP62E16256E-T Series
Timing Waveforms (continued)
Write Cycle (Byte Enable Controlled)
Address
tWR3
tAS1
tBW2
DATA tWHZ DATA
Notes: measured from address valid beginning Write. Write occurs during overlap (tWP, tBW) measured from earliest going high Write cycle. level high low. Transition measured ±200mV from steady state. This parameter sampled 100% tested.
(July, 2003, Version 1.0)
AMIC Technology, Corp.
LP62E16256E-T Series
Test Conditions
Input Pulse Levels Input Rise Fall Time Input Output Timing Reference Levels Output Load 0.2V -0.2V 0.9V Figures
30pF
Including scope jig.
Including scope jig.
Figure Output Load
Figure Output Load tCLZ, tOLZ, tCHZ, tOHZ, tWHZ,
Data Retention Characteristics -25°C 85°C) Symbol
Parameter
Data Retention
Min.
Max.
Unit
Conditions
0.2V
ICCDR
Data Retention Current
1.2V, 0.2V
tCDR
Chip Disable Data Retention Time Operation Recovery Time Rising Time from Data Retention Voltage Operating Voltage ICCDR: max.
Retention Waveform
LP62E16256E-70LLT
40°C
(July, 2003, Version 1.0)
AMIC Technology, Corp.
LP62E16256E-T Series
Data Retention Waveform
1.65V tCDR 1.2V 0.2V DATA RETENTION MODE 1.65V
Ordering Information
Part Access Time (ns) Operating Current Max. (mA) Standby Current Max. (µA) Package
LP62E16256EV-70LLT LP62E16256EU-70LLT
TSOP
(July, 2003, Version 1.0)
AMIC Technology, Corp.
LP62E16256E-T Series
Package Information TSOP TYPE Outline Dimensions
unit: inches/mm
0.254
Symbol
Dimension inch Min. 0.002 0.037 0.010 0.721 0.396 0.455 0.016 Nom. 0.039 0.014 0.006 0.725 0.400 0.031 0.463 0.020 0.031 Max. 0.047 0.041 0.018 0.729 0.404 0.471 0.024 0.036 0.004
Dimension Min. 0.05 0.95 0.25 18.31 10.06 11.56 0.40 Nom. 1.00 0.35 0.15 18.41 10.16 0.80 11.76 0.50 0.80 Max. 1.20 1.05 0.45 18.51 10.26 11.96 0.60 0.93 0.10
Notes: Dimension include interlead flash. Dimension does include dambar protrusion/intrusion. Dimension includes flash.
(July, 2003, Version 1.0)
AMIC Technology, Corp.
LP62E16256E-T Series
Package Information 48LD Outline Dimensions
(48TFBGA)
VIEW BOTTOM VIEW Ball#A1 CORNER 0.10 0.25 Ball*A1 CORNER (48X)
unit:
0.10 0.20(4X)
SIDE VIEW 0.25
(0.36)
SEATING PLANE
Symbol
Dimensions MIN. 1.04 0.20 0.48 5.90 7.90 -0.30 NOM. 1.14 0.25 0.53 6.00 8.00 3.75 5.25 0.75 0.35 MAX. 1.24 0.30 0.58 6.10 8.10 -0.40
Note: BALL DIAMETER, BALL PITCH, STAND-OFF PACKAGE THICKNESS DIFFERENT FROM JEDEC SPEC MO192 (LOW PROFILE FAMILY). PRIMARY DATUM SEATING PLANE DEFINED SPHERICAL CROWNS SOLDER BALLS. DIMENSION MEASURED MAXIMUM. THERE SHALL MINIMUM CLEARANCE 0.25mm BETWEEN EDGE SOLDER BALL BODY EDGE.
(July, 2003, Version 1.0)
AMIC Technology, Corp.

256K VOLTAGE CMOS SRAM Document Title 256K VOLTAGE CMOS SRAM Revi

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