512K VOLTAGE CMOS SRAM Document Title 512K VOLTAGE CMOS SRAM Revi

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512K VOLTAGE CMOS SRAM Document Title 512K VOLTAGE CMOS SRAM Revi

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LP62S4096E-T Series
512K VOLTAGE CMOS SRAM
Document Title 512K VOLTAGE CMOS SRAM Revision History
History
Change VCCmax from 3.3V 3.6V product family 55ns specification product family 32-pin TSSOP reverse type package
Issue Date
January 2002 April 2003
Remark
Final
(April, 2003, Version 3.0)
AMIC Technology, Corp.
LP62S4096E-T Series
512K VOLTAGE CMOS SRAM
Features
Power supply range: 2.7V 3.6V Access times: 55ns 70ns (max.) Current: Very power version: Operating: 30mA (max.) Standby: 10µA (max.) Full static operation, clock refreshing required inputs outputs directly TTL-compatible Common using three-state output Data retention voltage: (min.) Available 32-pin TSOP/TSSOP 36-ball package
General Description
LP62S4096E-T operating current 4,194,304-bit static random access memory organized 524,288 words bits operates power supply range: 2.7V 3.3V. built using AMIC's high performance CMOS process. Inputs three-state outputs compatible allow direct interfacing with common system structures. chip enable inputs provided POWER-DOWN device enable output enable input included easy interfacing. Data retention guaranteed power supply voltage package only
Product Family
Product Family Operating Temperature Range Speed Power Dissipation Data Retention Standby Operating (ICCDR, Typ.) (ISB1, Typ.) (ICC2, Typ.) Package Type TSOP TSSOP (Forward type) TSSOP (Reverse type)
LP62S4096E-T
-25°C +85°C
2.7V~3.6V
55ns 70ns
0.08µA
0.3µA
Typical values measured 3.0V, 25°C 100% tested. Data retention current 2.0V.
(April, 2003, Version 3.0)
AMIC Technology, Corp.
LP62S4096E-T Series
Configurations
TSOP/(TSSOP) (forward type) TSSOP (reverse type) (Chip Size Package) 36-pin View
I/O5 I/O6 I/O7 I/O8 I/O1 I/O2 I/O3 I/O4
LP62S4096EXR-T
LP62S4096EV-T (LP62S4096EX-T)
Name Name
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
Block Diagram
DECODER 1024 4096 MEMORY ARRAY
I/O1
INPUT DATA CIRCUIT
COLUMN
I/O8
CONTROL CIRCUIT
(April, 2003, Version 3.0)
AMIC Technology, Corp.
LP62S4096E-T Series
Description
Symbol Description
Recommended Operating Conditions
-25°C 85°C) Symbol Parameter Supply Voltage Ground Input High Voltage Input Voltage Output Load Output Load Min. -0.3 Typ. Max. +0.6 Unit
I/O1 I/O8 CE1,
Address Inputs Data Input/Outputs Ground Chip Enable Output Enable Write Enable Power Supply
(April, 2003, Version 3.0)
AMIC Technology, Corp.
LP62S4096E-T Series
Absolute Maximum Ratings*
-0.5V 4.0V IN/OUT Volt GND- -0.5V 0.5V Operating Temperature, Topr -25°C 85°C Storage Temperature, Tstg -55°C 125°C Temperature Under Bias, Tbias -10°C 85°C Power Dissipation, 0.7W
*Comments
Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage this device. These stress ratings only. Functional operation this device these other conditions above those indicated operational sections this specification implied intended. Exposure absolute maximum rating conditions extended periods affect device reliability.
Electrical Characteristics
Symbol Parameter
-25°C 85°C, 2.7V 3.6V, LP62S4096E-55LLT 70LLT Min. Typ. Max. CE1= CE2= =VIL VI/O CE1= VIL, CE2= II/O Min. Cycle, Duty 100%, CE1= CE2= VIH, II/O CE1= VIL, CE2= VIH, 1MHZ II/O 3.3V CE1= VIH, CE2= 3.3V 0.2V, 0.2V 0.2V 2.1mA -1.0mA Unit Conditions
Input Leakage Current
Output Leakage Current
Active Power Supply Current
ICC1
Dynamic Operating Current
ICC2
Dynamic Operating Current
Standby Power
ISB1
Supply Current
Output Voltage Output High Voltage
(April, 2003, Version 3.0)
AMIC Technology, Corp.
LP62S4096E-T Series
Truth Table
Mode Standby Standby Output Disable Read Write Note:
Operation High High High DOUT
Supply Current ISB, ISB1 ISB, ISB1 ICC, ICC1, ICC2 ICC, ICC1, ICC2 ICC, ICC1, ICC2
Capacitance 25°C, 1.0MHz)
Symbol CIN* CI/O* Parameter Input Capacitance Input/Output Capacitance Min. Max. Unit Conditions VI/O
These parameters sampled 100% tested.
Characteristics -25°C 85°C, 2.7V 3.6V)
Symbol Parameter LP62S4096E-55LLT Min. Read Cycle tACE1, tACE2 tCLZ1, tCLZ2 tOLZ tCHZ1, tCHZ2 tOHZ Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Output Valid Chip Enable Output Output Enable Output Chip Disable Output High Output Disable Output High Output Hold from Address Change Max. LP62S4096E-70LLT Min. Max. Unit
(April, 2003, Version 3.0)
AMIC Technology, Corp.
LP62S4096E-T Series
Characteristics (continued)
Symbol Parameter LP62S4096E-55LLT Min. Write Cycle tCW1 tWHZ Write Cycle Time Chip Enable Write Address Setup Time Address Valid Write Write Pulse Width Write Recovery Time Write Output High Data Write Time Overlap Data Hold from Write Time Output Active from Write Max. LP62S4096E-70LLT Min. Max. Unit
Notes: tCHZ, tOHZ tWHZ defined time which outputs achieve open circuit condition referred output voltage levels. Timing Waveforms Read Cycle 1(1)
Address
tOLZ5
tACE1 tACE2 tCLZ1 tCLZ2 DOUT
tOHZ tCHZ1 tCHZ2
(April, 2003, Version 3.0)
AMIC Technology, Corp.
LP62S4096E-T Series
Timing Waveforms (continued)
Read Cycle
Address
DOUT
Read Cycle
tACS1 tACS2 tCLZ1 tCLZ2
tCHZ1 tCHZ2
DOUT
Notes:
high Read Cycle. Device continuously enabled, CE2= VIH. Address valid prior coincident with transition transition high. VIL. Transition measured ±500mV from steady state. This parameter sampled 100% tested.
(April, 2003, Version 3.0)
AMIC Technology, Corp.
LP62S4096E-T Series
Timing Waveforms (continued)
Write Cycle (Write Enable Controlled)
Address tcw1 ,tcw2
tWR3
tAS1
tWP2
tWHZ7 tOW7 DOUT
(April, 2003, Version 3.0)
AMIC Technology, Corp.
LP62S4096E-T Series
Write Cycle (Chip Enable Controlled)
Address
tAS1
tCW1 tCW2
tWR3
tWHZ7 DOUT
Notes: measured from address valid beginning Write. Write occurs during overlap (tWP) high measured from earliest going high going going high Write cycle. high transition occurs simultaneously with transition after transition, outputs remain high impedance state. measured from later going going high Write. level high low. Transition measured ±500mV from steady state. This parameter sampled 100% tested.
(April, 2003, Version 3.0)
AMIC Technology, Corp.
LP62S4096E-T Series
Test Conditions
Input Pulse Levels Input Rise Fall Time Input Output Timing Reference Levels Output Load 0.4V 2.4V 1.5V Figures
30pF
Including scope jig.
Including scope jig.
Figure Output Load
Figure Output Load tCLZ, tOHZ, tOL, tCHZ, tWHZ,
Data Retention Characteristics -25°C 85°C)
Symbol Parameter Data Retention Min. Typ. Max. Unit Conditions 0.2V, 0.2V 2.0V, ICCDR Data Retention Current LL-Version 0.08 0.2V, 0.2V
tCDR
Chip Disable Data Retention Time Operation Recovery Time Rising Time from Data Retention Voltage Operating Voltage ICCDR: max.
Retention Waveform
LP62S4096E-55LLT 70LLT
40°C
(April, 2003, Version 3.0)
AMIC Technology, Corp.
LP62S4096E-T Series
Data Retention Waveform Controlled)
DATA RETENTION MODE
2.7V tCDR
2.7V
0.2V
Data Retention Waveform (CE2 Controlled)
DATA RETENTION MODE 2.7V tCDR 2.7V
0.2V
Ordering Information Part
LP62S4096EV-55LLT LP62S4096EX-55LLT LP62S4096EXR-55LLT LP62S4096EU-55LLT LP62S4096EV-70LLT LP62S4096EX-70LLT LP62S4096EXR-70LLT LP62S4096EU-70LLT
Access Time(ns)
Operating Current Max.(mA)
Standby Current Max.(uA)
Package
TSOP TSSOP (Forward) TSSOP (Reverse) TSOP TSSOP (Forward) TSSOP (Reverse)
(April, 2003, Version 3.0)
AMIC Technology, Corp.
LP62S4096E-T Series
Package Information TSOP TYPE 20mm) Outline Dimensions
unit: inches/mm
12.0°
GAUGE PLANE
0.25
Detail Detail
0.10(0.004)
Symbol
Dimensions inches 0.047 Max. 0.004±0.002 0.039±0.002 0.008±0.001 0.006±0.001 0.724±0.004 0.315±0.004 0.020 TYP. 0.787±0.007 0.020±0.004 0.031 TYP. 0.0167 TYP. 0.004 Max.
Dimensions 1.20 Max. 0.10±0.05 1.00±0.05 0.20±0.03 0.15±0.02 18.40±0.10 8.00±0.10 0.50 TYP. 20.00±0.20 0.50±0.10 0.80 TYP. 0.425 TYP. 0.10 Max.
Notes: maximum value dimension includes flash. Dimension does include resin fins. Dimension Board surface mount pitch design reference only. Dimension includes flash.
(April, 2003, Version 3.0)
AMIC Technology, Corp.
LP62S4096E-T Series
Package Information TSSOP TYPE 13.4mm) Outline Dimensions (Forward Type)
unit: inches/mm
12.0°
GAUGE PLANE
0.25
Detail Detail
0.10MM
SEATING PLANE
Symbol
Dimensions inches 0.049 Max. 0.002 Min. 0.039±0.002 0.008±0.001 0.006±0.0003 0.315±0.004 0.020 TYP. 0.528±0.008 0.465±0.004 0.02±0.008 0.0266 Min. 0.0109 TYP. 0.004 Max.
Dimensions 1.25 Max. 0.05 Min. 1.00±0.05 0.20±0.03 0.15±0.008 8.00±0.10 0.50 TYP. 13.40±0.20 11.80±0.10 0.50±0.20 0.675 Min. 0.278 TYP. 0.10 Max.
Notes: maximum value dimension includes flash. Dimension does include resin fins. Dimension Board surface mount pitch design reference only. Dimension includes flash.
(April, 2003, Version 3.0)
AMIC Technology, Corp.
LP62S4096E-T Series
Package Information TSSOP TYPE 13.4mm) Outline Dimensions (Reverse Type)
unit: inches/mm
0.25
GAUGE PLANE
12.0°
Detail
Detail
SEATING PLANE
0.10MM
Symbol
Dimensions inches 0.049 Max. 0.002 Min. 0.039±0.002 0.008±0.001 0.006±0.0003 0.315±0.004 0.020 TYP. 0.528±0.008 0.465±0.004 0.02±0.008 0.0266 Min. 0.0109 TYP. 0.004 Max.
Dimensions 1.25 Max. 0.05 Min. 1.00±0.05 0.20±0.03 0.15±0.008 8.00±0.10 0.50 TYP. 13.40±0.20 11.80±0.10 0.50±0.20 0.675 Min. 0.278 TYP. 0.10 Max.
Notes: maximum value dimension includes flash. Dimension does include resin fins. Dimension Board surface mount pitch design reference only. Dimension includes flash.
(April, 2003, Version 3.0)
AMIC Technology, Corp.
LP62S4096E-T Series
Package Information 36LD Outline Dimensions
VIEW BOTTOM VIEW Ball#A1 CORNER 0.10 0.25 Ball*A1 CORNER (36X)
unit:
0.10 0.20(4X)
SIDE VIEW 0.25
(0.36)
SEATING PLANE
Symbol
Dimensions MIN. 1.00 0.16 0.48 5.80 7.80 -0.25 NOM. 1.10 0.21 0.53 6.00 8.00 3.75 5.25 0.75 0.30 MAX. 1.20 0.26 0.58 6.20 8.20 -0.35
Note: BALL DIAMETER, BALL PITCH, STAND-OFF PACKAGE THICKNESS DIFFERENT FROM JEDEC SPEC MO192 (LOW PROFILE FAMILY). PRIMARY DATUM SEATING PLANE DEFINED SPHERICAL CROWNS SOLDER BALLS. DIMENSION MEASURED MAXIMUM. THEERE SHALL MINIMUM CLEARANCE 0.25mm BETWEEN EDGE SOLDER BALL BODY EDGE. BALL OPENING SUBSTRATE 0.25mm (SMD) SUGGEST DESIGN LAND SIZE 0.25mm (NSMD)
(April, 2003, Version 3.0)
AMIC Technology, Corp.

512K VOLTAGE CMOS SRAM Document Title 512K VOLTAGE CMOS SRAM Revi

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