Home Networking Board Design Using PCnet-Home Devices This applic

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Home Networking Board Design Using PCnetTM-Home Devices
Home Networking Board Design Using PCnet-Home Devices
This application note intended assist customers using AMD's Am79C978/Am79C978A PCnetTM-Home devices. Details concerning application information, circuit design, EMI, printed circuit layout techniques, component selection provided help ensure first-pass success implementing functional design that optimized signal quality. This document should used conjunction with product data sheet functional descriptions features devices, well OrCAD schematics provided Evaluation AMD's page. Contact your local Field Applications Engineer Sales Office questions discuss concerns have.
INTRODUCTION
Am79C978/Am79C978A devices highly integrated Home Networking devices implementing Fast-Ethernet 10/100 Mbps 802.3 Media Access Controller, 10BASE-T Physical Transceiver, Mbps HomePNA technology. Figure shows block diagram PCnet-Home device.
(10/100 PHY)
Magnetic
HRTX+ TXRX+
HR_PHY
10BASE-T
EEPROM Interface Block
10/100 Media Access Controller 802.3 Interface
Crystal Clock Source
22368A-1
Figure PCnet-Home Block Diagram
Publication# 22368 Rev: Amendment/0 Issue Date: November 1999
Board Design Features
Am79C978/Am79C978A PCnet-Home devices have following features:
Voltage Regulator LM3940IMP-3.3
Integrated Mbps HomePNA PHY, 10BASE-T PHY, 10/100 Mbps Integrated magnetics with HomePNA bandpass filter power surge protection against lightning EEPROM subvendor subsystem well 48-bit address Magic Packetinterfaced motherboards supporting remote wake-up Lowpass filter prevent noise from phone G.lite HomePNA line NetPHYTM-1LP (10/100 PHY) interface RJ-11s (one HomePNA port Phone/G.lite) RJ-45 Ethernet port LEDs Link, Activity, Speed, Collision Glueless compliant interface power management support PC98/PC99 compliance
VOUT
22368A-2
Figure Typical Linear Regulator Implementation
POWER SUPPLY
AMD's PCnet-Home devices operate from +3.3 ±300 power supply. Some systems have available +3.3 supply. easiest convert from supply +3.3 supply through linear regulator. Figure Converting from supply +3.3 supply recommended additional power dissipation. addition, optimal small signal receive sensitivity performance, linear regulator should used. advantage linear regulator that provides very quiet output, isolated from noise digital supply from bus. Since small signal receive performance sensitive power supply noise, clean outputs linear regulator contribute improved receive performance.
Device Placement Routing
adapter card design appendix shows optimized placement components (see layout plot). location Am79C978/Am79C978A devices have been chosen allow minimum length signal routing. Short signal traces reduce capacitive loading caused signal trace noise from adjacent signals. Care should given avoid routing digital signals across analog boundaries Since there minimum filtering secondary side transformer, also recommended that integrated magnetics placed near bracket (next RJ-11) prevent noise issue. appendix layout placement.
Bypass Capacitors
Great care should given power distribution decoupling specific Am79C978/Am79C978A power pins. Poor power decoupling these pins cause degradation HomePNA small signal receive sensitivity much Bypass capacitors more effective when located close pins chip. Table pins that require bypass. case 4-layer design, recommended that each supplied from their vias. preferred method layout bypass capacitors shown Figure
Home Networking Board Design Using PCnet-Home Devices
Table
Suggested Bypassed Power Pins PQFP
XCLK/XTAL
Power Names VDDCO power VDDHR_RX power HomePNA VDDHR_TX power HomePNA DVDDA_HR voltage DVDD_TX power 10BASE-T DVDD_RX power 10BASE-T DVDDA_HR power HomePNA DVDDD digital power
Bypass Caps
XTAL1
Am79C978
XTAL2
22368A-4
Figure Crystal Clock Source
crystal suppliers listed below:
Ecliptik Corporation www.ecliptik.com Epson Corporation www.epson.com
Note: 144-pin design, refer power signals Table
External Crystal Characteristics
When using crystal drive oscillator, following crystal specification Table used ensure less than ±0.5 jitter DO±.
DVDD
AVDD
DVSS
AVSS
Am79C978
Table
22368A-3
Crystal Characteristics
Units 0.022
Parameter Parallel Resonant Frequency Resonant Frequency Error Change Resonant Frequency With Respect Temperature (0°-70° Crystal Load Capacitance Motional Crystal Capacitance (C1) Internal Equivalent Series Resistance Shunt Capacitance
Figure Recommended Bypass Capacitors
CRYSTAL OSCILLATOR
PCnet-Home devices include on-chip oscillator circuitry allowing external crystal attached XTAL1 XTAL2 pins, XCLK/ XTAL tied LOW. Alternatively, clock source also used drive XTAL1 pin, which case XTAL2 MUST left unconnected XCLK/XTAL tied HIGH. Table shows appropriate clock select Figure shows clock interface. Table External Clock Source Selection
Clock Source crystal osc. Clock Select XCLK/XTAL XCLK/XTAL HIGH Name XTAL1 XTAL2 XTAL1
Note: *Requires trimming specification; trimmed total.
When selecting crystal PCnet-Home design, crystal should meet ppm, standard load capacitors pF), 0.005% tolerance (see Table
Home Networking Board Design Using PCnet-Home Devices
EEPROM INTERFACES
PCnet-Home devices provide 4-wire serial interface standard EEPROMs, such 93C46 from Atmel Corporation other vendors. EEPROM device operate from either +3.3 supply. EEPROM necessary store unique board subvendor well IEEE address order obtain Microsoft's WHQL logo. Each adapter card manufacturer responsibility ensuring that card contains unique 48-bit IEEE address assigned company IEEE. assigned base address number then programmed into EEPROM. addition, EEPROM provides manufacturer flexibility change other home networking default settings, such indication. EEPROM signal interface itself multiplexed with signals. Table Table EEPROM Interfaces
Name EECS EEDI/LED0 EESK/LED1 EEDO/LED3 LED2 LED4 EEPROM EECS EEDI EESK EEDO -LED0 LED1 LED3 LED2 LED4 LEDS
LED2 default active indicate SPEED. LED3 default active indicate TRANSMIT activity. LED4 programmable indicate various home network activity.
MAGNETIC INTERFACE
PCnet-Home devices include internal 10BASE-T Ethernet Mbps home networking. internal 10BASE-T used, 1.42:1 magnetic ratio required. addition, voltage divider circuit required bias received differential signal pair. voltage bias network 2K/1K should also have bypass that center volt node ground. attached schematic which improved Error Rate (BER). external 10/100 NetPHY-1LP device used, magnetic ratio required. Also, appropriate signal termination necessary unconnected 10BASE-T TX/RX signal pair. HomePNA Mode section below. According data sheets from vendors below, following surface mount magnetics should work Mbps HomePNA, 10BASE-T, 100BASE-T/TX applications (see Table Only part numbers each vendor listed brevity, most vendors offer number suitable devices. This meant comprehensive list. Magnetics vendors change their product offering very frequently, please contact vendor directly before finalizing design. Note: magnetics listed below have bandpass filter power surge protection built
Indication
LED0 default active indicate LINK status. LED1 default active indicate RECEIVE activity.
Table Magnetics Vendors
Part 10BASE-T Part HomePNAand HomePNA Only Magnetic Integrated Magnetic APC76085 RS556-5000-05 7074-37 EPB5035G B6003 FH166911 APC76160 RS556-5000-06 7084-30 EPB5036G B6006L FH166901 Part 10/100 BASE-T/TX Ethernet HomePNA Integrated Magnetic APC76165 RS556-5000-07 FGHR-S001NG1 7073-30 EPB5037G B6007 FH166916
Magnetics Vendor Belfuse Halo Midcom (Nanopulse) Electronics, Inc. Pulse Engineering
www.apcisdn.com www.belfuse.com www.haloelectronics.com www.midcom-inc.com www.pcainc.com www.pulseeng.com www.ycl.com
Home Networking Board Design Using PCnet-Home Devices
HomePNA Only Mode 10BASE-T Port Connected)
internal 10BASE-T port utilized, appropriate 10BASE-T output signals (TX± RX±) should resistively terminated. Figure more details. This termination helps reduce noise injected Ethernet link pulse back into HomePNA analog section. addition, only HomePNA magnetics should used prevent interference from floating 10BASE-T magnetic section both 10BASE-T/HomePNA magnetics used).
Keep digital signals other signals away from differential signals that might introduce noise differential pairs. Keep 20-MHz clock source away from HomePNA differential output pair prevent coupling differential pair. separate digital analog ground planes 4-layer board designed. Keep them same maintain same current return path.
Since PCnet-Home port utilizes telephone Ethernet cable, careful design techniques must considered order ensure successful first-pass requirements, Part Class Note: Part telecommunication requirements need tested since PCnet-Home only transfers data voice support like modem. Consult with your testing house more details.
+3.3
RXRX+
Am79C978
HomePNA Magnetic
HRCTAP Ring RJ-11
When routing HomePNA pair with magnetics close RJ-11 port, follow Part requirements i.e., there should power plane around area ring traces must have enough clearance least mils) isolate potential power surges. Keep ground return paths close signal paths. AMD's design, there same ground, i.e., separate analog digital ground planes. Isolated planes, (i.e., +3.3 plane), should avoided capacitively coupling planes together prevent discontinuities provide signal return path across isolated planes. used +3.3 planes together should good bypass (.01 or.1 should placed close center point signals that cross boundary each side group. chassis ground plane that connected bracket should isolated from signal plane prevent radiation from leaking through causing failure.
Additional information about layout reduce found http://www.amd.com/
22368A-5
Figure
Recommended Termination HomePNA Only Mode
LAYOUT RECOMMENDATION
following some general guidelines that will ensure success PCnet-Home design: Component placement should carefully considered order optimize shorten routing traces. Keep bypass capacitors close possible power pins, provide enough capacitors analog power pins. good rule thumb have capacitor each analog power pin. Table more details. Differential signal pairs from chip side magnetic side, such TX/RX 10BASE-T, HRTRXP HRTRXN HomePNA, should maintained identically (i.e., equal length same side minimize impedance mismatch) between routing pairs. 1015 trace thickness recommended with 8-10 space maintain impedance signal pair.
CONCLUSION
Following guidelines described this document will help ensure that customers designing with PCnetHome devices experience first-pass success. Contact your local FAEs SAEs samples, schematics, layout reviews.
Home Networking Board Design Using PCnet-Home Devices
Home Networking Board Design Using PCnet-Home Devices
APPENDIX
PCnet-Home Design
Home Networking Board Design Using PCnet-Home Devices
Home Networking Board Design Using PCnet-Home Devices
Home Networking Board Design Using PCnet-Home Devices
Home Networking Board Design Using PCnet-Home Devices
Home Networking Board Design Using PCnet-Home Devices
Home Networking Board Design Using PCnet-Home Devices
contents this document provided connection with Advanced Micro Devices, Inc. ("AMD") products. makes representations warranties with respect accuracy completeness contents this publication reserves right make changes specifications product descriptions time without notice. license, whether express, implied, arising estoppel otherwise, intellectual property rights granted this publication. Except forth AMD's Standard Terms Conditions Sale, assumes liability whatsoever, disclaims express implied warranty, relating products including, limited implied warranty merchantability, fitness particular purpose, infringement intellectual property right. AMD's products designed, intended, authorized warranted components systems intended surgical implant into body, other applications intended support sustain life, other application which failure AMD's product could create situation where personal injury, death, severe property environmental damage occur. reserves right discontinue make changes products time without notice.
1999 Advanced Micro Devices, Inc. rights reserved.
Trademarks AMD, logo, combinations thereof, HomePNA PCnet trademarks Advanced Micro Devices, Inc. Other product names used this publication identification purposes only trademarks their respective companies.

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