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Processor Model Data Sheet
Publication 23792 Rev: Issue Date: October 2000
2000 Advanced Micro Devices, Inc. rights reserved. contents this document provided connection with Advanced Micro Devices, Inc. ("AMD") products. makes representations warranties with respect accuracy completeness contents this publication reserves right make changes specifications product descriptions time without notice. license, whether express, implied, arising estoppel otherwise, intellectual property rights granted this publication. Except forth AMD's Standard Terms Conditions Sale, assumes liability whatsoever, disclaims express implied warranty, relating products including, limited implied warranty merchantability, fitness particular purpose, infringement intellectual property right. AMD's products designed, intended, authorized warranted components systems intended surgical implant into body, other applications intended support sustain life, other application which failure AMD's product could create situation where personal injury, death, severe property environmental damage occur. reserves right discontinue make changes products time without notice.
Trademarks AMD, logo, Athlon, combinations thereof, 3DNow! trademarks Advanced Micro Devices, Inc. trademark Intel Corporation. Digital Alpha trademarks Digital Equipment Corporation. Other product names used this publication identification purposes only trademarks their respective companies.
23792G-October 2000
AthlonProcessor Model Data Sheet
Contents
Revision History About This Data Sheet Overview
AthlonProcessor Model Microarchitecture Summary Overview Signaling Technology Push-Pull (PP) Drivers AthlonSystem Signals
Interface Signals
Logic Symbol Diagram Power Management
Power Management States Working State Halt State Stop Grant States. Probe State. Connect Disconnect Protocol Connect Protocol Connect State Diagram Clock Control
Thermal Design Electrical Data
6.10 6.11 6.12 6.13 Conventions Athlon Processor Model Interface Signal Groupings Voltage Identification (VID[4:0]) Frequency Identification (FID[3:0]) VCCA Characteristics Decoupling Operating Ranges Absolute Ratings VCC_CORE Voltage Current SYSCLK SYSCLK# Characteristics Athlon System Characteristics General Characteristics APIC Pins Characteristics
Contents
Preliminary Information AthlonProcessor Model Data Sheet
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Signal Power-Up Requirements
Power-Up Requirements Signal Sequence Timing Description Clock Multiplier Selection (FID[3:0]) Processor Warm Reset Requirements Athlon Processor Model Northbridge Reset Pins Introduction Pinout Diagram Socket Tabs Heatsink Clips Introduction List Detailed Descriptions A20M# Athlon System Pins Analog CLKFWDRST CLKIN, RSTCLK (SYSCLK) Pins. CONNECT COREFB COREFB# Pins DBRDY DBREQ# Pins FERR FID[3:0] Pins FLUSH# IGNNE# INIT# INTR Pin. JTAG Pins K7CLKOUT K7CLKOUT# Pins. Pins Pins Orientation Pins Bypass Test Pins PWROK SADDIN[1]# SADDOUT[1:0]# Pins
Mechanical Data
Descriptions
Contents
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AthlonProcessor Model Data Sheet
Scan Pins SCHECK[7:0]# SMI# STPCLK# SYSCLK SYSCLK# Pins SYSVREFMODE Pin. VCCA VID[4:0] Pins VREFSYS VCC_Z, VSS_Z Pins
Appendix
Ordering Information
Standard Athlon Processor Model Products
Conventions Abbreviations
Signals Bits Data Terminology Abbreviations Acronyms.
Contents
Preliminary Information AthlonProcessor Model Data Sheet
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Contents
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AthlonProcessor Model Data Sheet
List Figures
Figure Typical AthlonProcessor Model System Block Diagram Figure Figure Figure Figure Figure Figure Figure Figure Logic Symbol Diagram Athlon Processor Model Power Management States Example System Disconnect Sequence Exiting Stop Grant State/Bus Reconnect Sequence Northbridge Connect State Diagram Processor Connect State Diagram SYSCLK SYSCLK# Differential Clock Signals SYSCLK Waveform
Figure Signal Relationship Requirements During Power-Up Sequence Figure Typical Protocol Sequence Figure Package, Top, Side, Bottom Views Figure Socket with Outline Socket Heatsink Figure Socket Heatsink Side View Figure Athlon Processor Model Diagram- Topside View Figure Example Athlon Processor Model
List Figures
Preliminary Information AthlonProcessor Model Data Sheet
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viii
List Figures
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AthlonProcessor Model Data Sheet
List Tables
Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Thermal Design Power. AthlonProcessor Model Interface Signal Groupings FID[3:0] Characteristics VCCA Characteristics Operating Ranges. Absolute Ratings VCC_CORE Voltage Current. SYSCLK SYSCLK# Characteristics SYSCLK SYSCLK# Characteristics Athlon System Characteristics Athlon System Characteristics General Characteristics. APIC Pins Characteristics Protocol States Actions Name Abbreviations Socket Cross-Reference Location FID[3:0] Clock Multiplier Encodings VID[4:0] Code Voltage Definition Abbreviations Acronyms.
List Tables
Preliminary Information AthlonProcessor Model Data Sheet
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List Tables
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AthlonProcessor Model Data Sheet
Revision History
Date
Description Added information about front side (FSB) follows:
October 2000
"AMD AthlonProcessor Model Microarchitecture Summary" page Table "Thermal Design Power," page Table "VCC_CORE Voltage Current," page Table "SYSCLK SYSCLK# Characteristics," page Chapter "Ordering Information" page
October 2000
Revised VID[4:0] information Table page "VID[4:0] Pins" page Added Information about AthlonProcessor Model follows: Chapter "Overview" page Table "Thermal Design Power," page Table "Operating Ranges," page Table "VCC_CORE Voltage Current," page Revised include 1200 speed grade Chapter "Ordering Information" page Revised Maximum Typical Thermal Power numbers Table "Thermal Design Power," page Added note Table temperature. Revised table note "The Sleep Voltage used sleep state Powerup voltage before PWROK PWRGD asserted." Table "Operating Ranges," page Updated "Motherboard Design Guide, order# 90009" with document name "Socket Motherboard Design Guide, order# 24363" throughout book. Added SAI#[0] location AJ29 Figure "AMD AthlonProcessor Model Diagram-Topside View" page Added (AH6) Table "Pin Name Abbreviations," page Table "Socket Cross-Reference Location," page 55Revised connect (NC) pins grid array (PGA) follows:
October 2000
Figure "AMD AthlonProcessor Model Diagram-Topside View" page Table "Pin Name Abbreviations," page Table "Socket Cross-Reference Location," page Revised KLCKOUT/KCLKOUT# verbiage Chapter "K7CLKOUT K7CLKOUT# Pins" page
Revision History
Preliminary Information AthlonProcessor Model Data Sheet
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Date
Description Added information about 1.1-GHz AthlonProcessor Model follows: Chapter "Overview" page Table "Thermal Design Power," page Table "Operating Ranges," page Table "VCC_CORE Voltage Current," page Revised reorganized characteristics SYSCLK SYSCLK#. Table "SYSCLK SYSCLK# Characteristics," page Table "SYSCLK SYSCLK# Characteristics," page
August 2000
Revision History
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AthlonProcessor Model Data Sheet
Date
Description Added Table "Thermal Design Power," page Chapter "Thermal Design". Revised Chapter "Electrical Data" page follows: Added JTAG, APIC, Test, Miscellaneous rows Table "AMD AthlonProcessor Model Interface Signal Groupings," page Reorganized signals into their correct categories. Added "Conventions" page Revised information Table "VID[4:0] Characteristics," page Revised information Table "FID[3:0] Characteristics," page Added revised information Table "SYSCLK/SYSCLK# Characteristics," page Revised IVCCA information Table "VCCA Characteristics," page Revised maximum values Table "Absolute Ratings," page Revised reorganized information Table "VCC_CORE Voltage Current," page thermal information, Table "Thermal Design Power," page Changed VCC_CORE 1.75V speed grades. Made following changes Chapter
August 2000
Changed power source signal name from VDDA VCCA. Revised Figure "Signal Relationship Requirements during Power-Up Sequence" page Revised timing requirements Step page Revised reorganized Table "SYSCLK SYSCLK# Characteristics," page Added VCROSS symbol this table. Revisions continued next page.
Revision History
xiii
Preliminary Information AthlonProcessor Model Data Sheet
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Date
Continued:
Description Revised figures information Chapter "Mechanical Data" page Revised Chapter "Pin Descriptions" page follows: Changed FERR# FERR Figure "AMD AthlonProcessor Model Diagram- Topside View" page "FERR Pin" page more information. Revised definition Reference column Table "Socket Cross-Reference Location," page "Pin List" page Table "Socket Cross-Reference Location," page revised information following locations: (PICCLK), (PIC[0]#), (PIC[1]#), (VCC_Z), AE33 (SADDIN[5]#), AE35 (SDATAOUTCLK[0]#), AE37 (SDATA[9]#), (FERR), AJ21 (CLKFWDRST), AJ23 (VCCA), AN13 (PLLMON1), AN15 (PLLBYPASSCLK), AN21 (K7CLKOUT#), AN29 (SADINN[12]#), AN31 (SADINN[14]#), AN33 (SDATAINVAL#), AN35 (SADINN[13]#), AN37 (SADINN[9]#) Revised information "K7CLKOUT K7CLKOUT# Pins" page Removed specific resistor values "Detailed Descriptions" page specific implementation information, Motherboard Design Guide, order# 90009. Revised Chapter "Ordering Information" page
August 2000
June 2000
Initial public release.
Revision History
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AthlonProcessor Model Data Sheet
About This Data Sheet
This AthlonProcessor Model data sheet describes technical specifications Athlon Processor Model delivered package. information about Athlon processor module, AthlonProcessor Module Data Sheet, order#21016.
About This Data Sheet
Preliminary Information AthlonProcessor Model Data Sheet
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About This Data Sheet
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AthlonProcessor Model Data Sheet
Overview
AthlonProcessor Model powers next generation computing platforms, delivering compelling performance cutting-edge applications unprecedented computing experience.
Athlon processor with performance-enhancing cache memory latest member Athlonfamily processors designed meet computation-intensive requirements cutting-edge software applications running high-performance desktop systems, workstations, servers. Delivered package achieving frequencies 1.2-GHz (1200 MHz), Athlon processor delivers integer, floating-point multimedia performance most demanding applications running system platforms. cutting-edge software applications, including digital content creation, digital photo editing, digital video, image compression, video encoding streaming over internet, DVD, ommerc modeling, workstation-class computer-aided design (CAD), commercial desktop publishing, speech recognition, Athlon processor delivers compelling performance. also offers scalability `peace-of-mind' reliability that managers business users require enterprise computing. Athlon processor features seventh-generation microarchitecture with integrated cache, which supports growing processor system bandwidth requirements emerging software, graphics, I/O, memory technologies. Athlon processor's high-speed execution core includes multiple instruction decoders, dual-ported 128-Kbyte split level-one (L1) cache, 256-Kbyte on-chip cache, three independent integer pipelines, three address calculation pipelines, superscalar, fully pipelined, out-of-order, three-way floating-point engine. floating-point engine capable delivering superior performance numerically complex applications. Athlon processor microarchitecture incorporates enhanced 3DNow!technology, high-performance cache architecture, both 200-MHz 1.6-Gigabyte second
Chapter
Overview
Preliminary Information AthlonProcessor Model Data Sheet
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Gigabyte secoond Athlonsystem bus. Athlon system combines latest technological advances, such point-to-point topology, source-synchronous packet-based transfers, low-voltage signaling, provide most powerful, scalable available processor. addition, bine with chipset Athlon system interfaces with double-data rate (DDR) memory subsystems. Athlon processor binary-compatible with existing software backwards compatible with applications optimized MMXand 3DNow! instructions. Using data format single-instruction multiple-data (SIMD) operations based instruction model, Athlon processor produce many four, 32-bit, single-precision floating-point results clock cycle. enhanced 3DNow! technology implemented Athlon processor includes integer multimedia instructions software-directed data movement instructions optimizing such applications digital content creation streaming video internet, well inst ruct ions digit process (DSP)/communications applications.
AthlonProcessor Model Microarchitecture Summary
following features summarize Athlon processor microarchitecture:
industry's first nine-issue, superpipelined, superscalar processor microarchitecture designed high clock frequencies Multiple instruction decoders Three out-of-order, superscalar, fully pipelined floating-point execution units, which execute (floating-point), 3DNow! instructions Three out-of-order, superscalar, pipelined integer units Three out-of-order, superscalar, pipelined address calculation units 72-entry instruction control unit Advanced dynamic branch prediction Enhanced 3DNow! technology with instructions enable improved integer math calculations speech
Overview
Chapter
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AthlonProcessor Model Data Sheet
video encoding improved data movement internet plug-ins other streaming applications
200-MHz Athlon system (scalable beyond MHz) enabling leading-edge system bandwidth data movement-intensive applications High-performance cache architecture featuring integrated 128-Kbyte cache 16-way, on-chip 256-Kbyte cache total 384-Kbytes on-chip cache
performance cost-effective, industry-standard form factor. Athlon processor compatible with motherboards based AMD's Socket Figure page shows typical Athlon processor system block diagram. information about Athlon processor module, AthlonProcessor Module Data Sheet, order#21016.
Chapter
Overview
Preliminary Information AthlonProcessor Model Data Sheet
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AthlonProcessor System Controller (Northbridge) Memory DRAM
Peripheral Controller (Southbridge) System Management
SCSI
Dual EIDE BIOS
Figure Typical AthlonProcessor Model System Block Diagram
Overview
Chapter
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AthlonProcessor Model Data Sheet
Interface Signals
Overview
Athlonsystem architecture designed liver unprecede oveme bandw idth next-generation platforms, well high performance required enterprise-class application software. system architecture consists three high-speed channels unidirectional processor request channel, unidirectional probe channel, 72-bit bidirectional data channel, including 8-bit error code correction [ECC] protection), source-synchronous clocking, packet-based protocol. addition, system supports several control, clock, legacy signals. interface signals impedance controlled push-pull low-voltage swing signaling technology contained within Socket mechanical connector, which mechanically compatible with industry-standard SC242 connector. more information, "AMD AthlonSystem Signals" page Chapter "Pin Descriptions" page AthlonSystem Specification, order# 21902.
Signaling Technology
Athlon system uses low-voltage, swing signaling technology, which been enhanced provide larger noise margins, reduced ringing, variable voltage levels. signals push-pull impedance compensated. signal inputs differential receivers, which require reference voltage (VREF). reference signal used receivers determine signal asserted deasserted source. Termination resistors needed because driver impedance matched motherboard high impedance reflection used receiver bring signal past input threshold. more information about pins signals, Chapter "Pin Descriptions" page
Chapter
Interface Signals
Preliminary Information AthlonProcessor Model Data Sheet
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Push-Pull (PP) Drivers
Socket Athlon Processor Model supports Push-Pull (PP) drivers. system logic configures Athlon Processor Model with configuration parameter called SysPushPull (1=PP). impedance drivers match impedance motherboard external resistors connected pins. "ZN, VCC_Z, VSS_Z Pins" page more information.
AthlonSystem Signals
point-to-point interface with following three point-to-point channels:
13-bit unidirectional output address/command channel 13-bit unidirectional input address/command channel 72-bit bidirectional data channel
more information, Chapter "Electrical Data" page AthlonSystem Specification, order# 21902.
Interface Signals
Chapter
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AthlonProcessor Model Data Sheet
Logic Symbol Diagram
Clock
SYSCLK SDATA[63:0]# SDATAINCLK[3:0]# SDATAOUTCLK[3:0]# SCHECK[7:0]# SDATAINVAL# SDATAOUTVAL# SFILLVAL#
SYSCLK# VID[4:0] COREFB COREFB# PWROK
Data
Voltage Control Frequency Control
Probe/SysCMD Request
SADDIN[14:1]# SADDINCLK# SADDOUT[14:0]# SADDOUTCLK# PROCRDY CLKFWDRST CONNECT STPCLK# RESET#
AthlonProcessor Model
FID[3:0] FERR IGNNE# INIT# INTR A20M# SMI#
Legacy
Power Management Initialization
PICCLK PICD[1:0]#
APIC
Figure Logic Symbol Diagram
Chapter
Logic Symbol Diagram
Preliminary Information AthlonProcessor Model Data Sheet
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Logic Symbol Diagram
Chapter
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AthlonProcessor Model Data Sheet
Power Management
Power Management States
AthlonProcessor Model supports low-power Halt Stop Grant states. These states used Advanced Configuration Power Interface (ACPI) enabled operating systems processor power management. Figure shows power management states Athlon Processor Model figure includes ACPI "Cx" naming convention these states.
Halt
Execute SMI#, INTR, NMI, INIT#, RESET#
Working
(Read PLVL2 register throttling)
STPCLK# deasserted
STPCLK# asserted
System connected during following states: Probe state During transitions from Halt state Stop Grant state Stop Grant state Halt state
Figure AthlonProcessor Model Power Management States
Chapter
Incoming Probe
Probe State1
Probe Serviced
Incoming Probe Probe Serviced
Stop Grant Cache Snoopable
C3/S1 Stop Grant Cache Snoopable Sleep
Legend: Hardware transitions Software transitions
Power Management
Preliminary Information AthlonProcessor Model Data Sheet
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following paragraphs descr each powe management states. Note: power management states, system must disable system clock (SYSCLK/SYSCLK#) processor. Working State Halt State Working state refers state which processor executing instructions. When Athlon Processor Model executes instruction, processor issues Halt special cycle system bus. phase-lock loop (PLL) continues run, enabling processor monitor activity provide quick resume from Halt state. processor enters lower power state system logic (Northbridge) disconnects Athlon System response Halt special cycle. Halt state exited when processor samples INIT#, INTR, NMI, RESET#, SMI# asserted. Stop Grant States Athlon Processor Model enters Stop Grant state upon recognition assertion STPCLK# input. There mechanisms asserting STPCLK# hardware software. Southbridge force STPCLK# assertion throttling protect processor from exceeding maximum case temperature. This accomplished asserting THERM# input Southbridge. Throttling asserts STPCLK# percentage predefined throttling period: STPCLK# repetitively asserted deasserted until THERM# deasserted. Software force processor into Stop Grant state accessing ACPI-defined registers typically located Southbridge. Software places processor reading PLVL_2 register Southbridge. probes allowed, shown Figure page ACPI Thermal Zone defined processor, initiate throttling with STPCLK# using ACPI defined P_CNT register Southbridge. processor enters Northbridge during Stop Grant throttling. Stop Grant state also entered system sleep state based write SLP_TYP field ACPI-defined Power Management Chapter
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AthlonProcessor Model Data Sheet
power management control register. During sleep state, system software ensures master probe activity occurs. After recognizing assertion STPCLK#, Athlon Processor Model completes pending in-progress cycles acknowledges STPCLK# assertion issuing Stop Grant special cycle Athlon system bus. After Northbridge disconnects Athlon system response Stop Grant special cycle, processor enters low-power state dictated CLK_Ctl register. During Stop Grant states, processor latches INIT#, INTR interrupts enabled), NMI, SMI#, they asserted. Stop Grant state exited upon deassertion STPCLK# assertion RESET#. When STPCLK# deasserted, processor will initiate connection System disconnected. After processor enters Working state, pending interrupts recognized serviced processor resumes execution instruction boundary where STPCLK# initially recognized. RESET# sampled asserted during Stop Grant state, processor returns Working state reset process begins. Probe State Probe state entered when Northbridge initiates Athlon system connect required probe processor. processor been disconnected from system bus, Northbridge must initiate system connection prior probing processor snoop processor's caches example. When Probe state, processor responds probe cycle same manner when Working state. When probe been serviced, processor returns same state when entered Probe state (Halt Stop Grant state). Once Halt Stop Grant state, low-power disconnection from system bus.
Chapter
Power Management
Preliminary Information AthlonProcessor Model Data Sheet
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Connect Disconnect Protocol
Significant power savings Athlon Processor Model only occurs processor disconnected from system Northbridge while Halt Stop Grant state. Northbridge optionally initiate disconnect upon receipt Halt Stop Grant special cycle. option disconnecting controlled enable Northbridge. Northbridge requires processor service probe after system been disconnected, must first initiate system connect.
Connect Protocol
addition legacy STPCLK# signal Halt Stop Grant special cycles, Athlon system connect protocol includes CONNECT, PROCRDY, CLKFWDRST signals Connect special cycle. Athlon system disconnects initiated Northbridge response receipt Halt Stop Grant special cycle. Reconnect initiated processor response interrupt Halt, STPCLK# deassertion, Northbridge service probe. Northbridge contains BIOS programmable registers enable system disconnect response Halt Stop Grant special cycles. When Northbridge receives Halt Stop Grant special cycle from processor and, there outstanding probes data movements, Northbridge deasserts CONNECT minimum eight SYSCLK periods after last command sent processor. processor detects deassertion CONNECT rising edge SYSCLK, deasserts PROCRDY Northbridge. return, Northbridge asserts CLKFWDRST anticipation reestablishing connection some later point. Note: Northbridge must disconnect processor from Athlon system before issuing Stop Grant special cycle bus, passing Stop Grant special cycle Southbridge systems which connect Southbridge with LDT. This note applies current chipset implementation: alternate chipset implementations that require this possible.
Power Management
Chapter
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AthlonProcessor Model Data Sheet
Note: response Halt special cycles, Northbridge passes Halt special cycle Southbridge immediately. processor receive interrupt after sends Halt special cycle, STPCLK# deassertion after sends Stop Grant special cycle Northbridge before disconnect actually occurs. this case, processor sends Connect special cycle Northbridge, rather than continuing with disconnect sequence. response Connect special cycle, Northbridge cancels disconnect request. system required assert CONNECT signal before returning C-bit connect special cycle (assuming CONNECT been deasserted). more information, AthlonSystem Specification, order# 21902 definition C-bit Connect special cycle. Figure shows sequence events from Northbridge perspective, which leads disconnecting processor from Athlon system placing processor Stop Grant state.
STPCLK# System CONNECT PROCRDY CLKFWDRST Stop Grant Stop Grant
Figure Example System Disconnect Sequence following sequence events describes processor placed Stop Grant state when disconnect enabled within Northbridge: Southbridge asserts STPCLK# place processor Stop Grant state. When processor recognizes STPCLK# asserted, processor enters Stop Grant State, then issues Stop Grant special cycle Athlon system bus. Chapter Power Management
Preliminary Information AthlonProcessor Model Data Sheet
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When Stop Grant special cycle received Northbridge probe traffic pending, Northbridge deasserts CONNECT, initiating disconnect processor. processor responds Northbridge deasserting PROCRDY, acknowledging disconnect request. Northbridge asserts CLKFWDRST complete disconnect sequence. After processor disconnected from bus, Northbridge passes Stop Grant special cycle Southbridge. Figure shows signal sequence events that take processor Stop Grant state, reconnect processor Athlonsystem bus, processor into Working state.
STPCLK# PROCRDY CONNECT CLKFWDRST
Figure Exiting Stop Grant State/Bus Reconnect Sequence following sequence events removes processor from Stop Grant state reconnects Athlon system bus: Southbridge deasserts STPCLK# response resume event. When processor recognizes STPCLK# deassertion, asserts PROCRDY, notifying Northbridge reconnect bus. Northbridge asserts CONNECT. Northbridge finally deasserts CLKFWDRST, which synchronizes forwarded clocks between processor Northbridge.
Power Management
Chapter
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AthlonProcessor Model Data Sheet
Connect State Diagram
Figure Figure describe Northbridge processor connect state diagrams, respectively.
Disconnect Pending Connect
Disconnect Requested
Disconnect 7/D,C
Reconnect Pending
Probe Pending
Probe Pending
Condition disconnect requested probes still pending disconnect requested probes pending CONNECT special cycle from processor probes pending PROCRDY deasserted probe needs service PROCRDY asserted SYSCLK periods after CLKFWDRST deasserted. Although reconnected system interface, Northbridge must issue non-NOP SysDC commands minimum four SYSCLK periods after deasserting CLKFWDRST.
Action Deassert CONNECT SYSCLK periods after last SysDC sent
Assert CLKFWDRST Assert CONNECT Deassert CLKFWDRST
Figure Northbridge Connect State Diagram Chapter Power Management
Preliminary Information AthlonProcessor Model Data Sheet
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Connect Connect Pending Connect Pending Disconnect
Disconnect Pending
Condition CONNECT deasserted Northbridge (for previously sent Halt Stop Grant special cycle). Processor receives wake-up event must cancel disconnect request.
Action CLKFWDRST asserted Northbridge. Issue CONNECT special cycle.* Return internal clocks full speed assert PROCRDY
Connect special cycle only issued after pro-
Deassert PROCRDY slow down internal clocks. Processor wake-up event CONNECT asserted Northbridge. CLKFWDRST deasserted Northbridge. Forward clocks start SYSCLK periods after CLKFWDRST deasserted.
cessor wake-up event (interrupt STPCLK# deassertion) occurs. Athlon system connected Northbridge probe processor Connect special cycle issued that time only issued after subsequent processor wake-up event).
Figure Processor Connect State Diagram
Power Management
Chapter
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AthlonProcessor Model Data Sheet
Clock Control
processor implements Clock Control (CLK_Ctl) (address C001_001Bh) that determines internal clock divisor when Athlonsystem disconnected. Refer AthlonProcessor BIOS Developers Guide, order# 21656, more details CLK_Ctl register.
Chapter
Power Management
Preliminary Information AthlonProcessor Model Data Sheet
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Power Management
Chapter
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AthlonProcessor Model Data Sheet
Thermal Design
information about thermal design AthlonProcessor Model including layout airflow considerations, Thermal, Mechanical, Chassis Cooling Design www.amd.com. Table shows thermal design power. thermal design power represents maximum sustained power dissipated while executing publicly available software instruction sequences under normal system operation nominal VCC_CORE. Thermal solutions must monitor processor temperature prevent processor from exceeding maximum temperature. characterization 90°C frequencies 1000 MHz, 95°C frequencies 1100 above. Table Thermal Design Power
Voltage Maximum Thermal Typical Thermal Power Power Temperature 1.75
Frequency (MHz) 1000 1100 1133 1200
Chapter
Thermal Design
Preliminary Information AthlonProcessor Model Data Sheet
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Thermal Design
Chapter
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AthlonProcessor Model Data Sheet
Electrical Data
Conventions
conventions used this chapter follows:
Current specified being sourced processor negative. Current specified being sunk processor positive.
AthlonProcessor Model Interface Signal Groupings
electrical data this chapter presented separately each signal group. Table defines each group signals contained each group.
Table
AthlonProcessor Model Interface Signal Groupings
Signals VID[4:0], VCC_CORE, VCCA, COREFB, COREFB# Notes "Voltage Identification (VID[4:0])" page "VID[4:0] Pins" page "VCCA Characteristics" page "Frequency Identification (FID[3:0])" page "FID[3:0] Pins" page "SYSCLK SYSCLK# Characteristics" page "AMD AthlonSystem Characteristics" page "General Characteristics" page "General Characteristics" page "APIC Pins Characteristics" page "General Characteristics" page "General Characteristics" page
Signal Group Power
Frequency System Clocks
FID[3:0] SYSCLK, SYSCLK# (Tied CLKIN/CLKIN# RSTCLK/RSTCLK#), PLLBYPASSCLK#, PLLBYPASSCLK SADDIN[14:2]#, SADDOUT[14:2]#, SADDINCLK#, SADDOUTCLK#, SFILLVAL#, SDATAINVAL#, SDATAOUTVAL#, SDATA[63:0]#, SDATAINCLK[3:0]#, SDATAOUTCLK[3:0]#, SCHECK[7:0]#, CLKFWDRST, PROCRDY, CONNECT RESET#, INTR, NMI, SMI#, INIT#, A20M#, FERR, IGNNE#, STPCLK#, FLUSH# TMS, TCK, TRST#, TDI, PICD[1:0]#, PICCLK PLLTEST#, PLLMON1, PLLMON2, SCANCLK1, SCANCLK2, SCANSHIFTEN, SCANINTEVAL, ANALOG
System
Southbridge JTAG APIC Test
Miscellaneous DBREQ#, DBRDY, PWROK, PLLBYPASS#
Chapter
Electrical Data
Preliminary Information AthlonProcessor Model Data Sheet
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Voltage Identification (VID[4:0])
more information VID[4:0] characteristics, "VID[4:0] Pins" page
Frequency Identification (FID[3:0])
Table shows FID[3:0] characteristics. more information, "FID[3:0] Pins" page
Table
Note:
FID[3:0] Characteristics
Description Output Current Output High Voltage
Parameter
pins must pulled above this voltage external pullup resistor.
VCCA Characteristics
Table shows characteristics VCCA. more information, "VCCA Pin" page
Table
Symbol VVCCA IVCCA
VCCA Characteristics
Parameter VCCA Voltage (DC) VCCA Current VCCA Voltage (AC) 2.25 -100 2.75 +100 Units mA/GHz*
VVCCA-NOISE
Note:
Measured
Decoupling
Socket Motherboard Design Guide, order# 24363, contact your local office information about decoupling required motherboard with AthlonProcessor Model
Electrical Data
Chapter
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AthlonProcessor Model Data Sheet
Operating Ranges
Athlon Processor Model designed provide functional operation voltage temperature parameters within limits defined Table
Table
VCC_CORE
Operating Ranges
Description Processor core supply Temperature processor 650-1200 Processor core supply Sleep state 1.65V Nominal 1.75 1.85V Notes
Parameter VCC_CORESLEEP TDIE
Notes:
normal operating conditions (nominal VCC_CORE 1.75 Sleep Voltage used sleep state. more information Processor BIOS Developer's Guide, order# 21656. temperature frequencies 1000 lower.
Absolute Ratings
Athlon Processor Model should subjected conditions exceeding absolute ratings listed Table such conditions adversely affect long-term reliability result functional damage.
Table
VCC_CORE VCCA VPIN TSTORAGE
Absolute Ratings
Description AthlonProcessor Model core supply Athlon Processor Model Supply Voltage signal Storage temperature processor -0.5 -0.5 -0.5 VCC_CORE VCCA VCC_CORE
Parameter
Chapter
Electrical Data
Preliminary Information AthlonProcessor Model Data Sheet
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VCC_CORE Voltage Current
Table shows power current processor during normal reduced power states.
Table
VCC_CORE Voltage Current
Nominal Voltage Maximum Voltage Stop Grant (Maximum)1 Maximum (Power Supply Current)2 1.75 1.85 95°C 90°C Temperature
Frequency (MHz) 1000 1100 1133 1200
Notes:
Measured 1.3V Sleep state operating conditions. BIOS must program CLK_Ctrl 2967_9223h AthlonProcessor Model Measured Nominal voltage. 1.75
Electrical Data
Chapter
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AthlonProcessor Model Data Sheet
6.10
SYSCLK SYSCLK# Characteristics
Table shows characteristics SYSCLK SYSCLK# differential clocks. SYSCLK signal represents CLKIN RSTCLK tied together while SYSCLK# signal represents CLKIN# RSTCLK# tied together. Figure shows this condition.
Table
Symbol
SYSCLK SYSCLK# Characteristics
Description VCC_CORE/2 Units
VThreshold-DC Crossing before transition detected (DC) VThreshold-AC Crossing before transition detected (AC) ILEAK_P ILEAK_N VCROSS CPIN Leakage current through P-channel pullup VCC_CORE Leakage current through N-channel pulldown (Ground) Differential signal crossover Capacitance
VCROSS
VThreshold-DC 400mV
VThreshold-AC 450mV
Figure SYSCLK SYSCLK# Differential Clock Signals
Chapter
Electrical Data
Preliminary Information AthlonProcessor Model Data Sheet
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Table shows SYSCLK/SYSCLK# differential clock characteristics Athlon Processor Model Figure shows sample waveform. Table
Symbol
SYSCLK SYSCLK# Characteristics
Parameter Description Clock Frequency Duty Cycle Clock Period Units Notes
Notes:
Clock Period Stability Clock High Time Clock Time Clock Rise Time Clock Fall Time
Circuitry driving Athlon system clock inputs must exhibit suitably closed-loop jitter bandwidth allow track jitter. -20dB attenuation point, measured into 10-pF 20-pF load must less than 500kHz. Circuitry driving Athlon system clock inputs purposely alter Athlon system clock period (spread spectrum clock generators). cases Athlon system period violate spec above. Athlon system clock inputs vary from 100% specified period specified period maximum rate 100kHz. Minimum Clock Frequency
VCROSS
VThreshold-AC
Figure SYSCLK Waveform
Electrical Data
Chapter
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AthlonProcessor Model Data Sheet
6.11
AthlonSystem Characteristics
Table shows characteristics Athlonsystem used Athlon Processor Model
Table AthlonSystem Characteristics
Symbol VREF Parameter Input Reference Voltage VREF Nominal VREF Nominal VREF -500 IOUT -200µA IOUT (Ground) VCC_CORE Nominal 0.85*VCC_CORE -500 Condition Units Notes (0.5*VCC_CORE) (0.5*VCC_CORE) -100 +100 VCC_CORE VREF VCC_CORE+500
IVREF_LEAK_P VREF Tristate Leakage Pullup IVREF_LEAK_N VREF Tristate Leakage Pulldown ILEAK_P ILEAK_N
Notes:
Input High Voltage Input Voltage Output High Voltage Output Voltage Tristate Leakage Pullup Tristate Leakage Pulldown Input Capacitance
VREF: VREF nominally (1%) resistor divider from VCC_CORE. suggested divider resistor values ohms over ohms produce divisor 0.50. Example: VCC_CORE 1.75V, VREF 850mV (1.7 0.50). (Processor SysVrefMode Low) Peak-to-Peak noise VREF (AC) should exceed VREF (DC). Specified TDIE given Table VCC_CORE Table following processor inputs have twice listed capacitance because they connect input pads- SYSCLK, SYSCLK#. SYSCLK connects CLKIN/RSTCLK. SYSCLK# connects CLKIN#/RSTCLK#. more information, Table page
characteristics Athlon system shown Table parameters grouped based source destination signals involved.
Chapter
Electrical Data
Preliminary Information AthlonProcessor Model Data Sheet
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Table AthlonSystem Characteristics
Group Signals Symbol TRISE TFALL TSKEWSAMEEDGE Forward Clocks TSKEWDIFFEDGE
Parameter Output Rise Slew Rate Output Fall Slew Rate Output skew with respect same clock edge Output skew with respect different clock edge Input Data Setup Time Input Data Hold Time Capacitance input Clocks Capacitance output Clocks RSTCLK Output Valid Setup RSTCLK Hold from RSTCLK
Units V/ns V/ns
Notes
COUT
1000 2000
Sync
Notes:
Rise fall time ranges guidelines over which been characterized. TSKEW-SAMEEDGE maximum skew within clock forwarded group between signals between signal forward clock, measured package, with respect same clock edge. TSKEW-DIFFEDGE maximum skew within clock forwarded group between signals between signal forward clock, measured package, with respect different clock edges. Input times with respect appropriate Clock Forward Group input clock. synchronous signals include PROCRDY, CONNECT, CLKFWDRST. RSTCLK rising edge output valid PROCRDY. Test Load-25pF. setup CONNECT/CLKFWDRST rising edge RSTCLK. hold CONNECT/CLKFWDRST from rising edge RSTCLK.
Electrical Data
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AthlonProcessor Model Data Sheet
6.12
General Characteristics
Table shows Athlon Processor Model miscellaneous pins.
Table General Characteristics*
Symbol ILEAK_P ILEAK_N TDELAY TBIT
Notes:
Parameter Description Input High Voltage Input Voltage Output High Voltage Output Voltage Tristate Leakage Pullup Tristate Leakage Pulldown Output High Current Output Current Sync Input Setup Time Sync Input Hold Time Output Delay with respect RSTCLK Input Time Acquire
Condition
(VCC_CORE/2) 200mV -300 VCC_CORE -300
VCC_CORE 300mV VCC_CORE
Units
Notes
(Ground) VCC_CORE Nominal
20.0
These parameters were characterized VCC_CORESLEEP. Characterized across supply voltage range. Values specified nominal VCC_CORE. Scale parameters between VCC_CORE VCC_CORE Max. measured min, respectively. Synchronous inputs/outputs specified with respect RSTCLK RSTCK# pins. These aggregate numbers. Edge rates indicate range over which inputs were characterized. asynchronous operation, signal must persist this time guarantee capture. This value assumes RSTCLK frequency 10ns TBIT 2*fRST. approximate value standard case normal mode operation. This value dependent RSTCLK frequency, divisors, LowPower mode, core frequency. Reassertions signal within this time guaranteed seen core. This value assumes that skew between RSTCLK K7CLKOUT much less than phase. This value assumes RSTCLK K7CLKOUT running same frequency, though processor capable other configurations.
Chapter
Electrical Data
Preliminary Information AthlonProcessor Model Data Sheet
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Table General Characteristics* (continued)
Symbol TRPT TRISE TFALL CPIN
Notes:
Parameter Description Input Time Reacquire Signal Rise Time Signal Fall Time Capacitance
Condition
40.0
Units V/nS V/nS
Notes 9-13
These parameters were characterized VCC_CORESLEEP. Characterized across supply voltage range. Values specified nominal VCC_CORE. Scale parameters between VCC_CORE VCC_CORE Max. measured min, respectively. Synchronous inputs/outputs specified with respect RSTCLK RSTCK# pins. These aggregate numbers. Edge rates indicate range over which inputs were characterized. asynchronous operation, signal must persist this time guarantee capture. This value assumes RSTCLK frequency 10ns TBIT 2*fRST. approximate value standard case normal mode operation. This value dependent RSTCLK frequency, divisors, LowPower mode, core frequency. Reassertions signal within this time guaranteed seen core. This value assumes that skew between RSTCLK K7CLKOUT much less than phase. This value assumes RSTCLK K7CLKOUT running same frequency, though processor capable other configurations.
Electrical Data
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AthlonProcessor Model Data Sheet
6.13
APIC Pins Characteristics
Table shows Athlon Processor Model characteristics APIC pins.
Table APIC Pins Characteristics
Symbol ILEAK_P ILEAK_N TRISE TFALL CPIN
Notes:
Parameter Description Input High Voltage Input Voltage Output High Voltage Output Voltage Tristate Leakage Pullup Tristate Leakage Pulldown Output Current Signal Rise Time Signal Fall Time Capacitance
Condition
-300
2.625 2.625
Units
Notes
-300 (Ground)
V/nS V/nS
Characterized across supply voltage range Values specified nominal (1.5 Scale parameters with 2.625 maximum Edge rates indicate range over which inputs were characterized
Chapter
Electrical Data
Preliminary Information AthlonProcessor Model Data Sheet
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Electrical Data
Chapter
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AthlonProcessor Model Data Sheet
Signal Power-Up Requirements
This chapter describes AthlonProcessor Model power-up requirements during system power-up warm resets.
Power-Up Requirements
Figure shows relationship between signals system during power-up sequence. This figure details requirements processor.
Signal Sequence Timing Description
3.3V Supply VCCA (2.5V) (for PLL) VCC_CORE (Processor Core) RESET# NB_RESET#
PWROK
System Clock
Figure Signal Relationship Requirements During Power-Up Sequence Note: Figure represents several signals generically using names necessarily consistent with lists schematics.
Chapter
Signal Power-Up Requirements
Preliminary Information AthlonProcessor Model Data Sheet
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Power-Up Timing Requirements. requirements correspond numbers Figure RESET# must asserted before PWROK asserted Athlon Processor Model does correct clock multiplier PWROK asserted prior RESET# assertion. recommended that RESET# asserted least 10ns prior assertion PWROK. practice, Southbridges assert RESET# milliseconds before PWROK deasserted. motherboard voltage planes must specification before PWROK asserted. within
PWROK output voltage regulation circuit motherboard. PWROK indicates that VCC_CORE other voltage planes system within specification. motherboard required delay PWROK assertion minimum milliseconds from 3.3V supply being within specification. This ensures that system clock (SYSCLK/SYSCLK#) operating within specification when PWROK asserted. processor core voltage, VCC_CORE, must within specification dictated VID[4:0] pins driven processor before PWROK asserted. Before PWROK assertion, Athlon processor clocked ring oscillator. Athlon processor powered VCCA. processor does lock VCCA high enough processor logic switch some period before PWROK asserted. VCCA must within spec least microseconds before PWROK asserted. practice VCCA, VCC_CORE, other voltage planes must within specification several milliseconds before PWROK asserted. After PWROK asserted, processor locks operational frequency.
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AthlonProcessor Model Data Sheet
system clock (SYSCLK/SYSCLK#) must running within specification before PWROK asserted. When PWROK asserted, processor switches from driving internal processor clock grid from ring oscillator driving from PLL. reference system clock should valid this time. system clocks guaranteed running after 3.3V been within specification milliseconds. PWROK assertion deassertion RESET#. duration RESET# assertion during cold boots intended satisfy time takes lock with less than 1-ns phase error. processor begins after PWROK asserted internal clock grid switched from ring oscillator PLL. lock time take from hundreds nanoseconds tens microseconds. recommended that minimum time between PWROK assertion deassertion RESET# least 1.0ms. Southbridges enforce delay milliseconds between PWRGD (Southbridge version PWROK) assertion NB_RESET# deassertion. PWROK must monotonic. processor should switch between ring oscillator after initial assertion PWROK. NB_RESET# must asserted (causing CONNECT also assert) before RESET# deasserted. practice Southbridges enforce this requirement. NB_RESET# does assert until after RESET# deasserted, processor misinterprets CONNECT assertion (due NB_RESET# being asserted) beginning transfer (See "Serial Initialization Packet (SIP) Protocol" page 38). There must sufficient overlap resets ensure that CONNECT sampled asserted processor before RESET# deasserted. Clock Multiplier Selection (FID[3:0]) When RESET# deasserted, Northbridge samples FID[3:0] frequency from processor chipset-specific manner. more information, "FID[3:0] Pins" page orthbridge uses this informat other information sampled deassertion RESET# determine correct Serial Initialization Packet (SIP) send processor configuration system clock multiplier processor frequency indicated Chapter Signal Power-Up Requirements
Preliminary Information AthlonProcessor Model Data Sheet
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FID[3:0] code. sent processor using protocol. This protocol uses PROCRDY, CONNECT, CLKFWDRST signals, which synchronous SYSCLK. Serial Initialization Packet (SIP) Protocol. Figure shows protocol typical transfer processor after RESET# deassertion. Table describes requirements transfer from Northbridge processor. Processors Northbridges designed adhere protocol require motherboard intervention.
25ns 50ns 75ns 100ns 125ns
NB_Reset# RESET# CLKFWDRST CONNECT PROCRDY SYSCLK SADDOUTCLK# SADDOUT[14:2]# Start SIP1 SIPn
Figure Typical Protocol Sequence Table Protocol States Actions
State Action When NB_RESET# RESET# asserted, system asserts CONNECT CLKFWDRST processor asserts PROCRDY. When NB_RESET# deasserted, system deasserts CONNECT, continues assert CLKFWDRST. When RESET# deasserted, processor deasserts PROCRDY ready initialization (via Protocol).
Note: system must reset before processor deasserts PROCRDY
After more SYSCLK periods after deassertion PROCRDY, system deasserts CLKFWDRST. (States performed Socket legacy reasons) After more SYSCLK periods after deassertion CLKFWDRST, system again asserts CLKFWDRST
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Table Protocol States Actions (continued)
State Action Either assertion CLKFWDRST more SYSCLK periods later, processor expects start (CONNECT asserted) SIP. system delivers containing processor clock-forwarding initialization state over CONNECT. After transferred, system asserts holds CONNECT. This indicates transfer processor. more SYSCLK periods after receiving SIP, processor asserts PROCRDY indicate system that received SIP, initialized itself, ready. more SYSCLK periods after assertion PROCRDY, system deasserts CLKFWDRST. number SYSCLK periods after CLKFWDRST sampled deasserted, processor drives forward clocks.
Processor SYSCLK Ratio 3.5:1 SYSCLK Periods Delay (See Note (See Note
4.0:1 4.5:1 others Notes:
AthlonProcessor Model silicon deviates from spec. with SysClk delay these processor SysClk ratios.
Processor Warm Reset Requirements
RESET cannot asserted processor without also being asserted Northbridge. RESET# Northbridge same RESET#. minimum assertion RESET# millisecond. Southbridges enforce minimum assertion RESET# processor, Northbridge, milliseconds.
AthlonProcessor Model Northbridge Reset Pins
Chapter
Signal Power-Up Requirements
Preliminary Information AthlonProcessor Model Data Sheet
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Signal Power-Up Requirements
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AthlonProcessor Model Data Sheet
Mechanical Data
Introduction
AthlonProcessor Model connects motherboard through socket named Socket more information, Athlon Processor Socket Application Note, order# 90020.
Pinout Diagram
location designations Socket connector shown Figure page Voided (plugged) locations should have base that accepts contact, plate Socket should have openings. exceptions plugs outside corners, which should permanently closed accommodate contact. permissible, necessary manufacturing reasons, place contact base plug sites (except plugs outside corners). Socket sites, with plugs total. more information, Chapter "Pin Descriptions" page addition, Figure shows Socket package side view view.
Chapter
Mechanical Data
Preliminary Information AthlonProcessor Model Data Sheet
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Figure Package, Top, Side, Bottom Views Mechanical Data Chapter
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AthlonProcessor Model Data Sheet
Socket Tabs Heatsink Clips
Figure shows socket required Socket These features required support 300g heatsink. Figure page shows socket side view.
Note: Measurements
Figure Socket with Outline Socket Heatsink
Chapter
Mechanical Data
Preliminary Information AthlonProcessor Model Data Sheet
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Figure Socket Heatsink Side View
Mechanical Data
Chapter
23792G-October 2000
AthlonProcessor Model Data Sheet
Descriptions
Introduction
Figure page shows staggered grid array (SPGA) AthlonProcessor Model Because some names long grid, they abbreviated. Table page lists pins alphabetical order name, along with abbreviation where necessary. Table page lists pins cross-referenced their location.
Chapter
Descriptions
AthlonProcessor Model Data Sheet
IGNNE# VSS26 INTR VCC93 FERR VCC34 A20M# VSS38 STPC# VCC40 DBRDY VSS44 FID(2) VCC46 FID(0) VSS51 VCC53 SCNCK1 VSS57 VCC59 PICCLK VSS64 VID(0) VCC66 SAO#0 VSS70 SAO# VCC71 SAO#11 VSS81 SAO#7 VCC90 VSS101
SAO# SAO#9 VCC89 SAOCLK# VSS80 SAO# VCC70 SAO#1 VSS69 VID(1) VCC64 PICD#0 VSS63 VCC58 SCNINV VSS56 TRST# VCC52 FID(1) VSS50 FID(3) VCC45 DBREQ VSS43 PLTST# VCC39 PWROK VSS37 RESET# VCC33 INIT# VSS25 FLUSH# VSS102
SAO#5 VSS100 SAO#8 VSS91 SAO#4 VSS79 SAO# VSS68 VID(2) VCC65 PICD#1 VSS62 SCNSN VCC57 SCNCK2 VSS55 VCC51 VREF_S VSS48 VCC44 SVRFM VSS42 VCC37 VCC101 VSS103 VCC26 VSS104 SMI#
SAO#3 VCC99 SAO#2 VCC88 SAO#6
SD#55 VSS99 SD#54 VSS90 SD#52 VSS78 KEY8
SD#61 VCC98 SDOC# VCC87 SD#50 VCC80 VCC1
SD#53 VSS98 SCK#6 VSS89 SD#49 VSS77 VSS1
SD#63 VCC97 SD#51 VCC86 SDIC#3 VCC79
SD#62 VSS97 SD#60 VSS88 SD#48 VSS76 KEY6 VCC2 VSS2
SCK#7 VCC96 SD#59 VCC85 SD#58 VCC78 VCC3
SD#57 VSS96 SD#56 VSS87 SD#36 VSS75 VSS3
SD#39 VCC95 SD#37 VCC84 SD#46 VCC77
SD#35 VSS95 SD#47 VSS86 SCK#4 VSS74 KEY4 VCC4 VSS4
SD#34 VCC94 SD#38 VCC82 SDIC#2 VCC76
SD#44 VSS94 SD#45 VSS85 SD#33
SCK#5 VCC92 SD#43 VCC81 SD#32 VCC75
SDOC# VSS92 SD#42 VSS84 SCK#3 VCC74 SD#20 VSS73 SD#19 VCC69 VCC68 SD#26 VSS67 VSS66 SD#25 VCC63 VCC62 SD#24 VSS61 VSS59 SD#7 VCC56 VCC55 SD#5 VSS54 VSS53 SDIC#0 VCC50 VCC48 SCK#1 VSS47 VSS46 SD#8 VCC43 VCC42 SD#10 VSS41 VSS40 SAI#5 VCC36 SAI#2 VSS30 VSS29 SAIC# VSS18 VCC19 SAI#8 VSS28 VCC17 SDINV#
SD#40 VCC91 SD#41 VSS83 SD#31 VCC73 SD#23 VSS72 SDIC#1 VCC67 SCK#2 VSS65 SD#27 VCC61 SD#17 VSS58 SD#15 VCC54 SD#4 VSS52 SD#2 VCC47 SD#3 VSS45 SD#0 VCC41 SD#14 VSS39 SDOC# VCC35 SAI#11 VSS27 SAI#6 VCC18 SAI#4 VSS17 SAI#13
SD#30
SDOC#
SD#22
SD#21
VID(4) VID(3) VCC5 KEY10 VSS6 VCC6 VSS5
SD#29
SD#28
SD#18
VCC7 VSS8 VCC9 VSS10 KEY12 VCC11 VSS11 VSS12 VCC_Z VSS_Z KEY14
SD#16
Descriptions Chapter
VSS7
SD#6
AthlonProcessor Model Topside View
VCC8 VSS9 VCC10
SCK#0
SD#1
SD#12
SD#13
VCC12 COREFB VCC32 VCC25 VCC83
SD#11
SD#9
VSS13 COREFB VSS35 VSS23 VSS93
VCC13 KEY16 VCC31 ANLOG VCC24 PLMN2 VCC72 PLMN1
VSS14
VCC14
VSS15 VSS33 CLKFR VSS21 RCLK# K7CO VSS71 RCLK K7CO#
VCC15 VCC29 VCCA VCC22 CNNCT VCC49 PRCRDY
VSS16 VSS32 PLBYP# VSS20 VSS60
VCC16
KEY18
SAI#0 SFILLV# VCC20 SAI#1 SDOV# VCC28 SAI#12 SAI#14
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SAI#7
VSS34 VSS22 PLBYC# VSS82 PLBYC
VCC30 VCC23 CLKIN# VCC60 CLKIN
VCC27 VCC21 VCC38
VSS31
SAI#3
VSS19
SAI#10
VSS49
SAI#9
Figure AthlonProcessor Model Diagram-Topside View
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AthlonProcessor Model Data Sheet
Table Name Abbreviations
Abbreviation Full Name A20M# ANALOG CLKFWDRESET CLKIN CLKIN# CONNECT COREFB COREFB# DBRDY DBREQ# FERR FID[0] FID[1] FID[2] FID[3] FLUSH# IGNNE# INIT# INTR K7CLKOUT K7CLKOUT# KEY4 KEY6 KEY8 KEY10 KEY12 KEY14 KEY16 KEY18 AJ13 AJ21 AN17 AL17 AL23 AG11 AG13 AG19 AG21 AL21 AN21 AG15 AG29 AL25 AL27 AN25 AN27 AA31 Abbreviation Full Name AE31 AG23 AG25 AG31 AJ11 AJ15 AJ17 AJ19 AJ27 AL11 AN11 AD30 AF10 AF28 AF30 AF32
ANLOG CLKFR
CNNCT
K7CO K7CO#
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Preliminary Information AthlonProcessor Model Data Sheet
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Table Name Abbreviations (continued)
Abbreviation Full Name PICCLK PICD[0]# PICD[1]# PLLBYPASS# PLLBYPASSCLK PLLBYPASSCLK# PLLMON1 PLLMON2 PLLTEST# PROCREADY PWROK RESET# RSTCLK RSTCLK# SCANCLK1 SCANCLK2 SCANINTEVAL SCANSHIFTEN AC31 AH30 AJ25 AN15 AL15 AN13 AL13 AN23 AN19 AL19 Abbreviation STPC# SAI#0 SAI#1 SAI#2 SAI#3 SAI#4 SAI#5 SAI#6 SAI#7 SAI#8 SAI#9 SAI#10 SAI#11 SAI#12 SAI#13 SAI#14 SAIC# SAO#0 SAO#1 SAO#2 SAO#3 SAO#4 SAO#5 SAO#6 SAO#7 SAO#8 SAO#9 SAO#10 SAO#11 SAO#12 SAO#13 SAO#14 SAOCLK# SCK#0 SCK#1 SCK#2 SCK#3 SCK#4 Full Name STPCLK# SADDIN[0]# SADDIN[1]# SADDIN[2]# SADDIN[3]# SADDIN[4]# SADDIN[5]# SADDIN[6]# SADDIN[7]# SADDIN[8]# SADDIN[9]# SADDIN[10]# SADDIN[11]# SADDIN[12]# SADDIN[13]# SADDIN[14]# SADDINCLK# SADDOUT[0]# SADDOUT[1]# SADDOUT[2]# SADDOUT[3]# SADDOUT[4]# SADDOUT[5]# SADDOUT[6]# SADDOUT[7]# SADDOUT[8]# SADDOUT[9]# SADDOUT[10]# SADDOUT[11]# SADDOUT[12]# SADDOUT[13]# SADDOUT[14]# SADDOUTCLK# SCHECK[0]# SCHECK[1]# SCHECK[2]# SCHECK[3]# SCHECK[4]# AJ29 AL29 AG33 AJ37 AL35 AE33 AJ35 AG37 AL33 AN37 AL37 AG35 AN29 AN35 AN31 AJ33
PICD#0 PICD#1 PLBYP# PLBYC PLBYC# PLMN1 PLMN2 PLTST# PRCRDY
RCLK RCLK# SCNCK1 SCNCK2 SCNINV SCNSN
Descriptions
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Table Name Abbreviations (continued)
Abbreviation SCK#6 SCK#7 SD#0 SD#1 SD#2 SD#3 SD#4 SD#5 SD#6 SD#7 SD#8 SD#9 SD#10 SD#11 SD#12 SD#13 SD#14 SD#15 SD#16 SD#17 SD#18 SD#19 SD#20 SD#21 SD#22 SD#23 SD#24 SD#25 SD#26 SD#27 SD#28 SD#29 SD#30 SD#31 SD#32 SD#33 SD#34 SD#35 Full Name SMI# SCHECK[6]# SCHECK[7]# SDATA[0]# SDATA[1]# SDATA[2]# SDATA[3]# SDATA[4]# SDATA[5]# SDATA[6]# SDATA[7]# SDATA[8]# SDATA[9]# SDATA[10]# SDATA[11]# SDATA[12]# SDATA[13]# SDATA[14]# SDATA[15]# SDATA[16]# SDATA[17]# SDATA[18]# SDATA[19]# SDATA[20]# SDATA[21]# SDATA[22]# SDATA[23]# SDATA[24]# SDATA[25]# SDATA[26]# SDATA[27]# SDATA[28]# SDATA[29]# SDATA[30]# SDATA[31]# SDATA[32]# SDATA[33]# SDATA[34]# SDATA[35]# AA35 AA33 AE37 AC33 AC37 AA37 AC35 Abbreviation SCK#5 SD#37 SD#38 SD#39 SD#40 SD#41 SD#42 SD#43 SD#44 SD#45 SD#46 SD#47 SD#48 SD#49 SD#50 SD#51 SD#52 SD#53 SD#54 SD#55 SD#56 SD#57 SD#58 SD#59 SD#60 SD#61 SD#62 SD#63 SDIC#0 SDIC#1 SDIC#2 SDIC#3 SDINV# SDOC#0 SDOC#1 SDOC#2 SDOC#3 SDOV# SFILLV# Full Name SCHECK[5]# SDATA[37]# SDATA[38]# SDATA[39]# SDATA[40]# SDATA[41]# SDATA[42]# SDATA[43]# SDATA[44]# SDATA[45]# SDATA[46]# SDATA[47]# SDATA[48]# SDATA[49]# SDATA[50]# SDATA[51]# SDATA[52]# SDATA[53]# SDATA[54]# SDATA[55]# SDATA[56]# SDATA[57]# SDATA[58]# SDATA[59]# SDATA[60]# SDATA[61]# SDATA[62]# SDATA[63]# SDATAINCLK[0]# SDATAINCLK[1]# SDATAINCLK[2]# SDATAINCLK[3]# SDATAINVALID# SDATAOUTCLK[0]# SDATAOUTCLK[1]# SDATAOUTCLK[2]# SDATAOUTCLK[3]# SDATAOUTVALID# SFILLVAL# AN33 AE35 AL31 AJ31
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Preliminary Information AthlonProcessor Model Data Sheet
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Table Name Abbreviations (continued)
Abbreviation SD#36 Full Name SDATA[36]# TRST# VCC_CORE1 VCC_CORE2 VCC_CORE3 VCC_CORE4 VCC_CORE5 VCC_CORE6 VCC_CORE7 VCC_CORE8 VCC_CORE9 VCC_CORE10 VCC_CORE11 VCC_CORE12 VCC_CORE13 VCC_CORE14 VCC_CORE15 VCC_CORE16 VCC_CORE17 VCC_CORE18 VCC_CORE19 VCC_CORE20 VCC_CORE21 VCC_CORE22 VCC_CORE23 VCC_CORE24 VCC_CORE25 VCC_CORE26 VCC_CORE27 VCC_CORE28 VCC_CORE29 VCC_CORE30 VCC_CORE31 VCC_CORE32 VCC_CORE33 AB30 AF14 AF18 AF22 AF26 AM34 AK36 AK34 AK30 AK26 AK22 AK18 AK14 AK10 AH26 AM30 AH22 AH18 AH14 AH10 Abbreviation SVRFM VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58 VCC59 VCC60 VCC61 VCC62 VCC63 VCC64 VCC65 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71 VCC72 Full Name SYSVREFMODE VCC_CORE35 VCC_CORE36 VCC_CORE37 VCC_CORE38 VCC_CORE39 VCC_CORE40 VCC_CORE41 VCC_CORE42 VCC_CORE43 VCC_CORE44 VCC_CORE45 VCC_CORE46 VCC_CORE47 VCC_CORE48 VCC_CORE49 VCC_CORE50 VCC_CORE51 VCC_CORE52 VCC_CORE53 VCC_CORE54 VCC_CORE55 VCC_CORE56 VCC_CORE57 VCC_CORE58 VCC_CORE59 VCC_CORE60 VCC_CORE61 VCC_CORE62 VCC_CORE63 VCC_CORE64 VCC_CORE65 VCC_CORE66 VCC_CORE67 VCC_CORE68 VCC_CORE69 VCC_CORE70 VCC_CORE71 VCC_CORE72 AF36 AF34 AM26 AB36 AB34 AB32 AM22 AM18 AM14
VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33
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Table Name Abbreviations (continued)
Abbreviation VCC34 VCC74 VCC75 VCC76 VCC77 VCC78 VCC79 VCC80 VCC81 VCC82 VCC83 VCC84 VCC85 VCC86 VCC87 VCC88 VCC89 VCC90 VCC91 VCC92 VCC93 VCC94 VCC95 VCC96 VCC97 VCC98 VCC99 VCC100 VCC101 Full Name VCC_CORE34 VCC_CORE74 VCC_CORE75 VCC_CORE76 VCC_CORE77 VCC_CORE78 VCC_CORE79 VCC_CORE80 VCC_CORE81 VCC_CORE82 VCC_CORE83 VCC_CORE84 VCC_CORE85 VCC_CORE86 VCC_CORE87 VCC_CORE88 VCC_CORE89 VCC_CORE90 VCC_CORE91 VCC_CORE92 VCC_CORE93 VCC_CORE94 VCC_CORE95 VCC_CORE96 VCC_CORE97 VCC_CORE98 VCC_CORE99 VCC_CORE100 VCC_CORE101 VCC_Z VCCA VID[0] VID[1] VID[2] VID[3] VID[4] VREF_SYS VSS_Z VSS1 AM10 AJ23 Abbreviation VCC73 Full Name VCC_CORE73 VSS100 VSS101 VSS102 VSS103 VSS104 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS2 VSS20 VSS21 VSS22 VSS23 VSS25 VSS26 VSS27 VSS28 VSS29 VSS3 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS37 VSS38 VSS39 VSS4 VSS40 VSS41 VSS42 AF12 AF16 AF20 AF24 AM36 AK32 AK28 AK24 AK20 AK16 AK12 AH36 AM32 AH34 AH32 AH28 AH24 AH20 AH16 AH12 AD36 AD34 AD32
VREF_S
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Descriptions
Preliminary Information AthlonProcessor Model Data Sheet
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Table Name Abbreviations (continued)
Abbreviation Full Name VSS10 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS5 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS6 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 AM28 AM24 Abbreviation Full Name VSS43 VSS8 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS9 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 AM16 AM12
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Table Name Abbreviations (continued)
Abbreviation Full Name VSS66 VSS67 VSS68 VSS69 VSS7 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 AM20 Abbreviation Full Name
List
Table cross-references Socket location signal name. (Level) column shows electrical specification this pin. indicates push-pull mode driven single source. indicates open-drain mode that allows devices share pin. Note: Socket Athlon Processor Model supports push-pull drivers. more information, "Push-Pull (PP) Drivers" page (Port) column indicates this signal input (I), output (O), bidirectional signal. (Reference) column indicates this clock-forwarded signal should referenced VCC_CORE planes purpose providing proper current return paths signal routes. more information, Socket Motherboard Design Guide, order# 24363.
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Descriptions
Preliminary Information AthlonProcessor Model Data Sheet
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Description column contains cross-reference page with more information "Detailed Descriptions" (which starts page 62).
Descriptions
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AthlonProcessor Model Data Sheet
Table Socket Cross-Reference Location
Name SADDOUT[12]# SADDOUT[5]# SADDOUT[3]# SDATA[55]# SDATA[61]# SDATA[53]# SDATA[63]# SDATA[62]# SCHECK[7]# SDATA[57]# SDATA[39]# SDATA[35]# SDATA[34]# SDATA[44]# SCHECK[5]# SDATAOUTCLK[2]# SDATA[40]# SDATA[30]# SADDOUT[7]# SADDOUT[9]# SADDOUT[8]# SADDOUT[2]# SDATA[54]# SDATAOUTCLK[3]# SCHECK[6]# SDATA[51]# SDATA[60]# SDATA[59]# SDATA[56]# SDATA[37]# SDATA[47]# SDATA[38]# SDATA[45]# Page Page Page Description Page VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE Name Description
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Table Socket Cross-Reference Location (continued)
Name SDATA[43]# SDATA[42]# SDATA[41]# SDATAOUTCLK[1]# SADDOUT[11]# SADDOUTCLK# SADDOUT[4]# SADDOUT[6]# SDATA[52]# SDATA[50]# SDATA[49]# SDATAINCLK[3]# SDATA[48]# SDATA[58]# SDATA[36]# SDATA[46]# SCHECK[4]# SDATAINCLK[2]# SDATA[33]# SDATA[32]# SCHECK[3]# SDATA[31]# SDATA[22]# SADDOUT[10]# SADDOUT[14]# SADDOUT[13]# Page Page Page Page Page Page Page Page Page Page Description VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE Page Page Page VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE Page Page Name VCC_CORE Description
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Table Socket Cross-Reference Location (continued)
Name SDATA[20]# SDATA[23]# SDATA[21]# SADDOUT[0]# SADDOUT[1]# VID[4] SDATA[19]# SDATAINCLK[1]# SDATA[29]# VID[0] VID[1] VID[2] VID[3] SDATA[26]# SCHECK[2]# SDATA[28]# PICCLK PICD[0]# PICD[1]# SDATA[25]# SDATA[27]# SDATA[18]# Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Description Page Page Page Page Page VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE Page Page Page Page Page Name VCC_CORE Description
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Table Socket Cross-Reference Location (continued)
Name SCANSHIFTEN SDATA[24]# SDATA[17]# SDATA[16]# SCANCLK1 SCANINTEVAL SCANCLK2 SDATA[7]# SDATA[15]# SDATA[6]# TRST# SDATA[5]# SDATA[4]# SCHECK[0]# FID[0] FID[1] VREFSYS Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Description Page Page Page Page Page Page Page Name VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE VCC_CORE Description
SDATAINCLK[0]# SDATA[2]# SDATA[1]# FID[2] FID[3]
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Table Socket Cross-Reference Location (continued)
Name SCHECK[1]# SDATA[3]# SDATA[12]# DBRDY DBREQ# SYSVREFMODE Page Page Page Page Page Description Page Page Page Page Page Page Page Page Page Page Page Page Page Page Name Description Page Page Page Page Page Page Page Page Page Page Page Page
AA31 AA33 SDATA[8]# AA35 SDATA[0]# AA37 SDATA[13]# STPCLK# PLLTEST# VCC_Z
AB30 VCC_CORE AB32 VCC_CORE AB34 VCC_CORE AB36 VCC_CORE VCC_CORE VCC_CORE VCC_CORE
AC31 AC33 SDATA[10]# AC35 SDATA[14]# AC37 SDATA[11]# A20M# PWROK VSS_Z
AD30 AD32
AD34 AD36 AE31 AE33 SADDIN[5]# AE35 SDATAOUTCLK[0]# AE37 SDATA[9]# FERR RESET#
AF10 AF12 AF14 VCC_CORE AF16 AF18 VCC_CORE AF20
AG11 COREFB AG13 COREFB# AG15 AG17 AG19
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Table Socket Cross-Reference Location (continued)
AF24 AF26 VCC_CORE AF28 AF30 AF32 AF34 VCC_CORE AF36 VCC_CORE VCC_CORE VCC_CORE Page Page Page Page Page Name Description Page Page AG21 AG23 AG25 AG27 AG29 AG31 AG33 SADDIN[2]# AG35 SADDIN[11]# AG37 SADDIN[7]# IGNNE# INIT# VCC_CORE Page Page Page Page Page Page Page Page Page Page Page Page Page Page Name Description Page Page Page Page Page Page Page Page Page Page Page AF22 VCC_CORE
AH10 VCC_CORE AH12 AH14 VCC_CORE AH16 AH18 VCC_CORE AH20 AH22 VCC_CORE AH24 AH26 VCC_CORE AH28 AH30 AH32 AH34 AH36
AJ11 AJ13 Analog AJ15 AJ17 AJ19 AJ21 CLKFWDRST AJ23 VCCA AJ25 PLLBYPASS# AJ27 AJ29 SADDIN[0]# AJ31 SFILLVAL# AJ33 SADDINCLK# AJ35 SADDIN[6]# AJ37 SADDIN[3]# INTR FLUSH# VCC_CORE
AK10 VCC_CORE AK12
AL11
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Table Socket Cross-Reference Location (continued)
AK16 AK18 VCC_CORE AK20 AK22 VCC_CORE AK24 AK26 VCC_CORE AK28 AK30 VCC_CORE AK32 AK34 VCC_CORE AK36 VCC_CORE VCC_CORE AM10 VCC_CORE AM12 AM14 VCC_CORE AM16 AM18 VCC_CORE AM20 AM22 VCC_CORE AM24 AM26 VCC_CORE AM28 AM30 VCC_CORE AM32 AM34 VCC_CORE AM36 Page Name Description Name Description Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page AK14 VCC_CORE AL13 PLLMON2 AL15 PLLBYPASSCLK# AL17 CLKIN# AL19 RSTCLK# AL21 K7CLKOUT AL23 CONNECT AL25 AL27 AL29 SADDIN[1]# AL31 SDATAOUTVAL# AL33 SADDIN[8]# AL35 SADDIN[4]# AL37 SADDIN[10]# SMI#
AN11 AN13 PLLMON1 AN15 PLLBYPASSCLK AN17 CLKIN AN19 RSTCLK AN21 K7CLKOUT# AN23 PROCRDY AN25 AN27 AN29 SADDIN[12]# AN31 SADDIN[14]# AN33 SDATAINVAL# AN35 SADDIN[13]# AN37 SADDIN[9]#
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Detailed Descriptions
information this section pertains Table page specific resistor values, Socket Motherboard Design Guide, order# 24363.
A20M#
A20M# input from system used simulate address wrap-around 20-bit 8086. motherboard should treat (AH6) pin. socket designer option creating mold piece that blocks this location. However, sockets that populate must allowed, motherboard must always provide type this location. Socket implement location AH6. When socket that does provide hole location used, non-AMD PGA370 part does into Socket AthlonSystem Specification, order# 21902 information about system pins PROCRDY, SADDOUT[14:2]#, SADDOUTCLK#, SCHECK[7:0]#, DATA DATA DATA SDATAOUTCLK[3:0]#, SDATAOUTVAL#, SFILLVAL#. Treat this CLKFWDRST resets clock-forward circuitry both system processor. Connect CLKIN (AN17) with RSTCLK (AN19) name SYSCLK. Connect CLKIN# (AL17) with RSTCLK# (AL19) name SYSCLK#. Length match clocks from clock generator Northbridge processor. "SYSCLK SYSCLK# Pins" page more information. CONNECT input from system used power management clock-forward initialization reset. COREFB COREFB# outputs system that provide Athlon Processor Model core voltage feedback system.
AthlonSystem Pins
Analog CLKFWDRST CLKIN, RSTCLK (SYSCLK) Pins
CONNECT COREFB COREFB# Pins
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DBRDY DBREQ# Pins FERR
DBRDY (AA1) DBREQ# (AA3) routed debug connector. DBREQ# tied VCC_CORE with pullup resistor. FERR output system that asserted unmasked numerical exception independent CR0. FERR open-drain active High signal that must inverted level shifted active signal. more information about FERR FERR#, "Required Circuits" chapter Socket Motherboard Design Guide, order# 24363.
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FID[3:0] Pins
"Frequency Identification (FID[3:0])" page characteristics FID[3:0]. FID[3] (Y3), FID[2] (Y1), FID[1] (W3), FID[0] (W1) 4-bit processor clock-to-SYSCLK ratio. Table describes encodings clock multipliers FID[3:0]. Table FID[3:0] Clock Multiplier Encodings
FID[3]
Note:
FID[2]
FID[1]
FID[0]
Processor Clock SYSCLK Frequency Ratio 11.5 12.5 10.5
ratios greater than equal 12.5x have same FID[3:0] code 0011, which causes configuration ratios 12.5x greater same.
FID[3:0] signals open-drain processor outputs that Northbridge deassertion RESET# determine (serialization initialization packet) that gets sent processor. AthlonSystem Specification, order#21902 more information about protocol.
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AthlonProcessor Model Data Sheet
processor FID[3:0] outputs open drain 2.5V tolerant. prevent damage processor, these signals pulled High above they must electrically isolated from processor. information about FID[3:0] isolation circuit, Socket Motherboard Design Guide, order# 24363. FLUSH# debug connector, this should tied VCC_CORE with pullup resistor, SMI# with resistor that populated. IGNNE# input from system that tells processor ignore numeric errors. INIT# input from system that resets integer registers without affecting floating-point registers internal caches. Execution starts 0FFFF FFF0h. INTR input from system that causes processor start interrupt acknowledge transaction that fetches 8-bit interrupt vector starts execution that location. (Q1), (Q3), (U1), TRST# (U3), (U5) JTAG interface. Connect these pins directly motherboard debug connector. Pullup TDI, TCK, TMS, TRST# VCC_CORE. K7CLKOUT (AL21) K7CLKOUT# (AN21) each inches then terminated with resistor pair, ohms VCC_CORE ohms VSS. effective termination resistance voltage ohms VCC_CORE/2. These locations processor type keying forwards backwards compatibility (G7, G15, G17, G23, G25, AA7, AG7, AG9, AG15, AG17, AG27, AG29). Motherboard designers should treat pins like connect) pins. Pins" page more information. socket designer option creating mold piece that allows pins only where designated. However, sockets that populate pins must allowed, motherboard must always provide pins locations. motherboard should provide plated hole pin. hole should electrically connected anything. Descriptions
IGNNE# INIT#
INTR
JTAG Pins
K7CLKOUT K7CLKOUT# Pins
Pins
Pins
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Preliminary Information AthlonProcessor Model Data Sheet Orientation Pins
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input from system that causes non-maskable interrupt. present locations (see Processor Socket Application Note, order# 90020). Motherboard designers should allow socket these locations. PLLTEST# (AC3), PLLMON1 (AN13), PLLMON2 (AL13), PLLBYPASSCLK (AN15), PLLBYPASSCLK# (AL15) bypass test interface. This interface tied disabled motherboard. signals routed debug connector. four processor inputs (PLLTEST#, PLLMON1, PLLMON2) tied VCC_CORE with pullup resistors. Motherboard designs require power sequencing circuitry processor startup protection. startup complications occur PWROK asserted before following voltages valid:
Bypass Test Pins
PWROK
VCC_CORE voltage 3.3-V supply, which indicates system clocks stable.
more information, "Motherboard Required Circuits" chapter Socket Motherboard Design Guide, order# 24363. SADDIN[1]# SADDOUT[1:0]# Pins SADDIN[1]# tied with pulldown resistors, this supported Northbridge. SADDOUT[1:0]# these bits supported Northbridge. more information, AthlonSystem Specification, order# 21902. SCANSHIFTEN (Q5), SCANCLK1 (S1), SCANINTEVAL (S3), SCANCLK2 (S5) scan interface. This interface internal disabled with pulldown resistor motherboard. systems that support ECC, SCHECK[7:0]# should treated pins. SMI# input that causes processor enter system management mode.
Scan Pins
SCHECK[7:0]# SMI#
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STPCLK# SYSCLK SYSCLK# Pins
STPCLK# input that causes processor enter lower power mode issue Stop Grant special cycle. SYSCLK SYSCLK# differential input clock signals provided processor's from system-clock generator. "CLKIN, RSTCLK (SYSCLK) Pins" page more information. SYSVREFMODE (AA5) ensure that external VREFSYS voltage actual voltage used input buffers that scaling occurs internally between VREFSYS voltage input threshold. This tied with pulldown resistor, which required enable Push-Pull system functionality. VCCA processor supply. VCCA current ranges from GHz. Vmax 2.75 Vmin 2.25 Decouple this with 0.1-uF capacitor. information about VCCA pin, Table "VCCA Characteristics," page "Motherboard Required Circuits" chapter Socket Motherboard Design Guide, order# 24363. VID[4:0] signals outputs motherboard that indicate required VCC_CORE voltage processor. VCC_CORE (VID) sent motherboard VCC_CORE regulator. processor VID[4:0] outputs open drain. "Voltage Identification (VID[4:0])" page characteristics VID[4:0]. motherboard required pull VID[4:0] High voltage regulator supply voltage appropriate range Athlon Processor Model processor. These voltage values defined Table page Note: VID[3:0] Slot different code definition than VID[4:0] Socket
SYSVREFMODE
VCCA
VID[4:0] Pins
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Table VID[4:0] Code Voltage Definition
VID[4:0] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 VCC_CORE 1.850 1.825 1.800 1.775 1.750 1.725 1.700 1.675 1.650 1.625 1.600 1.575 1.550 1.525 1.500 1.475 VID[4:0] 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 VCC_CORE 1.450 1.425 1.400 1.375 1.350 1.325 1.300 1.275 1.250 1.225 1.200 1.175 1.150 1.125 1.100
more information, "Required Circuits" chapter Socket Motherboard Design Guide, order# 24363. VREFSYS VREFSYS (W5) drives threshold voltage system input receivers. VREFSYS VCC_CORE. addition, minimize VCC_CORE noise rejection from information, Socket Motherboard Design Guide, order# 24363. (AC5), VCC_Z (AC7), (AE5), VSS_Z (AE7) push-pull compensation circuit pins. VCC_ tied VCC_CORE. VSS_Z tied VSS. Push-Pull mode selected parameter SysPushPull asserted (SysPushPull=1), tied VCC_CORE with resistor that resistance matching impedance transmission line. tied with resistor that resistance matching impedance transmission line.
VCC_Z, VSS_Z Pins
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SysPushPull deasserted (SysPushPull=0), should resistively tied either VCC_CORE VSS, should left floating.
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Ordering Information
Standard AthlonProcessor Model Products
standard products available several operating ranges. ordering part numbers (OPN) formed combination elements, shown Figure
1200
FSB: MHz, C=266 Size Cache: =256Kbytes Case Temperature: Operating Voltage: 1.75V, P=1.7V Package Type: Speed: 0850=850 MHz, 0900=900 MHz, 1000=1000 MHz, 1100=1100 MHz, 1200=1200 MHz, etc. Family/Architecture: AthlonProcessor Model Architecture
Note: Spaces added number shown above viewing clarity only.
Figure Example AthlonProcessor Model
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Appendix
Conventions Abbreviations
This section contains information about conventions abbreviations used this document.
Signals Bits
Active-Low Signals-Signal names containing pound sign, such SFILL#, indicate active-Low signals. They asserted their Low-voltage state negated their High-voltage state. When used this context, High written with initial upper case letter. Signal Ranges-In range signals, highest lowest signal numbers contained brackets separated colon (for example, D[63:0]). Reserved Bits Signals-Signals bits marked reserved must driven inactive left unconnected, indicated signal descriptions. These bits signals reserved future implementations. When software reads registers with reserved bits, reserved bits must masked. When software writes such registers, must first read register change only non-reserved bits before writing back register. Three-State-In timing diagrams, signal ranges that high impedance shown straight horizontal line half-way between high levels.
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Preliminary Information AthlonProcessor Model Data Sheet
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Invalid Don't-Care-In timing diagrams, signal ranges that invalid don't-care filled with screen pattern.
Data Terminology
following list defines data terminology:
Quantities word bytes bits) doubleword four bytes bits) quadword eight bytes bits) Addressing-Memory addressed series bytes eight-byte (64-bit) boundaries which each byte separately enabled. Abbreviations-The following notation used bits bytes: Kilo 4-Kbyte page) Mega Mbits/sec) Giga Gbytes memory space) Table page more abbreviations. Little-Endian Convention-The byte with address xx.xx00 least-significant byte position (little end). byte diagrams, positions numbered from right left-the little right left. Data structure diagrams memory show addresses bottom high addresses top. When data items aligned, notation 64-bit data maps directly notation 64-bit-wide memory. Because byte addresses increase from right left, strings appear reverse order when illustrated. Ranges-In text, ranges shown with dash (for example, bits 9-1). When accompanied signal name, highest lowest numbers contained brackets separated colon (for example, AD[31:0]). Values-Bits either cleared Hexadecimal Binary Numbers-Unless context makes interpretation clear, hexadecimal numbers followed binary numbers followed
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Abbreviations Acronyms
Table contains definitions abbreviations used this document. Table Abbreviations
Abbreviation Gbit Gbyte Kbyte Mbit Mbyte Meaning Ampere Farad GigaGigabit Gigabyte Henry Hexadecimal KiloKilobyte MegaMegabit Megabyte Megahertz MilliMillisecond Milliwatt MicroMicroampere Microfarad Microhenry Microsecond Microvolt nanonanoampere nanofarad nanohenry nanosecond picopicoampere
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Table
Abbreviation
Abbreviations (continued)
Meaning picofarad picohenry picosecond Second Volt Watt
Table contains definitions acronyms used this document. Table Acronyms
Abbreviation ACPI APCI APIC BIOS BIST DIMM DRAM EIDE EISA EPROM FIFO GART HSTL Meaning Advanced Configuration Power Interface Accelerated Graphics Port Peripheral Component Interconnect Application Programming Interface Advanced Programmable Interrupt Controller Basic Input/Output System Built-In Self-Test Interface Unit Double-Data Rate Dual Inline Memory Module Direct Memory Access Direct Random Access Memory Error Correcting Code Enhanced Integrated Device Electronics Extended Industry Standard Architecture Enhanced Programmable Read Only Memory DigitalAlphaBus First First Graphics Address Remapping Table High-Speed Transistor Logic Integrated Device Electronics Industry Standard Architecture
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Table
Abbreviation JEDEC JTAG LVTTL MTRR PBGA PMSM POST SDRAM SMbus SRAM SROM
Acronyms (continued)
Meaning Joint Electron Device Engineering Council Joint Test Action Group Large Area Network Least-Recently Used Voltage Transistor Transistor Logic Most Significant Memory Type Range Registers Multiplexer Non-Maskable Interrupt Open-Drain Plastic Ball Grid Array Physical Address Peripheral Component Interconnect Page Directory Entry Page Directory Table Phase Locked Loop Power Management State Machine Power-On Suspend Power-On Self-Test Random Access Memory Read Only Memory Read Acknowledge Queue System DRAM Interface Synchronous Direct Random Access Memory Serial Initialization Packet System Management Serial Presence Detect Synchronous Random Access Memory Serial Read Only Memory Translation Lookaside Buffer Memory Transistor Transistor Logic Virtual Address Space Virtual Page Address
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Preliminary Information AthlonProcessor Model Data Sheet
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Table
Abbreviation
Acronyms (continued)
Meaning Video Graphics Adapter Universal Serial Zero Delay Buffer
Appendix
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