8-bit RISC Extended Microcontroller 2.00 DR8052EX soft core binar

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8-bit RISC Extended Microcontroller 2.00 DR8052EX soft core binar

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DR8052EX
8-bit RISC Extended Microcontroller 2.00
DR8052EX soft core binary-compatible with industry standard 8052 8-bit microcontroller achieve performance million instructions second today's integrated circuit technologies. DR8052EX RISC architecture that time faster compare original implementation. De-multiplexed Address/Data allow easy connection memory Over times data transfer faster than original implementation Three 16-bit timer/counters Eight Additional interrupts full-duplex serial ports controller data pointers (DPTR1 DPTR2) industry Support External SFRs Fully synthesizable, static synchronous design with internal tri-states original virtual clock frequency compare original implementation (over typical 0.25u technological process)
FEATURES
Software compatible standard 8052 RISC architecture times faster implementation 5-clk periods division bytes external standard Data Memory bytes internal dual port Data Memory bytes Program Memory User programmable RAMWE RAMRD pulses between clock periods than with
4-clk periods multiplication
DELIVERABLES
VHDL, Verilog source code VITAL simulation model test bench Synthesis scripts Technical documentation Technical support
DESIGN FEATURES
DATA MEMORY:
PINS DESCRIPTION
port0i[7:0] port1i[7:0] port2i[7:0] port3i[7:0] prgdata[7:0] xramdatai[7:0] ramdati[7:0] sfrdatai[7:0] int0 int1 int2 int3 int4 int5 int6 int7 int8 gate0 gate1 t2ex rxd0i rxd1i scli sdai port0o[7:0] port1o[7:0] port2o[7:0] port3o[7:0] prgaddr[15:0] xramaddr[23:0] xramdatao[7:0] xramwr xramrd ramsfraddr[7:0] ramsfrdatao[7:0] ramwe ramrd sfrwe sfrrd rxd0o rxd1o txd0 txd1 sclo sdao
TYPE
input input input input input input input input input input input input input input input input input input input input input input input input input input input input input output output output output output output output output output output output output output output output output output output output output output
DESCRIPTION
Global clock Global reset Port input Port input Port input Port input Data from program memory Data from ext. data memory Data from int. data memory Data from user SFR's External interrupt External interrupt External interrupt External interrupt External interrupt External interrupt External interrupt External interrupt External interrupt Timer input Timer input Timer input Timer gate input Timer gate input Timer trigger input Serial receiver input Serial receiver input clock line input data line input Port output Port output Port output Port output Program memory address External data memory address Data external data memory External data memory write External data memory read SFR's address Data internal data memory Internal data memory write enable Internal data memory read User SFR's write enable User SFR's read Serial receiver output Serial receiver output Serial transmitter output Serial transmitter output clock line output data line output
DR8052EX address Internal Data Memory bytes, bytes external Data function interconnect signals. Internal Data Memory implemented Single-Port synchronous asynchronous RAM.
EXTERNAL
SPECIAL
FUNCTION
REGISTERS: External Special Function Registers (ESFRs) added DR8052EX design. ESFRs memory mapped into Direct Memory between addresses same manner core SFRs occupy address that occupied core SFR.
STRETCH
MEMORY CYCLE REGISTER: Allows applications software adjust different external speeds (XRAMWR XRAMRD pulse between clock cycles).
EXTERNAL RAM:
Allows applications software access external data memory. Extra DPP( Data Page Pointer) register used segments swapping.
ADDITIONAL INTERRUPTS
Four additional level sensitive interrupts (INT2-INT5), three additional falling edge sensitive interrupts (INT6-INT8).
SYMBOL
trademarks mentioned this document trademarks their respective owners.
http://www.dcd.com.pl
Copyright 1999-2000 Digital Core Design. Rights Reserved.
port0i(7:0) port1i(7:0) port2i(7:0) port3i(7:0)
port0o(7:0) port1o(7:0) port2o(7:0) port3o(7:0)
Area 2892 1EAB System clock fmax
prgdata(7:0) prgaddr(15:0) xramdatai(7:0) xramdatao(7:0) xramaddr(23:0) xramrd xramwr ramdatai(7:0) ramsfrdatao(7:0) sfrdatai(7:0) ramsfraddr(7:0) ramrd ramwe sfrrd sfrwe
MODIFICATIONS
modification special request contact DCD. Headquarter: Wroclawska 41-902 Bytom POLAND e-mail: info@dcd.com.pl tel.
int0 int1 int2 int3 int4 int5 int6 int7 int8 gate0 gate1 t2ex rxd0i rxd1i scli sdai
Field Office: Texas Research Park 14815 Omicron suite
txd0 txd1 rxd0o rxd1o sclo sdao
Antonio, 78245 e-mail: info-us@dcd.com.pl tel. 0185 0635
Distributor: MTC-Micro Tech Consulting GmbH Weidegrund D-82194 Germany e-mail MTCinfo@mtc.de tel. 8142 5961-0 8142 5961-44
PERFORMANCE
following table gives survey about DR8052EX performance ALTERA® devices after Place Route (all features have been included): FLEX10K100E-1 Area 2832 1EAB System clock fmax APEX10K100E-1 Area System clock fmax ACEX1K100-1
trademarks mentioned this document trademarks their respective owners.
2930
http://www.dcd.com.pl
Copyright 1999-2000 Digital Core Design. Rights Reserved.

8-bit RISC Extended Microcontroller 2.00 DR8052EX soft core binar

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