8-bit RISC Microcontroller 2.00 DR8051 soft core binary-compatibl

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8-bit RISC Microcontroller 2.00 DR8051 soft core binary-compatibl

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DR8051
8-bit RISC Microcontroller 2.00
DR8051 soft core binary-compatible with industry standard 8051 8-bit microcontroller achieve performance million instructions second today's integrated circuit technologies. DR8051 RISC architecture that time faster compare original implementation. User programmable RAMWE RAMRD pulses between clock periods De-multiplexed Address/Data allow easy connection memory Over times data transfer faster than original implementation 16-bit timer/counters Full-duplex serial port Support External SFRs Fully synthesizable, static synchronous design with internal tri-states virtual clock frequency compare original implementation (over typical 0.25u technological process)
FEATURES
Software compatible with industry standard 8051 RISC architecture times faster than original implementation 4-clk periods multiplication 5-clk periods division bytes external standard Data Memory bytes internal dual port Data Memory bytes Program Memory
SPECIAL FEATURES
controller Floating-Point arithmetic coprocessor IEEE-754 standard single precision FADD, FSUB addition, subtraction FMUL, FDIV- multiplication, division FSQRT- square root
FUCOM compare FCHS change sign FABS absolute value Floating-Point math coprocessor IEEE754 standard single precision real, word short integers FADD, FSUB- addition, subtraction FMUL, FDIV- multiplication, division FSQRT- square root FUCOM- compare FCHS change sign FABS absolute value FSIN, FCOS- sine, cosine FPTAN, FPATAN- tangent, arcs tangent Allows applications software access external data memory. Extra DPP( Data Page Pointer) register used segments swapping. External Special Function Registers (ESFRs) added DR8051 design. ESFRs memory mapped into Direct Memory between addresses same manner core SFRs occupy address that occupied core SFR.
STRETCH MEMORY CYCLE REGISTER:
Allows applications software adjust different external speeds (XRAMWR XRAMRD pulse between clock cycles).
EXTERNAL RAM:
DELIVERABLES
VHDL, Verilog source code VITAL simulation model test bench Synthesis scripts Technical documentation Technical support
port0i(7:0) port1i(7:0) port2i(7:0) port3i(7:0) port0o(7:0) port1o(7:0) port2o(7:0) port3o(7:0)
SYMBOL
prgdata(7:0) prgaddr(15:0) xramdatai(7:0) xramdatao(7:0) xramaddr(23:0) xramrd xramwr ramdatai(7:0) ramsfrdatao(7:0) sfrdatai(7:0) ramsfraddr(7:0) int0 int1 gate0 gate1 rxdi ramrd ramwe sfrrd sfrwe
DESIGN FEATURES
DATA MEMORY:
DR8051 address Internal Data Memory bytes, bytes external Data function interconnect signals. Internal Data Memory implemented Single-Port synchronous asynchronous RAM.
EXTERNAL SPECIAL FUNCTION REGISTERS:
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rxdo
PINS DESCRIPTION
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Copyright 1999-2000 Digital Core Design. Rights Reserved.
port0i[7:0] port1i[7:0] port2i[7:0] port3i[7:0] prgdata[7:0] xramdatai[7:0] ramdati[7:0] sfrdatai[7:0] int0 int1 gate0 gate1 rxdi port0o[7:0] port1o[7:0] port2o[7:0] port3o[7:0] prgaddr[15:0] xramaddr[23:0] xramdatao[7:0] xramwr xramrd ramsfraddr[7:0] ramwe ramrd sfrwe sfrrd rxdo
TYPE
input input input input input input input input input input input input input input input input input
DESCRIPTION
Global clock Global reset Port input Port input Port input Port input Data from program memory Data from ext. data memory Data from int. data memory Data from user SFR's External interrupt External interrupt Timer input Timer input Timer gate input Timer gate input Serial receiver input
following table gives survey about DR8051 performance ALTERA® devices after Place Route (all features have been included): FLEX10K100E-1 Area 2049 1EAB System clock fmax APEX20K100E-1 Area 2120 System clock fmax ACEX1K100-1 Area 2096 System clock fmax
output Port output output Port output output Port output output Port output output Program memory address output External data memory address output Data external data memory output External data memory write output External data memory read output SFR's address output Internal data memory write enable output Internal data memory read output User SFR's write enable output User SFR's read output Serial receiver output output Serial transmitter output
ramsfrdatao[7:0] output Data internal data memory
PERFORMANCE
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MODIFICATIONS
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Copyright 1999-2000 Digital Core Design. Rights Reserved.
modification special request contact DCD. Headquarter: Wroclawska 41-902 Bytom POLAND e-mail: info@dcd.com.pl tel.
Field Office: Texas Research Park 14815 Omicron suite Antonio, 78245 e-mail: info-us@dcd.com.pl tel. 0185 0635
Distributor: MTC-Micro Tech Consulting GmbH Weidegrund D-82194 Germany e-mail MTCinfo@mtc.de tel. 8142 5961-0 8142 5961-44
trademarks mentioned this document trademarks their respective owners.
http://www.dcd.com.pl
Copyright 1999-2000 Digital Core Design. Rights Reserved.

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