December 2000; ver. 1.00 Data Sheet Easy-to-use MegaWizard® Plug-

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December 2000; ver. 1.00 Data Sheet Easy-to-use MegaWizard® Plug-

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SONET/SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM)
December 2000; ver. 1.00 Data Sheet
Easy-to-use MegaWizard® Plug-In generates MegaCore® variants Quartussoftware OpenCorefeature allow place-and-route, static timing analysis designs prior licensing Secure Register Transfer Level (RTL) simulation models allow simulation with user design third-party simulators Performs Synchronous Optical Network (SONET)/Synchronous Digital Hierarchy (SDH) framing Transport Convergence (TC) Processes Transport Overhead (TOH) Path Overhead (POH) Supports data rate 155.52 megabits second (Mbps) Complies with applicable standards, including: Bellcore, Synchronous Optical Network (SONET) Transport Systems: Common Generic Criteria, Generic Requirements GR-253CORE, Issue Revision January 1999 Bellcore, Synchronous Optical Network (SONET) Transport Systems: Common Generic Criteria, Issues List Report GR-253-ILR, Issue September 1996 International Telecommunication Union, Network node interface synchronous digital hierarchy (SDH), ITU-T 707, March 1996 International Telecommunication Union, Characteristics synchronous digital hierarchy (SDH) equipment functional blocks, ITU-T 783, January 1994 Optimized Altera® APEX20KE device architecture
Tools
Typical Applications
Figure Typical Application
Figure shows example system implementation STS3CFRM interfacing with other Altera MegaCore variants achieve Atransport over SONET.
Midbus rxclk Fiber Optic Module Clock Data Recovery SONET/SDH STS-3c/ STM-1 Framer (STS3CFRM)
Atlantic Interface
Serializer Deserializer
ACell Processor Mbps (CP155)
UTOPIA Interface (UTOPIA2SL)
txclk External
AIRbus
APEX Boundary
Note:
PIF-Processor Interface Block
Altera Corporation
A-DS-IPSONET-01
UTOPIA Level
SONET/SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM) Data Sheet
Other possible applications include:
Aswitches Digital Cross-Connection (DCC) systems Routers Multiplexers
Functional Description
STS3CFRM operates full-duplex mode, comprises four blocks (see Figure following list functions based full feature STS3CFRM. Table possible options.
Transport Overhead Receiver (RXTOH) Inputs SONET data Descrambles data (software enabled) Performs frame alignment Performs error checking Maintains counters buffers Captures bytes processing software, parameterized hardware extraction Path Overhead Receiver (RXPOH_0) Processes pointer Performs error checking Maintains counters buffers Captures bytes processing software, parameterized hardware extraction Outputs payload data Path Overhead Transmitter (TXPOH_0) Inputs payload data Allows flexible insertion software, parameterized hardware Generates parity bytes Maintains counters buffers Transport Overhead Transmitter (TXTOH) Generates pointer (normal, positive stuff, negative stuff, Data Flag (NDF) selected software) Allows flexible insertion software, parameterized hardware Generates parity bytes Maintains counters buffers Scrambles data (software enabled) Outputs SONET data
Altera Corporation
SONET/SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM) Data Sheet
Interfaces Protocols
interfaces support STS3CFRM: Middle interface (Midbus), Access Internal Registers (AIRbus) interface.
Midbus
Midbus interface simple synchronous full-duplex data path bus. STS3CFRM Midbus runs 19.44 over single byte lane each direction. receive (RX) direction, data transferred from Midbus master (RXPOH_0) slave. transmit (TX) direction, data transferred from slave master (TXPOH_0). each direction, Midbus carry eight bits clock cycle. includes midbus receive data (mrxdat_0[7:0]) midbus receive enable(mrxena_0) lines indicate valid data transfers direction, midbus transmit data (mtxdat_0[7:0]) midbus data enable(mtxena_0) lines indicate valid data requests direction.
AIRbus
AIRbus interface provides access internal registers using simple synchronous internal processor protocol. This consists separate read data (rdata[31:0]) write data (wdata[31:0]) buses, data transfer acknowledge (dtack) signal, block select (sel). address (addr[11:2]) read (read) signal indicate location type access within block. rdata buses dtack signals merged from multiple blocks using simple function. dtack signal sustained until block removed (four-way handshaking), meaning AIRbus cross clock domain boundaries. this block AIRbus data width bits.
Tools
More detailed information Midbus AIRbus available from Altera site
Altera Corporation
SONET/SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM) Data Sheet
Figure Block Diagram
Extract Extract rxpohval_0 rxpohclk_0 rxpohfp_0
rxldcc rxldccval rxe1f1e2 rxe1f1e2val rxe1f1e2fp
rxsdccval
rxpause rxreset_n
SONET
srxdat[7:0] srxval srxfr align_data[7:0] lopc
RXTOH RXPOH_0 mrxdat_0[7:0] mrxena_0 mrxval_0 mrxffp_0 mrxefp_0 mrxfoh_0 mrxeoh_0 mtxdat_0[7:0] mtxena_0 mtxval_0 mtxffp_0 mtxefp_0 mtxfoh_0 mtxeoh_0
txclk domain TXPOH_0
stxdat[7:0] stxval stxfr stxfp
SONET
TXTOH
txtohclk txtoh txtohen txtohfp txtohrdy txsdcc txsdccrdy txldcc txldccrdy txe1f1e2 txe1f1e2fp txe1f1e2rdy
read addr[11:2] rdata[31:0] wdata[31:0] dtack
txpohclk_0
txclk txpause txreset_n
Insert
AIRbus
Insert
Pin-Outs
following port list STS3CFRM. signal direction indicated input, output. Clock Domain Signals: rxclk (I), rxpause (I), rxreset_n (I); SONET Signals: srxdat[7:0](I), srxval (I), srxfr (I); Maintenance Signals: align_data[7:0](O),lopc (I), (O), (O), (O); Hardware Serial Extract Signals: rxtohclk (O), rxtoh (O), rxtohval (O), rxtohfp (O), rxsdcc (O), rxsdccval (O), rxldcc (O), rxldccval (O), rxe1f1e2 (O), rxe1f1e2val (O), rxe1f1e2fp (O); Hardware Serial Extract Signals: rxpohclk_0 (O), rxpoh_0 (O), rxpohval_0 (O), rxpohfp_0 (O); Midbus Signals: mrxdat_0[7:0] (O), mrxena_0 (O), mrxval_0 (O), mrxffp_0 (O), mrxefp_0 (O), mrxfoh_0 (O), mrxeoh_0 (O).
txpohen_0 txpohfp_0 txpohrdy_0
txpoh_0
Altera Corporation
Midbus
rxclk domain
rxpoh_0
rxtohclk rxtoh rxtohval rxtohfp
rxsdcc
rxclk
SONET/SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM) Data Sheet
Clock Domain Signals: txclk (I), txpause (I), txreset_n (I); SONET Signals: stxdat[7:0] (O), stxval (O), stxfr (I), stxfp (O); AIRbus Signals: (I), read (I), addr[11:2] (I),rdata[31:0] (O),wdata[31:0] (I), dtack (O), (O); Hardware Serial Insert Signals: txtohclk (O), txtoh (I), txtohen (I), txtohfp (O), txtohrdy (O), txsdcc (I), txsdccrdy (O), txldcc (I), txldccrdy (O), txe1f1e2 (I), txe1f1e2fp (O), txe1f1e2rdy (O); Hardware Serial Insert Signals: txpohclk_0 (O), txpoh_0 (O), txpohen_0 (I), txpohfp_0 (O), txpohrdy_0 (O); Midbus Signals: mtxdat_0[7:0] (I), mtxena_0 (O), mtxval_0 mtxffp_0 (O),mtxefp_0 (O), mtxfoh_0 (O), mtxeoh_0 (O).
Performance
Table shows required speed estimated gate count STS3CFRM APEX 20KE device. Table Performance
4,606-7,268 Notes:
numbers Logic Elements (LEs) Embedded System Blocks (ESBs) approximate Dec. 2000. They reflect range from basic full feature variant.
Note ESBs
6-16
fMAX (MHz)
19.44 required support 155.52 Mbps
Tools
Generating Variants
Table Optional
Table shows optional features available generate possible variants.
Note Options Parameters Choices
BM1S
4,606 1332
ESBs
Basic Configuration
Serial insertion/extraction bytes 64-byte insert, extract, expect buffers Automatic monitoring extracted section trace (transport overhead) 64-byte insert, extract, expect buffers Automatic monitoring extracted path trace (path overhead) error rate monitoring with second window Note:
numbers ESBs approximate Dec. 2000. Users strongly advised MegaWizard Plug-In Quartus software exact numbers each STS3CFRM variant.
Altera Corporation
SONET/SDH STS-3c/STM-1 Framer MegaCore Function (STS3CFRM) Data Sheet
Licensing
license required perform following trial operations using your custom logic:
Instantiation Place-and-Route Static Timing Analysis Simulation third-party simulator
Only when ready generate programming files, need obtain licenses through your local Altera sales representative. current variants single license with ordering code: PLSM-STS3CFRM.
Deliverables
following elements provided with STS3CFRM package:
Data Sheet User Guide Interface Functional Specifications (Midbus, AIRbus, etc.) MegaWizard Plug-In Encrypted gate level netlist Place-and-Route constraints (where necessary) Secure simulation model Sanity testbench Access problem reporting system
Innovation Drive Jose, 95134 (408) 544-7000 http://www.altera.com Applications Hotline: (800) 800-EPLD Customer Marketing: (408) 544-7104 Literature Services: lit_req@altera.com
Altera, APEX, APEX 20K, MegaCore, MegaWizard, OpenCore, Quartus trademarks and/or service marks Altera Corporation United States other countries. Altera acknowledges trademarks other organizations their respective products services mentioned this document. Altera products protected under numerous U.S. foreign patents pending applications, maskwork rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services. Copyright 2000 Altera Corporation. rights reserved.
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Altera Corporation

December 2000; ver. 1.00 Data Sheet Easy-to-use MegaWizard® Plug-

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