December 2000; ver. 1.00 Data Sheet Easy-to-use MegaWizard® Plug-

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December 2000; ver. 1.00 Data Sheet Easy-to-use MegaWizard® Plug-

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Packet Processor Mbps MegaCore Function (PP622)
December 2000; ver. 1.00 Data Sheet
Easy-to-use MegaWizard® Plug-In generates MegaCore® variants Quartussoftware OpenCorefeature allow place-and-route, static timing analysis designs prior licensing Secure Register Transfer Level (RTL) simulation models allow simulation with user design third-party simulators Full-duplex processing capability Octet-synchronous mode operation High-Level Data Link Control (HDLC)-type framing 622.08 megabits second (Mbps) transmission rate 32-bit Frame Check Sequence (FCS) Single channel processor interleaving) Internet Request Comments (RFC) 1662 compliant (some sections implemented) Optimized Altera® APEX20KE device architecture
Tools
Typical Applications
Figure shows example system implementation PP622 interfacing with other Altera MegaCore variants achieve over SONET. Midbus Atlantic interfaces allow PP622 connect several other devices including:
carrier processor Ethernet Media Access Controller (MAC) Direct Memory Access (DMA) controller Packet switch router
Figure Typical Application
Midbus Atlantic
Fiber Optic Module
Clock Data Recovery
Serializer Deserializer
SONET/ STS-12c/ STM-4 Framer (STS12CFRM)
Packet Processor Mbps (PP622)
POS-PHY Interface (POSPHY/P2)
txclk External
AIRbus
APEX Boundary
Note:
PIF-Processor Interface Block
Altera Corporation
A-DS-IPPPP622-01
POS-PHY Level 1/2/3/
rxclk
Packet Processor Mbps MegaCore Function (PP622) Data Sheet
Functional Description
PP622 capable performing HDLC-type framing. operates full-duplex mode, comprises blocks, illustrated Figure
following list functions based full feature PP622.
High-Level Data Link Control Receiver (RXHDLC) Inputs packets from Midbus interface Aligns receive bytes (software programmable) Descrambles receive frame between-frame flags using self-synchronizing scrambler (software programmable) Detects Start Frame (SOF) Decodes removes byte stuffing Checks receive FCS, removes from frame (software programmable) Outputs packets Atlantic interface High-Level Data Link Control Transmitter (TXHDLC) Takes packets from Atlantic interface Byte stuffs control bytes data transparency Calculates packet data (before stuffing), appends packet Sends more HDLC flag(s) after until packet available Scrambles transmit frame between-frame flags using self-synchronizing scrambler (software programmable) Outputs frames Midbus interface
Interfaces Protocols
Three interfaces support PP622: Middle interface (Midbus), Access Internal Registers (AIRbus) interface, Atlantic interface. Midbus interface simple synchronous full-duplex data path bus. PP622 Midbus runs 77.76 over single byte lane each direction. receive direction (RX), data transferred from Midbus master slave (PP622). transmit direction (TX), data transferred from slave (PP622) master. each direction, Midbus carry eight bits clock cycle. includes midbus receive data (mrxdat[7:0]) midbus receive enable (mrxena) lines indicate valid data transfers direction, midbus transmit data (mtxdat[7:0]) midbus transmit enable (mtxena) lines indicate valid data requests direction. Since PP622 slave Midbus work with Midbus master.
Altera Corporation
Packet Processor Mbps MegaCore Function (PP622) Data Sheet
AIRbus interface provides access internal registers using simple synchronous internal protocol. This consists separate read data (rdata[15:0]) write data (wdata[15:0]) buses, data transfer acknowledge (dtack) signal, select (sel) signal. address (addr[4:1]) read (read) signal indicate location type access within block. rdata buses dtack signals merged from multiple blocks using simple function. dtack signal sustained until block removed (four-way handshaking) meaning AIRbus cross clock domain boundaries. PP622 AIRbus slave with data width bits. Atlantic interface full-duplex synchronous protocol supporting both packets cells. PP622 Atlantic interface master using 8-bit wide data path deliver packets slave. example slave POS-PHY MegaCore variant shown Figure POS-PHY MegaCore variant includes First First (FIFO) buffer crossing clock domain.
Figure Block Diagram
More detailed information Midbus, AIRbus, Atlantic available from Altera site
Tools
PP622 arxena
rxclk
rxreset_n
RXHDLC
arxdav arxdiv arxval arxdat[7:0] arxsop arxeop arxerr
Midbus
mrxdat[7:0] mrxena
Atlantic
txclk txreset_n
atxena TXHDLC atxdiv atxdav atxval atxdat[7:0] atxeop atxsop atxerr
Midbus
mtxdat[7:0] mtxena
read
dtack
wdata[15:0]
addr[4:1]
AIRbus
Altera Corporation
rdata[15:0]
Packet Processor Mbps MegaCore Function (PP622) Data Sheet
Pin-Outs
following lists ports PP622. signal direction indicated input output. Clock Domain Signal: rxclk (I); Midbus Signals: mrxdat[7:0] (I), mrxena (I); Atlantic Signals: arxena (O), arxdav (I), arxdiv (O), arxval (O), arxdat[7:0] (O), arxsop (O), arxeop (O), arxerr (O). AIRbus Signals: (I), read (I), addr[4:1] (I), wdata[15:0] (I), rdata[15:0] (O), dtack (O), (O). Clock Domain Signals: txclk (I), txreset_n (I); Midbus Signals: mtxdat[7:0] (O), mtxena (I); Atlantic Signals: atxena (O), atxdiv (I), atxdav (I), atxval (I), atxdat[7:0] (I), atxsop (I), atxeop (I), atxerr (I).
Performance
Table shows required speed estimated gate count PP622 APEX 20KE device. Table Performance
1,286 Note:
numbers Logic Elements (LEs) Embedded System Blocks (ESBs) approximate Dec. 2000.
Note ESBs
fMAX (MHz)
77.76 required support 622.08 Mbps
Licensing
license required perform following trial operations using your custom logic:
Instantiation Place-and-Route Static Timing Analysis Simulation third-party simulator
Only when ready generate programming files, need obtain licenses through your local Altera sales representative. current variants single license with ordering code: PLSM-PP622.
Altera Corporation
Packet Processor Mbps MegaCore Function (PP622) Data Sheet
Deliverables
following elements provided with PP622 package:
Data Sheet User Guide Interface Functional Specifications (AIRbus, Midbus, Atlantic, etc.) MegaWizard Plug-In Encrypted gate level netlist Place-and-Route constraints (where necessary) Secure simulation model Sanity testbench Access problem reporting system
Innovation Drive Jose, 95134 (408) 544-7000 http://www.altera.com Applications Hotline: (800) 800-EPLD Customer Marketing: (408) 544-7104 Literature Services: lit_req@altera.com
Altera, APEX, APEX 20K, MegaCore, MegaWizard, OpenCore, Quartus trademarks and/or service marks Altera Corporation United States other countries. Altera acknowledges trademarks other organizations their respective products services mentioned this document. Altera products protected under numerous U.S. foreign patents pending applications, maskwork rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services. Copyright 2000 Altera Corporation. rights reserved.
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Altera Corporation

December 2000; ver. 1.00 Data Sheet Easy-to-use MegaWizard® Plug-

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