FN124 converter MODEL FN1242 Note: Specifications conta

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FN124 converter MODEL FN1242 Note: Specifications conta

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FN124
converter
MODEL FN1242
Note: Specifications contained here tentative. Functions layout subject changes.
NIIGATA SEIMITSU CO., LTD.
010913 1/18
FN1242
OVERVIEW
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FN1242 2CH-1 converter 24-bit digital audio. Fluency type interpolator built-in. newly designed multi-bit system with high jitter tolerance adopted modulator order improve basic performance analog output. setting external terminals, possible input direct stream digital (DSD) signals directly converter analog conversion. addition, with bandwidth analog filter differential voltage output buffer built-in, FN1242 reproduces high quality audio signals combination with external differential circuit.
FEATURES
24-bit, over sampling Fluency type interporator built-in. 100dB THD+N Under 0.004 %TYP Sampling frequency32 KHz192 Left justified MSB, Right justified MSB, format (16/20/24 interface). System clock Master clock frequencies selected automatically, certain combinations master clock frequency sampling frequency available. Various functions serial function control. Digital De-emphasis Filter: 32kHz/44.1kHz/48kHz (Selectable with external terminals) Soft Mute Linear Digital Attenuator Zero Data Detection Power supply voltage Digital (VDD) 3.0V 3.6V 5.5V Package 28pin SSOP
APPLICATIONS
FN1242 suitable improvement audio quality digital audio system such home audio system, audio system including SACD players, digital box, etc.
010913
NIIGATA SEIMITSU CO.,
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Block diagram
FN124
LRCK (CLK) BCK(RIN) DIN(LIN
SERIAL INTERFACE
OUTLP OUTLM
OVER SAMPLING FLUENCY INTERPOLATOR MUTE EMP0 EMP1 FMT0 FMT1 FMT2 TEST
MULTIBIT MODULATOR
VCOM
SERIAL INTERFACE
OUTRP OUTRM
ZERO DETECT
SYSTEM CLOCK
POWER SUPPLY
RSTB
Layout
SSOP
EMPH0 EMPH1 DVDD DGND BCK(DIR) DIN(DIL) LRCK(CLK) FMT0 FMT1 FMT2 TEST ZEROL OUTLP OUTLM AVDD1 AGND1 VCOM AGND2 AVDD2 OUTRM OUTRP ZEROR MUTE RSTB
NIIGATA SEIMITSU CO., LTD.
DVDD DGND AVDD1 AGND1 AVDD2 AGND2
ZELOL
ZELOR
010913 3/18
FN1242
Terminals
Name EMPH0
De-emphasis Filter Select.
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Function EMPH1,0 32kHz 44.1kHz 48kHz De-emphasis Function control latch Function control data Function control clock System clock Digital power supply (3.3V) Digital ground clock data (DIR) input when formatting Audio data. data (DIL) input when formatting clock input Data clock (CLK) input when formatting
Input Data Format Select.
EMPH1 DVDD DGND DIN(DIL) LRCK(CLK) FMT0
FMT1
FMT2 RSTB MUTE ZEROR OUTRP OUTRM AVDD2 AGND2 VCOM AGND1 AVDD1 OUTLM OUTLP ZEROL TEST
FMT2, 16bit first right-justified Reserve (unused) 20bit first right-justified 24bit first right-justified format 16,20,24bit first left-justified 16,20,24bit format Reserve (unused)
Reset input.
Soft Mute input channel zero data detection output R-ch analog audio output R-ch analog audio output R-ch analog power supply R-ch analog ground Analog common de-coupling terminal L-ch analog ground L-ch analog power supply analog audio output analog audio output channel zero data detection output Test terminal (connect DGND)
010913
NIIGATA SEIMITSU CO.,
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Electrical characteristics
FN124
Absolute maximum ratings Ta=25, DGND AGND1 AGND2 Item Symbol Ratings UNIT DVDD -0.3 Power supply voltage AVDDR AVDDL -0.3 -0.2 DVDD Input voltage -0.2 DVDD Output voltage -0.2 AVDD Tstg +125 Storage Temperature Note: Absolute maximum ratings highest value which doesn't harm chip. doesn't guarantee normal function. Recommended operational conditions Item Symbol DVDD Power supply voltage AVDD1 AVDD2 Operating Temperature
UNIT
Analog characteristics fs=44.1 Unless otherwise specified, Ta=25, AVDD1=AVDD2=5V, DVDD=3.3V, SYSCLK=384 24-bit data, Signal 1KHz, Measuring range 10KHz20KHz UNIT Item Condition Resolution Bits 0.004 THD+N Vo=-60dB Vo=-60dB, Dynamic Dynamic range EIAJ characteristics EIAJ ratio Channel separation Gain Error ±1.0 ±5.0 %ofFSR Inter Channel Gain Mismatch ±1.0 ±5.0 %ofFSR characteristics Zero Error Vp-p Output voltage Analog output Center voltage Load resistance -3dB bandwidth Analog filter -0.1 Frequency characteristics f=1kHz/ Current DVDD Power supply f=1kHz/ Current AVDD
NIIGATA SEIMITSU CO., LTD.
010913 5/18
FN1242
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Analog characteristics fs=96 Unless otherwise specified, Ta=25, AVDD1=AVDD2=5V, DVDD=3.3V, SYSCLK=384 24-bit data, Signal 1KHz, Measuring range 10KHz20KHz UNIT Item Condition Resolution THD+N Vo=-60dB Vo=-60dB, EIAJ EIAJ 1kHz 0.004 ±1.0 ±1.0 -0.1 Bits
Dynamic characteristic Dynamic range ratio Channel separation Gain Error characteristic Inter Channel Gain Mismatch Zero Error Output voltage Analog output Center voltage Load resistance -3dB bandwidth Analog filter Frequency characteristics Current DVDD Power supply Current AVDD
±5.0 %ofFSR ±5.0 %ofFSR Vp-p
Analog characteristics fs=192 Unless otherwise specified, Ta=25, AVDD1=AVDD2=5V, DVDD=3.3V, SYSCLK=384 24-bit data, Signal 1KHz, Measuring range 10KHz20KHz UNIT Item Condition Resolution Bits 0.004 THD+N Vo=-60dB Dynamic Vo=-60dB, characteristic Dynamic range EIAJ EIAJ ratio 1kHz Channel separation Gain Error ±1.0 ±5.0 %ofFSR characteristic Inter Channel Gain Mismatch ±1.0 ±5.0 %ofFSR Zero Error Vp-p Output voltage Analog output Center voltage Load resistance -3dB bandwidth Analog filter -0.1 Frequency characteristics Power supply Current DVDD Current AVDD
010913
NIIGATA SEIMITSU CO.,
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Digital filter characteristics Item Pass Band Passband Ripple Condition -3dB -6dB 0.42fs 0.51fs
FN124
De-emphais filter characteristics Item Symbol De-emphasis error fs=44.1 Group Delay characteristics Item Input logic level High Input logic level Output logic level High Output logic level characteristics Item Sampling frequency System clock frequency
-0.1
2/fs
+0.4
UNIT
Symbol
DVDD-0.6
DVDD
UNIT
Symbol fsck
44.1
UNIT
Signals input timing Left justified MSB, Right justified MSB, format signals input timing below.
LRCK
tDCY
tDCL tDCH
Item pulse cycle pulse width level pulse width level rise LRCK edge LRCK edge rise setup time hold time
Symbol tDCY tDCH tDCL
UNIT
NIIGATA SEIMITSU CO., LTD.
010913 7/18
FN1242
format signals input timing
tDCY
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tDCH tDCL
DATA LIN,
Item cycle pulse width level pulse width level DATA setup time DATA hold time
LRCK-SCK Timing
LRCK
Symbol tDCY tDCH tDCL
UNIT
tSCY
tSCH tSCL
Item pulse cycle pulse width level pulse width level rise LRCK edge LRCK edge rise Reset pulse width
RSTB
Symbol tSCY tSCH tSCL
UNIT
tRSTB
Item Reset pulse width
Symbol tRSTB
UNIT
010913
NIIGATA SEIMITSU CO.,
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Filter characteristics
-100
FN124
Characteristics Fluency type over sampling filter
Gain[dB]
Frequency [fs]
Attenuation characteristics
Frequency [fs]
De-emphasis filter characteristics
32kHz De-emphasis filter characteristics
Filter Gain[dB] Filter Characteristics 2000 4000 6000 8000 Frequency[Hz] 10000 12000 14000 Ideal Characteristics -0.8 -1.2 -1.6 16000 Gain Error -0.4 Gain Error[dB]
NIIGATA SEIMITSU CO., LTD.
Gain[dB]
010913 9/18
FN1242
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44.1KHz De-emphasis filter characteristics
Filter Gain[dB] 2000 4000 6000 8000 10000 12000 14000 16000 18000 20000 Frequency[Hz] Filter Characteristics Ideal characteristics Gain Error -0.4 -0.8 -1.2 -1.6 22000 Gain Error[dB]
48kHz De-emphasis filter characteristics
Filter Gain[dB] 2000 4000 6000 8000 10000 12000 14000 16000 18000 20000 Frequency[Hz] Ideal Characteristics Filter Characteristics Gain Error -0.4 -0.8 -1.2 -1.6 22000 Gain Error[dB]
010913 10/10
NIIGATA SEIMITSU CO.,
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Terminals
FN124
System clock FN1242 supports master clock frequencies 128fs, 192fs, 256fs, 384fs, 512fs, 768fs. However, certain combinations master clock frequency sampling frequency available. Sampling frequency 32kHz, 44.1kHz, 48kHz 88.2kHz, 96kHz 176.4kHz 192kHz 128fs 192fs 256fs 384fs 512fs 768fs
master clock frequencies automatically selected internally, however, performance guaranteed when combination sampling frequency master clock frequency shown above table. RSTB Reset internal circuit setting this terminal level. Function setting register reset. OUTLM, OUTLP, OUTRM, OUTRP terminals become while this terminal level.
ZEROL ZEROR When input data remains binary zero during 4095/BCK period, ZEROL ZEROR terminals LOW. ZEROL ZEROR correspond respectively. When input data binary zero, ZEROL ZEROR terminals immediately HIGH.
Audio format FMT2, FMT1, FMT0 Audio data input formats shown below. left justified, right justified, formats with selected length available setting with format setting terminals, FMT2, shown following table. FMT2 FMT1 FMT0 Audio format right justified Reserve (unused) right justified right justified format left justified 24bit 24bit Reserve (unused)
NIIGATA SEIMITSU CO., LTD.
010913 11/18
FN1242
LRCK, BCK,
LRCK
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Right Justified 16bit
Left Justified 16bit 20bit 24bit
20bit 24bit
LRCK
16bit 20bit
24bit
left justified format format, serial data beyond zero when input bit, serial data beyond zero when input bit. DIL, DIR, Audio input format shown below. Input data (DIL) terminal data (DIR) terminal. Input (data clock) LRCK terminal. data valid falling edge CLK. There restriction phase relationship between SCK.
Format Data
Data
LRCK Data Clock
64fs
010913 12/12
NIIGATA SEIMITSU CO.,
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Function setting
FN124
Functions controlled directly from input terminals using serial terminals (ML, MC). Setup directly from input terminals following functions directly from input terminals. De-emphasis EMPH1,EMPH0 EMPH1 EMPH0 De-emphasis 32kHz 44.1kHz 48kHz -emphasis filter ON/OFF coefficient corresponding sampling frequency selectable with EMPH1 EMPH0. Soft mute
Soft mute
Soft mute enabled when When setup functions using serial terminals instead input terminals, EMPH1, EMPH0 MUTE Setup using serial terminals (ML, Send serial control signal each terminals. serial control data data. register shown below.
MODE0 MODE1 MODE2
BIT1
BIT0
MUTE
EMPH1
EMPH0
signals input timing below.
tMC(min) 200ns tDC(min) tCD(min) tML(min) 100ns
NIIGATA SEIMITSU CO., LTD.
010913 13/18
FN1242
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mode control register basically three mode registers MODE0 MODE2), registers selected with serial data. First, select register with bits, then control each function with other bits. Control Register Mode (A1, Register MODE0 MODE1 MODE2
Attenuator (LDL, AL9-AL0LDR, AR9-AR0) MODE0 MODE1 digital control registers. using each (Lch) (Rch) (AL7 MSB, LSB), 1024-step attenuator controlled independently Lch/Rch. used attenuator value. When either "1", attenuator setup value becomes valid. When both "0", attenuator setup value valid, actual attenuator value remains previous level, updated until "1". minimum time required attenuator value shift from 1024/fs. Attenuation, ATT, given following formula.
log(DATA/1023 [dB]
DATA Attenuator setup value 3FFh Default 3FEh -0.00849dB 001h -60.1975dB 000h =MUTE Reset (RST) Reset Default Reset internal register. Functions reset default. register also reset. Length (BIT1, BIT0) BIT1 BIT0 Default Length 16bit 20bit 24bit Select length left justified format format. right justified format, length default.
010913 14/14 NIIGATA SEIMITSU CO.,
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Zero Detection Output Mode (ZM1, ZM0)
FN124
Output Mode Default Open Drain Pull-up Open Drain Push Pull Switch output mode zero detection output terminals, ZEROL ZEROR.
Attenuator control (ATC)
Attenuator control Default Lch/Rch Independent Lch/Rch Common When used attenuation level Lch, used attenuation level Rch. When used attenuation level Lch/Rch.
Soft mute (MUTE)
MUTE Soft mute Default
Enables soft mute.
De-emphais sontrol (EMPH1, EMPH0)
EMPH1 EMPH0 De-emphais Sampling frequebcy 44.1kHz 48kHz 32kHz Default
Select coefficient according de-emphasis filter On/Off sampling frequencies. Jitter Free Function When difference between LRCK does exceed (SCK clock period), functions continue operate normally. When timing error exceeds this value, automatically resynchronized, this will cause discontinuous operation. order minimize effect discontinuous operation analog signal, output data digital filter forced fixed BZP. When synchronization established, attenuation value returns setup value using digital attenuator.
Internal Conditin Normal Operatin Setup Value Attenuation Value
1024/fs
Resynchro -naization
Normal Operation Setup Value
NIIGATA SEIMITSU CO., LTD.
010913 15/18
FN1242
Application example
Audio Input
FN1242
De-emphsis Setup Mode Control Systm Clock 128/192/256/384/512/768fs +3.3V
10uF
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EMPH0 EMPH1 DVDD DGND LRCK FMT0 FMT1 FMT2
TEST ZEROL OUTLP OUTLM AVDD1 AGND1 VCOM AGND2 AVDD2 OUTRM OUTRP ZEROR MUTE RSTB
Audio Data Format Setup
Input
FN1242
System Clock 128/192/256/384/512/768fs +3.3V
10uF
EMPH0 EMPH1 DVDD DGND LRCK FMT0 FMT1 FMT2
TEST ZEROL OUTLP OUTLM AVDD1 AGND1 VCOM AGND2 AVDD2 OUTRM OUTRP ZEROR MUTE RSTB
0.1uF
Audio Data
010913 16/16
NIIGATA SEIMITSU CO.,
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Analog Output
5.0V
FN124
150pF
FN1242
0.1uF 100uF 0.1uF
5.1k 1.5k 4.7k 6.2k
OUTLP
330pF
6.2k
220pF
100pF
100uF
OUTLM
100pF 100pF
150pF
330pF 6.2k 5.1k 330pF 1.5k 4.7k 6.2k
5.0V
220pF
AVDD1 AGND1 VCOM
0.1uF
100uF
0.1uF
0.1uF
100uF
150pF
5.0V
5.1k 1.5k 4.7k 6.2k
AGND2
0.1uF
100uF 100pF
0.1uF 330pF 6.2k 220pF
AVDD2 OUTRM
100pF
100uF
OUTRP
100pF
150pF
330pF 6.2k 5.1k 330pF 1.5k 4.7k 6.2k
0.1uF
220pF
NIIGATA SEIMITSU CO., LTD.
010913 17/18
FN1242
Package
Package
Unit
DIMENSIONS MILLIMETER
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Marking
10.40
5.30 -0.1
±0.20
7.70
0.875
+0.05 0.10 -0.10 1.80 ±0.05
±0.12
0.65 ±0.12
0.15 ±0.05
0.85±0.05
10.20
-0.1
0.15 ±0.05 0.60 ±0.15 4°±3
0.3°
0.80±0.05
0.30 ±0.10
0.12 0.05
SEATING PLANE
10.15
-0.1
1.20 ±0.10
DETAIL
Marking
010913 18/18
NIIGATA SEIMITSU CO.,
5.30
-0.1

FN124 converter MODEL FN1242 Note: Specifications conta

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