Supports eight 10/100 Mbit/s Ethernet ports with RMII interface Capabl
|
|
|
Top Searches for this datasheet
AL126 Revision 8-Port 10/100 Mbit/s Dual Speed Fast Ethernet Switch
Supports eight 10/100 Mbit/s Ethernet ports with RMII interface Capable trunking Mbit/s link with link fail-over Full- half-duplex mode operation Supports addresses with VLAN without VLAN Scalable design stackable switch implementation RoX-II expansion link supports Gbit/s throughput Gigabit Ethernet ready with AL1022 Flexible prioritized queueing multimedia data traffic Layer switching with AL3000 RoX-II IEEE 802.3x flow control full-duplex operation Optional backpressure flow control support half-duplex operation 802.1p support with four priority levels 802.1q tag-based port-based VLAN support, VLAN table IGMP frame trapping Supports multicast groups RMON SNMP support with AL300A management (MIB) device 2.5V 3.3V operation Packaged 456-pin
AL126 eight-port 10/100 Mbit/s dual speed Ethernet switch. low-cost scalable solution ports achieved through low-cost buffer memory Allayer's proprietary RoX-IIarchitecture. addition, AL126 supports port-based 802.1q VLAN, 802.1p priority, IGMP frame trapping, multiple port aggregation trunks.
10/100
Switch Controller
Buffer Manager
10/100 Expansion Interface
10/100 High Speed Switch Fabric
Address Control
10/100
10/100
Address Table
Address Table Expansion
10/100 EEPROM Interface Management Information 10/100
10/100
Figure
System Block Diagram
Reference Only Allayer Communications
AL126 Revision
This document contains proprietary information which shall reproduced, transferred other documents, used other purpose without prior written consent Allayer Communications.
Disclaimer Allayer Communications reserves right make changes, without notice, product(s) described information contained herein order improve design and/or performance. Allayer Communications assumes responsibility liability these products, conveys license title under patent copyright these products, makes representations warranties that these products free from patent copyright infringement unless otherwise specified.
Life Support Applications Allayer Communications products designed life support appliances, systems, devices where malfunctions reasonably expected result personal injury.
10/00
Reference Only Allayer Communications
Table Contents
AL126 Overview Descriptions. Functional Description. RoX-II Interface. Data Reception. 3.2.1 3.2.2 3.2.3 3.2.4 3.3.1 3.3.2 3.3.3 Illegal Frame Length Long Frames False Carrier Events Frame Filtering. Broadcast Storm Control. Frame Transmission Preamble Regeneration
Frame Forwarding.
Half Duplex Mode Operation Secure Mode Operation Address Learning 3.6.1 3.7.1 3.7.2 Address Aging. Port Based VLAN Tagged VLAN VLAN Support.
3.10 3.11
Priority Queues User Priority Support Buffer Management Queue Behavior Multicast Group Support Trunking (Port Aggregation). Port Based Trunking (Port Aggregation) Trunking (Port Aggregation)
3.11.1 3.11.2 3.12 3.13
Spanning Tree Support. Flow Control Half Duplex (Backpressure). Full Duplex Flow Control (802.3x) Special Frame Identification Trapping.
3.13.1 3.13.2 3.13.3 3.14
Queue Management
Reference Only Allayer Communications
AL126 Revision
3.14.1 3.15 3.16 3.17 3.18
Congestion Control
Uplink Port. Port Monitoring. Media Independent Interface (MII) Management. Management Master Mode Management Slave Mode. Auto-negotiation Mode Other Options.
3.18.1 3.18.2 3.18.3 3.18.4 3.19 3.20
SGRAM Interface EEPROM Interface System Initialization Start Stop Write Cycle Timing. Read Cycle Timing Reprogramming EEPROM Configuration EEPROM
3.20.1 3.20.2 3.20.3 3.20.4 3.20.5 3.20.6 3.21
Register Descriptions
Timing Requirements. Electrical Specifications AL126 Mechanical Data. Appendix (VLAN Mapping Work Sheet) Appendix (Port Trunk Port Assignment Work Sheet) Appendix (Suggested Memory Components). Appendix (Memory Timing Requirements)
10/00
Reference Only Allayer Communications
AL126 Revision
AL126 Overview
AL126 eight-port 10/100 Ethernet switch chip with RoX-II expansion interface. RoX-IIinterface Gbit/s data ring (6.4 Gbit/s full-duplex) control ring interfaces. RoX-II support four switch chips management device (AL300A) router (AL3000) chip. Various combinations used different configurations. maximum port configuration will 32-port Mbit/s ports 24-port 10/100 Mbit/s plus Gigabit Ethernet ports, eight Gigabit ports. RoX-II interface supports management device, AL300A. SNMP RMON supported through this management device. following diagram shows 24+2G managed L3/4 router switch supported AL126, AL1022, AL300A.
Memory
32-bit Microprocessor
Ring
AL300A
AL126
AL126
AL126
AL1022
Figure
24+2G Managed Routing Switch
10/00
Reference Only Allayer Communications
AL126 Revision
AL126 provides eight 10/100 Mbit/s Ethernet ports with each port supporting both Mbit/s data rate. operation mode auto-negotiated through PHY. AL126 also supports trunking applications. chip provides optional load balancing schemes, explicit dynamic. With trunking, possible group eight full-duplex links together form single 1600-Mb link. device also supports current IEEE 802.3ad specification. Data received from interface stored external memory buffer. AL126 utilizes cost effective SGRAM provide 8-Mb 16-Mb buffer memory. AL126 provides flow control methods. half-duplex operations, optional jamming based flow control (also known backpressure) available prevent loss data. With this method flow control, switch will generate signal when receive-buffer full. full-duplex mode, AL126 utilizes IEEE 802.3x flow control mechanism. ports support multiple addresses. switch chip supports addresses with VLAN without VLAN through external SSRAM. managed switch applications, AL126 supports network management through network management option. When management option enabled, network statistics each port gathered sent across RoX-II bus. management information base chip will collect store data network management agent. Access statistic counters provided interface AL300A. AL126 operates only store forward mode. entire frame checked errors frames with errors automatically filtered forwarded destination port. device also provides multicast group addresses multicast applications. AL126 perform IGMP frame trapping forward them CPU. This allows participate IGMP protocol determine which ports should participate multicast session. switch initialized configured external EEPROM. unmanaged switch design, there need CPU. parallel interface utilized reprogram EEPROM field reconfiguration. device supports port-based tagged VLAN (IEEE 802.3ac/802.1q VLAN) workgroup segment switching applications. AL126 supports 802.1p with four levels priority queues. Relative priority controlled either programmable Weighted Round-Robin Strict Priority. device also provides levels security intrusion protection. Security implemented per-port basis. Other features include port monitoring broadcast storm filtering reduce broadcast traffic through switch.
10/00
Reference Only Allayer Communications
AL126 Revision
Diagram
Figure
AL126 Diagram (Top View)
10/00
Reference Only Allayer Communications
10/00 Reference Only Allayer Communications
Figure AL126 Lay-out
PBANC_8
VDD33
PBCS#
SYSCLK
PBA4
PBA8_9
ETD6
ETD2
ETA14
VDD33
PBD6
VDD33
PBD21
PBD9
PBD13
PBD27
PBD31
M7RXD1
M7RXDV
M7TXCLK
M7TXEN
M7TXD0
RICLK
EECLK
PBCAS#
VDD33
PBA1
PBA5
ETD9
ETD5
ETD1
PBD0
PBD3
PBD7
PBD18
PBD22
PBD10
VDD25
PBD24
PBD28
TRST#
M7RXD2
M7RXCLK
VDD33
M7TXD1
M0COL
EEDIO
PBWE#
PBRAS#
PBA2
PBA6
ETD8
ETD4
ETD0
PBD1
PBD4
PBD16
PBD19
PBD23
PBD11
PBD14
PBD25
PBD29
TCLK
VDD25
M7RXER
M7CRS
M7TXD3
M7TXD2
M0TXD2
M0TXD3
M0CRS
PBA9_10
PBA3
PBA7
ETD7
ETD3
ETA15
PBD2
PBD5
PBD17
PBD20
PBD8
PBD12
PBD15
PBD26
PBD30
M7RXD0
M7RXD3
ETA0
M7COL
M0TXEN
M0TXD0
M0TXD1
PBA0
VDD33
VDD25
VDD25
VDD33
VDD33
VDD33
VDD33
ETA4
ETA3
ETA2
ETA1
M0RXDV
M0RXCLK
M0RXER
M0TXCLK
VDD33
ETA8
ETA7
ETA6
ETA5
M0RXD0
M0RXD1
M0RXD2
M0RXD3
VDD33
ETA12
ETA11
ETA10
ETA9
AL126 View
DTOEB ETADSC# ETADV# VDD33 VDD33 ROD31 PBCLKI TEST0 ETA13 ETD11 ETD10 ETGW# ETCLKI ROD27 ROD28 ROD29 ROD30
ETD15
ETD14
ETD13
ETD12
ROCLK
ROD23
ROD24
ROD25
ROD26
RID28
RID29
RID30
RID31
VSS*
VSS*
VSS*
VSS*
VSS*
VSS*
VDD33
ROD19
ROD20
ROD21
ROD22
RID24
RID25
RID26
RID27
VDD33
VSS*
VSS*
VSS*
VSS*
VSS*
VSS*
VDD25
M6RXD3
M6RXD2
M6RXD1
M6RXD0
RID20
RID21
RID22
RID23
VSS*
VSS*
VSS*
VSS*
VSS*
VSS*
VDD33
M6TXCLK
M6RXER
R6RXCLK
M6RXDV
M1TXD3
M1CRS
ENBQ
M1COL
VSS*
VSS*
VSS*
VSS*
VSS*
VSS*
M6TXD2
M6TXD1
M6TXD0
M6TXEN
M1TXEN
M1TXD0
M1TXD1
M1TXD2
VSS*
VSS*
VSS*
VSS*
VSS*
VSS*
M6COL
M6CRS
M6TXD3
M1RXDV
M1RXCLK
M1RXER
M1TXCLK
VDD33
VSS*
VSS*
VSS*
VSS*
VSS*
VSS*
ROD15
ROD16
ROD17
ROD18
M1RXD0
M1RXD1
M1RXD2
M1RXD3
VDD25
ROD11
ROD12
ROD13
ROD14
RID16
RID17
RID18
RID19
VDD33
These pins should connected plane heat dissipation purpose.
ROD7
ROD8
ROD9
ROD10
RID12
RID13
RID14
RID15
VDD33
ROD3
ROD4
ROD5
ROD6
RID8
RID9
RID10
RID11
VDD33
M5RXD3
M5RXD2
M5RXD1
M5RXD0
RID4
RID5
RID6
RID7
VDD33
VDD33
M5TXCLK
M5RXER
M5RXCLK
M5RXDV
M2TXD3
M2CRS
M2COL
VDD33
VDD33
VDD25
VDD33
VDD25
VDD33
VDD33
M5TXD1
M5TXD0
M5TXEN
M2TXD0
M2TXD1
M2TXD2
RID2
RICTL7
RICTL3
RI3CTL1
RI2CTL3
M3COL
M3TXD2
M3TXCLK
M3RXD3
M4COL
M4TXD2
M4TXCLK
M4RXD3
RESET#
RO2CTL0
RO2CTL4
ROCTL0
ROCTL3
M5CRS
M5TXD3
M5TXD2
M2TXCLK
VDD33
M2TXEN
M2RXD1
RID1
RICTL6
RICTL2
RI3CTL0
RI2CTL2
MDIO
RICTLH
M3TXD1
M3RXER
M3RXD2
M4TXD1
M4RXER
M4RXD2
TESTMODE
RO2CTL1
RO2CTL5
ROCTL1
ROCTL4
ROCTL7
M5COL
M2RXCLK
M2RXER
VDD25
M2RXD0
RID0
RICTL5
RICTL1
RI2CTL5
RI2CTL1
DEVID1
M3CRS
M3TXD0
M3RXCLK
M3RXD1
M4CRS
M4TXD0
M4RXCLK
M4RXD1
EPBYPASS
RO2CTL2
RO3CTL0
ROCTLH
ROCTL5
RODH
ROD0
AL126 Revision
M2RXDV
M2RXD3
M2RXD2
RID3
RIDH
RICTL4
RICTL0
RI2CTL4
RI2CTL0
DEVID0
M3TXD3
M3TXEN
M3RXDV
M3RXD0
M4TXD3
M4TXEN
M4RXDV
M4RXD0
VDD33
RO2CTL3
RO3CTL1
ROCTL2
ROCTL6
ROD1
ROD2
AL126 Revision
Descriptions
AL126 supports MII/RMII interface. Ports through globally programmed RMII, Port independently programmable RMII. When RMII interface used; TXD3 TXD2 should left unconnected; RXD3, RXD2, TXCLK, RXDV, RXER, left unconnected because they have internal pull ups. RXCLK0 RXCLK3 should connected reference clock. date control signals clocked in/out rising edge reference clock RMII mode.
Table RMII/MII Interface (Port
NAME M0TXD3 M0TXD2 M0TXD1 M0TXD0 DESCRIPTION Transmit Data data transmitted transceiver. mode, signal M0TXEN M0TXD0 through M0TXD3 clocked rising edge M0TXCLK. RMII mode, M0TXD1 M0TXD0 clocked RMII reference clock M0RXCLK. During reset, these pins input mode read device existence information. Leave floating used. Transmit Enable Synchronous transmit clock mode. RMII mode, M0TXEN synchronous M0RXCLK. Transmit Clock Input. Mbit/s Mbit/s. (Not used RMII mode). Receive Data data from transceiver. mode, signal M0RXDV, M0RXER M0RXD0 through RXD3 sampled rising edge M0RXCLK. RMII mode, M0RXD3 M0RXD2 used. M0RXD1and M0RXD0 sampled rising edge RMII reference clock M0RXCLK. Receive Data Valid. Active high. Receive Clock (MII mode). RMII clock port Receive Data Error. Active high. (Not used RMII mode). Carrier Sense. Active high. Collision Detect. Active high. (Not used RMII mode).
M0TXEN
M0TXCLK M0RXD3 M0RXD2 M0RXD1 M0RXD0
M0RXDV M0RXCLK M0RXER M0CRS M0COL
10/00
Reference Only Allayer Communications
AL126 Revision
Table RMII/MII Interface (Port
NAME M1TXD3 M1TXD2 M1TXD1 M1TXD0 DESCRIPTION Transmit Data data transmitted transceiver. mode, signal M1TXEN TXD0 through M1TXD3 clocked rising edge TXCLK. RMII mode, M1TXD1 M1TXD0 clocked RMII reference clock M3RXCLK. Transmit Enable Synchronous transmit clock mode. RMII mode, M1TXEN synchronous M3RXCLK. Transmit Clock Input. Mbit/s Mbit/s. (Not used RMII mode). Receive Data data from transceiver. mode, signal M1RXDV, M1RXER M1RXD0 through M1RXD3 sampled rising edge M1RXCLK. RMII mode, M1RXD3 M1RXD2 used. M1RXD1and M1RXD0 sampled rising edge RMII reference clock M3RXCLK. Receive Data Valid. Active high. Receive Clock (MII mode). Receive Data Error. Active high. (Not used RMII mode). Carrier Sense. Active high. Collision Detect. Active high. (Not used RMII mode).
M1TXEN
M1TXCLK M1RXD3 M1RXD2 M1RXD1 M1RXD0
M1RXDV M1RXCLK M1RXER M1CRS M1COL
10/00
Reference Only Allayer Communications
AL126 Revision
Table RMII/MII Interface (Port
NAME M2TXD3 M2TXD2 M2TXD1 M2TXD0 DESCRIPTION Transmit Data data transmitted transceiver. mode, signal M2TXEN M2TXD0 through M2TXD3 clocked rising edge TXCLK. RMII mode, M2TXD1 M2TXD0 clocked RMII reference clock M3RXCLK. Transmit Enable Synchronous transmit clock mode. RMII mode, M2TXEN synchronous M3RXCLK. Transmit Clock Input. Mbit/s Mbit/s. (Not used RMII mode). Receive Data data from transceiver. mode, signal M2RXDV, M2RXER M2RXD0 through M2RXD3 sampled rising edge M3RXCLK. RMII mode, M2RXD3 M2RXD2 used. M2RXD1and M2RXD0 sampled rising edge RMII reference clock M3RXCLK. Receive Data Valid. Active high. Receive Clock (MII mode). Receive Data Error. Active high. (Not used RMII mode). Carrier Sense. Active high. Collision Detect. Active high. (Not used RMII mode).
M2TXEN
M2TXCLK M2RXD3 M2RXD2 M2RXD1 M2RXD0
M2RXDV M2RXCLK M2RXER M2CRS M2COL
10/00
Reference Only Allayer Communications
AL126 Revision
Table RMII/MII Interface (Port
NAME M3TXD3 M3TXD2 M3TXD1 M3TXD0 AF11 AC12 AD12 AE12 DESCRIPTION Transmit Data data transmitted transceiver. mode, signal M3TXEN M3TXD0 through M3TXD3 clocked rising edge TXCLK. RMII mode, M3TXD1 M3TXD0 clocked RMII reference clock M3RXCLK. Transmit Enable Synchronous transmit clock mode. RMII mode, M3TXEN synchronous M3RXCLK. Transmit Clock Input. Mbit/s Mbit/s. (Not used RMII mode). Receive Data data from transceiver. mode, signal M3RXDV, M3RXER RXD0 through RXD3 sampled rising edge M3RXCLK. RMII mode, M3RXD3 M3RXD2 used. M3RXD1and M3RXD0 sampled rising edge RMII reference clock M3RXCLK. Receive Data Valid. Active high. Receive Clock (MII mode). RMII clock ports 1~7. Receive Data Error. Active high. (Not used RMII mode). Carrier Sense. Active high. Collision Detect. Active high. (Not used RMII mode).
M3TXEN
AF12
M3TXCLK M3RXD3 M3RXD2 M3RXD1 M3RXD0
AC13 AC14 AD14 AE14 AF14
M3RXDV M3RXCLK M3RXER M3CRS M3COL
AF13 AE13 AD13 AE11 AC11
10/00
Reference Only Allayer Communications
AL126 Revision
Table RMII/MII Interface (Port
NAME M4TXD3 M4TXD2 M4TXD1 M4TXD0 AF15 AC16 AD16 AE16 DESCRIPTION Transmit Data data transmitted transceiver. mode, signal M4TXEN M4TXD0 through M4TXD3 clocked rising edge TXCLK. RMII mode, M4TXD1 M4TXD0 clocked RMII reference clock M3RXCLK. Transmit Enable Synchronous transmit clock mode. RMII mode, M4TXEN synchronous M3RXCLK. Transmit Clock Input. Mbit/s Mbit/s. (Not used RMII mode). Receive Data data from transceiver. mode, signal RX_DV, RX_ER RX_D0 through RX_D3 sampled rising edge M3RXCLK. RMII mode, M4RXD3 M4RXD2 used. M4RXD1and M4RXD0 sampled rising edge RMII reference clock M3RXCLK. Receive Data Valid. Active high. Receive Clock (MII mode). Receive Data Error. Active high. (Not used RMII mode). Carrier Sense. Active high. Collision Detect. Active high. (Not used RMII mode).
M4TXEN
AF16
M4TXCLK M4RXD3 M4RXD2 M4RXD1 M4RXD0
AC17 AC18 AD18 AE18 AF18
M4RXDV M4RXCLK M4RXER M4CRS M4COL
AF17 AE17 AD17 AE15 AC15
10/00
Reference Only Allayer Communications
AL126 Revision
Table RMII/MII Interface (Port
NAME M5TXD3 M5TXD2 M5TXD1 M5TXD0 AC25 AC26 AB24 AB25 DESCRIPTION Transmit Data data transmitted transceiver. mode, signal M5TXEN M5TXD0 through M5TXD3 clocked rising edge TXCLK. RMII mode, M5TXD1 M5TXD0 clocked RMII reference clock M3RXCLK. Transmit Enable Synchronous transmit clock mode. RMII mode, M5TXEN synchronous M3RXCLK. Transmit Clock Input. Mbit/s Mbit/s. (Not used RMII mode). Receive Data data from transceiver. mode, signal M5RXDV, M5RXER M5RXD0 through M5RXD3 sampled rising edge M3RXCLK. RMII mode, M5RXD3 M5RXD2 used. M5RXD1and M5RXD0 sampled rising edge RMII reference clock M3RXCLK. Receive Data Valid. Active high. Receive Clock (MII mode). Receive Data Error. Active high. (Not used RMII mode). Carrier Sense. Active high. Collision Detect. Active high. (Not used RMII mode).
M5TXEN
AB26
M5TXCLK M5RXD3 M5RXD2 M5RXD1 M5RXD0
AA23
M5RXDV M5RXCLK M5RXER M5CRS M5COL
AA26 AA25 AA24 AC24 AD25
10/00
Reference Only Allayer Communications
AL126 Revision
Table RMII/MII Interface (Port
NAME M6TXD3 M6TXD2 M6TXD1 M6TXD0 DESCRIPTION Transmit Data data transmitted transceiver. mode, signal M6TXEN M6TXD0 through M6TXD3 clocked rising edge TXCLK. RMII mode, M6TXD1 M6TXD0 clocked RMII reference clock M3RXCLK. Transmit Enable Synchronous transmit clock mode. RMII mode, M6TXEN synchronous M3RXCLK. Transmit Clock Input. Mbit/s Mbit/s. (Not used RMII mode). Receive Data data from transceiver. mode, signal M6RXDV, M6RXER M6RXD0 through M6RXD3 sampled rising edge M3RXCLK. RMII mode, M6RXD3 M6RXD2 used. M6RXD1and M6RXD0 sampled rising edge RMII reference clock M3RXCLK. Receive Data Valid. Active high. Receive Clock (MII mode). Receive Data Error. Active high. (Not used RMII mode). Carrier Sense. Active high. Collision Detect. Active high. (Not used RMII mode).
M6TXEN
M6TXCLK M6RXD3 M6RXD2 M6RXD1 M6RXD0
M6RXDV M6RXCLK M6RXER M6CRS M6COL
10/00
Reference Only Allayer Communications
AL126 Revision
Table RMII/MII Interface (Port
NAME M7TXD3 M7TXD2 M7TXD1 M7TXD0 DESCRIPTION Transmit Data data transmitted transceiver. mode, signal M7TXEN M7TXD0 through M7TXD3 clocked rising edge TXCLK. RMII mode, M7TXD1 M7TXD0 clocked RMII reference clock M3RXCLK. Transmit Enable Synchronous transmit clock mode. RMII mode, M7TXEN synchronous M3RXCLK. Transmit Clock Input. Mbit/s Mbit/s. (Not used RMII mode). Receive Data data from transceiver. mode, signal M7RXDV, M7RXER M7RXD0 through M7RXD3 sampled rising edge M3RXCLK. RMII mode, M7RXD3 M7RXD2 used. M7RXD1and M7RXD0 sampled rising edge RMII reference clock M3RXCLK. Receive Data Valid. Active high. Receive Clock (MII mode). Receive Data Error. Active high. (Not used RMII mode). Carrier Sense. Active high. Collision Detect. Active high. (Not used RMII mode).
M7TXEN
M7TXCLK M7RXD3 M7RXD2 M7RXD1 M7RXD0
M7RXDV M7RXCLK M7RXER M7CRS M7COL
10/00
Reference Only Allayer Communications
AL126 Revision
Table RoX-II Input Interface
NAME RID31 RID30 RID29 RID28 RID27 RID26 RID25 RID24 RID23 RID22 RID21 RID20 RID19 RID18 RID17 RID16 RID15 RID14 RID13 RID12 RID11 RID10 RID9 RID8 RID7 RID6 RID5 RID4 RID3 RID2 RID1 RID0 RIDH RICTL7 RICTL6 RICTL5 RICTL4 RICTL3 RICTL2 RICTL1 RICTL0 RICTLH AD11 DESCRIPTION
Ring Data Input.
Ring Data Header Input. High duration data, when idle. Ring Control Input.
Ring Control Header Input. Low/high each part control data word, high when idle.
10/00
Reference Only Allayer Communications
AL126 Revision
Table RoX-II Input Interface (Continued)
NAME RICLK RI2CTL5 RI2CTL4 RI2CTL3 RI2CTL2 RI2CTL1 RI2CTL0 RI3CTL1 RI3CTL0 DESCRIPTION Ring Clock. RICTL clocked rising edge RICLK. Second Ring Control Input.
Reserved Future Use.
10/00
Reference Only Allayer Communications
AL126 Revision
Table RoX-II Output Interface
NAME ROD31 ROD30 ROD29 ROD28 ROD27 ROD26 ROD25 ROD24 ROD23 ROD22 ROD21 ROD20 ROD19 ROD18 ROD17 ROD16 ROD15 ROD14 ROD13 ROD12 ROD11 ROD10 ROD9 ROD8 ROD7 ROD6 ROD5 ROD4 ROD3 ROD2 ROD1 ROD0 RODH ROCTL7 ROCTL6 ROCTL5 ROCTL4 ROCTL3 ROCTL2 ROCTL1 ROCTL0 ROCTLH AF26 AF25 AE25 AE24 AD24 AF23 AE23 AD23 AC23 AF22 AD22 AC22 AE22 DESCRIPTION
Ring Data Output.
Ring Data Header Output. High duration data, when idle. Ring Control Output.
Ring Control Header Output. Low/high each part control data word, keep high when idle.
10/00
Reference Only Allayer Communications
AL126 Revision
Table RoX-II Output Interface (Continued)
ROCLK Ring Clock. ROCTL clocked rising edge SYSCLK. ROCLK delayed version SYSCLK drive RICLK next device. Second Ring Control Output.
RO2CTL5 RO2CTL4 RO2CTL3 RO2CTL2 RO2CTL1 RO2CTL0 RO3CTL1 RO3CTL0
AD21 AC21 AF20 AE20 AD20 AC20 AF21 AE21
Reserved Future Use.
10/00
Reference Only Allayer Communications
AL126 Revision
Table SGRAM Interface
NAME PBD31 PBD30 PBD29 PBD28 PBD27 PBD26 PBD25 PBD24 PBD23 PBD22 PBD21 PBD20 PBD19 PBD18 PBD17 PBD16 PBD15 PBD14 PBD13 PBD12 PBD11 PBD10 PBD9 PBD8 PBD7 PBD6 PBD5 PBD4 PBD3 PBD2 PBD1 PBD0 PBA9_10 DESCRIPTION
SGRAM Data Bus.
This connected address when connected Mbit SGRAM address when connected Mbit SGRAM. This should connected SGRAMs. This connected address when connected Mbit SGRAM address when connected Mbit SGRAM. This should connected SGRAMs. This connected address when connected Mbit SGRAM unconnected when connected Mbit SGRAM. This should connected SGRAMs.
PBA8_9
PBANC_8
10/00
Reference Only Allayer Communications
AL126 Revision
Table SGRAM Interface (Continued)
NAME PBA7 PBA6 PBA5 PBA4 PBA3 PBA2 PBA1 PBA0 PBCS# PBRAS# PBCAS# PBWE# PBCLK DESCRIPTION These pins connected SGRAM address through respectively.
Chip Select. enables disables command decoder SGRAM. SGRAM Address Strobe. SGRAM Column Address Strobe. Write Enable. System Clock Output Drive SGRAM.
Table External Address Table SSRAM Interface
NAME ETD15 ETD14 ETD13 ETD12 ETD11 ETD10 ETD9 ETD8 ETD7 ETD6 ETD5 ETD4 ETD3 ETD2 ETD1 ETD0 DESCRIPTION
SSRAM Data Bus.
10/00
Reference Only Allayer Communications
AL126 Revision
Table External Address Table SSRAM Interface (Continued)
NAME ETA15 ETA14 ETA13 ETA12 ETA11 ETA10 ETA9 ETA8 ETA7 ETA6 ETA5 ETA4 ETA3 ETA2 ETA1 ETA0 ETADSC# ETADV# ETGW# ETOE# ETCLK DESCRIPTION
SSRAM Address Line.
Synchronous Address Status Controller. Synchronous Address Advance. Used advance SRAMs internal burst counter. Global Write. Enables full 32-bit write. Output Enable. Active low. This enables output driver. System Clock Output Drive SSRAM.
Table EEPROM Interface
NAME EEDIO NUMBER DESCRIPTION EEPROM Data Input Output boot-up. Data input output reverse EEDIO. Tri-stated after boot-up, external pull-up. EEPROM Clock Output boot-up. Clock input reverse EEDIO. Tri-stated after boot-up, external pull-up.
EECLK
10/00
Reference Only Allayer Communications
AL126 Revision
Table MDIO Interface
NAME MDIO NUMBER AC10 AD10 DESCRIPTION Management Clock. Management Data Input Output.
Table Miscellaneous Pins
NAME DEVID1 DEVID0 NUMBER AE10 AF10 DESCRIPTION Device Number. Should connected EEPROM AL126 will ID1, ID0> EEPROM address respond ID1, ID0> reverse EEDIO. Reset Test Mode Pin. This should grounded normal operation. Status Serial Output (for testing). This bypasses EEPROM setup. This should tied ground. System Clock. Enable 802.1q VLAN. Reserved Test Output. Leave unconnected. Reserved JTAG Scan. Testing output. Leave unconnected. Reserved JTAG Scan. Testing output. Leave unconnected. Reserved JTAG Scan. Testing output. Leave unconnected. Reserved JTAG Scan. Testing output. Leave unconnected. Reserved JTAG Scan. Testing output. Leave unconnected.
RESET# TESTMODE EPBYPASS SYSCLK ENBQ TEST0 TRST TCLK
AC19 AD19 AE19
10/00
Reference Only Allayer Communications
AL126 Revision
Table Power Interface
NAME VDD1 VDD2 NUMBER B17, C22, E10, M22, AB14, AB18, A12, A14, B24, E15, E19, E21, E22, H22, L22, N22, W22, Y22, AA5, AA22, AB7, AB13, AB17, AB21, AB22, AD2, AF19 A18, B21, B25, D24, D26, E11, E12, E13, E14, E16, E17, E18, E20, F22, G22, J22, L11, L12, L13, L14, L15, L16, M11, M12, M13, M14, M15, M16, N11, N12, N13, N14, N15, N16, P11, P12, P13, P14, P15, P16, P22, R11, R12, R13, R14, R15, R16, R22, R24, T11, T12, T13, T14, T15, T16, T22, U22, V22, AB3, AB5, AB6, AB8, AB9, AB10, AB11, AB12, AB15, AB16, AB19, AB20, AB23, AC3, AD15, AD26, AE26, AF24 DESCRIPTION Supply Voltage. Supply Voltage. Ground
10/00
Reference Only Allayer Communications
AL126 Revision
Functional Description
RoX-II Interface
switch system 24-port 10/100 Mbit/s switch with Gigabit Ethernet ports. This system utilizes Allayer's proprietary RoX-II architecture, which improved version original RoX-I Ring structure. RoX-II higher bandwidth built-in Layer capabilities. RoX-II Ring composed data ring control ring. data ring used transfer frame data, events, well system configuration status report messages. control ring used communicate RoX-II Ring protocol messages among devices switch backbone resources data transfer data ring. Each device ring input interface receiving data frames ring protocol messages from upstream device, output interface transmitting data frames ring protocol messages downstream device. management device (MIB) AL300A, resides RoX-II ring. provides network management functions devices ring. device collects network statistics switch system well provides system configuration devices. interface provided device. This supporting chip, AL300A, provides full statistical counters support both SNMP RMON network management.
Data Reception
port will into receive-state when RX_DV interface asserted. presents received data four-bit nibbles that synchronous receive clock MHz). AL126 will then attempt detect occurrence Start Frame Delimiter, (SFD 10101011), pattern. preamble data prior discarded. Once detected, Frame Check Sequence (FCS) verified, frame data forwarded stored buffer switch. 3.2.1 Illegal Frame Length During receiving process, will monitor length received frame. Legal Ethernet frames should have length less than bytes more than 1548 bytes. frames with illegal frame length discarded. 3.2.2 Long Frames AL126 handle frames 1548 bytes. frames longer than 1548 bytes will discarded. port continues receive data after 1548th byte, port's data will filtered. port half-duplex mode, port will longer able transmit receive data during long frame reception. 3.2.3 False Carrier Events Carrier Sense Signal (CRS) interface asserted receive data valid (RX_DV) signal asserted within bit-time (BT), port considered have false carrier event. false carrier event recorded counter.
10/00
Reference Only Allayer Communications
AL126 Revision
3.2.4 Frame Filtering AL126 will make filtering forwarding decisions each frame received, based frame routing table, VLAN mapping, port state, system configuration. Under following conditions, received frames filtered. AL126 will check received frames errors such symbol error, error, short event, runt, long event, etc. Frames with kind error will forwarded their destination port. frame heading source port will filtered. Frames heading disabled receiving port will filtered. input buffer port full, incoming frame will discarded. recommended that flow control used prevent loss data. flow control option enabled, this event will occur. remote station will transmit frames when input buffer becomes available. frame security violation, while security option enabled receiving port. Spanning Tree Protocol enabled, AL126 will forward frame below. port Block-N-Listen state Learning state, frame forwarded when BPDU frame, frame discarded otherwise. port Forwarding State, frame forwarded when BPDU frame.
Frame Forwarding
After frame received, Source Address (SA) Destination Address (DA) retrieved. used update port's address table described previously used determine frame's destination port. Address Lookup Engine will attempt match destination address with addresses stored address table. there match found, link between source port destination port then established. first destination address "0," frame regarded unicast frame. destination address passed Address Lookup Engine which returns matched destination port number identify which port frame should forwarded destination port within same VLAN receiving port, frame will forwarded. frame tagged with IEEE 802.3ac IEEE 802.1q VLAN tag, AL126 programmed support tagged VLAN, then tagged VLAN membership looked from VLAN table. destination port does belong VLANs specified receiving port, frame will discarded. event will recorded VLAN boundary violation. particular VLAN (whether port-based tagged) null membership, frames discarded well. There ways that AL126 handles frames with unknown destination. forwarding decision controlled Flood Control Option (System Configuration Register 00). Flood Control disabled, frame will forwarded ports (except receiving port) within
10/00
Reference Only Allayer Communications
AL126 Revision
same VLAN receiving port. Flood Control Option enabled, AL126 will forward frame only uplink port specified receiving port. Note: AL126 defines port either single port trunk, consistent with IEEE 802.3ad Port Aggregation Standard. port monitoring function enabled, frame forwarding decision also subject port monitoring configurations. first destination address "1," frame will handled multicast broadcast frame. AL126 does differentiate multicast frames from broadcast frames, except with following reserved bridge management group addresses, specified table IEEE 802.1d standard; GARP, IGMP, IEEE 802.3ad Port Aggregation control frames. Additionally, IEEE 802.3x Flow Control frames handled inside AL126 never forwarded other device, including CPU. destination ports broadcast frame ports within same VLAN except source port itself. Multicast/Broadcast frame trapping (MCtrap) enabled, multicast/broadcast frames will forwarded only. 3.3.1 Broadcast Storm Control unique features provided AL126 Broadcast Storm Control. This option allows user limit number broadcast frames into switch. This option implemented per-port basis. threshold number broadcast frames programmed System Configuration Register, Register MaxStorm. When Storm Control enabled number cumulated non-unicast frames over programmed threshold, broadcast frame discarded. Storm Control disabled number non-unicast frames received port over programmed threshold, AL126 will forward frame ports (except receiving port) within VLANs specified receiving port. port within specified VLAN, frame will also forwarded CPU. Broadcast-Storm-drop (System Configuration Register III, Register FlowCtrlBC) enabled, AL126 only drops broadcast frames, multicast frames. 3.3.2 Frame Transmission AL126 transmits frames accordance with IEEE 802.3 standard. AL126 sends frames with guaranteed minimum inter-packet (frame) (IPG) 96BT, even when received frames have less than minimum requirement. AL126 also supports transmission frames with 64BT (set System Configuration Register III, Register SIPG64). 3.3.3 Preamble Regeneration During transmit process, frame data read from memory buffer forwarded destination port's device nibbles. Seven bytes preamble signal (10101010) will generated first before (10101011) frame data sent, which then followed four bytes FCS. frame sourced from management engine (AL300A), frame modified VLAN tag/untag operation, calculated sent.
10/00
Reference Only Allayer Communications
AL126 Revision
Summary Programmable Control Transmit Receive control transmit receive per-port basis. options programmable Port Configuration Register (registers 1C). Data Rate Duplex Mode this option per-port option. Typically, data rate duplex mode auto-negotiated. override these modes, MDIOCfg[3:0] bits forced-mode (^b0111), PrtCfgMode desired setting. Flow Control flow control option selected full-duplex halfduplex operations separately. AL126 uses backpressure (either collision carrier based) half-duplex flow control IEEE 802.3x full-duplex flow control.
Half Duplex Mode Operation
true CSMA/CD (half-duplex) operation, logic will abort transmit-process collision detected through assertion collision (COL) signal MII. Re-transmission frame scheduled accordance IEEE 802.3's truncated binary exponential backoff algorithm. transmit process encountered consecutive collisions, excessive collision error reported, resulting frame dropped unless retry-on-excessive-collision (UltraMAC) option enabled. AL126 provides non-standard options collision handling. SuperMAC mode Register System Configuration Register provides more aggressive back-off where back-off limit three rather than ten. This will create more aggressive channel capture behavior than standard IEEE back-off algorithm. There well-known anomaly channel capture effect, where top-talker CSMA/CD (halfduplex operation) network capture significant percentage available bandwidth. This better known "channel-capture" effect. AL126 provides non-standard mode Binary Exponential Backoff Select (BebSel, System Configuration Register III, that uses binary back-off algorithm rather than standard exponential back-off algorithm reduce this channelcapture effect. Please refer Flow Control section this data sheet backpressure option half-duplex mode operation.
10/00
Reference Only Allayer Communications
AL126 Revision
Secure Mode Operation
AL126 provides security support per-port basis. Whenever secure mode enabled, (Security mode, Register through Port Configuration Register port will stop learning addresses address table each port will remain unchanged (i.e. frame aging function, enabled, address learning function, disabled). AL126 provides levels security protection. most severe intrusion protection disabling port experiencing intrusion. AutoSec mode, Register System Configuration Register when enabled, disables port frame with unlearned received secured port (security violation). Once port disabled, only enabled network management. Security management global option. alternative enable security local port level without security management. When AL126 configured this way, device will only discard frames that have security violations which will prevent intruders from accessing network. Summary Programmable Registers AutoSec (register this sets global security management option. AL126 will partition port that experiences security violation. Security (register this port configuration option. When this option enabled, port secured. When port receives security violation frame will discard frame disable port security management
Address Learning
table lookup engine provides switching information required route data frames. address lookup table through auto address learning (dynamic) manual entry (static). static addresses assigned address table EEPROM management device. static address entries will aged updated AL126. After frame received AL126, embedded source address (SA) destination addresses (DA) retrieved. source address retrieved from received frame automatically stored buffer. AL126 will then check errors security violations, perform search. there error security violation, chip will store source address address lookup table. been previously stored another port's table, AL126 will delete from previously stored location. Individual Address 48-bit unique address programmed learned. will masked, i.e. multicast AL126 provides on-chip Address-To-PortID/TrunkID table with entries frame destination lookup operations. Optional external SRAM used increase number address lookups 16K. (Note: When 802.1q VLAN support enabled QEnable mode, number internal address support reduced 0.5K, external table reduced 12K). AL126 address table contains both static addresses input EEPROM dynamically learned addresses. learns individual addresses from three different sources. Frames received with errors from local ports.
10/00
Reference Only Allayer Communications
AL126 Revision
Frames forwarded from other devices through ring device. Address Table Convergence message received from other switching devices ring. (TCNVG mode, Register System Configuration Register controls this function. IEEE 802.1d compliance, this mode should enabled). received frame contains source address that already been learned another port's address table aged (e.g. station moved from port another port switch), will perform following operation based switch's configuration. security option selected port, AL126 will consider this security violation. port non-protected port, AL126 will delete from previous port's address table update current port's address table. However, static address entry, address will updated.
3.6.1 Address Aging port's address register cleared power-up, hardware reset. aging option enabled, dynamically learned will cleared refreshed less than programmed time. AL126 address aging enabled AgeEN, (Register System Configuration Register, 12). Summary Programmable Options Address Learning Address Aging Time address aging aging time programmed System Configuration (MaxAge, bits 15~9, register 01). resolution normal address aging 5.36 seconds seconds with system clock. SlowAge (register programmed "1," resolution 10.72 seconds 13.4 seconds with system clock. Static Programmed Addresses twenty static addresses programmed EEPROM address Further static addresses programmed AL300A management engine. EEPROM section this document, AL300A data sheet more detail.
10/00
Reference Only Allayer Communications
AL126 Revision
VLAN Support
AL126 supports both Port Based VLAN, where VLAN membership determined port assignment, IEEE 802.1q (and IEEE 802.3ac) Tagged VLAN, where VLAN membership determined dynamically VLAN VID) embedded Tag. IEEE 802.1q tagged VLAN mode enabled QEnable (Register System Configuration IV). 3.7.1 Port Based VLAN Each port AL126 assigned multiple VLANs. Frames from source port will only forwarded destination ports within same VLAN domain. broadcast/multicast frame will forwarded ports within VLAN(s) source port except source port itself. unicast frame will forwarded destination port only destination port same VLAN source port. destination port belongs another VLAN, frame will discarded event will recorded VLAN boundary violation. Each port should assigned with dedicated uplink port. Unicast frames with unknown destination addresses will forwarded uplink port source port. uplink port either single port trunk. AL126 provides VLAN register ports (register mapping ports (32-bits). Each register contains 16-bits (total 32-bits) indicate VLAN group port. VLAN registers hold broadcast destination mask each source port. will indicate broadcast frames will forwarded from source port specified port. Note that source port must within source port VLAN, because broadcast frames must forwarded source port. trunked ports (aggregated group) must belong same VLAN. setting VLAN trunking, please section trunking detail. Port VLAN Example VLAN worksheet provided Appendix Simply marking ports wish send broadcast frame complete VLAN easily. Let's assume want VLAN groups sixteen port switch. Group consists 8,10, Group consists Note: might easier mark VLAN ports first then delete source ports that don't want broadcast frames returned 3.7.2 Tagged VLAN While port-based VLAN widely used industry, there standard that governs implementation. IEEE 802.1q/802.3ac standard specifies tag-based VLAN. AL126 also supports this standard compliant tag-based VLAN. AL126 supports full (VLAN Identification) tag, eight user priority values tag, preserves state bit. ports membership each VLAN value
10/00
Reference Only Allayer Communications
AL126 Revision
dynamically determined received frame. frame tagged, then default VLAN received port used determine membership. Each VLAN entry consist VID, VLAN membership ports RoX-II Bus, untag behavior each port. Please refer AL300A Data Sheet more information. VLAN searches performed AL126 hardware with external SSRAM, while table entry each active pre-programmed through indirect resource access registers (register 0x43 0x47), accessible from AL300A reverse EEDIO. following table shows entry format mapping into indirect access registers.
bit) bits) IRAD4, TTTT_TTTT TTTT_TTTT TTTT_TTTT bits) IRAD3, TTTT_TTTT TTTT_TTTT TTTT_TTTT bits) IRAD2, TTTT_TTTT TTTT_TTTT TTTT_TTTT bits) IRAD1, TTTT_TTTT TTTT_TTTT TTTT_TTTT
bits) IRAD5, 0000_0000_0000 0000_0000_0001 0000_0000_0010 1111_1111_1111
Used (Priority-Only Tag)
VLAN entry, bits ("T") each physical port 32-ports) will define "action" packet with that that port. corresponding actions are: "00" drop packet, "01" pass packet without change, "10" packet tagged, then with ingress port default VID), "11" untag packet tagged, then untag). ("M") will define whether management port VLAN; will allow frame forwarding management from that VLAN, will not. tagging/untagging performed frame being sent management CPU. VLAN entries indirect resource access command, issued from AL300A management device reverse EEDIO interface. Five indirect access data registers should diagram above, IRAD[4:1] contains action bitmap device[3:0], IRAD5= 2*(zzzzzzzzzzzz)+M, where "zzzzzzzzzzzz" 12-bit management bit. Indirect access command register, IRAC, should 0x7000 VLAN table writing. IRAC should after IRAD[5:1]. reserved priority-only tagged frames, treated frame untagged VLAN membership rules (the priority field still used selecting proper priority queue). value 0FFF reserved IEEE 802.1 future use, although AL126 does treat VID=0FFF special way. default priority assigned each source port physical ports, plus management port) default incoming frames that port. lookup performed input port tag/untag operation performed output port, 32+1 default tags have programmed each AL126 device through default registers (registers 0x4E 0x6E).
10/00
Reference Only Allayer Communications
AL126 Revision
Priority Queues User Priority Support
IEEE 802.1p user priority value used queue frame particular priority queue. AL126 supports total four priority queues complete controls manage these queues. User priority value arbitrarily mapped four prioritized queues programming register Priority Queue Assignment Register. This register maps each user priority numbers four AL126 priority queues. Even with tagged VLAN mode disabled (QEnable de-asserted), user priorities field still used priority queuing. Four priority queues serviced Weighted Round-Robin Strict Priority mode. This mode controlled PQWRREn, (Register System Configuration Register III, When Strict Priority mode enabled, frames Queue serviced until queue empty, followed Queue While servicing lower priority queues, higher priority queue empty, higher priority queue serviced until empty. busy network, lower priority queues could starved. When Weighted Round-Robin mode enabled, relative priority each queue programmed Register Priority Queue Weighted Round-Robin Control Register. Each queue serviced, average, relative integer value each queue. higher value means queue serviced higher frequency than lower value queue. weight zero special meaning because queue with zero value acts lowest priority queue even with Weighted Round-Robin mode enabled. This means that other queues must empty before queue with zero weight serviced.
Buffer Management Queue Behavior
AL126 offers complete controls manage congestion real-time multimedia traffic. Each output port queue depth trigger programmable threshold, upon reaching this threshold, certain actions taken. This includes dropping frames destined congested port particular priority queue. Queue depth control port queue. These modes operation controlled register Output Queue Management Register When both Queue Port Maximum limit control enabled, then selected action taken when maximum queue depth reached. instance, Queue used voice traffic, where desirable drop voice frames rather than deliver ones sustained congestion, Queue would programmed with Q2MaxLimEn well MaxLimEn ports. Maximum queue depth programmable each queue (that used ports) Register Output Queue Management Register action taken controlled MaxDrop, Register Output Queue Management Register When MaxDrop enabled, frames dropped respective queue when MaxLim reached. When MaxDrop disabled, frames kept input buffers input port backpressures once input buffer full. AL126 also maintains dedicated multicast queue outgoing multicast frame parking. transmit frame from sources, local from another device RoX-II ring. output queue, source selected multicast queue, device will channel copy frame head multicast queue output queue transmission.
10/00
Reference Only Allayer Communications
AL126 Revision
3.10 Multicast Group Support
With management CPU, AL126 support multicast specified RFC1112. AL126 will trap IGMP (internet group management protocol) frames going CPU, will setup AL126 multicast forwarding table, based multicast group information resolved from IGMP protocol. After table initialization, AL126 will forward IPMC frames related ports only, instead ports. AL126 supports possible multicast addresses, although only active multicast groups supported simultaneously hardware. Since AL126 performs multicast search based full 48-bit address, also support private multicast groups other than standard IPMC. Both table entry multicast group bitmap entry needs AL126 initialize multicast group. entry formatted <IPMC address: 01-00-5e-xx-xxxx><IPMC index>, IPMC table entry formatted <IPMC index><Port bitmap>. It's CPU's responsibility assign maintain IPMC index. IPMC Port bitmap defined same tagged VLAN which allows IPMC used tagged VLAN environment. only "pass" "drop" bitmap non-tagged application avoid confusion. Tagged VLAN section details port bitmap definitions. Both table IPMC table indirect resource access command issued from AL300A management device reverse EEDIO interface. Setting IPMC table very similar setting VLAN tag, only IPMC index instead IRAD5 0x6800 instead 0x7000 IRAC. Setting IPMC address table exactly same setting entry, only IPMC index instead port number into IRAD1.
3.11 Trunking (Port Aggregation)
AL126 offers alternative Port Aggregation methods. Port based trunking backward compatible Allayer's RoX-I family switches (AL100 AL116 series switches) allows direct mapping ingress traffic particular port trunk (aggregation) group. Layer Trunking implementation IEEE 802.3ad Port Aggregation standard that offers enhanced automatic load balancing algorithm. These mode trunking methods mutually exclusive, selected L2Trunk, Register System Configuration Register 3.11.1 Port Based Trunking (Port Aggregation) AL126 supports trunking/port aggregation. Port aggregation trunking basically method treat multiple physical links single logical link. benefit trunking able group multiple lower speed links into higher speed link. example, four full-duplex Fast Ethernet ports Mbit/s used single 800-Mbit/s link. This very useful switch switch, switch server, switch router applications. AL126 considers trunk single port entity regardless trunk composition. four ports grouped together single trunk link port-based trunking. grouping ports trunk must from ports same device. total trunks device supported. multiple link trunk, links within trunk should have equal amount traffic order achieve maximum efficiency. requirements transmission that frames being transmitted must order. Therefore, some sort load balancing among links trunk deployed.
10/00
Reference Only Allayer Communications
AL126 Revision
3.11.1.1 Load Balancing port-based load balancing method explicit port assignment scheme. requires each individual port assigned specific link (trunk port) trunk. port assigned, frames might forwarded trunk random this could cause frames order. port-based load balancing trunk two, three, four-port trunk. During transmit, frame will forwarded from source port assigned trunk port. When frame received from trunk ports, forwarded destination port within VLAN. essence, AL126 treats trunk single port within same VLAN. traffic ports evenly distributed among trunk ports, load balancing achieved aggregate bandwidth trunk high Mbit/s (full-duplex). 3.11.1.2 Trunk Configuration Trunk group configuration accomplished through programming configuration registers. AL126 also provide capability trap IEEE 802.3ad frames allow configure aggregated links based IEEE recommended protocol exchange. 3.11.1.3 Trunk Port Assignment maximum number trunks Allayer's RoX-II architecture eight. Port Configuration Registers provide ability designate port member trunk. trunk consist four trunk ports. trunk group must consist either four ports bottom four ports. example, trunk consist either port port Each trunk port's number sequence corresponding order port devices. example, port (See Figure
AL126
Ports
Trunk Port
Trunk Port
Figure
Trunk Port Numbering
3.11.1.4 Port Based Trunk Load Balancing port-based load balancing, trunk port must assigned each port defined trunks. port assignment done programming Port Trunk Port Registers 34). port assignment worksheet provided Appendix recommended that ports evenly distributed among trunk ports prevent overloading single trunk port. following procedure trunk.
10/00
Reference Only Allayer Communications
AL126 Revision
Select trunk ports using Port Configuration Registers Assign ports Trunk Port Register 36). port should assigned appropriate trunk using this register. trunk port itself, port assignment should assigned itself. port trunk port worksheet provided Appendix Assign port trunk port port trunk port register. This necessary because each port group trunk must assigned trunk port. assigning trunk port itself, broadcast frames will sent back source port. Assign ports trunk port same VLAN using register port VLAN grouping should only include trunk port assigned other trunk ports. This ensure that broadcast frames will only forwarded assigned port. Port Based Trunking Load Balancing Example Note: specific bits register reference notation, where register number number. following procedure design 8-port switch with 3-port trunk. desired trunk ports Therefore, port configuration register bits 17.9, 19.9, 1B.9 want assign port trunk port port trunk port port trunk port trunk ports therefore trunk number assignment port trunk port register bits should therefore 2F.3= 2F.2= 30.3= 30.2= 31.3= 31.2= 32.3= 32.2= 33.3= 33.2= trunk ports, trunk ports should assigned with their port number port trunk port register. port trunk port bits should 34.3= 34.2= 35.3= 35.2= 36.3= 36.2= Assigning VLAN. VLAN should assigned shown. bits while bits 1E.6 1E.7 because port assigned port other ports similarly. Bits through reserved should VLAN mapping registers. Appendix provide work sheets port trunk port VLAN assignment.
10/00
Reference Only Allayer Communications
AL126 Revision
Table VLAN Mapping Port Based Load Balancing Trunk
PORT 6/REG. PORT 7/REG. PORT 0/REG. PORT 1/REG. PORT 2/REG. PORT 3/REG. PORT 4/REG. PORT 5/REG.
PORT
3.11.2 Trunking (Port Aggregation) Trunking automatically load-balances among member ports through unique statistical methods, provides link resiliency (link-fail-over function) when more links trunk group fails. Trunking selected L2Trunk, Register System Configuration Register 3.11.2.1 Trunk Configuration Trunk (Port Aggregation) configuration accomplished through programming configuration registers. AL126 provides capability trap IEEE 802.3ad frames allows configure aggregated links based IEEE recommended protocol exchange. 3.11.2.2 Trunk Port Assignment Each device supports trunks, each trunk have through eight ports members. total eight trunk groups four switching devices RoX-II possible. Each device must aware other devices trunk configuration. These configured Register through Register Layer Trunking Assignment Registers through Unlike portbased trunking groups, Trunk group programmed bit-map member ports each trunk.
10/00
Reference Only Allayer Communications
AL126 Revision
3.11.2.3 Trunk Load Balancing load balancing algorithm uses randomized seed based Destination address, Source Address, both Destination Source Addresses, non-randomized Each trunk groups randomization method selected Register Layer Trunking Protocol Register. This randomization sequence creates 12-bit value, which used random seed value load balancing algorithm. L2KeySel, Register System Configuration Register bits 1~0, used select which 3-bit field random seed value. Normally this register doesn't need adjusted normal operation. AL126 uses robust unique algorithm ensure statistically equal loads whether trunk group member ports group. 3.11.2.4 Link Fail Over AL126 supports link fail-over when more member ports trunk fail. This feature enabled L2FailEn Register System Configuration Register member port trunk experiences link failure, AL126 detects this condition divides frame-flow that used assigned failed port other member ports. load balancing algorithm also applies this case, which statistically ensures equal load rest member ports. link healed, then only frame-flow that re-assigned other member ports restored back original link. When frame-flow restored onto original link, queue needs flushed avoid mis-ordered frames. This flushing mechanism selected setting L2Timer value Register System Configuration Register Bits 5~4. This Link FailOver feature only available trunking mode.
3.12 Spanning Tree Support
AL126 capability support implementation Spanning Tree Protocol. ports programmed port state required Spanning Tree Protocol. Spanning Tree Protocol option enabled, AL126 will forward frame below. port Block-N-Listen State Learning State, frame forwarded BPDU frame, frame discarded otherwise. outgoing frames except outgoing BPDUs will masked from path PHY. port Forwarding State, frame forwarded BPDU frame. source addresses incoming frames from will learned then forwarded based switch routing decision. outgoing frames will transmitted PHY. port Learning State, source addresses incoming frames from will learned. incoming frames except incoming BPDUs from will discarded after being learned, outgoing frames except outgoing BPDUs will masked from path PHY.
10/00
Reference Only Allayer Communications
AL126 Revision
3.13 Flow Control
AL126 operate different modes, half- full-duplex. Each port operate either full half-duplex configured have flow control enabled flow control independently per-port basis. 3.13.1 Half Duplex (Backpressure) half-duplex flow control option elected, backpressure will used flow control. Whenever receive frame buffer port full, port will start sending signal through port. remote station will defer transmission after sensing signal. Backpressure flow control applied ensure that there dropped frames. AL126 supports types backpressure, collision based carrier based. Carrier based backpressure generated AL126, when switch port's frame buffer full. AL126 will cease line when port buffer space available frame reception. jamming signal programmed either 64BT 96BT. Collision based backpressure generated AL126 only when switch port receives frame frame buffer full. AL126 will cease line when line idle. carrier based backpressure several advantages over collision based backpressure. Collision based backpressure cause late collisions. After consecutive collisions, could drop frames. AL126 option drop frames after collisions. However, terminal still drop frames. Therefore, recommend carrier based backpressure preferred method halfduplex flow control. this mode operation, also recommend that signal should 64BT. This because 96BT, terminal might still able transmit frames cause collisions. excessive collisions cause frames dropped. AL126 also supports collision based backpressure customers that prefer that type backpressure. 3.13.2 Full Duplex Flow Control (802.3x) full-duplex mode, AL126 will transmit receive frames accordance IEEE 802.3x. transmission channel receiving channel operate independently. incoming direction, whenever receive frame buffer port full, port will send PAUSE frame with delay value maximum. PAUSE frame will deter incoming frame from flowing into port. After occupancy receiving frame buffer reduced below FlowControlOff threshold, port will then send PAUSE frame with delay value zero, resume receiving incoming frame flow. outgoing direction, whenever incoming PAUSE frame with non-zero delay value received through port, port will stop next frame transmission after ongoing frame transmission finished, start pause timer. will resume frame transmission either after pause timer expired when PAUSE frame with zero delay value received. PAUSE frame defined special type, code.
10/00
Reference Only Allayer Communications
AL126 Revision
When 802.3x flow control option elected, device will program appropriate autonegotiation capability field. When AL126 used full-duplex mode, recommended that flow control should turned prevent buffer from overflow loss frames. connected device 802.3x capability, then link recommended half-duplex. 3.13.3 Special Frame Identification Trapping AL126 capable identifying special frames forwards them required. AL126 inspects load incoming frames, frame types selected (register 03), will then forward frame CPU. following types frame trapping supported AL126 addition BPDU frames.
NAME IPMC COMMENT Multicast Mapping Frames. AL126 directly supports multicast addresses. that needed support multicast procedure mapping host addresses ethernet multicast address placing low-order bits address into order bits ethernet multicast address 01-00-5E-00-00-00 (hex). Because there significant bits, more than host group address mapped same ethernet multicast address. Internet Group Management Protocol. This internet multicast support bridges. Generic Attribute Registration Protocol. This required 802.1p 802.1q support. Address Resolution Protocol. This required TCP/IP stack. Controls Frames 802.3ad Trunking Control.
IGMP GARP 802.3ad
3.14 Queue Management
AL126 supports four priority queues each port AL126. frames that come into AL126 stored into shared memory buffer lined transmission queues corresponding destination port. priority assigned contained received frames. definition priority programmed register AL126 will transmit frames based priority queue assigned priority tag. AL126 provides modes priority scheduling (selectable register 02); Strict Priority Scheduling Weighted Priority Scheduling. Strict Priority Scheduling simple scheduling scheme that will schedule highest priority frames transmitted first. shortcoming this method priority frames might starved bandwidth there very high traffic high priority frames. alternative Weighted Priority Scheduling which assigns weight different levels that provide priority frames fair chance accessing bandwidth. weight each priority programmed register
10/00
Reference Only Allayer Communications
AL126 Revision
3.14.1 Congestion Control AL126 provides options congestion control. When port congested, AL126 will backpressure flow control deter further traffic from entering switch. Although this good prevent frame loss, desirable some applications. AL126 therefore allows users program queue able drop frames when number frames reaches watermark programmed that queue. broadcast multicast frames, AL126 also provides capability dropping frames from Mbit/s multicast queue keep Mbit/s forwarding speed.
3.15 Uplink Port
uplink port provides connect switch with repeater hub, workgroup switch, router, type interconnecting device compliance with IEEE 802.3 standards. port also designated uplink port. flood control enabled, AL126 will send frames with unmatched multicast/ broadcast frames uplink port. very important that each port assigned uplink port Port Configuration Register to1C) uplink disabled, data frames might lost. uplink port should configured within same VLAN source port. uplink port member VLAN, broadcast multicast frames will forwarded designated uplink port. Multiple VLANs share same uplink port. AL126 will direct following frames uplink port. Frames with unicast destination address that does match with address stored switch. Frames with broadcast/multicast destination address uplink port same VLAN. When configuring uplink port, uplink port should designate itself uplink port. Summary Programmable Register Trunk Port Designation (register this register provides option designating uplink port either port, trunk CPU. details register descriptions.
3.16 Port Monitoring
AL126 supports port monitoring. This feature provides complete network monitoring capability Mbit/s. copy egress (TX) data ingress (RX) data monitored port sent their respective snooping ports. monitored port selected register AL126 allows transmit receive data monitored different snooping ports. snooping ports also selected register Summary Programmable Register Port Monitoring Register (register this register selects target monitored port snooping port. 5-bit Port_ID designates port. format Port_ID [Dev_ID].[Port_ID]. [Dev_ID] device number [Port_ID] port number.
10/00
Reference Only Allayer Communications
AL126 Revision
3.17 Media Independent Interface (MII)
each port AL126 connected through standard interface. reception, received data (RXD) sampled rising edge receive clock (RX_CLK). Assertion receive data valid (RX_DV) signal will cause look start SFD. transmission, transmit data enable (TX_EN) signal asserted when first preamble nibble sent transmit data (TXD) lines. transmit data clocked rising edge transmit clock (TX_CLK). Prior transaction, AL126 will output thirty-two bits preamble signal. After preamble, "01" signal used indicate start frame. write operation, device will send "01" signal write operation. Following "01" write signal will five-bit address device 5-bit register address. "10" turn around signal then used avoid contention during read transaction. After turn around, 16-bit data will written into register. After completion write transaction, line will high impedance state. read operation, AL126 will output "10" indicate read operation after start frame indicator. Following "10" read signal will 5-bit address device 5bit register address. Then, AL126 will cease driving MDIO line, wait 1-bit time. During this time, MDIO should high impedance state. device will then synchronize with next driven device, continue read 16-bits data from register. detail timing requirements management signals described section "Timing Requirements." MDIO port disabled through port configuration register. This allows engineers 100Base-TX transceiver without auto-negotiation capability interconnect. this mode operation, communication with AL126. Therefore, AL126 will assert link status soon initialization completed assumes connected operating specified operating duplex mode speed.
3.18 Management
AL126 supports transceiver management through serial MDIO signal lines. device provides modes management, master slave mode. master mode operation, AL126 controls operation modes link while controls operating mode slave mode. 3.18.1 Management Master Mode this mode, AL126 will continuously poll status devices through serial management interface, without intervention. device will also configure capability fields ensure proper operation link. access registers devices through interface provided management device, AL300A. configuration link automatic. link capability programmed AL126 through port configuration register. AL126 reads from standard IEEE registers determine auto-negotiated operating speed mode. there need manually operation mode because flow control cabling issues, AL126 port operation mode manually through MDIO interface (see EEPROM section programming AL126).
10/00
Reference Only Allayer Communications
AL126 Revision
used reprogram AL126, operating mode changed without reset powered down. order ensure link operating desired mode, should renegotiate either through command unplugging RJ45. 3.18.2 Management Slave Mode slave mode, controls programming operating mode. AL126 will continuously poll status devices through serial management interface, without intervention determine operation mode link. access registers devices through interface provided management device. This mode management very useful unmanaged switches. operating mode link changed programming mode through jumper without assists from CPU. AL126 also supports 100Base-TX transceivers without MDIO interface interface. When MDIO disabled, AL126 will operate operation mode specified Port Configuration Register 1C). 3.18.3 Auto-negotiation Mode AL126 also turn auto-negotiation capability PHY. When auto-negotiation turned off, AL126 slave mode transceiver will determine link's operating mode. 3.18.4 Other Options Some Legacy Fast Ethernet devices cost devices have auto-negotiation capability. those cases, transceiver will able perform auto-negotiation. switch transceiver will typically parallel detection update information transceiver's register. Unfortunately, such register addresses vendor specific. AL126 provides register (register specify register address AL126 read. AL126 will read from that register configure port operation accordingly. Register also provides some additional flexibility's some PHYs market. general, system designer should devices port port etc., port Lucent Quad PHY, LU3X54FT, utilizes address 00000 broadcast address. register allows AL126 start with address 01000. This provision allows engineers work around PHYs that have problems handling address 00000. Quad PHYs market today have 2-port ordering chip pinout, clockwise counter clockwise. Register programs AL126 port order either direction. This provision enables engineers implement designs with easily. There also slow MDIO clock KHz) available PHYs that capable handling high speed MDIO clock. some reason, transceiver connected device that device fails auto-negotiate, AL126 will default data rate duplex mode default setting port configuration register.
10/00
Reference Only Allayer Communications
AL126 Revision
3.19 SGRAM Interface
ports AL126 work Store-And-Forward mode that ports support both Mbps Mbps data speed. AL126 utilizes central memory buffer pool which shared ports within same device. After frame received, passed across SGRAM interface stored buffer. During transmit, frame retrieved from buffer pool forwarded destination port. AL126 designed 8-Mbit SGRAM 16-Mbit SGRAM cost performance. SGRAM essentially SDRAM. Dynamic memories must refreshed periodically prevent data loss. SGRAM auto-refresh which also uses refresh address counter. SGRAM auto-refresh command generates pre-charge command internally SGRAM. AL126 will insert auto-refresh command once every SGRAM accessed page burst access mode very high speed access. This burst mode repeatedly accessing same column. burst mode reaches column address, then wraps around first column address (=0) continues count until interrupted read/write, pre-charge, burst stop command. AL126 will initialize SGRAM automatically. pre-charges banks inserts eight auto-refresh commands. will also program mode registers AL126 read write operations.
3.20 EEPROM Interface
AL126 provides three functions with EEPROM interface; system initialization, obtaining system status, reconfiguration system real time. 3.20.1 System Initialization EEPROM interface provided manufacturer provide pre-configured system their customers. Customers change reconfigure their system retain their preferences. EEPROM contains configuration initialization information, which accessed power reset. AL126 uses 24C02 serial EEPROM device (2048 bits organized bits organization EEPROM data shown Table During start AL126 will detect presence EEPROM. EEPROM present, AL126 will initialized attached management device RoX-II ring. initialization command received, device will operate. reset held low, AL126's EEPROM interface will into high impedance state. This feature very useful reprogramming EEPROM during installation reconfiguration. There ways that EEPROM reprogrammed, external parallel port residing ring. reprogramming using parallel port, signal used hold RESET low; EEPROM interface will then high impedance state. external device then program EEPROM through EDIO ECLK pins. EEPROM address should same device with (EEPROM) grounded. example, EEPROM device address device address 001.
10/00
Reference Only Allayer Communications
AL126 Revision
Device Type Identifier
Device Address
Figure
EEPROM Address Format
3.20.2 Start Stop write cycle started start ended stop bit. start transition from high EEDIO when high. operation terminates when EEDIO goes from high when high (Figure Following start condition, writing device must output address EEPROM. most significant four bits EEPROM address device type identifier. These four bits 1010. EEPROM device address should device number. EECLK output from AL126. EEDIO input AL126 reading EEPROM output writing (See Figures When accessing EEPROM, reset held before writing operation begin.
EECLK
EEDIO
Data Address Valid
START
Data Change
STOP
Figure
Start Stop
10/00
Reference Only Allayer Communications
AL126 Revision
3.20.3 Write Cycle Timing EECLK output from AL126 while EEDIO bi-directional signal. When accessing EEPROM, reset held initialization AL126 must finished before write operation begin. typical write operation shown Figure
Device Address
Start
Stop
EEDIO
8-Bit Word Address
8-Bit Data
Acknowledge
Acknowledge
Acknowledge
Figure
Typical Write Cycle
3.20.4 Read Cycle Timing Read operations initiated same manner write operations, with exception that EEPROM address "1."
Device Address Device Address
Start
Start
Stop
EEDIO
8-Bit Word Address
8-Bit Data
Acknowledge
Acknowledge
Acknowledge
Acknowledge
Figure
Typical Read Cycle
3.20.5 Reprogramming EEPROM Configuration There ways that system reconfigured. Figure shows application using parallel interface reprogram EEPROM. this application, parallel port holds reset pins low, which forces EEDIO pins high impedance. Once pins high impedance, EEPROM programmed parallel port. Once parallel port releases reset pins, devices will start download EEPROM data reconfigure devices.
10/00
Reference Only Allayer Communications
AL126 Revision
alternate reconfiguring system input data directly into AL126. After initialization, EEPROM interface virtual EEPROM. order this method work, EEPROM's address must 0XX, AL126's address will 1XX. customer program AL126 EEPROM. read write timing same EEPROM. Because read well write AL126, status register read from AL126. This will serve very useful tool diagnostic unmanaged switch.
AL126
Reset
EECLK EEDIO
EEPROM Parallel Port
AL126
Reset
EECLK EEDIO
EEPROM
Reset
AL126
EECLK EEDIO
EEPROM
Reset
AL126
EECLK EEDIO
EEPROM
Figure
Programming EEPROM with Parallel Port
10/00
Reference Only Allayer Communications
AL126 Revision
3.20.6 EEPROM Note: specific bits register referenced notation, where register number number. Table shows EEPROM addresses cross-referenced register/bit AL126. Addresses through configuring device. They downloaded AL126 during reset power Address indicates last address entry. static address used switch, address should programmed. Addresses used programming explicit address entry.
format address shown follows; YXXXXX represents: then XXXXX 5-bit individual port number. Y=1, then XXXXX either trunk port represented followed 3-digit [trunk number, port represented 11ZZZ where don't care.
Table Static Address Entry Format EEPROM
EEPROM ADDRESS
Reserved (Must zero) Reserved Port YXXXXX Trunk YXXYYY
Address [47:40] Address [39:32] Address [31:24] Address [23:16] Address [15:8] Address [7:0]
10/00
Reference Only Allayer Communications
AL126 Revision
Table AL126 EEPROM Mapping
EEPROM PHYSICAL ADDRESS 00-01 02-03 04-05 06-07 08-09 0A-0B 0C-0D 0E-0F 10-11 12-13 14-15 16-17 18-19 1A-1B 1C-1D 1E-1F 20-21 22-23 24-25 26-27 28-29 2A-2B 2C-2D 2E-2F 30-31 32-33 34-35 36-37 38-39 DESCRIPTION System Configuration System Configuration System Configuration System Configuration System Performance Tuning Vendor Specific Port Monitoring Configuration Priority Queue Assignment Output Queue Management Output Queue Management Priority Queue Weight Round Robin RoX-II Control RoX-II Control Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration
10/00
Reference Only Allayer Communications
AL126 Revision
Table AL126 EEPROM Mapping (Continued)
3A-3B 3C-3D 3E-3F 40-41 42-43 44-45 46-47 48-49 4A-4B 4C-4D 4E-4F 50-51 52-53 54-55 56-57 58-59 5A-5B 5C-5D 5E-5F 60-61 62-63 64-65 66-67 68-69 6A-6B 6C-6D 6E-6F 70-71 72-73 74-75 76-7D Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN VLAN Extension CheckSum VLAN Extension Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Testing Control Testing Control Last Entry Location Static Entry
10/00
Reference Only Allayer Communications
AL126 Revision
Table AL126 EEPROM Mapping (Continued)
7E-85 86-8D 8E-95 96-9D 9E-A5 A6-AD AE-B5 B6-BD BE-C5 C6-CD CE-D5 D6-DD DE-E5 E6-ED EE-F5 F6-FD FE-FF Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Reserved
10/00
Reference Only Allayer Communications
AL126 Revision
3.21 Register Descriptions Table Register Description
REGISTER REGISTER NAME System Configuration System Configuration System Configuration System Configuration System Performance Tuning Vendor Specific Status Port Monitoring Configuration Priority Queue Assignment Output Queue Management Output Queue Management Priority Queue Weight Round-Robin RoX-II Control RoX-II Control Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration REVEPADDR [00, [02, [04, [06, [08, [0a, [0c, [0e, [10, [12, [14, [16, [18, [1a, [1c, [1e, [20, [22, [24, [26, [28, [2a, [2c, [2e, [30, [32, [34,
10/00
Reference Only Allayer Communications
AL126 Revision
Table Register Description (Continued)
Port Configuration Port Configuration Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN VLAN Extension VLAN Extension Port Trunk Port Assignment/Layer Trunking Assignment Port Trunk Port Assignment/Layer Trunking Assignment Port Trunk Port Assignment/Layer Trunking Assignment Port Trunk Port Assignment/Layer Trunking Assignment Port Trunk Port Assignment/Layer Trunking Protocol Select Port Trunk Port Assignment Port Trunk Port Assignment [36, [38, [3a, [3c, [3e, [40, [42, [44, [46, [48, [4a, [4c, [4e, [50, [52, [54, [56, [58, [5a, [5c, [5e, [60, [62, [64, [66, [68, [6a,
10/00
Reference Only Allayer Communications
AL126 Revision
Table Register Description (Continued)
Port Trunk Port Assignment Testing Control Testing Control System Status Register Port Operation Status Port Operation Status Port Operation Status Port Operation Status Port Operation Status Port Operation Status Port Operation Status Port Operation Status Indirect Resource Access Command Indirect Resource Access Data Indirect Resource Access Data Indirect Resource Access Data Indirect Resource Access Data Indirect Resource Access Data Monitored Source Host (MAC Address [47:32]) Monitored Source Host (MAC Address [31:16]) Monitored Source Host (MAC Address [15:0]) Monitored Destination Host (MAC Address [47:32]) Monitored Destination Host (MAC Address [31:16]) Monitored Destination Host (MAC Address [15:0]) Port Default Priority/VLAN Port Default Priority/VLAN Port Default Priority/VLAN Port Default Priority/VLAN Port Default Priority/VLAN Port Default Priority/VLAN [6c, [6e, [70, [72, [74, [76, [78, [7a, [7c, [7e, [80, [82, [84, [86, [88, [8a, [8c, [8e, [90, [92, [94, [96, [98, [9a, [9c, [9e, [a0, [a2, [a4, [a6,
10/00
Reference Only Allayer Communications
AL126 Revision
Table Register Description (Continued)
Port Default Priority/VLAN Port Default Priority/VLAN Port Default Priority/VLAN Port Default Priority/VLAN Port Default Priority/VLAN Port Default Priority/VLAN Port Default Priority/VLAN Port Default Priority/VLAN Port Default Priority/VLAN Port Default Priority/VLAN Port Default Priority/VLAN Port Default Priority/VLAN Port Default Priority/VLAN Port Default Priority/VLAN Port Default Priority/VLAN Port Default Priority/VLAN Port Default Priority/VLAN Port Default Priority/VLAN Port Default Priority/VLAN Port Default Priority/VLAN Port Default Priority/VLAN Port Default Priority/VLAN Port Default Priority/VLAN Port Default Priority/VLAN Port Default Priority/VLAN Port Default Priority/VLAN Local Default Priority/VLAN Reserved CheckSum [a8, [aa, [ac, [ae, [b0, [b2, [b4, [b6, [b8, [ba, [bc, [be, [c0, [c2, [c4, [c6, [c8, [ca, [cc, [ce, [d0, [d2, [d4, [d6, [d8, [da, [dc, [de, [e0,
10/00
Reference Only Allayer Communications
AL126 Revision
System Configuration Register (Register registers global system configuration registers. option selected this register affects overall system operation.
Table System Configuration Register (Register
NAME CPUprst DESCRIPTION Present. This used indicate AL126 initialized from EEPROM. This AL126 when detects EEPROM present configuration initialized. device assumes that present waits initialize this device. Flooding Control. Controls forwarding unicast frames with unknown destinations received from non-uplink ports. Disable. Frames received with unknown unicast destination address will forwarded ports (excluding receiving port) within VLANs specified receiving port. (IEEE 802.1d compliant) Enable. Frames received with unknown unicast destination address will forwarded uplink port specified receiving port. Auto Security Enforcement. Auto security off. security violation secured port will change port state. Auto security security violation secured port will cause port into DISABLE state. Switch Table Entry Aging Control. Only dynamically learned addresses will aged. explicit entries will age. aging time programmed register Disable. table aging process disabled. Enable. table aging process enabled hardware process ages every dynamically learned table entry. (IEEE 802.1d compliant) Address Table Convergence Control. Disable. device will share locally learned addresses with other devices RoX-II Bus. Enable. device will background process periodically transfer locally learned table entries other devices learn. (IEEE 802.1d compliant) Spanning Tree Protocol Enable Control. Disable. BPDU frames received from network ports will treated regular broadcast frames. Enable. BPDU frames received from network ports will forwarded only port. (IEEE 802.1d compliant, this setting system network management).
FloodCtl
AutoSec
AgeEN
TCNVG
STPEN
10/00
Reference Only Allayer Communications
AL126 Revision
Table System Configuration Register (Register (Continued)
PinMon Port Incoming Frame Flow Monitoring (port snooping) Enable Control. monitored snooping port configuration register Disable Enable Port Outgoing Frame Flow Monitoring (port snooping) Enable Control. monitored snooping port configuration register Disable Enable Configuration Ready. This AL126 provide indication that register file initialization completed CPU. initialized. Register file initialization done. Network Management Enable Control. Disable. device will generate events management device (such AL300A AL3000). Enable. device will generate events propagate them management device. System Initialization Done. Meaningful only when AL126 initialized CPU. sets this after registers static entries programmed. Select RMII Ports through (See Register Port Disable. device will operate mode. Enable. device will operate RMII mode. Layer Trunking Mode. Trunked (Port Aggregation) port selection given frame based either Layer Source Destination Address based ports trunk assignment. Disable. Trunking decisions will based port-based trunk port assignment registers. Enable. Trunking decisions will based source port addresses. Frame Aging Time Enable. MaxDelay bits register time-out limit. Device will time-out frames based MaxDelay. Device will time-out frames. (IEEE 802.1d compliant)
PoutMon
CPUcfgrdy
NetMgmt
CPUInitDone
SelRMII
L2Trunk
TimeoutEn
Reserved
10/00
Reference Only Allayer Communications
AL126 Revision
Table System Configuration Register (Register
15~9 NAME MaxAge DESCRIPTION MaxAge. This seven-bit register containing unsigned integer determining address-aging timer. resolution normal address aging 5.36 seconds seconds with system clock. SlowAge (register programmed "1," resolution 10.72 seconds 13.4 seconds with system clock. Reset Disable. Reset link down. Don't Reset link down. MaxDelay. This sets timer maximum allowable frame aging through switch TimeoutDis (register option elected. This value slowed down factor eight setting Register SlowAge bit. second. seconds. seconds. seconds. MaxStorm. This sets threshold number consecutive broadcast frames allowed from port. storm control option selected Port Configuration Registers (registers 1C). frames. frames. frames. frames. SuperMAC. When this option selected, AL126 controller will more aggressive back algorithm. This enables switch transmit frame earlier. (Meaningful only half-duplex mode). Disable. Device will perform IEEE 802.3 standard exponential back algorithm when collision occurs. Enable. When collision occurs, device will back slots. L2TKeySel. Selects address bits address based trunk port assignment. most applications, this field does need adjusted. hashkey pattern hashkey pattern hashkey pattern hashkey pattern
PhyResetDis
MaxDelay
MaxStorm
SuperMAC
Reserved L2KeySel
10/00
Reference Only Allayer Communications
AL126 Revision
Table System Configuration Register (Register
NAME SelRMIIP0 DESCRIPTION Selects RMII Port (See Register Ports Disable. Port operates mode. Enable. Port operates RMII mode. Disables Unknown Frame Forwarding AL300A, thereby CPU. Clock Select. System clock MHz. System clock MHz. Layer Trunk Group Enable. Disable Enable Layer Trunk Group Enable. Disable Enable Slow Timing. Slows down normal address aging timer specified register MaxAge field. Normal aging. resolution normal address aging 5.36 seconds seconds with system clock. Slow down. resolution 10.72 seconds 13.4 seconds with system clock. Backpressure Inter-packet Gap. Used half-duplex backpressure operation when carrier-based backpressure selected. BpIPG 96BT. BpIPG 64BT. Standard Inter-packet Gap. Used normal frame transmission. 96BT. (IEEE 802.3 compliant) 64BT. Backpressure Rate. Used when collision based backpressure operation selected. Collide with every frame. Collide every frames. Collide every frames. Collide every frames. Frame Buffer SGRAM Size. Mbit SGRAM. Mbit SGRAM. Backpressure Collision. Selects backpressure mechanism halfduplex (CSMA/CD) operation. based. Collision based.
CPUOffL ClkSel
L2T0En
L2T1En
SlowAge
BpIPG64
SIPG
BPRate
SG16M
BPCOL
10/00
Reference Only Allayer Communications
AL126 Revision
Table System Configuration Register (Register (Continued)
ETEnb External Table Enable. (Must have external SSRAM present). This table also used IEEE 802.1q tagged VLAN database. Disable Enable Binary Exponential Backoff Select Half-duplex (CSMA/CD) Operation. Standard (IEEE 802.3 compliant). Avoid channel capture binary back-off algorithm. Priority Queue Arbitration Method. Selects either weighted roundrobin strict priority. Strict priority. Weighted round-robin. Relative priority register Broadcast Storm Control Selection. Flow control Multicast Broadcast. Flow control only Broadcast.
BebSel
PQWRREn
FlowCtrlBC
Table System Configuration Register (Register
NAME QEnable DESCRIPTION Enables 802.1q VLAN Tagging. This requires external address table SSRAM corresponding control bit, register External Table, should set. Disable Enable Supports AL300A Protocol. Must AL300A present RoX-II Ring. Disable Enable Gateway Device Present. Enables support Ring Gateway device. Disable Enable Enables Alternative Ring Gateway Device Support. Disable Enable IPMC Frame Trap Enable. Enables Multicast Frame Trap AL300A (management) AL3000 (Router). Disable Enable IGMP Frame Trap Enable. Disable Enable GARP-Type (e.g. GVRP, GMRP) Frame Trap Enable. Disable Enable Frame Trap Enable. Disable Enable
AL300AEn
GWPrst
ALTGW IPMCtrap
IGMPtrap GARPtrap ARPtrap
10/00
Reference Only Allayer Communications
AL126 Revision
Table System Configuration Register (Register (Continued)
802Xtrap Trunking Control Frame Trap Enable. Enables IEEE 802.3ad Port Aggregation Control Frame Trap. Disable Enable Layer Trunk Link Fail Recovery Enable. Enables automatic link-fail over protection trunks (Aggregated ports). This only effective when Register L2Trunk set. Disable Enable Layer Trunk Link Recover Timer Control. Selects queue flushing timer used when failed link trunk healed traffic restored healed link. This field value meaningful only when Register L2Trunk Register L2FailEn set. Disable 1/16 Device Gigabit Device. Gigabit device (such AL1022) occupies RoX-II Ring Device Disable Enable Device Gigabit Device. Gigabit device (such AL1022) occupies RoX-II Ring Device Disable Enable Device Gigabit Device. Gigabit device (such AL1022) occupies RoX-II Ring Device Disable Enable Device Gigabit Device. Gigabit device (such AL1022) occupies RoX-II Ring Device Disable Enable
L2FailEn
L2Timer
D3GigaOn
D2GigaOn
D1GigaOn
D0GigaOn
10/00
Reference Only Allayer Communications
AL126 Revision
System Performance Tuning Control Register (Register fields this register performance characteristics RoX-II Ring. register recommended value based RoX-II Ring operating frequency. Recommended Settings: 0001 1001 0101 1100 with dual control ring enabled; 0001 0001 0001 0100 MHz.
Table System Performance Tuning Control Register (Register
15~14 NAME SysPerf1 CasDelay DESCRIPTION Refer Recommendation Above. Sets Frame Buffer Memory SGRAM/SDRAM Latency. Latency (Default) Latency Refer Recommendation Above.
12~0
SysPerf0
Vendor Operating Mode (Register Configuration) This register used program vendor specific option. also used programming Vendor Specific register location location operation status. Please refer respective 10/100 Fast Ethernet data sheet MDIO programming section) connected AL126 appropriate register settings.
Table Vendor Operating Mode (Register
NAME MSBSel DESCRIPTION Most Significant Selection. address 00xxx. address 10xxx. MDIO Clock Speed Selection. Normal (RoX-II Ring Clock divided 128, @100 MHz) Select slow clock MII. (RoX-II Ring Clock divided 4096, @100 MHz) Reverse Order. multi-PHY package, some vendors numbers ports clockwise others counterclockwise. These re-mapped consistent with switch system's port numbering scheme setting this register. address order from 111; (normal). address order from 000. Operating Mode Register. Address vendor specific operating mode register that typically holds results parallel link capability detection.
MIISlowClk
RevOrder
12~8
PHYOpReg
10/00
Reference Only Allayer Communications
AL126 Revision
Table Vendor Operating Mode (Register (Continued)
PHYOpSp Operating Speed Location. location within register specified PHYOpReg where attached PHY's operating speed stored. Operating Mode Location. location within register specified PHYOpReg where attached PHY's operating mode (full/ half-duplex) stored.
PHYOpMd
Port Monitoring Configuration Register (Register This register configures port monitoring ("snooping" "sniffer" port). sets monitored port snooping ports.
Table Port Monitoring Configuration Register (Register
14~10 NAME Reserved MdPID MgIPID Device Port Port Being Monitored. DeviceID[1:0]+PortID[2:0]. Device Port Destination Port Receive Monitored Port's Ingress Frames. This port same port MgOPID. DeviceID[1:0]+PortID[2:0]. Device Port Destination Port Receive Monitored Port's Egress Frames. This port same port MgIPID. DeviceID[1:0]+PortID[2:0]. DESCRIPTION
MgOPID
Priority Queue Assignment Register (Register Recommended Setting: 1111 1010 0100 0001 AL126 allows tagged priority assigned four priority queues. AL126 will transmit frames based priority queue, priority tag.
Table Priority Queue Assignment Register (Register
15~14 NAME PL7QA DESCRIPTION Select User Priority Value VLAN Mapping AL126's Priority Queue. Queue Queue Queue Queue User Priority Value Queue Assignment. User Priority Value Queue Assignment. User Priority Value Queue Assignment. User Priority Value Queue Assignment. User Priority Value Queue Assignment.
13~12 11~10
PL6QA PL5QA PL4QA PL3QA PL2QA
10/00
Reference Only Allayer Communications
AL126 Revision
Table Priority Queue Assignment Register (Register (Continued)
PL1QA PL0QA User Priority Value Queue Assignment. User Priority Value Queue Assignment.
Output Queue Management Register (Register Recommended Setting: 0011 1111 1111 1111
Table Output Queue Management Register (Register
NAME MaxDrop DESCRIPTION Output Over Drop Option. Selects queue behavior when queue maximum depth limit reached. Flow control first. Drop enable.
Reserved CPUMaxLimEn M0MaxLimEn Q3MaxLimEn AL300A Limit Enable. Disable Enable Mbit/s Multicast Queue Limit Control Enable. Disable Enable Priority Queue Limit Control Enable. maximum limit control enabled, both queue port maximum limit control must enabled control enabled. Disable Enable Priority Queue Limit Control Enable. Priority Queue Limit Control Enable. Priority Queue Limit Control Enable. Output Port Limit Control Enable. limit control enabled, both queue port limit control must enabled control enabled. Disable Enable Output Port Limit Control Enable. Output Port Limit Control Enable. Output Port Limit Control Enable. Output Port Limit Control Enable. Output Port Limit Control Enable. Output Port Limit Control Enable. Output Port Limit Control Enable.
Q2MaxLimEn Q1MaxLimEn Q0MaxLimEn P7MaxLimEn
P6MaxLimEn P5MaxLimEn P4MaxLimEn P3MaxLimEn P2MaxLimEn P1MaxLimEn P0MaxLimEn
10/00
Reference Only Allayer Communications
AL126 Revision
Output Queue Management Register (Register Recommended Setting: 0001 0001 0001 0001
Table Output Queue Management Register (Register
15~12 NAME Q3MaxLim DESCRIPTION Maximum buffer blocks priority queue hold both priority queue output port limit controls enabled. AL126 uses this value buffer-full status "Queue Status" registers each output priority queues. When this threshold reached, "Operation Status Communication Message" with <buffer full> sent onto RoX-II data ring. frame queue request must honored regardless this bit. water mark sending <buffer available> less than limit, except limit (it's watermark which used test mode. 0000: 0001: 0010: 0011: 0100: 0101: 0110: 0111: 1000: 1001: 1010: 1011: 1100: 1101: 1110: 1111: Maximum buffer blocks priority queue hold both priority queue output port limit control this queue enabled. Maximum buffer blocks priority queue hold both priority queue output port limit control this queue enabled. Maximum buffer blocks priority queue hold both priority queue output port limit control this queue enabled.
11~8
Q2MaxLim Q1MaxLim Q0MaxLim
10/00
Reference Only Allayer Communications
AL126 Revision
Priority Queue Weight Round-Robin Control Register (Register Recommended Setting: 1111 0111 0011 0001 This register controls weight each priority queue, when weight priority queuing selected. Note: weight should bigger equal weight should bigger equal weight should bigger equal
Table Priority Queue Weight Round-Robin Control Register (Register
15~12 NAME Q3RRWeight DESCRIPTION Weight Queue Round-robin Scheme. 0000 0001 1110 1111 (Note that applicable 0000.) Weight Queue Round-robin Scheme. Weight Queue Round-robin Scheme. Weight Queue Round-robin Scheme.
11~8
Q2RRWeight Q1RRWeight Q0RRWeight
RoX-II Control Register (Register Recommended Setting: 0000 0000 0000 0000 This register, along with register sets "route" bitmap from device this device. Each Route 5-bits representing device device physical connections. each respective that represents path back this device RoX-II ring. least significant position used Device ID=0 while most significant position used Device ID=4. RoX-II devices don't have connected Device sequence. this bit-map means that data path from this Device bit-map device active. this Device then D1Route zero, since does RoX-II Ring transfer data itself. AL300A present RoXII ring, include AL300A device Route Field programming. Example: Consider RoX-II Ring where devices connected sequence Device that Device ->Device Device Device Device (AL3000)->Device device with Device ID=0, D0Route 00000, because device. D1Route 11110, because from Device ID=1 Device ID=0, Device through Device present. D2Route 11100, because from Device ID=2 Device ID=0, Device through Device present. D3Route 11000, because from Device ID=3 Device ID=0, Device through Device present. D4Route 10000, because from Device ID=4 Device ID=0, Device only present drive this device (Device
10/00
Reference Only Allayer Communications
AL126 Revision
Table RoX-II Control Register (Register
NAME DualREn DESCRIPTION Dual Control Ring Enable. RoX-II Ring separate data control ring. control ring either 8-bit wide mode 14-bit mode. Setting this enables 14-bit mode, required maximum RoX-II Ring performance. Disable. Control ring 8-bit mode. Enable. Control ring 14-bit mode. Route Selection from Device this Device. Refer example above Register description. Route Selection from Device this Device. Refer example above Register description. Route Selection from Device this Device. Refer example above Register description.
14~10
D2Route D1Route D0Route
RoX-II Control Register (Register Recommended Setting: 0000 0000 0000 0000
Table RoX-II Control Register (Register
NAME OneDev DESCRIPTION RoX-II Internal Loop Back Enable. this device only device RoX-II Ring, signals internally closed when this set. Disable Enable Memory Mode Selection. Selects Device ID=4, such AL3000. Select devices with packet memory (such AL126 AL3000), select devices with dual packet memory (such AL1022). Single buffer. Dual buffers. Memory Mode Selection Device ID=3. Select devices with packet memory (such AL126 AL3000), select devices with dual packet memory (such AL1022). Single buffer (e.g. AL126) Dual buffers (AL1022) Memory Mode Selection Device Memory Mode Selection Device Memory Mode Selection Device
HiMmode
D3Mmode
D2Mmode D1Mmode D0Mmode
10/00
Reference Only Allayer Communications
AL126 Revision
Table RoX-II Control Register (Register (Continued)
NAME HiRoute DESCRIPTION Route Selection from AL3000 (always Device this Device. Refer example above register description. Route Selection from Device this Device. Refer example above Register description.
D3Route
Port Configuration Registers Registers local port configuration. There port configurations port. Port port configuration uses register Port register etc. Uplink this six-bit link which assigns uplink port trunk. uplink local stack, format Port: [Dev_ID] [Port_ID] Trunk: [100] [Trunk_ID] CPU: [100000] Router: [100001] uplink remote stack, Stack: [101] [Stack_ID] remote stack will assign final port/trunk Note: port/trunk uplink, uplink should port/trunk frame with unlearned will then filtered.
Table Port Configuration Registers
15~10 NAME UpLinkID DESCRIPTION Uplink Associated with Port. Uplink used when unknown received register FloodCtl enable this uplink feature. 0xxyyy: Local port with DEVID PID. 110xxx: Local trunk with Trunk_ID. 100000: Local CPU. 100001: Local router. 101xxx: Remote stack uplink with Stack_ID. Others: Reserved Trunk Member Port. Individual port. This port member trunk port.
Tmember
Reserved
10/00
Reference Only Allayer Communications
AL126 Revision
Table Port Configuration Registers (Continued)
StormCTL Broadcast Storm Control Enable. Global setting register FlowCtrlBC controls whether this storm control acts multicast broadcast, just broadcast frames. register MaxStorm sets maximum allowed multicast/broadcast frames given time. Storm control disable. broadcast frame will throttled. Storm control enable. accumulated number broadcast frames input buffer port over threshold specified system configuration register, incoming broadcast frames will discarded until number been reduced below threshold. Intrusion Protection. Security control frames received from nonuplink ports. When Security AutoSec (register set, this port will disabled upon detection unknown source address. Security off. forwarding decision made about frames received from port will involve source address checking. Security Frames received from port with unknown source address with source address learned previously from another port will discarded. Local Port VLAN Membership. Non-member. Multicast/Broadcast frames received from port will forwarded local port (AL300A AL3000). Member. Multicast/Broadcast frames received from port will forwarded local port addition other member ports specified VLAN VLAN Extension register port (excluding source port). Learning Disable. This used designate port uplink port, since unmatched frames will forwarded ports with learned address. Source address from this port will learned. Source address from this port will learned. Spanning Tree Port State Control. Disable. incoming frames from will discarded; outgoing frames will masked from path PHY. Blocking-N-Listening. incoming frames except incoming BPDUs from will discarded; outgoing frames except outgoing BPDUs will masked from path PHY. Learning. source information incoming frames from will learned, incoming frames except incoming BPDUs from will discarded after being learned; outgoing frames except outgoing BPDUs will masked from path PHY. Forwarding. source information incoming frames from will learned, incoming frames will forwarded based switch routing decision; outing frames will transmitted PHY.
Security
LCPUOn
LrnDis
PortST
Reserved
10/00
Reference Only Allayer Communications
AL126 Revision
Table Port Configuration Registers
NAME Reserved PHYR6Skip Skip Check Register MDIO. IEEE compliant operation. Skips register link auto-negotiation completion. After completes, MDIO logic skips checking Expansion Register Link partner enable (register read Link Partner Ability (register immediately determine operation mode PHY. When this set, MDIO register initialized preserve control ability advertisement before initiating autonegotiation. Control ability initialized Previous value preserved. Ignore auto-complete link MDIO flow. This mode useful interfacing some PHYs 100BASE-FX (fiber). IEEE compliant operation. Skips auto-complete. Flow Control Full-Duplex (IEEE 802.3x) Enable. Flow Control Half-Duplex Enable. MDIO Configuration. 0001: Selects master mode. When AL126 this mode, will capability advertisement register. link will auto-negotiate highest capability. 0010: Selects slave mode. When AL126 this mode, will capability advertisement register. link will auto-negotiate highest capability. 0111: Selects forced mode. When AL126 this mode, will turn auto-negotiation will select link's operating mode. MDIO Disable. MDIO enabled. MDIO disabled. Force Link Status. Effective only when MDIOCfg master forced mode, when MDIODis disable. Link down. Link DESCRIPTION
PHYCTLAD
PHYACSkip
FlowCtrlFdEn FlowCtrlHdEn MDIOCfg[3:0]
MDIODis
LinkUp
10/00
Reference Only Allayer Communications
AL126 Revision
Table Port Configuration Registers
PrtCfgMode[3:0] Force Port Operation Mode. Effective only when MDIOCfg master forced mode, when MDIODis disable. PrtCfgMode[3] full-duplex. PrtCfgMode[2] half-duplex. PrtCfgMode[1] full-duplex. PrtCfgMode[0] half-duplex.
Table Port VLAN Registers
15~8 NAME Dev3Map DESCRIPTION Port VLAN corresponding port port device with DEVID Non-member port. Member port. Port VLAN corresponding port port device with DEVID Explanation same above.
Dev2Map
Table Port VLAN Registers
15~8 NAME Dev1Map DESCRIPTION Port VLAN corresponding port port device with DEVID Non-member port. Member port. Port VLAN corresponding port port device with DEVID Non-member port. Member port.
Dev0Map
10/00
Reference Only Allayer Communications
AL126 Revision
VLAN Extension Register (Register Recommended Setting: 0000 0000 0000 0000
Table VLAN Extension Register (Register
NAME P7GW7On DESCRIPTION RoX-II Ring Gateway Device VLAN Membership Port Non-member. Broadcast frames received from port will forwarded Gateway Device Member. Broadcast frames received from port will forwarded Gateway Device addition other member ports specified VLAN LCPUOn port configuration register, (excluding source port). Gateway Device VLAN Membership Port Gateway Device VLAN Membership Port Gateway Device VLAN Membership Port Gateway Device VLAN Membership Port Gateway Device VLAN Membership Port Gateway Device VLAN Membership Port Gateway Device VLAN Membership Port
P6GW7On P5GW7On P4GW7On P3GW7On P2GW7On P1GW7On P0GW7On Reserved
10/00
Reference Only Allayer Communications
AL126 Revision
Table VLAN Extension Register (Register
15~8 NAME Reserved P7GW6On P6GW6On P5GW6On P4GW6On P3GW6On P2GW6On P1GW6On P0GW6On Gateway Device VLAN Membership Port Gateway Device VLAN Membership Port Gateway Device VLAN Membership Port Gateway Device VLAN Membership Port Gateway Device VLAN Membership Port Gateway Device VLAN Membership Port Gateway Device VLAN Membership Port Gateway Device VLAN Membership Port DESCRIPTION
Register Group Port Based Trunking Registers (Registers Port Trunk Port assignment register assigns port trunk port-based load balancing trunking. Please example trunking section. port trunk port work sheet provided Appendix
PORT NUMBER
REGISTER
10/00
Reference Only Allayer Communications
AL126 Revision
Table Trunk Port Assignment Register (2F~36)
15~14 NAME Port7TP DESCRIPTION Trunk Link Trunk Port PortID represented [DEVID, TID, 00]. PortID represented [DEVID, TID, 01]. PortID represented [DEVID, TID, 10]. PortID represented [DEVID, TID, 11]. Trunk Link Trunk Port Explanation same above. Trunk Link Trunk Port Explanation same above. Trunk Link Trunk Port Explanation same above. Trunk Link Trunk Port Explanation same above. Trunk Link Trunk Port Explanation same above. Trunk Link Trunk Port Explanation same above. Trunk Link Trunk Port Explanation same above.
13~12 11~10
Port6TP Port5TP Port4TP Port3TP Port2TP Port1TP Port0TP
Register Grouping Layer Trunking (2F~33) Using registers 2F~33 defined selected trunking method register L2Trunk. L2Trunk zero (port-based trunking), then table above effective. Trunk Address based trunking), then alternate table below effective. Layer Trunking Assignment Register (Register Recommended Setting: 1111 0000 0000 1111
Table Layer Trunking Assignment Register (Register
15~8 NAME T1Member T0Member DESCRIPTION Assign Trunk Member Trunk Assign Trunk Member Trunk
10/00
Reference Only Allayer Communications
AL126 Revision
Layer Trunking Assignment Register (Register Recommended Setting: 1111 0000 0000 1111
Table Layer Trunking Assignment Register (Register
15~8 NAME T3Member T2Member DESCRIPTION Assign Trunk Member Trunk Assign Trunk Member Trunk
Layer Trunking Assignment Register (Register Recommended Setting: 1111 0000 0000 1111
Table Layer Trunking Assignment Register (Register
15~8 NAME T5Member T4Member DESCRIPTION Assign Trunk Member Trunk Assign Trunk Member Trunk
Layer Trunking Assignment Register (Register Recommended Setting: 1111 0000 0000 1111
Table Layer Trunking Assignment Register (Register
15~8 NAME T7Member T6Member DESCRIPTION Assign Trunk Member Trunk Assign Trunk Member Trunk
10/00
Reference Only Allayer Communications
AL126 Revision
Layer Trunking Protocol Register (Register Recommended Setting: 0000 0000 0000 0000
Table Layer Trunking Protocol Register (Register
15~14 NAME T7Ptcl DESCRIPTION Layer Trunk Protocol Control. 00=DA+SA crc. 01=SA crc. 10=DA crc. 11=DA+SA bits. Layer Trunk Protocol Control. Layer Trunk Protocol Control. Layer Trunk Protocol Control. Layer Trunk Protocol Control. Layer Trunk Protocol Control. Layer Trunk Protocol Control. Layer Trunk Protocol Control.
13~12 11~10
T6Ptcl T5Ptcl T4Ptcl T3Ptcl T2Ptcl T1Ptcl T0Ptcl
Test Control Register (Register Reserved Allayer's Use. Recommended Setting: 0000 0000 0000 0000
Table Testing Register (Register
15~6 NAME Reserved TypeOnly 802.3x Flow Control Frame Recognition Control. Check control frame address addition control type field. Check only control type field. DESCRIPTION
Reserved
10/00
Reference Only Allayer Communications
AL126 Revision
Test Control Register (Register Reserved Allayer's Use. This register reserved Allayer's use. recommended setting 0000 1000 0000 1100.
Table Testing Register (Register
15~12 11~10 NAME Reserved WmarkSel Reserved Backpressure Watermark Select. Backpressure available block count Backpressure available block count Backpressure available block count Test mode. Each block 2Kbyte. Reserved DESCRIPTION
Reserved
Note: Most bits this register reserved factory testing except WmarkSel bits. These bits level buffer trigger backpressure eliminate buffer overflow.
Table System Status Register (Register
NAME EPTimeOut DESCRIPTION EEPROM Time Out. EEPROM initializes device. Device ready programmed CPU. Checksum correct. EEPROM chec
Other recent searches
VCO190-1850T - VCO190-1850T VCO190-1850T Datasheet
NE552R479A - NE552R479A NE552R479A Datasheet
MW500-1502 - MW500-1502 MW500-1502 Datasheet
MAX1302 - MAX1302 MAX1302 Datasheet
MAX1303 - MAX1303 MAX1303 Datasheet
EN55022A - EN55022A EN55022A Datasheet
DLA11C - DLA11C DLA11C Datasheet
ADE-602-083B - ADE-602-083B ADE-602-083B Datasheet
2N7000KL - 2N7000KL 2N7000KL Datasheet
BS170KL - BS170KL BS170KL Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
