Supports seven 10/100 Mbit/s Ethernet ports with RMII 10/100 Mbit/s Et
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AL125 Revision Port 10/100 Mbit/s Dual Speed Fast Ethernet Switch
Supports seven 10/100 Mbit/s Ethernet ports with RMII 10/100 Mbit/s Ethernet port with MII/RMII interface Capable trunking Mbit/s link with link fail-over Full- half-duplex mode operation Supports addresses with VLAN without VLAN Scalable design stackable switch implementation RoX-II expansion link supports Gbit/s throughput Gigabit Ethernet ready with AL1022 Flexible prioritized queueing multimedia data traffic Layer switching with AL3000 RoX-II IEEE 802.3x flow control full-duplex operation Optional backpressure flow control support half-duplex operation 802.1p support with four priority levels 802.1q based port based VLAN support, VLAN table IGMP frame trapping Supports multicast groups RMON SNMP support with AL300A management (MIB) device 2.5V 3.3V operation Packaged 352-pin
AL125 eight-port 10/100 Mbit/s dual speed Ethernet switch. low-cost scalable solution 32-ports achieved through low-cost buffer memory Allayer's proprietary RoX-IIarchitecture. addition, AL125 supports port based 802.1q based VLAN, 802.1p priority, multiple port aggregation trunks.
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Switch Controller
Buffer Manager
10/100 Expansion Interface
10/100 High Speed Switch Fabric
Address Control
10/100
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Address Table
Address Table Expansion
10/100 EEPROM Interface Management Information 10/100
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Figure
System Block Diagram
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This document contains proprietary information which shall reproduced, transferred other documents, used other purpose without prior written consent Allayer Communications.
Disclaimer Allayer Communications reserves right make changes, without notice, product(s) described information contained herein order improve design and/or performance. Allayer Communications assumes responsibility liability these products, conveys license title under patent copyright these products, makes representations warranties that these products free from patent copyright infringement unless otherwise specified.
Life Support Applications Allayer Communications products designed life support appliances, systems, devices where malfunctions reasonably expected result personal injury.
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Table Contents
AL125 Overview Descriptions. Functional Description. RoX-II Interface. Data Reception. 3.2.1 3.2.2 3.2.3 3.2.4 3.3.1 3.3.2 3.3.3 Illegal Frame Length Long Frames False Carrier Events Frame Filtering. Broadcast Storm Control. Frame Transmission Frame Generation.
Frame Forwarding.
Half Duplex Mode Operation Secure Mode Operation Address Learning 3.6.1 3.7.1 3.7.2 Address Aging. Port Based VLAN Tagged VLAN. VLAN Support.
3.10 3.11
Priority Queues User Priority Support Buffer Management Queue Behavior Multicast Group Support Trunking (Port Aggregation). Port Based Trunking (Port Aggregation) Trunking (Port Aggregation)
3.11.1 3.11.2 3.12 3.13
Spanning Tree Support. Flow Control Half Duplex (Backpressure). Full Duplex Flow Control (802.3x) Special Frame Identification Trapping.
3.13.1 3.13.2 3.13.3 3.14
Queue Management
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3.14.1 3.15 3.16 3.17 3.18
Congestion Control
Uplink Port. Port Monitoring. Reduced Media Independent Interface (RMII). Management. Management MDIO Management Master Mode Management Slave Mode. Auto-negotiation Mode Other Options.
3.18.1 3.18.2 3.18.3 3.18.4 3.18.5 3.19 3.20
SGRAM Interface EEPROM Interface System Initialization Start Stop Write Cycle Timing. Read Cycle Timing Reprogramming EEPROM Configuration EEPROM
3.20.1 3.20.2 3.20.3 3.20.4 3.20.5 3.20.6 3.21
Register Descriptions
Timing Requirements. Electrical Specifications AL125 Mechanical Data. Appendix (VLAN Mapping Work Sheet) Appendix (Port Trunk Port Assignment Work Sheet) Appendix (Suggested Memory Components). Appendix (Memory Timing Requirements)
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AL125 Overview
AL125 eight-port 10/100 ethernet switch chip with RoX-II expansion interface. RoX-IIinterface Gbit/s interface (6.4 Gbit/s full-duplex). RoX-II support four switch chips management router chip. Various combinations used different configurations. maximum port configuration will 32-port Mbit/s ports 24port 10/100 Mbit/s plus Gigabit Ethernet ports, eight gigabit ports. Higher port count stacking configurations achieved with additional bridges crossbar devices. RoX-II interface supports external management device, AL300A. SNMP RMON supported through this management device. RoX-II interface also supports Layer Layer switching provided AL3000. Because AL3000 AL300A functions integrated, there need AL300A AL3000 already RoX-II bus. following diagram shows 24+2G managed L3/4 router switch supported AL125, AL1022, AL3000.
Memory
32-bit Microprocessor
Ring
AL300A AL3000
AL125
AL125
AL125
AL1022
Figure
24+2G Managed Routing Switch
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AL125 provides eight 10/100 Mbit/s Ethernet ports with each port supporting both Mbit/s data rate. operation mode auto-negotiated through PHY. AL125 also supports trunking applications. chip provides optional load balancing schemes, explicit dynamic. With trunking, possible group eight full-duplex links together form single 1600 Mbit/s link. device also supports current IEEE 802.3ad specification. Data received from interface stored external memory buffer. AL125 utilizes cost effective SGRAM provide 8-Mbit 16-Mbit buffer memory. AL125 provides flow control methods. half-duplex operations, optional jamming based flow control (also known backpressure) available prevent loss data. With this method flow control, switch will generate signal when receive-buffer full. full-duplex mode, AL125 utilizes IEEE 802.3x flow control mechanism. ports support multiple addresses. switch chip supports addresses with VLAN without VLAN through external SSRAM. managed switch applications, AL125 supports network management through network management option. When management option enabled, network statistics each port gathered sent across RoX-II bus. management information base chip will collect store data network management agent. Access statistic counters provided interface AL300A. AL125 operates only store forward mode. entire frame checked errors frames with errors automatically filtered forwarded destination port. device also provides multicast group addresses multicast applications. AL125 perform IGMP frame trapping forward them CPU. This allows participate IGMP protocol determine which ports should participate multicast session. switch initialized configured external EEPROM. unmanaged switch design, there need CPU. parallel interface utilized reprogram EEPROM field reconfiguration. device supports port based tagged VLAN (IEEE 802.3ac/802.1q VLAN) workgroup segment switching applications. AL125 supports 802.1p with four levels priority queues. Relative priority controlled either programmable weighted round robin strict priority. device also provides levels security intrusion protection. Security implemented per-port basis. Other features include port monitoring broadcast storm filtering reduce broadcast traffic through switch.
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Diagram
Figure
Diagram (Top View)
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RICLK EEDIO PBWEN PBA0 PBA4 PBA8_9 ETD6 ETD2 ETA14 PBD3 PBD7 PBD19 PBD23 PBD11 PBD15 PBD27 PBD30 M7RXD0
Figure
M7RXD1 EECLK PBCS# SYSCLK PBA1 PBA5 ETD9 ETD5 ETD1 PBD0 PBD4 PBD16 PBD20 PBD8 PBD12 PBD24 PBD28 PBD31 M0CRS PBCAS# PBRAS# PBA2 PBA6 ETD8 ETD4 ETD0 PBD1 PBD5 PBD17 PBD21 PBD9 PBD13 PBD25 PBD29 M7TXD1 M7TXD0 M7TXEN M0TXD1 M0TXD2 PBA9_10 PBA3 PBA7 ETD7 ETD3 ETA15 PBD2 PBD6 PBD18 PBD22 PBD10 PBD14 PBD26 ETA2 ETA1 ETA0 M7CRS M0RXER M0TXCLK M0TXEN VDD25 VDD33 VDD25 VDD33 VDD33 VDD25 VDD33 VDD25 ETA6 ETA5 ETA4 ETA3 M0RXD2 M0RXD3 M0RXDV VDD25 VDD33 VDD33 VDD25 ETA10 ETA9 ETA8 ETA7 ETADVN# M0RXD0 VDD25 VDD25 VDD25 VDD25 TESTO ETA13 ETA12 ETA11 ETGW# ETCLKI ETOEB VDD33 VDD33 VDD33 VDD33 ROD29 ROD30 ROD31 PBCLKI ETD13 ETD12 ETD11 VDD25 VDD25 ROD25 ROD26 ROD27 ROD28 RID30 RID31 ETD15 VDD33 VDD33 ROD22 ROD23 ROCLK ROD24 RID26 RID27 RID28 VDD33 VDD33 M6RXD0 ROD19 ROD20 ROD21 RID22 RID23 RID24 VDD25 VDD25 M6TXD1 M6TXD0 M6TXEN M6RXD1 M1TXD1 M1CRS RID20 VDD33 VDD33 VDD33 VDD33 ROD16 ROD17 ROD18 M6CRS M1RXD0 M1RXD1 M1TXEN VDD25 VDD25 VDD25 VDD25 ROD12 ROD13 ROD14 ROD15 RID16 RID17 RID18 VDD25 VDD33 VDD33 VDD25 ROD8 ROD9 ROD10 ROD11
PBANC_8
M0COL
M0TXD3
M0TXD0
AL125 Information
M0RXCLK
M0RXD1
ETADSC#
ETD10
ETD14
RID29
RID25
RID21
M1TXD0
RID19
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RID12 RID13 RID14 VDD25 VDD33 VDD25 VDD33 VDD33 VDD25 VDD33 VDD25 RID8 RID9 RID10 RID0 RICTL5 RICTL1 RI2CTL4 RI2CTL0 DEVID0 M3TXEN M4CRS M4RXD1 EPBYPASS RO2CTL3 ROCTL0 RID5 RID6 RID3 RIDH RICTL4 RICTL0 RI2CTL3 M3CRS M3RXCLK M4TXD1 M4RXD0 RO2CTL0 ROCTL4 ROCTL1 M2CRS M2RXD1 RID2 RICTL7 RICTL3 RICTLH RI2CTL2 MDIO M3TXD1 M3RXD1 M4TXD0 RESET# RO2CTL1 RO2CTL5 ROCTL2 M2TXEN M2RXD0 RID1 RICTL6 RICTL2 RI2CTL5 RI2CTL1 DEVID1 M3TXD0 M3RXD0 M4TXEN TESTMODE RO2CTL2 ROCTLH ROCTL3
RID15
RID11
ROD4
ROD5
ROD6
ROD7
RID7
ROCTL4
M5RXD1
M5RXD0
ROD3
RID4
ROCTL5
RODH
M5TXEN
VDD33
M2TXD1
ROCTL6
ROD0
ROD2
M5TXD0
M2TXD0
ROCTL7
ROD1
M5CRS
M5TXD1
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Descriptions
AL125 supports RMII interface Ports through RMII Port When RMII interface used; TXD3 TXD2 should left unconnected; RXD3, RXD2, TXCLK, RXDV, RXER, should pulled high low; RXCLK0 RXCLK3 should connected reference clock. date control signals clocked in/out rising edge reference clock RMII mode.
Table RMII/MII Interface (Port
NAME M0TXD3 M0TXD2 M0TXD1 M0TXD0 DESCRIPTION Transmit Data (MII Mode) data transmitted transceiver. Signal M0TXEN M0TXD0 through M0TXD3 clocked rising edge M0TXCLK. Transmit Data (RMII Mode) M0TXD1 M0TXD0 clocked RMII reference clock M0RXCLK. During reset, these pins input mode read device existence information. Leave floating used. Transmit Enable Synchronous transmit clock mode. RMII mode, M0TXEN synchronous M0RXCLK. Transmit Clock Input. Mbit/s Mbit/s. (Not used RMII mode). Receive Data data from transceiver. interface, signal M0RXDV, M0RXER M0RXD0 through M0RXD3 sampled rising edge M0RXCLK. RMII mode, M0RXD3 M0RXD2 used. M0RXD1and M0RXD0 sampled rising edge RMII reference clock M0RXCLK. Receive Data Valid. Active high. Receive Clock (MII mode). RMII clock port Receive Data Error. Active high. (Not used RMII mode). Carrier Sense. Active high. Collision Detect. Active high. (Not used RMII mode).
M0TXEN
M0TXCLK
M0RXD3 M0RXD2 M0RXD1 M0RXD0
M0RXDV M0RXCLK M0RXER M0CRS M0COL
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Table RMII Interface (Port
NAME M1TXD1 M1TXD0 DESCRIPTION Transmit Data data transmitted transceiver. Signal M1TXEN, M1TXD0 M1TXD1 clocked rising edge M3RXCLK. Transmit Enable Synchronous M3RXCLK. Receive Data data from transceiver. Signal M1RXD0 M1RXD1 sampled rising edge M3RXCLK. Carrier Sense. Active high.
M1TXEN M1RXD1 M1RXD0 M1CRS
Table RMII Interface (Port
NAME M2TXD1 M2TXD0 DESCRIPTION Transmit Data data transmitted transceiver. Signal M2TXEN, M2TXD0 M2TXD1 clocked rising edge M3RXCLK. Transmit Enable Synchronous M3RXCLK. Receive Data data from transceiver. Signal M2RXD0 M2RXD1 sampled rising edge M3RXCLK. Carrier Sense. Active high.
M2TXEN M2RXD1 M2RXD0 M2CRS
Table RMII Interface (Port
NAME M3TXD1 M3TXD0 DESCRIPTION Transmit Data data transmitted transceiver. Signal M3TXEN, M3TXD0 M3TXD1 clocked rising edge M3RXCLK. Transmit Enable Synchronous M3RXCLK. Receive Data data from transceiver. Signal M3RXD0 M3RXD1 sampled rising edge M3RXCLK.
M3TXEN M3RXD1 M3RXD0
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Table RMII Interface (Port (Continued)
NAME M3RXCLK M3CRS DESCRIPTION RMII Clock Port 1~7. Carrier Sense. Active high.
Table RMII Interface (Port
NAME M4TXD1 M4TXD0 DESCRIPTION Transmit Data data transmitted transceiver. Signal M4TXEN, M4TXD0 M4TXD1 clocked rising edge M3RXCLK. Transmit Enable Synchronous M3RXCLK. Receive Data data from transceiver. Signal M4RXD0 M4RXD1 sampled rising edge M3RXCLK. Carrier Sense. Active high.
M4TXEN M4RXD1 M4RXD0 M4CRS
Table RMII Signal (Port
NAME M5TXD1 M5TXD0 DESCRIPTION Transmit Data data transmitted transceiver. Signal M5TXEN, M5TXD0 M5TXD1 clocked rising edge M3RXCLK. Transmit Enable Synchronous M3RXCLK. Receive Data data from transceiver. Signal M5RXD0 M5RXD1 sampled rising edge M3RXCLK. Carrier Sense. Active high.
M5TXEN M5RXD1 M5RXD0 M5CRS
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Table RMII Interface (Port
NAME M6TXD1 M6TXD0 DESCRIPTION Transmit Data data transmitted transceiver. Signal M6TXEN, M6TXD0 M6TXD1 clocked rising edge M3RXCLK. Transmit Enable Synchronous M3RXCLK. Receive Data data from transceiver. Signal M6RXD0 M6RXD1 sampled rising edge M3RXCLK. Carrier Sense. Active high.
M6TXEN M6RXD1 M6RXD0 M6CRS
Table RMII Interface (Port
NAME M7TXD1 M7TXD0 DESCRIPTION Transmit Data data transmitted transceiver. Signal M7TXEN, M7TXD0 M7TXD1 clocked rising edge M3RXCLK. Transmit Enable Synchronous M3RXCLK. Receive Data data from transceiver. Signal M7RXD0 M7RXD1 sampled rising edge M3RXCLK. Carrier Sense. Active high.
M7TXEN M7RXD1 M7RXD0 M7CRS
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Table RoX-II Input Interface
NAME RID31 RID30 RID29 RID28 RID27 RID26 RID25 RID24 RID23 RID22 RID21 RID20 RID19 RID18 RID17 RID16 RID15 RID14 RID13 RID12 RID11 RID10 RID9 RID8 RID7 RID6 RID5 RID4 RID3 RID2 RID1 RID0 RIDH RICTL7 RICTL6 RICTL5 RICTL4 RICTL3 RICTL2 RICTL1 RICTL0 RICTLH DESCRIPTION
Ring Data Input.
Ring Data Header Input. High duration data, when idle. Ring Control Input.
Ring Control Header Input. Low/high each part control data word, high when idle.
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Table RoX-II Input Interface (Continued)
NAME RICLK RI2CTL5 RI2CTL4 RI2CTL3 RI2CTL2 RI2CTL1 RI2CTL0 DESCRIPTION Ring Clock. RICTL clocked rising edge RICLK. Second Ring Control Input.
Table RoX-II Output Interface
NAME ROD31 ROD30 ROD29 ROD28 ROD27 ROD26 ROD25 ROD24 ROD23 ROD22 ROD21 ROD20 ROD19 ROD18 ROD17 ROD16 ROD15 ROD14 ROD13 ROD12 ROD11 ROD10 ROD9 ROD8 ROD7 ROD6 ROD5 ROD4 ROD3 ROD2 ROD1 ROD0 DESCRIPTION
Ring Data Output.
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Table RoX-II Output Interface (Continued)
RODH ROCTL7 ROCTL6 ROCTL5 ROCTL4 ROCTL3 ROCTL2 ROCTL1 ROCTL0 ROCTLH Ring Data Header Output. High duration data, when idle. Ring Control Output.
Ring Control Header Output. Low/high each part control data word, keep high when idle. Ring Clock. ROCTL clocked rising edge SYSCLK. ROCLK delayed version SYSCLK drive RICLK next device. Second Ring Control Output.
ROCLK
RO2CTL5 RO2CTL4 RO2CTL3 RO2CTL2 RO2CTL1 RO2CTL0
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Table SGRAM Interface
NAME PBD31 PBD30 PBD29 PBD28 PBD27 PBD26 PBD25 PBD24 PBD23 PBD22 PBD21 PBD20 PBD19 PBD18 PBD17 PBD16 PBD15 PBD14 PBD13 PBD12 PBD11 PBD10 PBD9 PBD8 PBD7 PBD6 PBD5 PBD4 PBD3 PBD2 PBD1 PBD0 PBA9_10 DESCRIPTION
SGRAM Data Bus.
This connected address when connected Mbit/s SGRAM address when connected Mbit/s SGRAM. This should connected SGRAMs. This connected address when connected Mbit/s SGRAM address when connected Mbit/s SGRAM. This should connected SGRAMs. This connected address when connected Mbit/s SGRAM unconnected when connected Mbit/s SGRAM. This should connected SGRAMs.
PBA8_9
PBANC_8
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Table SGRAM Interface (Continued)
NAME PBA7 PBA6 PBA5 PBA4 PBA3 PBA2 PBA1 PBA0 PBCS# PBRAS# PBCAS# PBWE# PBCLK DESCRIPTION These pins connected SGRAM address through respectively.
Chip Select. enables disables command decoder SGRAM. SGRAM Address Strobe. SGRAM Column Address Strobe. Write Enable. System Clock Output Drive SGRAM.
Table External Address Table SSRAM Interface
NAME ETD15 ETD14 ETD13 ETD12 ETD11 ETD10 ETD9 ETD8 ETD7 ETD6 ETD5 ETD4 ETD3 ETD2 ETD1 ETD0 DESCRIPTION
SSRAM Data Bus.
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Table External Address Table SSRAM Interface (Continued)
NAME ETA15 ETA14 ETA13 ETA12 ETA11 ETA10 ETA9 ETA8 ETA7 ETA6 ETA5 ETA4 ETA3 ETA2 ETA1 ETA0 ETADSC# ETADV# ETGW# ETOE# ETCLK DESCRIPTION
SSRAM Address Line.
Synchronous Address Status Controller. Synchronous Address Advance. Used advance SRAMs internal burst counter. Global Write Enables full 32-bit write. Output Enable. Active low. This enables output driver. System Clock Output Drive SSRAM.
Table EEPROM Interface
NAME EEDIO NUMBER DESCRIPTION EEPROM Data Input Output Boot-up. Data input output reverse EEDIO. Tri-stated after boot-up, external pull-up. EEPROM Clock, Output boot-up. Clock input reverse EEDIO. Tri-stated after boot-up, external pull-up.
EECLK
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Table MDIO Interface
NAME MDIO NUMBER DESCRIPTION Management Clock. Management Data Input Output.
Table Miscellaneous Pins
NAME DEVID1 DEVID0 NUMBER DESCRIPTION Device Number. Should connected EEPROM AL125 will ID1, ID0> EEPROM address respond ID1, ID0> reverse EEDIO. Reset Test Mode Pin. This should grounded normal operation. Left Unconnected. Status Serial Output (for testing). EEPROM Setup Bypass. This should tied ground. System Clock. Connected.
RESET# TESTMODE TEST0 EPBYPASS SYSCLK
B19,
Table Power Interface
NAME VDD1 VDD2 NUMBER E12, E14, F14, G15, G16, J16, M16, P15, P16, R14, T12, E10, E11, E13, F13, H15, H16, K16, L16, N15, N16, R13, T10, T11, T13, V20, E15, E16, F10, F11, F12, F15, F16, J10, J11, J12, J15, K10, K11, K12, K15, L10, L11, L12, L15, M10, M11, M12, M15, R10, R11, R12, R15, R16, T15, DESCRIPTION Supply Voltage. Supply Voltage. Ground
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Functional Description
RoX-II Interface
switch system 24-port 10/100 Mbit/s switch with Gigabit Ethernet ports. This system utilizes Allayer's proprietary RoX-II architecture, which improved version original ring structure. RoX-II higher bandwidth built-in Layer capabilities. RoX-II ring composed data ring control ring. data ring used transfer frame data, events, well system configuration status report messages. control ring used communicate RoX-II ring protocol messages among devices switch backbone resources data transfer data ring. Each device ring input interface receiving data frames ring protocol messages from upstream device, output interface transmitting data frames ring protocol messages downstream device. management device (MIB) AL300A, resides RoX-II ring. provides network management functions devices ring. device collects network statistics switch system well provides system configuration devices. interface provided device. This supporting chip, AL300A, provides full statistical counters support both SNMP RMON network management.
Data Reception
port will into receive-state when RX_DV interface asserted. presents received data four-bit nibbles that synchronous receive clock MHz). AL125 will then attempt detect occurrence Start Frame Delimiter, (SFD 10101011), pattern. preamble data prior discarded. Once detected, Frame Check Sequence (FCS) verified, frame data forwarded stored buffer switch. 3.2.1 Illegal Frame Length During receiving process, will monitor length received frame. Legal Ethernet frames should have length less than bytes more than 1536 bytes. frames with illegal frame length discarded. 3.2.2 Long Frames AL125 handle frames 1536 bytes. frames longer than 1536 bytes will discarded. port continues receive data after 1536th byte, port's data will filtered. port half-duplex mode, port will longer able transmit receive data during long frame reception. 3.2.3 False Carrier Events carrier sense signal (CRS) interface asserted receive data valid (RX_DV) signal asserted within 16BT, port considered have false carrier event. false carrier event recorded counter.
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3.2.4 Frame Filtering AL125 will make filtering forwarding decisions each frame received, based frame routing table, VLAN mapping, port state, system configuration. Under following conditions, received frames filtered. AL125 will check received frames errors such symbol error, error, short event, runt, long event, etc. Frames with kind error will forwarded their destination port. frame heading source port will filtered. Frames heading disabled receiving port will filtered. input buffer port full, incoming frame will discarded. recommended that flow control used prevent loss data. flow control option enabled, this event will occur. remote station will transmit frames when input buffer becomes available. frame security violation, while security option enabled receiving port. Spanning Tree Protocol enabled, AL125 will forward frame below. port Block-N-Listen state Learning state, frame forwarded when BPDU frame, frame discarded otherwise. port Forwarding State, frame forwarded when BPDU frame.
Frame Forwarding
After frame received, source address (SA) destination address (DA) retrieved. used update port's address table described previously used determine frame's destination port. Address Lookup Engine will attempt match destination address with addresses stored address table. there match found, link between source port destination port then established. first destination address "0," frame regarded unicast frame. destination address passed Address Lookup Engine which returns matched destination port number identify which port frame should forwarded destination port within same VLAN receiving port, frame will forwarded. destination port does belong VLANs specified receiving port, frame will discarded. event will recorded VLAN boundary violation. particular VLAN null membership, frames discarded well. There ways that AL125 handles frames with unknown destination. forwarding decision controlled Flood Control Option (System Configuration Register 00). Flood Control disabled, frame will forwarded ports (except receiving port) within same VLANs receiving port. Flood Control option enabled, AL125 will forward frame only uplink port specified receiving port.
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Note: AL125 defines port either single port trunk, consistent with IEEE 802.3ad Port Aggregation Standard. port monitoring function enabled, frame forwarding decision also subject port monitoring configurations. first destination address "1," frame will handled multicast broadcast frame. AL125 does differentiate multicast frames from broadcast frames, except with following reserved bridge management group addresses, specified table IEEE 802.1d standard; GARP, IGMP, IEEE 802.3ad Port Aggregation control frames. Additionally, IEEE 802.3x Flow Control control frames handled inside AL125 never forwarded other device, including CPU. destination ports broadcast frame ports within same VLAN except source port itself. Multicast/Broadcast frame trapping (MCtrap) enabled, multicast/broadcast frames will forwarded only. 3.3.1 Broadcast Storm Control unique features provided AL125 Broadcast Storm Control. This option allows user limit number broadcast frames into switch. This option implemented per-port basis. threshold number broadcast frames programmed register When Storm Control enabled number cumulated non-unicast frames over programmed threshold, broadcast frame discarded. Storm Control disabled number non-unicast frames received port over programmed threshold, AL125 will forward frame ports (except receiving port) within VLANs specified receiving port. port within specified VLAN, frame will also forwarded CPU. Broadcast-Storm-drop (BConly_SC) enabled, AL125 will only drop broadcast frames multicast frames. 3.3.2 Frame Transmission AL125 transmits frames accordance with IEEE 802.3 standard. AL125 will send frames with guaranteed minimum inter-frame 96BT, even when received frames have less than minimum requirement. AL125 also supports transmission frames with 64BT (optional). 3.3.3 Frame Generation During transmit process, frame data read from memory buffer forwarded destination port's device nibbles. Seven bytes preamble signal (10101010) will generated first before (10101011) frame data sent, which then followed four bytes FCS.
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Summary Programmable Control Transmit Receive control transmit receive per-port basis. options programmable Port Configuration Register (registers 1C). Data Rate Duplex Mode this option per-port option. Typically, speed auto-negotiated. manual over-ride, appropriate port configuration register programmed. Flow Control flow control implemented independently per-port basis. AL125 uses backpressure half-duplex flow control IEEE 802.3x full-duplex flow control. Flood Control AL125 provides modes unmatched address forwarding. flood-to-all option elected, AL125 will forward unmatched frames ports. Secure Mode security option implemented per-port basis. When port configured secured mode, security violation will disable port. security violation defined frame without matched secured port's address table.
Half Duplex Mode Operation
true CSMA/CD (half-duplex) operation, logic will abort transmit-process collision detected through assertion collision (COL) signal MII. Retransmission frame scheduled accordance IEEE 802.3's truncated binary exponential backoff algorithm. transmit process encountered consecutive collisions, excessive collision error reported, resulting frame dropped unless retry-onexcessive-collision (UltraMAC) option enabled. AL125 provides non-standard options collision handling. SuperMAC mode Register System Configuration Register provides more aggressive back-off where back-off limit three rather than ten. This will create more aggressive channel capture behavior than standard IEEE back-off algorithm. There well-known anomaly channel capture effect, where top-talker CSMA/CD network capture significant percentage available bandwidth. AL125 provides nonstandard mode, Binary Exponential Backoff Select, selected System Configuration Register III, that uses binary back-off algorithm rather than standard exponential back-off algorithm. Please refer Flow Control section this data sheet backpressure option half-duplex mode operation.
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Secure Mode Operation
AL125 provides security support per-port basis. Whenever secure mode enabled, register through Port Configuration Register port will stop learning addresses address table each port will remain unchanged (i.e. frame aging function, enabled, address learning function, disabled). AL125 provides levels security protection. most severe intrusion protection disabling port experiencing intrusion. AutoSec mode, Register System Configuration Register when enabled, disables port frame with unlearned received secured port (security violation). Once port disabled, only enabled network management. Security management global option. alternative enable security local port level without security management. When AL125 configured this way, device will only discard frames that have security violations which will prevent intruders from accessing network. Summary Programmable Registers AutoSec (register this sets global security management option. AL125 will partition port that experiences security violation. Security (register this port configuration option. When this option enabled, port secured. When port receives security violation frame will discard frame disable port security management
Address Learning
table lookup engine provides switching information required route data frames. address lookup table through auto address learning (dynamic) manual entry (static). static addresses assigned address table EEPROM management device. static address entries will aged updated AL125. After frame received AL125, embedded source address (SA) destination addresses (DA) retrieved. source address retrieved from received frame automatically stored buffer. AL125 will then check errors security violations, perform search. there error security violation, chip will store source address address lookup table. been previously stored another port's table, AL125 will delete from previously stored location. Individual Address 48-bit unique address programmed learned. will masked, i.e. multicast AL125 provides on-chip Address-To-PortID/TrunkID table with entries frame destination lookup operations. Optional external SRAM used increase number address lookup 16K. (Note: When 802.1q VLAN support enabled QEnable mode, number internal address support reduced 0.5K, external table reduced 12K). AL125 address table contains both static addresses input EEPROM dynamically learned addresses. learns individual addresses from three different sources. Frames received with errors from local ports.
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Frames forwarded from other devices through ring device. Address Table Convergence message received from other switching devices ring. (TCNVG mode, Register System Configuration Register controls this function. IEEE 802.1d compliance, this mode should enabled). received frame contains source address that already been learned another port's address table aged (e.g. station moved from port another port switch), will perform following operation based switch's configuration. security option selected port, AL125 will consider this security violation. port non-protected port, AL125 will delete from previous port's address table update current port's address table. However, static address entry, address will updated.
3.6.1 Address Aging port's address register cleared power-up, hardware reset. aging option enabled, dynamically learned will cleared refreshed less than programmed time. AL125 address aging enabled AgeEN, (Register System Configuration Register, 12). Summary Programmable Options Address Learning Address Aging Time address aging aging time programmed System Configuration (MaxAge, bits 15~9, register 01). resolution normal address aging 5.36 seconds seconds with system clock. SlowAge (register programmed "1," resolution 10.72 seconds 13.4 seconds with system clock. Static Programmed Addresses twenty static addresses programmed EEPROM address Further static addresses programmed AL300A management engine. EEPROM section this document, AL300A data sheet more detail.
VLAN Support
AL125 supports both Port Based VLAN, where VLAN membership determined port assignment, IEEE 802.1q (and IEEE 802.3ac) Tagged VLAN, where VLAN membership determined dynamically VLAN VID) embedded Tag. IEEE 802.1q tagged VLAN mode enabled QEnable (Register System Configuration IV). 3.7.1 Port Based VLAN Each port AL125 assigned multiple VLANs. Frames from source port will only forwarded destination ports within same VLAN domain. broadcast/multicast frame will forwarded ports within VLAN(s) source port except source port itself. unicast frame will forwarded destination port only destination port
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same VLAN source port. destination port belongs another VLAN, frame will discarded event will recorded VLAN boundary violation. Each port should assigned with dedicated uplink port. Unicast frames with unknown destination addresses will forwarded uplink port source port. uplink port either single port trunk. AL125 provides VLAN register ports (register mapping ports bits). Each register contains 16-bits (total bits) indicate VLAN group port. VLAN registers hold broadcast destination mask each source port. will indicate broadcast frames will forwarded from source port specified port. Note that source port must within source port VLAN, because broadcast frames must forwarded source port. trunked ports (aggregated group) must belong same VLAN. setting VLAN trunking, please section trunking detail. Port VLAN Example VLAN worksheet provided Appendix Simply marking ports wish send broadcast frame complete VLAN easily. Let's assume want VLAN groups sixteen port switch. Group consists 8,10, Group consists Note: might easier mark VLAN ports first then delete source ports that don't want broadcast frames returned 3.7.2 Tagged VLAN While port based VLAN widely used industry, there standard that governs implementation. IEEE 802.3q/802.3ac standard specifies based VLAN. AL125 also supports this standard compliant based VLAN. AL125 supports full (VLAN Identification) tag, eight user priority values tag, preserves state bit. ports membership each VLAN value dynamically determined received frame. frame tagged, then default VLAN received port used determine membership. Each VLAN entry consist VID, VLAN membership ports RoX-II Bus, untag behavior each port. Please refer AL300A Data Sheet more information. VLAN searches performed AL125 hardware with external SSRAM, while table entry each active pre-programmed through indirect resource access registers (register 0x43 0x47), accessible from AL300A reverse EEDIO. following table shows entry format mapping into indirect access registers.
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bits) IRAD5, 0000_0000_0000 0000_0000_0001 0000_0000_0010 1111_1111_1111
bit)
bits) IRAD4,
bits) IRAD3, TTTT_TTTT TTTT_TTTT TTTT_TTTT
bits) IRAD2, TTTT_TTTT TTTT_TTTT TTTT_TTTT
bits) IRAD1, TTTT_TTTT TTTT_TTTT TTTT_TTTT
Used (Priority-Only Tag) TTTT_TTTT TTTT_TTTT TTTT_TTTT
VLAN entry, bits ("T") each physical port ports) will define "action" packet with that that port. corresponding actions are: "00" drop packet, "01" pass packet without change, "10" packet tagged, then with ingress port default VID), "11" untag packet tagged, then untag). ("M") will define whether management port VLAN; will allow packet forwarding management from that VLAN, will not. tagging/untagging performed frame sending management CPU. VLAN entries indirect resource access command, issued from AL300A management device reverse EEDIO interface. Five indirect access data registers should diagram above, IRAD[4:1] contains action bitmap device[3:0], IRAD5= 2*(zzzzzzzzzzzz)+M, where "zzzzzzzzzzzz" 12-bit management bit. Indirect access command register, IRAC, should 0x7000 VLAN table writing. IRAC should after IRAD[5:1]. reserved priority-only tagged frame, treated frame untagged VLAN membership rules (priority field still used selecting proper priority queue). value 0FFF reserved IEEE 802.1 future use, although AL125 does treat VID=0FFF special way. default priority assigned each source port physical ports, plus management port) default incoming frames that port. lookup performed input port tag/untag operation performed output port, 32+1 default tags have programmed each AL125 device through default registers (registers 0x4E 0x6E).
Priority Queues User Priority Support
IEEE 802.1p user priority value used queue frame particular priority queue. AL125 supports total four priority queues complete controls manage these queues. User priority value arbitrarily mapped four prioritized queues programming register Priority Queue Assignment Register. This register maps each user priority numbers four AL125 priority queues. Even with tagged VLAN
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mode disabled (QEnable de-asserted), user priorities field still used priority queuing. Four priority queues serviced Weighted Round Robin Strict Priority mode. This mode controlled PQWRREn, (Register System Configuration Register III, When Strict Priority mode enabled, frames Queue serviced until queue empty, followed Queue While servicing lower priority queues, higher priority queue empty, higher priority queue serviced until empty. busy network, lower priority queues could starved. When Weighted Round Robin mode enabled, relative priority each queue programmed Register Priority Queue Weighted Round-Robin Control Register. Each queue serviced, average, relative integer value each queue. higher value means queue serviced higher frequency than lower value queue. weight zero special meaning because queue with zero value acts lowest priority queue even with Weighted Round Robin mode enabled. This means that other queues must empty before queue with zero weight serviced.
Buffer Management Queue Behavior
AL125 offers complete controls manage congestion real-time multimedia traffic. Each output port queue depth trigger programmable threshold, upon reaching this threshold, certain action taken. This includes dropping frames destined this congested port particular priority queue. Queue depth control port queue. These modes operation controlled Register Output Queue Management Register When both Queue Port Maximum limit control enabled, then selected action taken when maximum queue depth reached. instance, Queue used voice traffic, where desirable drop voice packets rather than deliver ones sustained congestion, Queue would programmed with Q2MaxLimEn well MaxLimEn ports. Maximum queue depth programmable each queue (that used ports) Register Output Queue Management Register action taken controlled MaxDrop, Register Output Queue Management Register When MaxDrop enabled, frames dropped respective queue when MaxLim reached. When MaxDrop disabled, frames kept input buffers input port backpressures once input buffer full. AL125 also maintains dedicated multicast queue outgoing multicast frame parking. transmit frame from sources, local from another device RoX-II ring. output queue, source selected multicast queue, device will channel copy frame head multicast queue output queue transmission.
3.10 Multicast Group Support
With management CPU, AL125 support multicast specified RFC1112. AL125 will trap IGMP (internet group management protocol) frames going CPU, will setup AL125 multicast forwarding table, based multicast group information resolved from IGMP protocol. After table initialization, AL125 will forward IPMC frames related ports only, instead ports. AL125 supports possible multicast addresses, although only active multicast groups supported simultaneously
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hardware. Since AL125 performs multicast search based full 48-bit address, also support private multicast groups other than standard IPMC. Both table entry multicast group bitmap entry needs AL125 initialize multicast group. entry formatted <IPMC address: 01-00-5e-xx-xxxx><IPMC index>, IPMC table entry formatted <IPMC index><Port bitmap>. It's CPU's responsibility assign maintain IPMC index. Both table IPMC table indirect resource access command issued from AL300A management device reverse EEDIO interface. IPMC index IRAD5 0x6800 IRAC. Setting IPMC address table exactly same setting entry, only IPMC index instead port number into IRAD1.
3.11 Trunking (Port Aggregation)
AL125 offers alternative Port Aggregation methods. Port Based Trunking backward compatible Allayer's family switches (AL100 AL116 series switches) allows direct mapping ingress traffic particular port trunk (aggregation) group. Layer Trunking IEEE 802.3ad Port Aggregation standard implementation with enhanced automatic load balancing algorithm. These mode trunking methods mutually exclusive, selected L2Trunk, Register System Configuration Register 3.11.1 Port Based Trunking (Port Aggregation) AL125 supports trunking/port aggregation. Port aggregation trunking basically method treat multiple physical links single logical link. benefit trunking able group multiple lower speed links into higher speed link. example, four full-duplex Fast Ethernet ports Mbit/s links used single 800-Mbit/s link. This very useful switch switch, switch server, switch router applications. AL125 considers trunk single port entity regardless trunk composition. four ports grouped together single trunk link port based trunking. grouping ports trunk must from ports same device. total trunks device supported. multiple link trunk, links within trunk should have equal amount traffic order achieve maximum efficiency. requirements transmission that frames being transmitted must order. Therefore, some sort load balancing among links trunk deployed. 3.11.1.1 Load Balancing port based load balancing method explicit port assignment scheme. requires each individual port assigned specific link (trunk port) trunk. port assigned, frames might forwarded trunk random this could cause frames order. port based load balancing trunk two, three, four-port trunk. During transmit, frame will forwarded from source port assigned trunk port. When frame received from trunk ports, forwarded destination port within VLAN. essence, AL125 treats trunk single port within same VLAN. traffic ports evenly distributed among trunk ports, load balancing achieved aggregate bandwidth trunk high Mbit/s (full-duplex).
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3.11.1.2 Trunk Configuration Trunk group configuration accomplished through programming configuration registers. AL125 also provide capability trap IEEE 802.3ad frames allow configure aggregated links based IEEE recommended protocol exchange. 3.11.1.3 Trunk Port Assignment maximum number trunks Allayer's RoX-II architecture eight. Port Configuration Registers provide ability designate port member trunk. trunk consist four trunk ports. trunk group must consist either four ports bottom four ports. example, trunk consist either port port Each trunk port's number sequence corresponding order port devices. example, port (See Figure
AL125
Ports
Trunk Port
Trunk Port
Figure
Trunk Port Numbering
3.11.1.4 Port Based Trunk Load Balancing port-based load balancing, trunk port must assigned each port defined trunks. port assignment done programming Port Trunk Port Registers 34). port assignment worksheet provided Appendix recommended that ports evenly distributed among trunk ports prevent overloading single trunk port. following procedure trunk. Select trunk ports using Port Configuration Registers Assign ports Trunk Port Register 36). port should assigned appropriate trunk using this register. trunk port itself, port assignment should assigned itself. port trunk port worksheet provided Appendix Assign port trunk port port trunk port register. This necessary because each port group trunk must assigned trunk port. assigning trunk port itself, broadcast frames will sent back source port. Assign ports trunk port same VLAN using register
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port VLAN grouping should only include trunk port assigned other trunk ports. This ensure that broadcast frames will only forwarded assigned port. Port Based Trunking Load Balancing Example Note: specific bits register reference "X.Y" notation, where register number number. following procedure design eight-port switch with three-port trunk. desired trunk ports Therefore, port configuration register bits 17.9, 19.9, 1B.9 want assign port trunk port port trunk port port trunk port trunk ports therefore trunk number assignment port trunk port register bits should therefore 2F.3= 2F.2= 30.3= 30.2= 31.3= 31.2= 32.3= 32.2= 33.3= 33.2= trunk ports, trunk ports should assigned with their port number port trunk port register. port trunk port bits should 34.3= 34.2= 35.3= 35.2= 36.3= 36.2= Assigning VLAN. VLAN should assigned shown. bits while bits 1E.6 1E.7 because port assigned port other ports similarly. Bits through reserved should VLAN mapping registers. Appendix provide work sheets port trunk port VLAN assignment.
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Table VLAN Mapping Port Based Load Balancing Trunk
PORT 6/REG. PORT 7/REG. PORT 0/REG. PORT 1/REG. PORT 2/REG. PORT 3/REG. PORT 4/REG. PORT 5/REG.
PORT
3.11.2 Trunking (Port Aggregation) Trunking automatically load-balances among member ports through unique statistical methods, provides link resiliency (link-fail-over function) when more links trunk group fails. Trunking selected L2Trunk, Register System Configuration Register 3.11.2.1 Trunk Configuration Trunk (Port Aggregation) configuration accomplished through programming configuration registers. AL125 provides capability trap IEEE 802.3ad frames allows configure aggregated links based IEEE recommended protocol exchange. 3.11.2.2 Trunk Port Assignment Each device supports trunks, each trunk have through eight ports members. total eight trunk groups four switching devices RoX-II possible. Each device must aware other devices' trunk configuration. These configured Register through Register Layer Trunking Assignment Registers through Unlike port based trunking groups, Trunk group programmed bit-map member ports each trunk.
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3.11.2.3 Trunk Load Balancing load balancing algorithm uses randomized seed based Destination address, Source Address, both Destination Source Addresses, non-randomized Each trunk group's randomization method selected Register Layer Trunking Protocol Register. This randomization sequence creates 12-bit value, which used random seed value load balancing algorithm. L2KeySel, Register System Configuration Register Bits 1~0, used select which three-bit field random seed value. Normally this register doesn't need adjusted normal operation. AL125 uses robust unique algorithm ensure statistically equal loads whether trunk group member ports group. 3.11.2.4 Link Fail Over AL125 supports link fail-over when more member ports trunk fail. This feature enabled L2FailEn Register System Configuration Register Bits member port trunk experiences link failure, AL125 detects this condition divides frame-flow that used assigned failed port other member ports. load balancing algorithm also applies this case, which statistically ensures equal load rest member ports. link healed, then only frame-flow that re-assigned other member ports restored back original link. When frame-flow restored onto original link, queue needs flushed avoid mis-ordered frames. This flushing mechanism selected setting L2Timer value Register System Configuration Register Bits 5~4. This Link Fail-Over feature only available trunking mode.
3.12 Spanning Tree Support
AL125 capability support implementation Spanning Tree Protocol. ports programmed port state required spanning tree protocol. Spanning Tree Protocol option enabled, AL125 will forward frame below. port Block-N-Listen State Learning State, frame forwarded BPDU frame, frame discarded otherwise. outgoing frames except outgoing BPDUs will masked from path PHY. port Forwarding State, frame forwarded BPDU frame. source addresses incoming frames from will learned then forwarded based switch routing decision. outgoing frames will transmitted PHY. port Learning State, source addresses incoming frames from will learned. incoming frames except incoming BPDUs from will discarded after being learned, outgoing frames except outgoing BPDUs will masked from path PHY.
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3.13 Flow Control
AL125 operate different modes, half- full-duplex. Each port operate either full- half-duplex configured have flow control enabled flow control independently per-port basis. 3.13.1 Half Duplex (Backpressure) half-duplex flow control option elected, backpressure will used flow control. Whenever receive frame buffer port full, port will start sending signal through port. remote station will defer transmission after sensing signal. Backpressure flow control applied ensure that there dropped frames. AL125 supports types backpressure, collision based carrier based. Carrier based backpressure generated AL125, when switch port's frame buffer full. AL125 will cease line when port buffer space available frame reception. jamming signal programmed either 64BT 96BT. Collision based backpressure generated AL125 only when switch port receives frame frame buffer full. AL125 will cease line when line idle. carrier based backpressure several advantages over collision based backpressure. Collision based backpressure cause late collisions. After consecutive collisions, could drop frames. AL125 option drop frames after collisions. However, terminal still drop frames. Therefore, recommend carrier based backpressure preferred method halfduplex flow control. this mode operation, also recommend that signal should 64BT. This because 96BT, terminal might still able transmit frames cause collisions. excessive collisions cause frames dropped. AL125 also supports collision based backpressure customers that prefer collision based backpressure. 3.13.2 Full Duplex Flow Control (802.3x) full-duplex mode, AL125 will transmit receive frames accordance IEEE 802.3x. transmission channel receiving channel operate independently. incoming direction, whenever receive frame buffer port full, port will send PAUSE frame with delay value maximum. PAUSE frame will deter incoming frame from flowing into port. After occupancy receiving frame buffer reduced below FlowControlOff threshold, port will then send PAUSE frame with delay value zero, resume receiving incoming frame flow. outgoing direction, whenever incoming PAUSE frame with non-zero delay value received through port, port will stop next frame transmission after ongoing frame transmission finished, start pause timer. will resume frame transmission either after pause timer expired when PAUSE frame with zero delay value received. Pause frame defined special type, code.
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When 802.3x flow control option elected, device will program appropriate auto-negotiation capability field. When AL125 used full-duplex mode, recommended that flow control should turned prevent buffer from overflow loss frames. connected device 802.3x capability, then link recommended half-duplex. 3.13.3 Special Frame Identification Trapping AL125 capable identifying special frames forwards them required. AL125 inspects load incoming frames, frame types selected (register 03), will then forward frame CPU. following types frame trapping supported AL125 addition BPDU frames.
NAME IPMC COMMENT multicast mapping frames. AL125 directly supports multicast addresses. that needed support multicast procedure mapping host addresses Ethernet multicast address placing low-order bits address into order bits Ethernet multicast address 01-00-5E-00-00-00 (hex). Because there significant bits, more than host group address mapped same Ethernet multicast address. Internet Group Management Protocol. This internet multicast support bridges. Generic Attribute Registration Protocol. This required 802.1q. Address Resolution Protocol. This required TCP/IP stack. Controls frames 802.3ad trunking control.
IGMP GARP 802.3ad
3.14 Queue Management
AL125 supports four priority queues each port AL125. frames that come into AL125 stored into shared memory buffer lined transmission queues corresponding destination port. priority assigned contained received frames. definition priority programmed register AL125 will transmit frames based priority queue assigned priority tag. AL125 provides modes priority scheduling (selectable register 02); Strict Priority Scheduling Weighted Priority Scheduling. Strict Priority Scheduling simple scheduling scheme that will schedule highest priority frames transmitted first. shortcoming this method priority frames might starved bandwidth there very high traffic high priority frames. alternative Weighted Priority Scheduling which assigns weight different levels that provide priority frames fair chance accessing bandwidth. weight each priority programmed register
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3.14.1 Congestion Control AL125 provides options congestion control. When port congested, AL125 will backpressure flow control deter further traffic from entering switch. Although this good prevent frame loss, desirable some applications. AL125 therefore allows users program queue able drop frames when number frames reaches water mark programmed that queue. broadcast multicast frames, AL125 also provides capability dropping frames from Mbit/s multicast queue keep Mbit/s forwarding speed.
3.15 Uplink Port
uplink port provides connect switch with repeater hub, workgroup switch, router, type interconnecting device compliance with IEEE 802.3 standards. port also designated uplink port. flood control enabled, AL125 will send frames with unmatched multicast/ broadcast frames uplink port. very important that each port assigned uplink port Port Configuration Register to1C) uplink disabled, data frames might lost. uplink port should configured within same VLAN source port. uplink port member VLAN, broadcast multicast frames will forwarded designated uplink port. Multiple VLANs share same uplink port. AL125 will direct following frames uplink port. Frames with unicast destination address that does match with address stored switch. Frames with broadcast/multicast destination address uplink port same VLAN. When configuring uplink port, uplink port should designate itself uplink port. Summary Programmable Register Trunk Port Designation (register this register provides option designating uplink port either port, trunk CPU. details register descriptions.
3.16 Port Monitoring
AL125 supports port monitoring. This feature provides complete network monitoring capability Mbit/s. copy egress (TX) data ingress (RX) data monitored port sent their respective snooping ports. monitored port selected register AL125 allows transmit receive data monitored different snooping ports. snooping ports also selected register Summary Programmable Register Port Monitoring Register (06) this register selects target monitored port snooping port. 5-bit Port_ID designates port. format Port_ID [Dev_ID].[Port_ID]. [Dev_ID] device number [Port_ID] port number.
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3.17 Reduced Media Independent Interface (RMII)
Port AL125 option mode. frame reception, received data (RXD[3:0]) sampled rising edge receive clock (RX_CLK). Assertion receive data valid (RX_DV) signal will cause look start SFD. transmission, transmit data enable (TX_EN) signal asserted when first preamble nibble sent transmit data (TXD[3:0]) lines. transmit data clocked rising edge transmit clock (TX_CLK). Prior transaction, AL125 will output 32-bits preamble signal then after preamble, "01" signal used indicate start frame.
3.18 Management
AL125 supports transceiver management through serial MDIO signal lines. device provides modes management, master slave mode. master mode operation, AL125 controls operation modes link slave mode controls operating mode. 3.18.1 Management MDIO write operation, device will send "01" signal write operation. Following "01" write signal there will 5-bit address device 5-bit register address. "10" turn around signal then used avoid contention during read transaction. After turn around, 16-bit data will written into register then after completion write transaction, line will high impedance state. read operation, AL125 will output indicate read operation after start frame indicator. Following "10" read signal will five-bit address device five-bit register address. Then, AL125 will cease driving MDIO line, wait time. During this time, MDIO should high impedance state. device will then synchronize with next driven device, continue read 16-bit data from register. detail timing requirement management signals described section "Timing Requirement." 3.18.2 Management Master Mode master mode, AL125 will continuously poll status devices through serial management interface. device will also configure capability fields ensure proper operation link. configuration link automatic. link capability programmed AL125 through port configuration register. AL125 reads from standard IEEE registers determine auto-negotiated operating speed mode. there need manually operation mode because flow control cabling issues, AL125 port operation mode through MDIO interface (see EEPROM section programming AL125).
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3.18.3 Management Slave Mode slave mode, controls programming operating mode. AL125 will continuously poll status devices through serial management interface determine operation mode link. This mode management very useful unmanaged switch. operating mode link changed programming mode through jumper. AL125 also supports 100Base-TX transceivers without MDIO interface interface. Note that this available port only. When MDIO disabled, AL125 will operate operation mode specified Port Configuration Register (register 1C). 3.18.4 Auto-negotiation Mode AL125 also turn auto-negotiation capability PHY. When auto-negotiation turned off, AL125 slave mode transceiver will determine link's operating mode. 3.18.5 Other Options Some Legacy Fast Ethernet devices other cost devices have auto-negotiation capability. those cases when transceiver will able perform auto-negotiation, switch transceiver will typically parallel detection update information transceiver's register. Unfortunately, such register addresses vendor specific. AL125 provides register (register specify register address AL125 read. AL125 will read from that register configure port operation accordingly. Register also provides some additional flexibility's some PHYs market. general, system designer should devices port port port Certain PHYs utilize address 00000 broadcast address. register allows AL125 start with address 01000. This provision allows engineers work around PHY's that have problems handling address 00000. Quad PHYs have 2-port ordering chip pinout, both clockwise counter clockwise. Register programs AL125 port order either direction. This provision enables engineers easily implement designs with PHY. There also slow MDIO clock KHz) available that capable handling high speed MDIO clock. some reason, transceiver connected device that device fails auto negotiate, AL125 will default data rate duplex mode default setting port configuration register.
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3.19 SGRAM Interface
ports AL125 work Store-And-Forward mode that ports support both Mbps Mbps data speed. AL125 utilizes central memory buffer pool which shared ports within same device. After frame received, passed across SGRAM interface stored buffer. During transmit, frame retrieved from buffer pool forwarded destination port. AL125 designed Mbit/s SGRAM Mbit/s SGRAM cost performance. SGRAM essentially SDRAM. Dynamic memories must refreshed periodically prevent data loss. SGRAM auto-refresh which also uses refresh address counter. SGRAM auto-refresh command generates pre-charge command internally SGRAM. AL125 will insert auto-refresh command once every SGRAM accessed page burst access mode very high speed access. This burst mode repeatedly accessing same column. burst mode reaches column address, then wraps around first column address (=0) continues count until interrupted read/write, pre-charge, burst stop command. AL125 will initialize SGRAM automatically. pre-charges banks inserts eight auto-refresh commands. will also program mode registers AL125 read write operations.
3.20 EEPROM Interface
AL125 provides three functions with EEPROM interface; system initialization, obtaining system status, reconfiguration system real time. 3.20.1 System Initialization EEPROM interface provided manufacturer provide pre-configured system their customers. Customers change reconfigure their system retain their preferences. EEPROM contains configuration initialization information, which accessed power reset. AL125 uses 24C02 serial EEPROM device (2048 bits organized bits organization EEPROM data shown Table During start AL125 will detect presence EEPROM. EEPROM present, AL125 will initialized attached management device RoXII ring. initialization command received, device will operate. reset held low, AL125's EEPROM interface will into high impedance state. This feature very useful reprogramming EEPROM during installation reconfiguration. There ways that EEPROM reprogrammed, external parallel port residing ring. reprogramming using parallel port, signal used hold RESET low; EEPROM interface will then high impedance state. external device then program EEPROM through EDIO ECLK pins. EEPROM address should same device with (EEPROM) grounded. example, EEPROM device address device address 001.
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Device Type Identifier
Device Address
Figure
EEPROM Address Format
3.20.2 Start Stop write cycle started start ended stop bit. start transition from high EEDIO when high. operation terminates when EEDIO goes from high when high (Figure Following start condition, writing device must output address EEPROM. most significant four bits EEPROM address device type identifier. These four bits 1010. EEPROM device address should device number. EECLK output from AL125. EEDIO input AL125 reading EEPROM output writing (See Figures When accessing EEPROM, reset held before writing operation begin.
EECLK
EEDIO
Data Address Valid
START
Data Change
STOP
Figure
Start Stop
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3.20.3 Write Cycle Timing EECLK output from AL125 while EEDIO bi-directional signal. When accessing EEPROM, reset held initialization AL125 must finished before write operation begin. typical write operation shown Figure
Device Address
Start
Stop
EEDIO
8-Bit Word Address
8-Bit Data
Acknowledge
Acknowledge
Acknowledge
Figure
Typical Write Cycle
3.20.4 Read Cycle Timing Read operations initiated same manner write operations, with exception that EEPROM address "1."
Device Address Device Address
Start
Start
Stop
EEDIO
8-Bit Word Address
8-Bit Data
Acknowledge
Acknowledge
Acknowledge
Acknowledge
Figure
Typical Read Cycle
3.20.5 Reprogramming EEPROM Configuration There ways that system reconfigured. Figure shows application using parallel interface reprogram EEPROM. this application, parallel port holds reset pins low, which forces EEDIO pins high impedance. Once pins high impedance, EEPROM programmed parallel port. Once parallel port releases reset pins, devices will start download EEPROM data reconfigure devices.
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alternate reconfiguring system input data directly into AL125. After initialization, EEPROM interface virtual EEPROM. order this method work, EEPROM's address must 0XX, AL125's address will 1XX. customer program AL125 EEPROM. read write timing same EEPROM. Because read well write AL125, status register read from AL125. This will serve very useful tool diagnostic unmanaged switch.
AL125
Reset
EECLK EEDIO
EEPROM Parallel Port
AL125
Reset
EECLK EEDIO
EEPROM
Reset
AL125
EECLK EEDIO
EEPROM
Reset
AL125
EECLK EEDIO
EEPROM
Figure
Programming EEPROM with Parallel Port
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3.20.6 EEPROM Note: specific bits register referenced "X.Y" notation, where register number number. Table shows EEPROM addresses cross-referenced register/bit AL125. Addresses through configuring device. They downloaded AL125 during reset power address indicates last address entry. static address used switch, address should programmed. Addresses used programming explicit address entry. format address shown follows; YXXXXX represents: then XXXXX 5-bit individual port number. Y=1, then XXXXX either trunk port represented followed digit [trunk number, port represented 11ZZZ where don't care.
Table Static Address Entry Format EEPROM
EEPROM ADDRESS
Reserved (Must zero) Reserved Port YXXXXX Trunk YXXYYY
Address [47:40] Address [39:32] Address [31:24] Address [23:16] Address [15:8] Address [7:0]
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Table AL125 EEPROM Mapping
EEPROM PHYSICAL ADDRESS 00-01 02-03 04-05 06-07 08-09 0A-0B 0C-0D 0E-0F 10-11 12-13 14-15 16-17 18-19 1A-1B 1C-1D 1E-1F 20-21 22-23 24-25 26-27 28-29 2A-2B 2C-2D 2E-2F 30-31 32-33 34-35 36-37 38-39 DESCRIPTION System Configuration System Configuration System Configuration System Configuration System Performance Tuning Vendor Specific Port Monitoring Configuration Reserved Output Queue Management Output Queue Management Reserved RoX-II Control RoX-II Control Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration
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Table AL125 EEPROM Mapping (Continued)
3A-3B 3C-3D 3E-3F 40-41 42-43 44-45 46-47 48-49 4A-4B 4C-4D 4E-4F 50-51 52-53 54-55 56-57 58-59 5A-5B 5C-5D 5E-5F 60-61 62-63 64-65 66-67 68-69 6A-6B 6C-6D 6E-6F 70-71 72-73 74-75 76-7D Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN VLAN Extension CheckSum VLAN Extension Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Testing Control Testing Control Last Entry Location Static Entry
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Table AL125 EEPROM Mapping (Continued)
7E-85 86-8D 8E-95 96-9D 9E-A5 A6-AD AE-B5 B6-BD BE-C5 C6-CD CE-D5 D6-DD DE-E5 E6-ED EE-F5 F6-FD FE-FF Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Reserved
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3.21 Register Descriptions Table Register Description
REGISTER REGISTER NAME System Configuration System Configuration System Configuration System Configuration System Performance Tuning Vendor Specific Status Port Monitoring Configuration Reserved Output Queue Management Output Queue Management Reserved RoX-II Control RoX-II Control Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration REVEPADDR [00, [02, [04, [06, [08, [0a, [0c, [0e, [10, [12, [14, [16, [18, [1a, [1c, [1e, [20, [22, [24, [26, [28, [2a, [2c, [2e, [30, [32, [34,
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Table Register Description (Continued)
Port Configuration Port Configuration Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN VLAN Extension VLAN Extension Port Trunk Port Assignment/Layer Trunking Assignment Port Trunk Port Assignment/Layer Trunking Assignment Port Trunk Port Assignment/Layer Trunking Assignment Port Trunk Port Assignment/Layer Trunking Assignment Port Trunk Port Assignment/Layer Trunking Protocol Select Port Trunk Port Assignment Port Trunk Port Assignment [36, [38, [3a, [3c, [3e, [40, [42, [44, [46, [48, [4a, [4c, [4e, [50, [52, [54, [56, [58, [5a, [5c, [5e, [60, [62, [64, [66, [68, [6a,
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Table Register Description (Continued)
Port Trunk Port Assignment Testing Control Testing Control System Status Register Port Operation Status Port Operation Status Port Operation Status Port Operation Status Port Operation Status Port Operation Status Port Operation Status Port Operation Status Indirect Resource Access Command Indirect Resource Access Data Indirect Resource Access Data Indirect Resource Access Data Indirect Resource Access Data Indirect Resource Access Data Monitored Source Host (MAC address [47:32]) Monitored Source Host (MAC address [31:16]) Monitored Source Host (MAC address [15:0]) Monitored Destination Host (MAC address [47:32]) Monitored Destination Host (MAC address [31:16]) Monitored Destination Host (MAC address [15:0]) Port Default Priority/VLAN Port Default Priority/VLAN Port Default Priority/VLAN Port Default Priority/VLAN Port Default Priority/VLAN Port Default Priority/VLAN [6c, [6e, [70, [72, [74, [76, [78, [7a, [7c, [7e, [80, [82, [84, [86, [88, [8a, [8c, [8e, [90, [92, [94, [96, [98, [9a, [9c, [9e, [a0, [a2, [a4, [a6,
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Table Register Description (Continued)
Port Default Priority/VLAN Port Default Priority/VLAN Port Default Priority/VLAN Port Default Priority/VLAN Port Default Priority/VLAN Port Default Priority/VLAN Port Default Priority/VLAN Port Default Priority/VLAN Port Default Priority/VLAN Port Default Priority/VLAN Port Default Priority/VLAN Port Default Priority/VLAN Port Default Priority/VLAN Port Default Priority/VLAN Port Default Priority/VLAN Port Default Priority/VLAN Port Default Priority/VLAN Port Default Priority/VLAN Port Default Priority/VLAN Port Default Priority/VLAN Port Default Priority/VLAN Port Default Priority/VLAN Port Default Priority/VLAN Port Default Priority/VLAN Port Default Priority/VLAN Port Default Priority/VLAN Local Default Priority/VLAN Reserved CheckSum [a8, [aa, [ac, [ae, [b0, [b2, [b4, [b6, [b8, [ba, [bc, [be, [c0, [c2, [c4, [c6, [c8, [ca, [cc, [ce, [d0, [d2, [d4, [d6, [d8, [da, [dc, [de, [e0,
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System Configuration Register (Register registers global system configuration registers. option selected this register affect overall system operation.
Table System Configuration Register (Register
NAME CPUprst DESCRIPTION Present. This AL125 when detects EEPROM present. device will assume that present wait initialize this device. Flooding Control. Control forwarding unicast frames with unknown destination received from non-uplink ports. Disable. Frames received with unknown unicast destination address will forwarded ports (excluding receiving port) within VLANs specified receiving port. (IEEE 802.1D Compliant) Enable. Frames received with unknown unicast destination address will forwarded uplink port specified receiving port. Auto Security Enforcement. Auto security off. security violation secured port will change port state. Auto security security violation secured port will cause port into DISABLE state. Switch Table Entry Aging Control. Only dynamically learned addresses will aged. explicit entries will age. aging time programmed register Disable. table aging process will stopped. Enable. table aging process will running every dynamically learned table entry. (IEEE 802.1D Compliant) Address Table Convergence Control. Disable. device will share locally learned addresses with other devices RoX-II Bus. Enable. device will background process periodically transfer locally learned table entries other devices learn. (IEEE 802.1D Compliant) Spanning Tree Protocol Enable Control. Disable. BPDU frames received from network ports will treated regular broadcast frames. Enable. BPDU frames received from network ports will forwarded only port. Port Incoming Frame Flow Monitoring Enable Control. monitored snooping port configuration register Disable. Enable.
FloodCtl
AutoSec
AgeEN
TCNVG
STPEN
PinMon
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Table System Configuration Register (Register (Continued)
PoutMon Port Outgoing Frame Flow Monitoring Enable Control. monitored snooping port configuration register Disable. Enable. Configuration Ready. This AL125 provide indication that register file initialization completed CPU. initialized. Register file initiation done. Network Management Enable Control. Disable. device will generate events management device (such AL300A AL3000). Enable. device will generate events propagate them onto ring. System Initialization Done. Meaningful only initialization mode. sets this after registers static entries programmed. Select RMII ports through (See register Port Always Layer Trunking. Disable. Trunking decisions will based port based trunk port assignment registers. Enable. Trunking decisions will based source port addresses. Time Enable. Device will time-out frames based MaxDelay. Device will time-out frames. (IEEE 802.1D Compliant) MaxDelay bits Reg, time-out limit.
CPUcfgrdy
NetMgmt
CPUInitDone
SelRMII
L2Trunk
TimeoutEn
Reserved
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Table System Configuration Register (Register
15~9 NAME MaxAge DESCRIPTION MaxAge. This seven-bit register containing unsigned integer determining address-aging timer. resolution normal address aging 5.36 seconds seconds with system clock. SlowAge (register programmed "1," resolution 10.72 seconds 13.4 seconds with system clock. Reset Disable. Reset link down Don't Reset link down. MaxDelay this sets timer maximum allowable frame delay through switch TimeoutDis (register option elected. second seconds seconds seconds MaxStorm this sets threshold number consecutive broadcast frames allowed from port. storm control option selected Port Configuration Registers (registers 1C). frames frames frames frames SuperMAC when this option selected, AL125 controller will more aggressive back algorithm. This enables switch transmit frame earlier. (Meaningful only half-duplex mode). Disable. Device will perform IEEE 802.3 standard exponential back algorithm when collision occurs. Enable. When collision occurs, device will back slots. L2KeySel selects address bits address based trunk port assignment. hashkey pattern hashkey pattern hashkey pattern hashkey pattern
PhyResetDis
MaxDelay
MaxStorm
SuperMAC
Reserved L2KeySel
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Table System Configuration Register (Register
NAME SelRMIIP0 DESCRIPTION Select RMII port (see Register Ports Disable. device will operate regular mode Enable. device will operate RMII mode. Disables unknown frame forwarding local CPU. System clock MHz. System clock MHz. Layer Trunk Enable. Disable Enable Layer Trunk Enable. Disable Enable Timing. Slows down normal address aging timer specified register MaxAge field. Normal Aging. resolution normal address aging 5.36 seconds seconds with system clock. Slow Down. resolution 10.72 seconds 13.4 seconds with system clock. Backpressure Inter-Packet Gap. BpIPG 96BT BpIPG 64BT Standard Inter-Packet Gap. 96BT 64BT BackPressure Rate. (collision based) Jams every frame. every frames. every frames. every frames. SGRAM Size. Mbit/s SGRAM Mbit/s SGRAM Backpressure Collision. Selects backpressure mechanism halfduplex (CSMA/CD) operation. based. Collision based.
CPUOffL ClkSel L2T0En
L2T1En
SlowAge
BpIPG64
SIPG
BPRate
SG16M
BPCOL
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Table System Configuration Register (Register (Continued)
ETEnb External Table Enable. Disable Enable Binary Exponential Backoff Select. Standard Avoid channel capture. Priority Queue Weight Round-Robin Enable. Disable Enable Flow Control Multicast Broadcast. Flow Control Broadcast.
BebSel
PQWRREn
FlowCtrlBC
Table System Configuration Register (Register
NAME QEnable AL300En GWPrst ALTGW IPMCtrap IGMPtrap GARPtrap ARPtrap 802Xtrap L2FailEn L2Timer DESCRIPTION Supports 802.1q VLAN Tagging. Disable Enable Supports AL300A Protocol. Disable Enable Gateway Device Present. Disable Enable Enable Alternative Gateway Device. Disable Enable IPMC Frame Trap Enable. Disable Enable IGMP Frame Trap Enable. Reserved. GARP Frame Trap Enable. Disable Enable Frame Trap Enable. Disable Enable Trunking Control Frame Trap Enable. Disable Enable Layer Trunk Link Fail Recover Enable. Disable Enable Layer Trunk Link Recover Timer Control. Disable 1/16
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Table System Configuration Register (Register (Continued)
D3GigaOn D2GigaOn D1GigaOn D0GigaOn Device Gigabit Device. Disable Enable Device Gigabit Device. Disable Enable Device Gigabit Device. Disable Enable Device Gigabit Device. Disable Enable
System Performance Tuning Control Register (Register Recommended Settings: 0001 1001 1010 1100 with dual ring enabled; 0001 0001 0001 0100 MHz.
Table System Performance Tuning Control Register (Register
15~14 12~0 NAME Reserved CasDelay Reserved Latency (Default) Latency DESCRIPTION
Vendor Operating Mode (Register Configuration) This register used program vendor specific option. also used programming Vendor Specific register location location operation status.
Table Vendor Operating Mode (Register
12~8 NAME MSBSel MIISlowClk RevOrder PHYOpReg Address 00xxx Address 10xxx Normal Select Slow Clock MII. Address order from 111; (normal) Address order from Operating Mode Register. Register where attached PHY's operating condition stored. DESCRIPTION
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Table Vendor Operating Mode (Register (Continued)
PHYOpSp Operating Speed Location. location within register specified above where attached PHY's operating speed stored. Operating Mode Location. location within register specified above where attached PHY's operating mode (full/half-duplex) stored.
PHYOpMd
Port Monitoring Configuration Register (Register This register configures port monitoring. sets monitored port snooping ports.
Table Port Monitoring Configuration Register (Register
14~10 NAME Reserved MdPID MgIPID MgOPID Monitored Port Monitoring Port Incoming Frame Flow. Monitoring Port Outgoing Frame Flow. DESCRIPTION
Priority Queue Assignment Register (Register Recommended Setting: 1111 1010 0100 0001 AL126 allows tagged priority assigned four priority queues. AL126 will transmit frames based priority queue, priority tag.
Table Priority Queue Assignment Register (Register
15~14 13~12 11~10 NAME PL7QA PL6QA PL5QA PL4QA PL3QA PL2QA PL1QA PL0QA DESCRIPTION Priority Level Queue Assignment Queue Queue Queue Priority Level Queue Assignment. Priority Level Queue Assignment. Priority Level Queue Assignment. Priority Level Queue Assignment. Priority Level Queue Assignment. Priority Level Queue Assignment. Priority Level Queue Assignment. Queue
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Output Queue Management Register (Register Recommended Setting: 0011 1111 1111 1111
Table Output Queue Management Register (Register
NAME MaxDrop Output Over Drop Option. Flow control first. Drop enable. DESCRIPTION
Reserved CPUMaxLimEn M0MaxLimEn Q3MaxLimEn Q2MaxLimEn Q1MaxLimEn Q0MaxLimEn P7MaxLimEn P6MaxLimEn P5MaxLimEn P4MaxLimEn P3MaxLimEn P2MaxLimEn P1MaxLimEn P0MaxLimEn AL300A Limit Enable. Disable Enable Mbit/s Multicast Queue Limit Control Enable. Disable Enable Priority Queue Limit Control Enable. Disable Enable Priority Queue Limit Control Enable. Priority Queue Limit Control Enable. Priority Queue Limit Control Enable. Output Port Limit Control Enable. Disable Enable Output Port Limit Control Enable. Output Port Limit Control Enable. Output Port Limit Control Enable. Output Port Limit Control Enable. Output Port Limit Control Enable. Output Port Limit Control Enable. Output Port Limit Control Enable.
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Output Queue Management Register (Register Recommended Setting: 0001 0001 0001 0001
Table Output Queue Management Register (Register
15~12 NAME Q3MaxLim DESCRIPTION Maximum buffer blocks priority queue hold both priority queue output port limit controls enabled. AL125 uses this value buffer-full status "Queue Status" registers each output priority queues. When this threshold reached, "Operation Status Communication Message" with <buffer full> sent onto RoX-II Data Ring. frame queue request must honored regardless this bit. water mark sending <buffer available> less than limit, except limit (it's watermark which used test mode. 0000: 0001: 0010: 0011: 0100: 0101: 0110: 0111: 1000: 1001: 1010: 1011: 1100: 1101: 1110: 1111: Maximum buffer blocks priority queue hold both priority queue output port limit control this queue enabled. Maximum buffer blocks priority queue hold both priority queue output port limit control this queue enabled. Maximum buffer blocks priority queue hold both priority queue output port limit control this queue enabled.
11~8
Q2MaxLim Q1MaxLim Q0MaxLim
Priority Queue Weight Round-Robin Control Register (Register Recommended Setting: 1111 0111 0011 0001 This register controls weight each priority queue, when weight priority queuing selected. Note: weight should bigger equal weight should bigger equal weight should bigger equal
Table Priority Queue Weight Round-Robin Control Register (Register
15~12 11~8 NAME Q3RRWeight Q2RRWeight Q1RRWeight Q0RRWeight DESCRIPTION Weight Queue round robin scheme. 0000 0001 1110 1111 Weight Queue Round Robin Scheme. Weight Queue Round Robin Scheme. Weight Queue Round Robin Scheme.
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RoX-II Control Register (Register Recommended Setting: 0000 0000 0000 0000 This register along with Register sets "route" bitmap from device this device. Each route five bits standing possible five segments RoX-II ring. right-most segment driven device following physical connection from right left. Devices don't have connected sequence according device bitmap means that route will travel that segment.
Table RoX-II Control Register (Register
14~10 NAME DualREn D2Route D1Route D0Route DESCRIPTION Dual Control Ring Enable. Disable Enable Route Selection from Device this Device. Route Selection from Device this Device. Route Selection from Device this Device.
RoX-II Control Register (Register Recommended Setting: 0000 0000 0000 0000
Table RoX-II Control Register (Register
NAME OneDev HiMmode D3Mmode D2Mmode D1Mmode D0Mmode HiRoute D3Route DESCRIPTION RoX-II Internal Loop Back Enable. Disable Enable Memory Mode Selection AL3000. Single buffer Dual buffers Memory Mode Selection Device Memory Mode Selection Device Memory Mode Selection Device Memory Mode Selection Device Route Selection from AL3000 this Device. Route Selection from Device this Device.
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Port Configuration Registers Registers local port configuration. There port configurations port. Port port configuration uses register Port register etc. Uplink this six-bit link which assigns uplink port trunk. uplink local stack, format Port: [Dev_ID] [Port_ID] Trunk: [100] [Trunk_ID] CPU: [100000] Router: [100001] uplink remote stack, Stack: [101] [Stack_ID] remote stack will assign final port/trunk Note: port/trunk uplink, uplink should port/trunk frame with unlearned will then filtered.
Table Port Configuration Registers
15~10 NAME UpLinkID DESCRIPTION Uplink associated with port. 0xxyyy: Local port with DEVID PID. 110xxx: Local trunk with Trunk_ID. 100000: Local CPU. 100001: Local router. 101xxx: Remote stack uplink with Stack_ID. Others: Reserved. Trunk Member Port. Individual port. Trunk port.
Tmember
Reserved StormCTL Broadcast Storm Control Enable. Storm control disable. broadcast frame will throttled. Storm control enable. accumulated number broadcast frames input buffer port over threshold specified system configuration register, incoming broadcast frames will discarded until number been reduced below threshold. Intrusion protection security control frames received from nonuplink ports. Security off. forwarding decision made about frames received from port will involve source address checking. Security Frames received from port with unknown source address with source address learned previously from another port will discarded.
Security
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Table Port Configuration Registers (Continued)
LCPUOn Local Port VLAN Membership. Non-member. Broadcast frames received from port will forwarded local port. Member. Broadcast frames received from port will forwarded local port addition other member ports specified VLAN VLAN Extension register port (excluding source port). Learning Disable. This used designate port uplink port, since unmatched frames will forwarded ports with learned address. Source address from this port will learned. Source address from this port will learned. Port State Control. Disable. incoming frames from will discarded; outgoing frames will masked from path PHY. Blocking-N-Listening. incoming frames except incoming BPDUs from will discarded; outgoing frames except outgoing BPDUs will masked from path PHY. Learning. source information incoming frames from will learned, incoming frames except incoming BPDUs from will discarded after being learned; outgoing frames except outgoing BPDUs will masked from path PHY. Forwarding. source information incoming frames from will learned, incoming frames will forwarded based switch routing decision; outing frames will transmitted PHY.
LrnDis
PortST
Reserved
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Table Port Configuration Registers
NAME Reserved PHYR6Skip PHYCTLAD PHYACSkip FlowCtrlFdEn FlowCtrlHdEn MDIOCfg[3:0] Skip Check Register MDIO flow. Control Advertisement Default. Ignore Auto-complete Link MDIO Flow. Flow Control Full-Duplex Enable. Flow Control Half-Duplex Enable. MDIO Configuration. 0001: Selects master mode. When AL125 this mode, will capability advertisement register. link will auto-negotiate highest capability. 0010: Selects slave mode. When AL125 this mode, will capability advertisement register. link will auto-negotiate highest capability. 0111: Selects forced mode. When AL125 this mode, will turn auto-negotiation will select link's operating mode. MDIO Disable. Link Down Link [100F, 100H, 10F, 10H] DESCRIPTION
MDIODis LinkUp PrtCfgMode[3:0]
Table Port VLAN Registers
15~8 NAME Dev3Map DESCRIPTION Port VLAN corresponding port7 port0 device with DEVID Non-member port. Member port. Port VLAN corresponding port7 port0 device with DEVID Explanation same above.
Dev2Map
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Table Port VLAN Registers
15~8 NAME Dev1Map DESCRIPTION Port VLAN corresponding port7 port0 device with DEVID Non-Member Port. Member Port. Port VLAN corresponding port7 port0 device with DEVID Explanation same above.
Dev0Map
VLAN Extension Register (Register Recommended Setting: 0000 0000 0000 0000
Table VLAN Extension Register (Register
NAME P7GW7On DESCRIPTION Gateway Device VLAN Membership Port Non-Member. Broadcast frames received from port will forwarded Gateway Device Member. Broadcast frames received from port will forwarded Gateway Device addition other member ports specified VLAN LCPUOn port configuration register, (excluding source port). Gateway Device VLAN Membership Port Gateway Device VLAN Membership Port Gateway Device VLAN Membership Port Gateway Device VLAN Membership Port Gateway Device VLAN Membership Port Gateway Device VLAN Membership Port Gateway Device VLAN Membership Port
P6GW7On P5GW7On P4GW7On P3GW7On P2GW7On P1GW7On P0GW7On Reserved
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Table VLAN Extension Register (Register
15~8
NAME Reserved P7GW6On P6GW6On P5GW6On P4GW6On P3GW6On P2GW6On P1GW6On P0GW6On
DESCRIPTION
Gateway Device VLAN Membership Port Gateway Device VLAN Membership Port Gateway Device VLAN Membership Port Gateway Device VLAN Membership Port Gateway Device VLAN Membership Port Gateway Device VLAN Membership Port Gateway Device VLAN Membership Port Gateway Device VLAN Membership Port
Table Trunk Port Assignment Registers (2F~36)
15~14 NAME Port7TP DESCRIPTION Trunk Link Trunk Port PortID represented [DEVID, TID, 00]. PortID represented [DEVID, TID, 01]. PortID represented [DEVID, TID, 10]. PortID represented [DEVID, TID, 11]. Trunk Link Trunk Port Explanation same above. Trunk Link Trunk Port Explanation same above. Trunk Link Trunk Port Explanation same above. Trunk Link Trunk Port Explanation same above. Trunk Link Trunk Port Explanation same above. Trunk Link Trunk Port Explanation same above. Trunk Link Trunk Port Explanation same above.
13~12 11~10
Port6TP Port5TP Port4TP Port3TP Port2TP Port1TP Port0TP
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Layer Trunking Assignment Register (Register Recommended Setting: 1111 0000 0000 1111
Table Layer Trunking Assignment Register (Register
15~8 NAME T1Member T0Member DESCRIPTION Assign Trunk Member Trunk Assign Trunk Member Trunk
Layer Trunking Assignment Register (Register Recommended Setting: 1111 0000 0000 1111
Table Layer Trunking Assignment Register (Register
15~8 NAME T3Member T2Member DESCRIPTION Assign Trunk Member Trunk Assign Trunk Member Trunk
Layer Trunking Assignment Register (Register Recommended Setting: 1111 0000 0000 1111
Table Layer Trunking Assignment Register (Register
15~8 NAME T5Member T4Member DESCRIPTION Assign Trunk Member Trunk Assign Trunk Member Trunk
Layer Trunking Assignment Register (Register Recommended Setting: 1111 0000 0000 1111
Table Layer Trunking Assignment Register (Register
15~8 NAME T7Member T6Member DESCRIPTION Assign Trunk Member Trunk Assign Trunk Member Trunk
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Layer Trunking Protocol Register (Register Recommended Setting: 0000 0000 0000 0000
Table Layer Trunking Protocol Register (Register
15~14 NAME T7Ptcl DESCRIPTION Layer Trunk Protocol Control. 00=DA+SA crc. 01=SA crc. 10=DA crc. 11=DA+SA bits. Layer Trunk Protocol Control. Layer Trunk Protocol Control. Layer Trunk Protocol Control. Layer Trunk Protocol Control. Layer Trunk Protocol Control. Layer Trunk Protocol Control. Layer Trunk Protocol Control.
13~12 11~10
T6Ptcl T5Ptcl T4Ptcl T3Ptcl T2Ptcl T1Ptcl T0Ptcl
Test Control Register (Register Reserved Allayer's use. Recommended Setting: 0000 0000 0000 0000
Table Testing Register (Register
15~6 NAME Reserved TypeOnly 802.3x Flow Control Frame Recognition Control. Check control frame address addition control type field. Check only control type field. DESCRIPTION
Reserved
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Test Control Register (Register Reserved Allayer's use. This register reserved Allayer's use. recommended setting 0000 1000 0000 1100.
Table Testing Register (Register
15~12 11~10 NAME Reserved WmarkSel Reserved Backpressure Watermark Select. Backpressure available block count Backpressure available block count Backpressure available block count Test Mode. Each block 2Kbyte. Reserved DESCRIPTION
Reserved
Note: Most bits this register reserved factory testing except WmarkSel bits. These bits level buffer trigger backpressure eliminate buffer overflow.
Table System Status Register (Register
NAME EPTimeOut DESCRIPTION EEPROM Time Out. EEPROM initializes device. Device ready programmed CPU. Checksum correct. EEPROM checksum error. SGRAM Initialization Done. SRAM Initialization Done. Register Initialization Done. Traffic Counter.
10~7
CheckSumErr Sgraminitdone Sraminitdone Reginitdone TrafCnt Reserved Version
AL125 0011.
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Table Port Operation Status Registers
NAME LinkFail Port Link Status. Normal Fail Port Status. Normal Error Port Security Violation. Normal Violation port mode ([1:0]) 2'b01 2'b11: Pause Disable. Pause Enable. port mode ([1:0]) 2'b00 2'b10: Backpressure Based CRS. Backpressure Based Collision. Port Broadcast Storm Status. Normal Stormed Port Input Buffer Full Status. Normal Input buffer full experienced. Table Entry Unavailability Learning. Normal Unavailability experienced. Port Jabber Status. Normal Jabber experienced. Port Late Collision Status. Normal Late collision experienced. Port Transmit Pause Status. transmit pause experienced. Transmit pause experienced. Port Carrier Sense Loss During Transmission Status. carrier sense loss experienced. Carrier sense loss experienced. DESCRIPTION
PHYError
Sviolation
FlowCtrl
Stormed
InBFull
TblUNAVL
Jabbered
LateCOL
TxPaused
CRSLoss
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Table Port Operation Status Registers (Continued)
FalseCRS False Carrier Status. Normal False carrier experienced. Transmit Queue Underflow Status. Normal Underflow experienced. Frame Time Out. Normal. Underflow experienced. Port Operating Mode. Mbit/s half-duplex. Mbit/s full-duplex. Mbit/s half-duplex. Mbit/s full-duplex.
Underflow
TimeOut
PortMode
Indirect Resource Access Command Register (Register This register used managing resource switch.
Table Indirect Resource Access Command Register (Register
NAME CmdDone Command Done. command. Done command. Read/Write Operation Command. Read operation. Write operation. Type Accessed Resource. 000: Registers 001: EEPROM 010: SGRAM 011: Address Tables Read: sequential read Write: address learn 100: Address Tables (II) Read: address search Write: address delete 101: IPMC Table 110: VLAN Table 111: Reserved DESCRIPTION
Operation
13~11
ResType
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Table Indirect Resource Access Command Register (Register (Continued)
ExtRD ResType Operation On-chip address table sequential read. Off-chip address table sequential read. Address Entry Within Accessed Resource. Off-Chip Address Table Sequential Read, iradata4 stores Address Entry will overwritten output data. VLAN table access, iradata5[12:1] stores address iradata5[0] holds most significant (MSB) data. IPMC table access, iradata5[0] holds data.
10~0
ResAddr
Table Indirect Resource Access Data Register (Register
15~0 NAME IRAData DESCRIPTION Indirect Resource Access Data
Table Indirect Resource Access Data Register (Register
15~0 NAME IRAData DESCRIPTION Indirect Resource Access Data
Table Indirect Resource Access Data Register (Register
15~0 NAME IRAData DESCRIPTION Indirect Resource Access Data III.
Table Indirect Resource Access Data Register (Register
15~0 NAME IRAData DESCRIPTION Indirect Resource Access Address/Data
Table Indirect Resource Access Data Register (Register
15~0 NAME IRAData DESCRIPTION Indirect Resource Access Address/Data
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RMON Source Destination Registers These registers used RMON manager frame counting. RMON manager counts frames (destination) from (source) these addresses stored register. 48-bit address programmed three separate registers. Source address stored registers destination address register
Table Monitored Source Host Register (Register
15~0 NAME SRCMAC[47:32] DESCRIPTION Monitored Source Host Address [47:32].
Table Monitored Source Host Register (Register
15~0 NAME SRCMAC[31:16] DESCRIPTION Monitored Source Host Address [31:16].
Table Monitored Source Host Register (Register
15~0 NAME SRCMAC[15:0] DESCRIPTION Monitored Source Host Address [15:0].
Table Monitored Destination Host Register (Register
15~0 NAME DSTMAC[47:32] DESCRIPTION Monitored Destination Host Address [47:32].
Table Monitored Destination Host Register (Register
15~0 NAME DSTMAC[31:16] DESCRIPTION Monitored Destination Host Address [31:16].
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Table Monitored Destination Host Register (Register
15~0 NAME DSTMAC[15:0] DESCRIPTION Monitored Destination Host Address [15:0].
Table Default Priority Register (Register 4E~6E)
14~12 11~0 NAME Reserved Priority Reserved Default Port Priority. DESCRIPTION
Table Checksum (Register
15~8 NAME CheckSum Reserved Checksum. DESCRIPTION
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Timing Requirements
Table Transmit Timing
SYMBOL ttdv ttxev DESCRIPTION TXCLK valid time. TXCLK TXEN valid time. UNIT
Table RMII Transmit Timing
SYMBOL ttdv ttxev DESCRIPTION TXCLK valid time. TXCLK TXEN valid time. UNIT
Note: Delays assuming 10pf loading output pins.
TXCLK
ttxev
ttxev
TXEN
ttdv
DATA
DATA
DATA
DATA
DATA
DATA
Figure
Transmit Timing Diagram
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Table Receive Timing
SYMBOL trxds trxdh DESCRIPTION RX_DV, RXD, RX_ER, setup time RX_DV, RXD, RX_ER hold time UNIT
Table RMII Receive Timing
SYMBOL trxds trxdh DESCRIPTION RX_DV, RXD, RX_ER, setup time. RX_DV, RXD, RX_ER hold time. UNIT
RXCLK
trxdh
RXDV
trxds trxdh
DATA
DATA
DATA
DATA
DATA
DATA
Figure
RMII/MII Receive Timing Diagram
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Table RoX-II Timing
SYMBOL troxs troxh DESCRIPTION Setup time Hold time UNIT
RICLK troxs troxh
Figure
RoX-II Timing
Table Management (MDIO) Read Timing
SYMBOL DESCRIPTION high time time period MDIO setup time MDIO hold time UNIT
MDIO
Figure
Management Read Timing
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Table Management (MDIO) Write Timing
SYMBOL DESCRIPTION high time time period MDIO output delay UNIT
MDIO
Figure
Management Write Timing
Table SGRAM Refresh Timing
SYMBOL tCHI tCKH tCKS DESCRIPTION Access hold time. Access setup time. PBCS#, PBRAS#, PBWE# hold time. Clock high level width. System clock cycle time. hold time. setup time. Clock level width. PBCS#, PBRAS#, PBWE# setup time. Precharge command period. Auto-refresh auto-refresh period. UNIT
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Table SGRAM Read Timing
SYMBOL tchi tckh tcks tras trcd DESCRIPTION Access time. Access hold time. Access setup time. PBCS#, PBRAS#, PBWE# hold time. Clock high level width. System clock cycle time. hold time. setup time. Clock level width. PBCS#, PBRAS#, PBWE# setup time. Data high impedance time. Data impedance time. Data hold time. Active precharge command period. Active read delay. UNIT
Note: This timing requirement SGRAM running Latency Typically speed grade SGRAM needs used.
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Table SGRAM Write Timing
SYMBOL tchi tckh tcks tras trcd DESCRIPTION Access hold time. Access setup time. PBCS#, PBRAS#, PBWE# hold time. Clock high level width. System clock cycle time. hold time. setup time. Clock level width. PBCS#, PBRAS#, PBWE# setup time. Data hold time. Data setup time. Active precharge command period. Active read delay. 100,000 UNIT
Note: This timing requirement SGRAM running Latency Typically speed grade SGRAM needs used.
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AL125 Revision
Electrical Specifications
Note: Operation absolute maximum ratings could cause permanent damage device.
Table Maximum Ratings
Supply Voltage (VDD25) Supply Voltage (VDD33) Input Voltage Output Voltage Supply Voltage Input Voltage Output Voltage Storage Temperature -0.3V 2.75V -0.3V 3.6V -0.3 VDD33 0.3V -0.3 VDD33 0.3V -0.6V 6.0V -0.6 VDD33 0.3V -0.6 VDD33 0.3V +150
Table Recommended Operation Conditions
Supply Voltage Operating Temperature Power Dissipation 2.5V 0.25V (VDD25)/ 3.3V 0.3V(VDD33) (typical)
Table Electrical Characteristics
PARAMETER DESCRIPTION Output voltage-high, Ioh=4mA. Output voltage-low, Ioh=4mA. High impedance state output current. Input current-high. (With pull-up pull-down) Input current-low. (With pull-up pull-down) Input high voltage. Input voltage. Supply current. 0.7*VDD33 330mA(2.5) 350mA(3.3) 0.3*VDD33 UNIT
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AL125 Revision
AL125 Mechanical Data
352-Pin
24.13
0.75
1.27
0.56 1.17
2.33 0.75 0.60
Figure
AL125 Mechanical Dimensions
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AL125 Revision
Appendix (VLAN Mapping Work Sheet)
PORT 6/REG.
PORT
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PORT 7/REG.
PORT 0/REG.
PORT 1/REG.
PORT 2/REG.
PORT 3/REG.
PORT 4/REG.
PORT 5/REG.
AL125 Revision
Appendix (Port Trunk Port Assignment Work Sheet)
PORT 0/REG.
PORT 1/REG.
PORT 2/REG.
PORT 3/REG.
PORT 4/REG.
PORT 5/REG.
PORT 6/REG.
TRUNK PORT
BIT/ VALUE
TRUNK BITS TRUNK BITS
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PORT 7/REG.
AL125 Revision
Appendix (Suggested Memory Components)
Note: This only partial list memory components that used Allayer devices. AL125 uses Frame Buffer SGRAM chips that require 32-bit wide SGRAM SDRAM, that faster with latency AL125 uses Table Memory SSRAM chips that require Sync Burst pipelined SSRAM, faster. following lists some memory that used AL125.
DEVICE AL125
FREQ.
Mbit SGRAM
Mbit SGRAM MoSys MG802C512L-10 Etron EM636227Q-7 MS82V16520-7
SSRAM Micron MT58LC64K32D8LG-6.6 Micron MT58L64L32PT-6.6 71V632S4PF
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AL125 Revision
Appendix (Memory Timing Requirements)
Note: These recommended timing requirements systems.
Table SSRAM Timing Requirements
SYMBOL toehz toehz DESCRIPTION high output high-Z. Data setup time. high output high-Z data setup time. Clock data output valid. 5.9ns 4.2ns
Table SGRAM Timing Requirements
SYMBOL tras trcd DESCRIPTION System clock cycle time. Active active delay. Active precharge delay. valid output delay. Active read/write delay. Precharge active delay. 10ns 70ns 40ns 20ns 30ns
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AL125 Revision
Rev. History Prelim. rev. Updated MaxAge information (table 22). Updated SlowAge information (table 23). Changed Testing Control Register (38) reflect watermark information. Updated uplink information Port Config. Register
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Index
Numerics 24+2G Managed Routing Switch Address Aging Address Learning AL125 Mechanical Dimensions AL125 Information Appendix (VLAN Mapping Work Sheet) Appendix (Port Trunk Port Assignment Work Sheet) Appendix (Suggested Memory Components) Appendix (Memory Timing Requirements) Broadcast Storm Control Buffer Management Queue Behavior Checksum (Register Congestion Control Data Reception Electrical Characteristics Default Priority Register (Register 4E~6E) EEPROM Interface EEPROM External Address Table SSRAM Interface False Carrier Events Flow Control Frame Filtering Frame Forwarding Frame Generation Frame Transmission Full Duplex Flow Control (802.3x) Functional Description Half Duplex (Backpressure) Half Duplex Mode Operation Illegal Frame Length Indirect Resource Access Command Register (Register Indirect Resource Access Data Register (Register Indirect Resource Access Data Register (Register Indirect Resource Access Data Register (Register Indirect Resource Access Data Register (Register Indirect Resource Access Data Register (Register Multicast Group Support Trunk Load Balancing Trunking (Port Aggregation) Layer Trunking Assignment Register (Register Layer Trunking Assignment Register (Register Layer Trunking Assignment Register (Register Layer Trunking Assignment Register (Register Layer Trunking Protocol Register (Register Link Fail Over Load Balancing Long Frames Maximum Ratings MDIO Interface Receive Timing Transmit Timing Miscellaneous Pins Monitored Destination Host Register (Register Monitored Destination Host Register (Register Monitored Destination Host Register (Register Monitored Source Host Register (Register Monitored Source Host Register (Register Monitored Source Host Register (Register Auto-negotiation Mode Other Options Output Queue Management Register (Register Output Queue Management Register (Register Configuration) Management Management (MDIO) Write Timing Management Master Mode Management MDIO Management Slave Mode Descriptions Diagram (Top View) Port Based Load Balancing Example Port Based Trunk Load Balancing Port Based Trunking (Port Aggregation) Port Based VLAN Port Configuration Registers Port Configuration Registers Port Monitoring Port Monitoring Configuration Register (Register Port Operation Status Registers Port VLAN Registers Port VLAN Registers Port VLAN Example Power Interface Priority Queue Assignment Register (Register Priority Queue Weight Round-Robin Control Register (Register Priority Queues User Priority Support Programming EEPROM with Parallel Port Queue Management
Reference Only Allayer Communications
AL125 Revision
Read Cycle Timing Recommended Operation Conditions Reduced Media Independent Interface (RMII) Register Descriptions AL126 Reprogramming EEPROM Configuration RMII Interface (Port RMII Interface (Port RMII Interface (Port RMII Interface (Port RMII Interface (Port RMII Interface (Port RMII Receive Timing RMII Signal (Port RMII Transmit Timing RMII/MII Interface (Port RMON Source Destination Registers RoX-II (Input Interface) RoX-II Timing RoX-II Control Register (Register RoX-II Control Register (Register RoX-II Interface RoX-II Output Interface Secure Mode Operation SGRAM Interface SGRAM Timing Requirements SGRAM Write Timing Spanning Tree Support Special Frame Identification Trapping Start Stop Static Address Entry Format EEPROM Summary Programmable Control Transmit Receive Summary Programmable Options Address Learning System Configuration Register (Register System Configuration Register (Register System Configuration Register (Register System Configuration Register (Register System Initialization System Performance Tuning Control Register (Register System Status Register (Register Tagged VLAN Test Control Register (Register Testing Control Register (Register Timing Requirements Trunk Configuration Trunk Port Assignment Trunk Port Assignment Registers (2F~36) Trunking (Port Aggregation) Uplink Port Vendor Operating Mode (Register VLAN Extension Register (Register VLAN Extension Register (Register VLAN Mapping Port Based Load Balancing Trunk VLAN Support
Write Cycle Timing
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