Supports eight 10/100 Mbit/s Ethernet ports with RMII interface Capabl
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AL116 Revision Port 10/100 Mbit/s Dual Speed Fast Ethernet Switch
Supports eight 10/100 Mbit/s Ethernet ports with RMII interface Capable trunking Mbit/s link Full- half-duplex mode operation Speed auto-negotiation through MDIO Built-in storage addresses expandable Designed utilize low-cost SGRAM Scalable design stackable switch implementation expansion link supports Gbit/s throughput Serial EEPROM interface low-cost system configuration Gigabit Ethernet ready Automatic source address learning Secure mode traffic filtering Broadcast storm control Port monitoring support IEEE 802.3x flow control full-duplex operation Optional backpressure flow control support half-duplex operation Supports store-and-forward mode switching VLAN support RMON SNMP support with external management (MIB) device 3.3V operation Packaged 456-pin
Product Description AL116 eight-port 10/100 Mbit/s dual speed Ethernet switch. low-cost scalable solution ports achieved through low-cost buffer memory Allayer's proprietary RoXarchitecture. addition, AL116 supports VLAN multiple link aggregation trunks.
10/100
Switch Controller
Buffer Manager
10/100 Expansion Interface
10/100 High Speed Switch Fabric
Address Control
10/100
10/100
Address Table
Address Table Expansion
10/100 EEPROM Interface Management Information 10/100
10/100
Figure
System Block Diagram
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This document contains proprietary information which shall reproduced, transferred other documents, used other purpose without prior written consent Allayer Communications.
Disclaimer Allayer Communications reserves right make changes, without notice, product(s) described information contained herein order improve design and/or performance. Allayer Communications assumes responsibility liability these products, conveys license title under patent copyright these products, makes representations warranties that these products free from patent copyright infringement unless otherwise specified.
Life Support Applications Allayer Communications products designed life support appliances, systems, devices where malfunctions reasonably expected result personal injury.
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Table Contents
AL116 Overview Descriptions. Functional Description. Interface. Data Reception. 3.2.1 3.2.2 3.2.3 3.2.4 3.3.1 3.3.2 3.3.3 Illegal Frame Length. Long Frames False Carrier Events Frame Filtering. Broadcast Storm Control. Frame Transmission. Frame Generation.
Frame Forwarding.
Half Duplex Mode Operation Secure Mode Operation Address Learning 3.6.1 Address Aging. VLAN Support. Port Aggregation (Trunking). 3.8.1 3.8.2 3.8.3 3.8.4 Load Balancing Trunk Port Assignment Port Based Trunk Loading Based Load Balancing
3.10
Spanning Tree Support. Flow Control Half Duplex Flow Control (Backpressure) Full Duplex Flow Control (802.3x)
3.10.1 3.10.2 3.11 3.12 3.13 3.14 3.15
Queue Management Uplink Port. Port Monitoring. Media Independent Interface (MII) Reduced Media Independent Interface (RMII).
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3.16
Management. Management MDIO Management Master Mode Management Slave Mode. Auto-negotiation Mode Other Options. System Initialization Start Stop Write Cycle Timing Read Cycle Timing Reprogramming EEPROM Configuration. EEPROM MAP.
3.16.1 3.16.2 3.16.3 3.16.4 3.16.5 3.17 3.17.1 3.17.2 3.17.3 3.17.4 3.17.5 3.17.6 3.18
EEPROM Interface
SGRAM Interface
Register Description Timing Requirements. Electrical Specifications AL116 Mechanical Data. Appendix (VLAN Mapping Work Sheet) Appendix (Port Trunk Port Assignment Work Sheet) Appendix (Suggested Memory Components).
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AL116 Overview
interface Gbit/s interface (4.8 Gbit/s full-duplex). interface support four switch chips. Various combinations used different configurations. maximum port configuration will either 32-100 Mbit/s ports 24-100 Mbit/s ports plus Gigabit Ethernet ports. interface also supports external management device, AL300A. SNMP RMON supported through this external management device. AL116 provides eight 10/100 Mbit/s Ethernet ports. Each port supports both Mbit/ data rate. operation mode auto-negotiated PHY. ports full-duplex capable. device also supports VLAN workgroup segment switching applications. AL116 also supports trunking applications. chip provides optional load balancing schemes, explicit dynamic. With trunking, possible group four full-duplex links together form single Mbit/s link. Data received from interface stored external memory buffer. AL116 utilizes cost effective SGRAM provide 8-Mbit 16-Mbit buffer memory. During transmission, data obtained from buffer memory routed destination port. event collision during half-duplex operations, control will back retransmit accordance IEEE 802.3 specification. AL116 provides flow control methods. half-duplex operations, optional jamming based flow control (also known backpressure) available prevent loss data. With this method flow control, switch will generate signal when receive-buffer full. sending station will transmit until line clear. full-duplex mode, AL116 utilizes IEEE 802.3x flow control mechanism. ports support multiple addresses. switch chip supports addresses internally. These addresses shared among eight ports. Additional SRAM added provide support addresses. initialization configuration switch programmed external EEPROM. unmanaged switch design, there need CPU. Field reconfiguration achieved using parallel interface reprogram EEPROM. managed switch applications AL116 supports network management through network management option. When management option enabled, network statistic each port gathered sent across bus. management information base chip will collect store data network management agent. Access statistic counters provided interface device. AL116 also supports port based VLAN. VLAN register used configure destination ports multicast broadcast frames. device also provides levels security intrusion protection. Security implemented port basis. AL116 operates only store forward mode. entire frame checked error. Frames with errors automatically filtered will forwarded destination port. Other features include port monitoring broadcast storm throttling.
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AL116 Diagram
Figure
Diagram (Top View)
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Descriptions
AL116 also supports RMII interface. When RMII interface used TXD3, TXD2, TXCLK, RXDV, RXER, should left unconnected. RXCLK should connected reference clock. RXCLK provided each individual port reduce clock skew.
Table RMII/MII Interface (Port
NAME M0TXD3 M0TXD2 M0TXD1 M0TXD0 DESCRIPTION Transmit Data data transmitted transceiver. mode, signal TX_EN TXD0 through TX_D3 clocked rising edge TX_CLK. RMII mode, M0TXD1 M0TXD0 clocked RMII reference clock M0RXCLK. Transmit Enable Synchronous transmit clock mode. RMII mode, M0TXEN synchronous M0RXCLK. Transmit Clock Input. Mbit/s Mbit/s. (Not used RMII mode). Receive Data data from transceiver. interface, signal RX_DV, RX_ER RX_D0 through RX_D3 sampled rising edge M0RXCLK. RMII mode, M0RXD3 M0RXD2 used. M0RXD1and M0RXD0 sampled rising edge RMII reference clock M0RXCLK. Receive Data Valid. Active high. Receive Clock (MII mode). RMII clock port Receive Data Error. Active high. (Not used RMII mode). Carrier Sense. Active high. Collision Detect. Active high. (Not used RMII mode).
M0TXEN
M0TXCLK M0RXD3 M0RXD2 M0RXD1 M0RXD0
M0RXDV M0RXCLK M0RXER M0CRS M0COL
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Table RMII/MII Interface (Port
NAME M1TXD3 M1TXD2 M1TXD1 M1TXD0 DESCRIPTION Transmit Data data transmitted transceiver. mode, signal TX_EN TXD0 through TX_D3 clocked rising edge TX_CLK. RMII mode, M1TXD1 M1TXD0 clocked RMII reference clock M3RXCLK. Transmit Enable Synchronous transmit clock mode. RMII mode, M1TXEN synchronous M3RXCLK. Transmit Clock Input. Mbit/s Mbit/s. (Not used RMII mode). Receive Data data from transceiver. interface, signal RX_DV, RX_ER RX_D0 through RX_D3 sampled rising edge M3RXCLK. RMII mode, M1RXD3 M1RXD2 used. M1RXD1and M1RXD0 sampled rising edge RMII reference clock M3RXCLK. Receive Data Valid. Active high. Receive Clock (MII mode). RMII clock port Receive Data Error. Active high. (Not used RMII mode). Carrier Sense. Active high. Collision Detect. Active high. (Not used RMII mode).
M1TXEN
M1TXCLK M1RXD3 M1RXD2 M1RXD1 M1RXD0
M1RXDV M1RXCLK M1RXER M1CRS M1COL
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Table RMII/MII Interface (Port
NAME M2TXD3 M2TXD2 M2TXD1 M2TXD0 DESCRIPTION Transmit Data data transmitted transceiver. mode, signal TX_EN TXD0 through TX_D3 clocked rising edge TX_CLK. RMII mode, M2TXD1 M2TXD0 clocked RMII reference clock M3RXCLK. Transmit Enable Synchronous transmit clock mode. RMII mode, M2TXEN synchronous M3RXCLK. Transmit Clock Input. Mbit/s Mbit/s. (Not used RMII mode). Receive Data data from transceiver. interface, signal RX_DV, RX_ER RX_D0 through RX_D3 sampled rising edge M3RXCLK. RMII mode, M2RXD3 M2RXD2 used. M2RXD1and M2RXD0 sampled rising edge RMII reference clock M3RXCLK. Receive Data Valid. Active high. Receive Clock (MII mode). RMII clock port Receive Data Error. Active high. (Not used RMII mode). Carrier Sense. Active high. Collision Detect. Active high. (Not used RMII mode).
M2TXEN
M2TXCLK M2RXD3 M2RXD2 M2RXD1 M2RXD0
M2RXDV M2RXCLK M2RXER M2CRS M2COL
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Table RMII/MII Interface (Port
NAME M3TXD3 M3TXD2 M3TXD1 M3TXD0 AD10 DESCRIPTION Transmit Data data transmitted transceiver. mode, signal TX_EN TXD0 through TX_D3 clocked rising edge TX_CLK. RMII mode, M3TXD1 M3TXD0 clocked RMII reference clock M3RXCLK. Transmit Enable Synchronous transmit clock mode. RMII mode, M3TXEN synchronous M3RXCLK. Transmit Clock Input. Mbit/s Mbit/s. (Not used RMII mode). Receive Data data from transceiver. interface, signal RX_DV, RX_ER RX_D0 through RX_D3 sampled rising edge M3RXCLK. RMII mode, M3RXD3 M3RXD2 used. M3RXD1and M3RXD0 sampled rising edge RMII reference clock M3RXCLK. Receive Data Valid. Active high. Receive Clock (MII mode). RMII clock port Receive Data Error. Active high. (Not used RMII mode). Carrier Sense. Active high. Collision Detect. Active high. (Not used RMII mode).
M3TXEN
AE10
M3TXCLK M3RXD3 M3RXD2 M3RXD1 M3RXD0
AF10 AF12 AD12 AC12 AF11
M3RXDV M3RXCLK M3RXER M3CRS M3COL
AE11 AD11 AC11
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Table RMII/MII Signal (Port
NAME M4TXD3 M4TXD2 M4TXD1 M4TXD0 AD16 AE16 AF16 AD17 DESCRIPTION Transmit Data data transmitted transceiver. mode, signal TX_EN TXD0 through TX_D3 clocked rising edge TX_CLK. RMII mode, M4TXD1 M4TXD0 clocked RMII reference clock M3RXCLK. Transmit Enable Synchronous transmit clock mode. RMII mode, M4TXEN synchronous M3RXCLK. Transmit Clock Input. Mbit/s Mbit/s. (Not used RMII mode). Receive Data data from transceiver. interface, signal RX_DV, RX_ER RX_D0 through RX_D3 sampled rising edge M3RXCLK. RMII mode, M4RXD3 M4RXD2 used. M4RXD1and M4RXD0 sampled rising edge RMII reference clock M3RXCLK. Receive Data Valid. Active high. Receive Clock (MII mode). RMII clock port Receive Data Error. Active high. (Not used RMII mode). Carrier Sense. Active high. Collision Detect. Active high. (Not used RMII mode).
M4TXEN
AE17
M4TXCLK M4RXD3 M4RXD2 M4RXD1 M4RXD0
AF17 AF19 AD19 AC19 AF18
M4RXDV M4RXCLK M4RXER M4CRS M4COL
AE18 AD18 AC18 AD15 AF15
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Table RMII/MII Signal (Port
NAME M5TXD3 M5TXD2 M5TXD1 M5TXD0 AF26 AE26 AD25 AC24 DESCRIPTION Transmit Data data transmitted transceiver. mode, signal TX_EN TXD0 through TX_D3 clocked rising edge TX_CLK. RMII mode, M5TXD1 M5TXD0 clocked RMII reference clock M3RXCLK. Transmit Enable Synchronous transmit clock mode. RMII mode, M5TXEN synchronous M3RXCLK. Transmit Clock Input. Mbit/s Mbit/s. (Not used RMII mode). Receive Data data from transceiver. interface, signal RX_DV, RX_ER RX_D0 through RX_D3 sampled rising edge M3RXCLK. RMII mode, M5RXD3 M5RXD2 used. M5RXD1and M5RXD0 sampled rising edge RMII reference clock M3RXCLK. Receive Data Valid. Active high. Receive Clock (MII mode). RMII clock port Receive Data Error. Active high. (Not used RMII mode). Carrier Sense. Active high. Collision Detect. Active high. (Not used RMII mode).
M5TXEN
AC25
M5TXCLK M5RXD3 M5RXD2 M5RXD1 M5RXD0
AC26 AA26 AA24 AA23 AB26
M5RXDV M5RXCLK M5RXER M5CRS M5COL
AB25 AB24 AB23 AE24 AE25
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Table RMII/MII Signal (Port
NAME M6TXD3 M6TXD2 M6TXD1 M6TXD0 DESCRIPTION Transmit Data data transmitted transceiver. mode, signal TX_EN TXD0 through TX_D3 clocked rising edge TX_CLK. RMII mode, M6TXD1 M6TXD0 clocked RMII reference clock M3RXCLK. Transmit Enable Synchronous transmit clock mode. RMII mode, M6TXEN synchronous M3RXCLK. Transmit Clock Input. Mbit/s Mbit/s. (Not used RMII mode). Receive Data data from transceiver. interface, signal RX_DV, RX_ER RX_D0 through RX_D3 sampled rising edge M3RXCLK. RMII mode, M6RXD3 M6RXD2 used. M6RXD1and M6RXD0 sampled rising edge RMII reference clock M3RXCLK. Receive Data Valid. Active high. Receive Clock (MII mode). RMII clock port Receive Data Error. Active high. (Not used RMII mode). Carrier Sense. Active high. Collision Detect. Active high. (Not used RMII mode).
M6TXEN
M6TXCLK M6RXD3 M6RXD2 M6RXD1 M6RXD0
M6RXDV M6RXCLK M6RXER M6CRS M6COL
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Table RMII/MII Signal (Port
NAME M7TXD3 M7TXD2 M7TXD1 M7TXD0 DESCRIPTION Transmit Data data transmitted transceiver. mode, signal TX_EN TXD0 through TX_D3 clocked rising edge TX_CLK. RMII mode, M7TXD1 M7TXD0 clocked RMII reference clock M3RXCLK. Transmit Enable Synchronous transmit clock mode. RMII mode, M7TXEN synchronous M3RXCLK. Transmit Clock Input. Mbit/s Mbit/s. (Not used RMII mode). Receive Data data from transceiver. interface, signal RX_DV, RX_ER RX_D0 through RX_D3 sampled rising edge M3RXCLK. RMII mode, M7RXD3 M7RXD2 used. M7RXD1and M7RXD0 sampled rising edge RMII reference clock M3RXCLK. Receive Data Valid. Active high. Receive Clock (MII mode). RMII clock port Receive Data Error. Active high. (Not used RMII mode). Carrier Sense. Active high. Collision Detect. Active high. (Not used RMII mode).
M7TXEN
M7TXCLK M7RXD3 M7RXD2 M7RXD1 M7RXD0
M7RXDV M7RXCLK M7RXER M7CRS M7COL
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Table Input Interface
NAME RID31 RID30 RID29 RID28 RID27 RID26 RID25 RID24 RID23 RID22 RID21 RID20 RID19 RID18 RID17 RID16 RID15 RID14 RID13 RID12 RID11 RID10 RID9 RID8 RID7 RID6 RID5 RID4 RID3 RID2 RID1 RID0 RIDH RICTL7 RICTL6 RICTL5 RICTL4 RICTL3 RICTL2 RICTL1 RICTL0 RICTLH RICLK DESCRIPTION
Ring Input Device.
Ring Control Signal.
Ring Clock.
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Table Output Interface
NAME ROD31 ROD30 ROD29 ROD28 ROD27 ROD26 ROD25 ROD24 ROD23 ROD22 ROD21 ROD20 ROD19 ROD18 ROD17 ROD16 ROD15 ROD14 ROD13 ROD12 ROD11 ROD10 ROD9 ROD8 ROD7 ROD6 ROD5 ROD4 ROD3 ROD2 ROD1 ROD0 RODH ROCTL7 ROCTL6 ROCTL5 ROCTL4 ROCTL3 ROCTL2 ROCTL1 ROCTL0 ROCTLH AF23 AE23 AD23 AC23 AF22 AE22 AD22 AF21 AE21 AD21 AC21 AF20 AE20 AD20 DESCRIPTION
Ring Output Device.
Ring Output Data Header.
Ring Control Data.
Ring Output Control Header.
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Table SGRAM Interface
NAME PBD31 PBD30 PBD29 PBD28 PBD27 PBD26 PBD25 PBD24 PBD23 PBD22 PBD21 PBD20 PBD19 PBD18 PBD17 PBD16 PBD15 PBD14 PBD13 PBD12 PBD11 PBD10 PBD9 PBD8 PBD7 PBD6 PBD5 PBD4 PBD3 PBD2 PBD1 PBD0 PBA10_9 DESCRIPTION
SGRAM Data Sheet.
This connected address when connected SGRAM address when connected SGRAM. This connected address when connected SGRAM address when connected SGRAM. This connected address when connected SGRAM connect SGRAM.
PBA9_8
PBANC8
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Table SGRAM Interface (Continued)
NAME PBA7 PBA6 PBA5 PBA4 PBA3 PBA2 PBA1 PBA0 PBCS# PBRAS# PBCAS# PBWE# PBCLK DESCRIPTION SGRAM address line PBA0-PBA8 sampled during ACTIVE command (row address) READ/WRITE command (column address with PBA8 defining auto precharge).
Chip Select. enables disables command decoder SGRAM. SGRAM Address Strobe. SGRAM Column Address Strobe. Write Enable. System clock output drive SGRAM.
Table External Address Table SRAM Interface
NAME ETD15 ETD14 ETD13 ETD12 ETD11 ETD10 ETD9 ETD8 ETD7 ETD6 ETD5 ETD4 ETD3 ETD2 ETD1 ETD0 AB11 AB12 AB14 AB18 AB19 AB20 DESCRIPTION
SRAM Data Bus.
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Table External Address Table SRAM Interface (Continued)
NAME ETA15 ETA14 ETA13 ETA12 ETA11 ETA10 ETA9 ETA8 ETA7 ETA6 ETA5 ETA4 ETA3 ETA2 ETA1 ETA0 ETADSC# ETADV# ETGW# ETOE# ETCLK AA22 DESCRIPTION
SRAM Address Line.
Synchronous Address Status Controller. Synchronous Address Advance. Used advance SRAMs internal burst counter. Global Write. Enables full 32-bit write. Output Enable. Active low. This enables output driver. System Clock Output.
Table EEPROM Interface
NAME EEDIO EECLK NUMBER DESCRIPTION EEPROM Data Input Output. EEPROM Clock.
Table MDIO Interface
NAME MDIO NUMBER AD13 AE13 DESCRIPTION Management Clock. Management Data Input Output.
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Table Miscellaneous Pins
NAME DEVID1 DEVID0 RESET# TESTMODE EPBYPASS SYSCLK TRST TCLK NUMBER AF13 AC14 AD14 AE14 AF14 DESCRIPTION Device Number. Reset Test Mode Pin. This should grounded normal operation. Status Serial Output (for testing). This bypasses EEPROM setup. This should tied ground. system clock. Reserved JTAG scan. Testing output. Leave unconnected. Reserved JTAG scan. Testing output. Leave unconnected. Reserved JTAG scan. Testing output. Leave unconnected. Reserved JTAG scan. Testing output. Leave unconnected. Reserved JTAG scan. Testing output. Leave unconnected.
Table Power Interface
NAME NUMBER A18, A19, A23, A24, A26, B12, B15, B23, C10, C12, C15, D10, D17, D18, D23, E25, K23, L23, M23, N25, U23, Y23, AA2, AA25, AB4, AC8, AC9, AC10, AC15, AC16, AC20, AD24, AE8, AE15, AE19, AF2, AF3, AB15, AB16, A20, B13, C13, C24, D19, G23, H23, J23, J25, R23, T23, U25, W23, AC4, AC5, AC7, AC13, AC17, AC22, AE12, AF24, AF25, DESCRIPTION Ground
(3.3V)
supply voltage.
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Table Power Interface (Continued)
NAME VccM NUMBER AD26 DESCRIPTION Supply voltage MII. interface, VccM should 3.3V interface, VccM should 3.3V. Connect.
E10, E18, E19, G22, J22, R22, U22, AB5, AB7, AB8, AB10, AB13, AB17, AB21, AB22, M22, W22,
MXTXD3 MXTXD2 MXTXD1 MXTXD0 MXTXEN MXTXCLK MXRXD3 MXRXD2 MXRXD1 MXRXD0 MXRXDV MXRXCLK MXRXER MXCRS MXCOL PBD[n] PBA[n] PBBA PBCS PBRAS PBCAS PBWE PBDSF PBDQM PBCLK
10/100 10/100 10/100 10/100 10/100 10/100 10/100 10/100 High Speed Switch Fabric
Switch Controller Expansion Interface Address Control
ROD[n] ROCTL[n] RODH ROCTLH RID[n] RICTL[n] RIDH RICTLH RICLK Control Signals ETA[n] ETD[n]
SRAM Interface Address Table
Buffer Manager
Management Management Information EEPROM Interface
MDIO
EEDIO EECLK DEVID1 DEVID0 RESET
Figure
Interface Block Diagram
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Functional Description
Interface
switch system shown Figure 24-port 10/100 Mbit/s switch with Gigabit Ethernet ports. This system utilizes Allayer's proprietary architecture. architecture ring structure that serves system backplane.
AL300A
AL116
AL116
AL116
AL1000
Figure
Managed Switch using with Port Mbps Gpbs Ports
ring composed data ring control ring. data ring used transfer frame data, events, well system configuration status report messages. control ring used communicate ring protocol messages among devices switch backbone resources data transfer data ring. Each device ring input interface receiving data frames ring protocol messages from upstream device, output interface transmitting data frames ring protocol messages downstream device. management device (MIB) resides ring. provides network management function devices ring. device collects network statistics switch system well provides system configurations devices. interface provided device. This supporting chip, AL300A, provides full statistical counters support both SNMP RMON network management.
Data Reception
port will into receive-state when RX_DV interface asserted. presents received data four-bit nibbles that synchronous receive clock MHz). AL116 will then attempt detect occurrence (10101011) pattern. preamble data prior discarded. Once detected, frame data forwarded stored buffer switch. 3.2.1 Illegal Frame Length During receiving process, will monitor length received frame. Legal Ethernet frames should have length less than bytes more than 1536 bytes. frames with illegal frame length discarded.
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3.2.2 Long Frames AL116 handle frames 1536 bytes. frames longer than 1536 bytes will discarded. port continued receive data after 1536th byte, port's data will filtered. port half-duplex mode, port will longer able transmit receive data during long frame reception. 3.2.3 False Carrier Events carrier sense (CRS) signal interface asserted receive data valid (RX_DV) signal asserted within 16BT, port considered have false carrier event. false carrier event recorded counter. 3.2.4 Frame Filtering AL116 will make filtering forwarding decisions each frame received based frame routing table, VLAN Mapping, port state, system configuration. Under following conditions, received frames filtered. AL116 will check received frames errors such symbol error, error, short event, runt, long event, etc. Frames with kind error will forwarded their destination port. frame heading source port will filtered. Frames heading disabled receiving port will filtered. input buffer port full, incoming frame will discarded. recommended that flow control used prevent loss data. flow control option enabled, this event will occur. remote station will transmit frame when input buffer becomes available. frame security violation security option enabled receiving port. Spanning Tree Protocol enabled, AL116 will forward frame below. port Block-N-Listen state Learning state, frame forwarded when BPDU frame, otherwise frame discarded. port Forwarding State, forward frame when BPDU frame.
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Frame Forwarding
After frame received, source address (SA) destination address (DA) retrieved. used update port's address table described previously used determine frame's destination port. Address Lookup Engine will attempt match destination address with addresses stored address table. there match found, link between source port destination port then established. first destination address "0," frame regarded unicast frame. destination address passed Address Lookup Engine; which returns matched destination port number identify which port should frame forwarded destination port within same VLAN receiving port, frame will forwarded. destination port does belong VLANs specified receiving ports, frame will discarded. event will recorded VLAN boundary violation. There ways that AL116 handles frames with unknown destination. forwarding decision controlled Flood Control option (System Configuration register 00). Flood Control disabled, frame will forwarded ports (except receiving port) within same VLAN receiving port. Flood Control option enabled, AL116 will forward frame only uplink port specified receiving port. Note: AL116 defines port either single port trunk. port monitoring function enabled, frame forwarding decision also subject port monitoring configurations. first destination address "1," frame will handled multicast broadcast frame. AL116 does differentiate multicast frames from broadcast frames except reserved bridge management group address, specified Table IEEE 802.1d standard. destination ports broadcast frame ports within same VLAN except source port itself. Multicast/Broadcast frame trapping (MCtrap) enabled, multicast/broadcast frames will forwarded only. 3.3.1 Broadcast Storm Control unique features provided AL116 Broadcast Storm control. This option allows user limit number broadcast frames into switch. This option implemented port basis. threshold number broadcast frames programmed register When Storm Control enabled number cumulated non-unicast frames over programmed threshold, broadcast frame discarded. Storm Control disabled number non-unicast frames received port over programmed threshold, AL116 will forward frame ports (except receiving port) within VLANs specified receiving port. port within specified VLAN, frame will also forwarded CPU. Broadcast-Storm-drop (BConly_SC) enabled, AL116 will only drop broadcast frames multicast frames.
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3.3.2 Frame Transmission AL116 transmits frames accordance IEEE 802.3 standard. AL116 will send frames with guaranteed minimum inter-packet/frame (IPG) 96BT, even received frames have less than minimum requirement. AL116 also supports transmission frames with 64BT (optional). 3.3.3 Frame Generation During transmit process, frame data read from memory buffer forwarded destination port's device nibbles. Seven bytes preamble signal (10101010) will generated first before (10101011) frame data sent. Four bytes sent last. Summary Programmable Control Transmit Receive control transmit receive port basis. options programmable Port Configuration Register (registers 1C). Data Rate Duplex Mode this option port option. Typically, speed auto negotiated. manual override, appropriate port configuration register programmed. Flow Control flow control implemented independently port basis. AL116 uses backpressure half-duplex flow control IEEE 802.3x full-duplex flow control. Flood Control AL116 provides modes unmatched address forwarding. flood-to-all option elected, AL116 will forward unmatched frames ports. Secure Mode security option implemented port basis. When port configured secured mode, security violation will disable port. security violation defined frame without matched secured port's address table.
Half Duplex Mode Operation
half-duplex operation, logic will abort transmit-process collision detected through assertion collision (COL) signal MII. Re-transmission frame scheduled accordance IEEE 802.3's truncated binary exponential backoff algorithm. transmit process encountered consecutive collisions, excessive collision error reported, AL116 will re-transmit frame unless retry-on-excessive-collision (REC) option enabled. retry-on-excessive-collision (REC) enabled, number collisions reset zero transmission started soon time inter-packet passed after last collision. collision detected after 512BT transmission, late collision error will reported, frame will still retransmitted after proper backoff time. AL116 also provides option aggressive back Port Configuration Register 01.3 (SuperMAC). This option allows back only three slots. This will create more aggressive channel capture behavior than standard IEEE backoff algorithm.
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Secure Mode Operation
AL116 provides security support port basis. Whenever secure mode enabled, port will stop learning addresses. address table each port will remain unchanged. this mode operation, address lookup table will freeze additional address will learned. AL116 provides levels security protection. most severe intrusion protection disabling port experiencing intrusion. security management (SecMgmt register will disable port frame with unlearned received secured port (security violation). Once port disabled, only enabled network management. Security management global option. alternative enable security local port level without security management. When AL116 configured such, device will only discard frames that have security violation. This used environment where intruders prevented from accessing network. Summary Programmable Registers SecMgmt Register (register this sets global security management option. AL116 will partition port that experience security violations. Security Register (register this port configuration option. When this option enabled, port secured. When port receives security violation frame will discard frame security management disable port security management
Address Learning
table lookup engine provides switching information required routing data frames. address look table through auto address learning (dynamic) manual entry (static). static addresses assigned address table EEPROM management device. static address entries will aged updated AL116. After frame received AL116, embedded source address (SA) destination addresses (DA) retrieved. source address retrieved from received frame automatically stored buffer. AL116 will then check error security violation, perform search. there error security violation, chip will store source address address lookup table. been previously stored another port's table, AL116 will delete from previously stored location. Individual Address 48-bit unique address programmed learned. will masked, i.e. multicast AL116 provides on-chip MACAddress-To-PortID/TrunkID table with entries frame destination look-up operation. Optional external SRAM used increase number address lookup 16K. AL116 address table contains both static addresses input EEPROM dynamically learned address. learns individual addresses from three different sources. Frames received with errors from local ports. Frames forwarded from other devices through ring device.
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Table Convergence message received from ring, which issued device itself. received frame contains source address that already been learned another port's address table aged out, will perform following operation based switch's configuration. security option selected port, AL116 will consider this security violation. port non-protected port, AL116 will delete from previous port's address table update current port's address table. However, static address entry, address will updated. 3.6.1 Address Aging port's address register cleared power-up, hardware reset. aging option enabled, dynamically learned will cleared refreshed less than programmed time. Summary Programmable Options Address Learning Address Aging Time address aging aging time programmed System Configuration (register 01). resolution aging time normally 1-second increments. AgeRes (register programmed resolution will 2-second increments. Static Programmed Addresses twenty static addresses programmed EEPROM address EEPROM section programming more detail.
VLAN Support
Each port AL116 assigned multiple VLANs. Frames from source port will only forwarded destination ports within same VLAN domain. broadcast/multicast frame will forwarded ports within VLAN(s) source port except source port itself. unicast frame will forwarded destination port only destination port same VLAN source port. Otherwise, frame will treated frame with unknown destination port belongs another VLAN, frame will discarded event will recorded VLAN boundary violation. Each port should assigned dedicated uplink port. Unicast frames with unknown destination addresses will forwarded uplink port source port. uplink port either single port trunk. AL116 provides VLAN register ports (register mapping ports bits). Each register contains 16-bit bit-map (total bits) indicate VLAN group port. VLAN registers hold broadcast destination mask each source port. will indicate that broadcast frames will routed from source port specified port. Note that source port must within source port VLAN, because broadcast frames routed source port. setting VLAN trunking, please section trunking detail.
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VLAN Example VLAN worksheet provided Appendix Simply marking ports wish send broadcast frame complete VLAN easily. Let's assume want VLAN groups sixteen port switch: Group consists Group consists Note: might easier mark VLAN ports first then delete source ports that don't want broadcast frames returned. completed VLAN shown Table
Table VLAN Mapping Port Based Load Balancing Trunk
PORT 6/REG. PORT 7/REG. PORT 0/REG. PORT 1/REG. PORT 2/REG. PORT 3/REG. PORT 4/REG. PORT 5/REG.
PORT
DEVICE
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Table VLAN Mapping Port Based Load Balancing Trunk (Continued)
PORT 6/REG. PORT 7/REG. PORT 0/REG. PORT 1/REG. PORT 2/REG. PORT 3/REG. PORT 4/REG. PORT 5/REG.
PORT
DEVICE
Port Aggregation (Trunking)
AL116 supports port aggregation/trunking. Port aggregation trunking basically method treat multiple physical links single logical link. benefit trunking able group multiple lower speed links into higher speed link. example, four full-duplex Mbit/s links used single 800-Mbps link. This very useful switch switch, switch server, switch router application. AL116 considers trunk single port entity regardless trunk composition. four ports grouped together single trunk link. grouping ports trunk must from four ports bottom four ports device, i.e. port port total eight trunks supported chip sets. multiple link trunk, links within trunk should have equal amount traffic order achieve maximum efficiency. requirements transmission that frames being transmitted must order. Therefore, some sort load balancing among links trunk deployed. AL116 offers alternative load balancing methods which selected System Configuration Register (register 00).
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3.8.1 Load Balancing load-balancing methods that AL116 uses support trunking port based address based. port based load balancing method explicit port assignment scheme. requires each individual port assigned specific link (trunk port) trunk. port assigned, frames might routed trunk random this could cause frames order. port based load balancing trunk two, three four-port trunk. During transmit, frame will routed from source port assigned trunk port. When frame received from trunk ports, will routed destination port within VLAN. essence, AL116 treats trunk single port within same VLAN. ports traffic evenly distributed among trunk ports, load balancing achieved aggregate bandwidth trunk high Mbit/s (full-duplex). alternative address based load balancing. When AL116 receives frame with trunk destination, will automatically forward frame port trunk based source address. address load balancing decision based proprietary algorithm. algorithm assumes trunk four-port trunk. Therefore, address based load balancing used, trunk must consist four ports. (Use based load balancing three port trunks could result loss frame.) advantage port based load balancing ability support three port trunks. 3.8.2 Trunk Port Assignment maximum number trunks Allayer's architecture eight. Port Configuration Registers provides ability designate port member trunk. trunk consist four trunk ports. trunk group must consist either four ports bottom four ports. example, trunk consist either port port Each trunk port's number sequence corresponding order port devices. example, port (See Figure
AL116
Ports
Trunk Port
Trunk Port
Figure
Trunk Port Numbering
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3.8.3 Port Based Trunk Loading port-based load balancing, trunk port must assigned each port defined trunks. port assignment done programming Port Trunk Port registers 34). recommended that ports evenly distributed among trunk ports prevent overloading single trunk port. following procedure trunk. Port Based Load Balancing Example Register bits reference where register number number. back data sheet worksheet provided port trunk port VLAN assignment. example designing eight-port switch with three-port trunk. desired trunk ports Therefore, port configuration register bits 17.9, 19.9, 1B.9 Assign Port trunk port Port trunk port port trunk port trunk ports therefore trunk number assignment port trunk port register bits should therefore 2D.2=1, 2D.3=0 2E.2=0, 2E.3=1 2F.2=1, 2F.3=1 30.2=0, 30.3=1 31.2=1, 31.3=1 Trunk ports should assigned with their port number port trunk port register. port trunk port bits should 32.2=0, 32.3=1 33.2=1, 33.3=0 34.2=1, 34.3=1
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Table Trunking Port Assignment
PORT 0/REG. PORT 1/REG. PORT 2/REG. PORT 3/REG. PORT 4/REG. PORT 5/REG. PORT 6/REG. PORT 7/REG.
TRUNK PORT
VALUE
Trunk Bits Trunk Bits Trunk Bits Trunk Bits Trunk Bits
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Table Trunking Port Assignment (Continued)
PORT 0/REG. PORT 1/REG. PORT 2/REG. PORT 3/REG. PORT 4/REG. PORT 5/REG. PORT 6/REG. PORT 7/REG.
TRUNK PORT
VALUE
Trunk Bits Trunk Bits Trunk Bits
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3.8.4 Based Load Balancing address based load balancing, there need assign port trunk port. AL116 dynamically assigns address trunk port. address based trunks must consist four trunk ports. bits chosen their randomness. statistically random bits will ensure good load balancing among four trunk ports. following procedure trunk; Select address loading setting 00.3 Select trunk ports using register Assign ports trunk port same VLAN using register port VLAN grouping should include trunk ports. Since AL116 will assign port addresses, frames from single port routed trunk ports. Based Load Balancing Example simplicity, example eight port switch with four-port trunk. desired trunk port Therefore, port configuration register bits 15.9, 17.9, 19.9, 1B.9 Assigning VLAN. VLAN assigned shown. bits except ports themselves.
Table VLAN Mapping Based Load Balancing Trunk
PORT 6/REG. PORT 7/REG. PORT 0/REG. PORT 1/REG. PORT 2/REG. PORT 3/REG. PORT 4/REG. PORT 5/REG.
PORT
DEVICE
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Table VLAN Mapping Based Load Balancing Trunk (Continued)
PORT 6/REG. PORT 7/REG. PORT 0/REG. PORT 1/REG. PORT 2/REG. PORT 3/REG. PORT 4/REG. PORT 5/REG.
PORT
DEVICE
Spanning Tree Support
AL116 capability support implementation Spanning Tree Protocol. ports programmed port state required spanning tree protocol. Spanning Tree Protocol option enabled, AL116 will forward frame below. port Block-N-Listen State Learning State, frame forwarded BPDU frame; otherwise frame discarded. outgoing frames except outgoing BPDUs will masked from path PHY. port Forwarding State, frame forwarded BPDU frame. source addresses incoming frames from will learned then forwarded based switch routing decision. outgoing frames will transmitted PHY.
port learning, source addresses incoming frames from will learned. incoming frames except incoming BPDUs from will discarded after being learned; outgoing frames except outgoing BPDUs will masked from path PHY.
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3.10 Flow Control
AL116 operate different modes, half- full-duplex. Each port operate either full- half-duplex configured have flow control enabled flow control independently port basis. 3.10.1 Half Duplex Flow Control (Backpressure) half-duplex flow control option elected, backpressure will used flow control. Whenever occupancy receiving frame buffer port full, port will start sending signal through port. After sensing signal, remote station will defer transmission. Backpressure flow control applied ensure that there dropped frame. AL116 supports types backpressure, collision based carrier based. Carrier based backpressure generated AL116 when switch port's frame buffer full. AL116 will cease line when port buffer space available frame reception. jamming signal programmed either 64BT 96BT. Collision Based backpressure generated AL116, only when switch port receives frame. AL116 will cease line when line idle. carrier based backpressure several advantages over collision based backpressure. Collision based backpressure cause late collisions. After consecutive collisions, could drop frames. AL116 option drop frame after collisions. However, terminal still drop frames. Therefore, recommend carrier based back pressure preferred method halfduplex flow control. this mode operation, also recommend that signal should 64BT. This because 96BT, terminal might still able transmit frame cause collision. excessive collision could cause frames dropped. AL116 also supports collision based backpressure customers that prefer collision based backpressure. 3.10.2 Full Duplex Flow Control (802.3x) full-duplex mode, AL116 will transmit receive frames accordance 802.3x. this mode, transmission channel receiving channel operate independently. incoming direction, whenever occupancy receiving frame buffer port full, port will send PAUSE frame with delay value maximum. PAUSE frame will deter incoming frame from flowing into port. After occupancy receiving frame buffer reduced below FlowControlOff threshold, port will then send PAUSE frame with delay value zero, resume receiving incoming frame flow. outgoing direction, whenever incoming PAUSE frame with non-zero delay value received through port, port will stop next frame transmission after ongoing frame transmission finished, start pause timer. will resume frame transmission either after pause timer expired when PAUSE frame with zero delay value received. When 802.3x flow control option elected, device will program appropriate autonegotiation capability field. When AL116 used full-duplex mode, recommended
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that flow control turned This prevent buffer from overflow loss frames. connected device 802.3x capability, then link recommended half-duplex.
3.11 Queue Management
Each port AL116 individual transmission receive queues. frames come into AL116 stored into shared memory buffer, lined transmission queues corresponding destination port. Each port AL116 input frame queue, dedicated queue buffer locally generated management event messages. Each output port maintains output frame queue for, dedicated multicast queue outgoing multicast frame parking. transmit frame from sources, local from another device ring. output queue, source selected multicast queue, device will channel copy frame head multicast queue output queue transmission. output queue, source selected local input queue, device will channel from local DRAM buffer output queue upon requested DRAM bandwidth that available. output queue, source selected from another device ring, device will send message that device trying channel through ring from source input queue that device local output queue. multicast queue, source selected local input queue, device will channel from local DRAM buffer multicast queue upon requested DRAM bandwidth available. multicast queue, source selected from another device ring, device will send message that device trying channel through ring from source input queue that device local multicast queue.
3.12 Uplink Port
uplink port provides connect switch repeater hub, workgroup switch, router, type interconnecting device compliance with IEEE 802.3 standard. port also designated uplink port. flood control enabled, AL116 will send frames with unmatched multicast/ broadcast frames uplink port. very important that each port assigned uplink port Port Configuration Register to1C), data frames might lost. uplink port should configured within same VLAN source port. uplink port member VLAN, broadcast multicast frames will forwarded designated uplink port. Multiple VLANs share same uplink port. AL116 will direct following frames uplink port: Frames with unicast destination address that does match with address stored switch. Frames with broadcast/multicast destination address uplink port same VLAN.
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Note: When configuring uplink port, uplink port should designate itself uplink port. Summary Programmable Register Designate Uplink Port (register this register provides option designate uplink port either port, trunk CPU. detail register description.
3.13 Port Monitoring
AL116 supports port monitoring which provides complete network monitoring capability Mbit/s. copy egress (TX) data ingress (RX) data monitored port sent their respective snooping ports. monitored port selected register AL116 allows transmit receive data monitored different snooping ports. snooping ports also selected register Summary Programmable Register Port Monitoring (register selects target monitored port snooping port. 5-bit Port_ID designates port. format Port_ID [Dev_ID].[Port_ID]. [Dev_ID] device number [Port_ID] port number.
3.14 Media Independent Interface (MII)
each port AL116 connected through standard interface. reception, received data (RXD) sampled rising edge receive clock (RX_CLK). Assertion receive data valid (RX_DV) signal will cause look start SFD. transmission, transmit data enable (TX_EN) signal asserted when first preamble nibble sent transmit data (TXD) lines. transmit data clocked rising edge transmit clock (TX_CLK). Prior transaction, AL116 will output thirty-two bits preamble signal. After preamble, signal used indicate start frame.
3.15 Reduced Media Independent Interface (RMII)
AL116 also supports RMII interface. RMII interface activated through System Configuration Register. RMII only signal pins clock pin. signal pins TXD0, TXD1, RXD0, RXD1, TXEN CRS. RXCLK common reference clock MHz. AL116 provides clock each port minimize clock skew effect. Note: When RMII used, other pins interface should left unconnected. reception, received data (RXD) sampled rising edge receive clock (RX_CLK). Assertion signal indicates receive channel active. di-bit RXD[1:0] nominally "00" until detect valid send preamble "01." Valid data will follow SFD.
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transmission, transmit data enable (TX_EN) signal asserted when first preamble nibble sent transmit data (TXD) lines. transmit data clocked rising edge reference clock. Prior data transaction, AL116 will output di-bits `01' preamble signal. After preamble, "11" signal used indicate start frame.
3.16 Management
AL116 supports transceiver management through serial MDIO signal lines. device provides modes management, master slave mode. master mode operation, AL116 controls operation modes link. slave mode controls operating mode. 3.16.1 Management MDIO There difference MDIO operation between RMII. write operation, device will send "01" signal write operation. Following "01" write signal will 5-bit address device 5-bit register address. "10" turn around signal then used avoid contention during read transaction. After turn around, data will written into register afterwards line will high impedance state. read operation, AL116 will output "10" indicate read operation after start frame indicator. Following "10" read signal will 5-bit address device 5bit register address. Then, AL116 will cease driving MDIO line, wait time. During this time, MDIO should high impedance state. device will then synchronize with next driven device, continue read data from register. detail timing requirement management signals described section "Timing Requirement." MDIO port disabled through port configuration register. This allows engineers 100Base-TX transceiver without auto-negotiation capability interconnect. this mode operation, communication with AL116. Therefore, AL116 will assert link status soon initialization completed assumes connected operating specified operating duplex mode speed. 3.16.2 Management Master Mode this mode, AL116 will continuously poll status devices through serial management interface, without intervention. device will also configure capability fields ensure proper operation link. access registers devices through interface provided management device, AL300A. configuration link automatic. link capability programmed AL116 through port configuration register. AL116 reads from standard IEEE registers determine auto-negotiated operating speed mode. there need manually operation mode because flow control cabling issues, AL116 port operation mode manually through MDIO interface (see EEPROM section programming AL116). used reprogram AL116, operating mode changed without reset powered down. order ensure link operating desired mode, should renegotiate either through command unplugging RJ45.
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3.16.3 Management Slave Mode slave mode, controls programming operating mode. AL116 will continuously poll status devices through serial management interface, without intervention determine operation mode link. access registers devices through interface provided management device AL300A. This mode management very useful unmanaged switches. operating mode link changed programming mode through jumper without assistance from CPU. AL116 also supports 100Base-TX transceivers without MDIO interface interface. When MDIO disabled, AL116 will operate operation mode specified Port Configuration Register (register 1C). 3.16.4 Auto-negotiation Mode AL116 also turn auto-negotiation capability PHY. When auto-negotiation turned off, AL116 slave mode transceiver will determine link's operating mode. 3.16.5 Other Options Some legacy Fast Ethernet devices cost devices have auto-negotiation capability. those cases, transceiver will able perform auto-negotiation. switch transceiver will typically parallel detection update information transceiver's register. Unfortunately, such register addresses vendor specific. AL116 provides register (register specify register address AL116 read. AL116 will read from that register configure port operation accordingly. Register also provides some additional flexibility's some PHYs market. general, system designer should devices port port port Lucent Quad PHY, LU3X54FT, utilizes address 00000 broadcast address. register allows AL116 start with address 01000. This provision allows engineers work around PHYs that have problem handling address 00000. Quad PHYs market today have port-ordering chip pinout, clockwise counter clockwise. Register programs AL116 port order either direction. This provision enables engineers easily implement designs with PHY. There also slow MDIO clock KHz) available that capable handling high speed MDIO clock. Examples these PHYs LXT970 LXT974. some reason, transceiver connected device that device fail auto-negotiate. AL116 will default data rate duplex mode default setting port configuration register.
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3.17 EEPROM Interface
AL116 provides three functions with EEPROM interface; system initialization, obtaining system status, reconfiguration system real time. 3.17.1 System Initialization EEPROM interface provided manufacturer provide pre-configured system their customers. Customers change configure their system retain their preferences. EEPROM contains configuration initialization information, which accessed power reset. organization EEPROM data shown Table AL116 uses 24C02 serial EEPROM device (2048 bits organized bits During start AL116 will detect presence EEPROM. EEPROM present, AL116 will initialized attached management device ring. initialization command received, device will operate. reset held low, AL116's EEPROM interface will into high impedance state. This feature very useful reprogramming EEPROM during installation reconfiguration. There ways that EEPROM reprogrammed, external parallel port residing ring. reprogramming using parallel port, signal used hold RESET low; EEPROM interface will then high impedance state. external device then programmed EEPROM through EDIO ECLK pins. EEPROM address should same device with (EEPROM) grounded. example, EEPROM device address device address 001.
Device Type Identifier Device Address
Figure
EEPROM Address Format
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3.17.2 Start Stop write cycle started start ended stop bit. start transition from high EEDIO when high. operation terminates when EEDIO goes from high when high (Figure Following start condition, writing device must output address EEPROM. most significant four bits EEPROM address device type identifier. These four bits 1010. EEPROM device address should device number. EECLK output from AL116. EEDIO input AL116 reading EEPROM output writing (See Figure through 10).
EECLK
EEDIO
Data Address Valid
START
Data Change
STOP
Figure
Start Stop
3.17.3 Write Cycle Timing When accessing EEPROM, reset held before writing operation begin.
Start
Device Address
Stop
EEDIO
Word Address
Data
Acknowledge
Acknowledge
Acknowledge
Figure
Typical Write Operation
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3.17.4 Read Cycle Timing Read operations initiated same manner write operations, with exception that EEPROM address "1."
Device Address Device Address
Start
Start
EEDIO
Word Address
Data
Acknowledge
Acknowledge
Acknowledge
Figure
Typical Read Operation
3.17.5 Reprogramming EEPROM Configuration There ways that system reconfigured. Figure shows application using parallel interface reprogram EEPROM. this application, parallel port holds reset pins low, force EEDIO pins high impedance. Once pins high impedance, EEPROM programmed parallel port. Once parallel port releases reset pins, devices will start download EEPROM data reconfigure devices. alternate reconfiguring system input data directly into AL116. After initialization, EEPROM interface virtual EEPROM. order this method work EEPROM's address must 0XX, AL116's address will 1XX. customer program AL116 EEPROM. read write timing same EEPROM. Because read well write AL116, status register read from AL116. This will serve very useful tool diagnostic unmanaged switch.
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Reset AL116 EECLK EEDIO EEPROM Parallel Port
AL116
Reset EECLK EEDIO EEPROM
Reset AL116
EECLK EEDIO EEPROM
Reset AL116 EECLK EEDIO EEPROM
Figure
Programming EEPROM with Parallel Port
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3.17.6 EEPROM Note: specific bits register referenced "X.Y" notation, where register number number. Table shows EEPROM addresses cross-referenced register/bit AL116. Addresses through configuring device. They downloaded AL116 during reset power Address should programmed 0000 0001 0001 0100. address indicates last address entry. static address used switch, address should programmed. Addresses used programming static address entry. format address shown follows when YXXXXX represents: then XXXXX 5-bit individual port number. Y=1, then XXXXX either trunk port represented followed digit [trunk number, port represented 11ZZZ where don't care.
Table EEPROM Addresses
Address Reserved Address 00YXXXXX Address 72-73 Address [42:32] Address 74-75 Address [31:16] Address 76-77 Address [15:0]
Table AL116 EEPROM Mapping
EEPROM PHYSICAL ADDRESS 02-03 04-05 06-07 08-09 0A-0B 0C-0D 0E-0F DESCRIPTION System Configuration [15:8] System Configuration [7:0] System Configuration System Configuration 0000 0001 0001 0100 Reserved Vendor Specific Snooping Port Configuration Monitored Host [47:32] AL116 REGISTER/BIT 00.15 00.8 00.7 00.0 01.15 01.0 02.15 02.0 03.15 03.0 04.15 04.0 05.15 05.0 06.15 06.0 07.15 07.0
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Table AL116 EEPROM Mapping (Continued)
10-11 12-13 14-15 16-17 18-19 1A-1B 1C-1D 1E-1F 20-21 22-23 24-25 26-27 28-29 2A-2B 2C-2D 2E-2F 30-31 32-33 34-35 36-37 38-39 3A-3B 3C-3D 3E-3F 40-41 42-43 44-45 46-47 48-49 4A-4B Monitored Host [31:16] Monitored Host [15:0] Monitored Host [47:32] Monitored Host [31:16] Monitored Host [15:0] Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN 08.15 08.0 09.15 09.0 0A.15 0A.0 0B.15 0B.0 0C.15 0C.0 0D.15 0D.0 0E.15 0E.0 0F.15 0F.0 10.15 10.0 11.15 11.0 12.15 12.0 13.15 13.0 14.15 14.0 15.15 15.0 16.15 16.0 17.15 17.0 18.15 18.0 19.15 19.0 1A.15 1A.0 1B.15 1B.0 1C.15 1C.0 1D.15 1D.0 1E.15 1E.0 1F.15 1F.0 20.15 20.0 21.15 21.0 22.15 22.0 23.15 23.0 24.15 24.0 25.15 25.0
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Table AL116 EEPROM Mapping (Continued)
4C-4D 4E-4F 50-51 52-53 54-55 56-57 58-59 5A-5B 5C-5D 5E-5F 60-61 62-63 64-65 66-67 68-69 6A-6B 6C-6D 70-71 72-73 74-75 76-77 78-7F 80-87 88-8F 90-97 98-9F A0-A7 A8-AF Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Reserved Checksum Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Reserved Last Entry Address Static Entry (Port Number) Static Entry (MAC [47:32]) Static Entry (MAC [31:16]) Static Entry (MAC [15:0]) Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry 2D.15 2D.0 2E.15 2E.0 2F.15 2F.0 30.15 30.0 31.15 31.0 32.15 32.0 33.15 33.0 34.15 34.0 26.15 26.0 27.15 27.0 28.15 28.0 29.15 29.0 2A.15 2A.0 2B.15 2B.0 2C.15 2C.0
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Table AL116 EEPROM Mapping (Continued)
B0-B7 B8-BF C0-C7 C8-CF D0-D7 D8-DF E0-E7 E8-EF F0-F7 F8-FF Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry Static Entry
3.18 SGRAM Interface
ports AL116 work Store-And-Forward mode that ports support both Mbit/s Mbit/s data speed. AL116 utilize central memory buffer pool, which shared ports within same device. After frame received, passed across SGRAM interface stored buffer. During transmit, frame retrieved from buffer pool forwarded destination port. AL116 designed Mbit SGRAM Mbit SGRAM cost performance. SGRAM accessed page burst access mode very high speed access. This burst mode repeatedly accessing same column. burst mode reaches column address, then wraps around first column address (=0) continues count until interrupted news read/write, pre-charge, burst stop command. AL116 will initialize SGRAM automatically. pre-charges banks inserts eight auto-refresh commands. will also program mode registers AL116 read write operations. SGRAM essentially SDRAM. Dynamic memories must refreshed periodically prevent data loss. SGRAM auto-refresh which also uses refresh address counters. SGRAM Auto-refresh command generates pre-charge command internally SGRAM. AL116 will insert auto-refresh command once every
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Register Description
Table Register Table Summary
REGISTER REGISTER DESCRIPTION System Configuration System Configuration System Configuration Reserved Testing Register Vendor Specific Status Port Monitoring Configuration Monitored Source Host [47:32] Monitored Source Host [31:16] Monitored Source Host [15:0] Monitored Destination Host [47:32] Monitored Destination Host [31:16] Monitored Destination Host [15:0] Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration Port Configuration
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Table Register Table Summary
Port Configuration Port Configuration Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port VLAN Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Port Trunk Port Assignment Reserved Reserved Reserved Reserved
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Table Register Table Summary
System Status Register Port Operation Status Port Operation Status Port Operation Status Port Operation Status Port Operation Status Port Operation Status Port Operation Status Port Operation Status Indirect Resource Access Command Indirect Resource Access Data Indirect Resource Access Data Indirect Resource Access Data Indirect Resource Access Data Check
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System Configuration Register (Register registers global system configuration registers. option selected this register affect overall system operation.
Table System Configuration Register (Register
NAME CPUprst FloodCtl DESCRIPTION Present. This AL116, when detects EEPROM absent. device will assume present. Flooding Control. Controls forwarding unicast frames with unknown destination received from non-uplink ports. Disable. Frames received with unknown unicast destination address will forwarded ports (excluding receiving port) within VLANs specified receiving port. Enable. Frames received with unknown unicast destination address will forwarded uplink port specified receiving port. Security Enforcement. Security Off. security violation secured port will change port state. Security security violation secured port will cause port into DISABLE state. Switch Table Entry Aging Control. Disable. table aging process will stopped. Enable. table aging process will running every dynamically learned table entry. Table Convergence Control. Disable. device will communicate with other devices about locally learned table entries. Enable. device will slow background process periodically transfer locally learned table entries other devices learn. Spanning Tree Protocol Enable Control. Disable. BPDU frames received from network ports will treated regular broadcast frames. Enable. BPDU frames received from network ports will forwarded only port. Port Incoming Frame Flow Monitoring Enable Cable. Disable Enable Port Outgoing Frame Flow Monitoring Enable Cable. Disable Enable
SecMgmt
AgeEn
TCNVG
STPEN
PInMon
POutMon
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Table System Configuration Register (Register (Continued)
CPUcfgrdy Configuration Ready. This AL116 when AL116 initialized CPU. initialized. Register file initialization done. Network Management Enable Control. Disable. device will generate events. Enable. device will generate events propagate them onto ring. System Initialization Complete. This when initialization completed under initialization mode. unmanaged switch, this relevant. Interface. RMII Interface. Layer Trunk Loading Method. Port based loading. Trunking decisions will based Trunk Port Assignment Registers. address based loading. Trunking decisions will based source port addresses. Frame Time Enable. Device will timeout frames based MaxDelay. Device will timeout frames. Reserved factory use. Bits should
NetMgmt
InitDone
RMII L2Trunk
TimeoutEN
Reserved
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Table System Configuration Register (Register
15~8 NAME MaxAge MaxDelay DESCRIPTION Maximum dynamically learned entries. 0000 0000: sec. 1111 1111: sec. Maximum frame transition delay through switch. second seconds seconds seconds Maximum number broadcast frames that accumulated each input frame buffer. frames frames frames frames Disable. Device will perform IEEE standard exponential back algorithm when collision occurs. Enable. When collisions occur, AL116 will back slots. Retry Excessive Collision. Normal collision handling. Retry transmission after consecutive collisions. Select bits position address trunk assignment. Source Address [1:0] Source Address [3:2] Source Address [5:4] Source Address [7:6]
MaxStorm
SuperMAC
L2TbitSel
Table System Configuration Register (Register
NAME Reserved DisPHYRst DESCRIPTION Reserved (Must Reset Option. Reset link down MDIO flow. Don't reset link down MDIO flow. Writing will reset status registers. First page. Second page. Binary Exponential Backoff Select. Normal Binary exponential.
StatusReset RegPg BebSel
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Table System Configuration Register (Register (Continued)
SlowAge Aging Time Resolution Normal aging. Slow down aging. Backpressure Select Enable. 96BT 64BT Standard Control. 96BT 64BT Backpressure Port Rate. (Collision based) SGRAM Select. 8Mbit/s SGRAM 16Mbit/s SGRAM Backpressure Control. Carrier based. Collision based. External Table Enable. Disable Enable Table Size Selection. Multicast/Broadcast Frame forward only. Flow control multicast. Flow control broadcast.
BpIPG84
IPG64
PRate SG16M
BPCOL
ETEnb
ET16K
MCTrap FlowCtrlBC
Reserved Register (Register This register reserved Allayer's use. bits should 0000 0001 0001 0100. Testing Register (Register This register reserved Allayer's use. bits should 0000 0000 0000 1000.
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Vendor Specific Register (Register This register used program vendor specific options. also used programming Vendor Specific register location location operation status.
Table Vendor Specific Register (Register
12~8 NAME PHYAD MCIkSpd PortOrder PHYOpReg PHYSpBit PHYDxModeBit DESCRIPTION Setting this will program MDIO address addresses Setting this will reduce MDIO clock speed 17HKz. Setting this will reverse ID/port number switch. PHY's Operation Status Register Number. PHY's Data Rate Status Register Number. PHY's Operating Duplex Mode Status Register Number.
Port Monitoring Configuration Register (Register This register configures port monitoring. sets monitored port snooping ports.
Table Port Monitoring Configuration Register (Register
14~10 NAME Reserved MdPID MgIPID MgOPID should Monitored Port Snooping Port incoming frame flow. Snooping Port outgoing frame flow. DESCRIPTION
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RMON Source Destination Registers (Registers These registers used RMON manager frame counting. RMON manager counts frames (destination) from (source) these addresses stored register. address programmed three separate registers. Source address stored registers destination address register
Table RMON Source Destination Registers (Registers
REGISTER 15~0 15~0 15~0 NAME SRCMAC[47:32] SRCMAC[31:16] SRCMAC[15:0] DESCRIPTION Monitored Source Host Address Monitored Source Host Address Monitored Source Host Address
Table RMON Source Destination Registers (Registers
REGISTER 15~0 15~0 15~0 NAME DSTMAC[47:32] DSTMAC[31:16] DSTMAC[15:0] DESCRIPTION Monitored Destination Host Address Monitored Destination Host Address Monitored Destination Host Address
Port Configuration Registers (Registers Registers local port configuration. There port configurations port. Port port configuration uses register Port register etc. Port Configuration Register Uplink this six-bit link assign uplink port local port. uplink port three types; single port, trunk port. uplink single port, format port [0][Dev_ID][Port_ID] uplink trunk, then bits should read [100][trunk number]. trunk number numbered [Dev_ID][Trunk_ID]. local port uplink port, uplink should port frame with unlearned will then filtered.
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Table Port Configuration Register
15~10 NAME UpLinkID DESCRIPTION Uplink associated with port. 0XXYYY: Port with device port 100XXN: Trunk with device trunk 111XXX: Port. Others: Reserved. Trunk Member Port. Individual port. Member trunk port. should zero. Broadcast Storm Control Enable. Storm control disable. broadcast frame will throttled. Storm control enable. accumulated number broadcast frames input buffer port over threshold specified system configuration register, incoming broadcast frames will discarded until number been reduced below threshold. Intrusion Protection. Security control frames received from nonuplink ports. Security off. forwarding decision made about frames received from port will involve source address checking. Security frames received from port with unknown source address with source address learned previously from another port will discarded. Port VLAN Membership. Non-member. Broadcast frames received from port will forwarded port. Member. Broadcast frames received from port will forwarded port addition other member ports specified VLAN register port (excluding source port). Learning Disable. Source address from this port will learned. Source address from this port will learned.
Tmember
Reserved StormCTL
Security
CPUOn
LrnDis
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Table Port Configuration Register (Continued)
PortST Port State Control. Disable. incoming frames from will discarded; outgoing frames will masked from path PHY. Blocking-N-Listening. incoming frames except incoming BPDUs from will discarded; outgoing frames except outgoing BPDUs will masked from path PHY. Learning. source information incoming frames from will learned; incoming frames except incoming BPDUs from will discarded after being learned; outgoing frames except outgoing BPDUs will masked from path PHY. Forwarding. source information incoming frames from will learned; incoming frames will forwarded based switch routing decision; outgoing frames will transmitted PHY. Reserved (Must
Reserved
Table Port Configuration Register
15~12 NAME Reserved FlowCtrlFdEn FlowCtrlHdEn MDIOCfg[3:0] Reserved Flow Control Full Duplex Enable. Flow Control Half Duplex Enable. MDIO Configuration. 0001: Master mode management. 0010: Slave mode management. 0111: Force mode. MDIO Disable. MDIO enabled. MIDO disabled. This relevant when MDIO enabled. When MDIO disabled, this forces port into link link down state. Link Down. Link Full Duplex Mode. Half Duplex Mode. Full Duplex Mode. Half Duplex Mode. DESCRIPTION
MDIODis
LinkUp
PrtMode100F PrtMode100H PrtMode PrtMode
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Port VLAN Registers (Registers These registers provide VLAN each port. VLAN worksheet provided Appendix
Table Port VLAN Registers (Registers
REGISTER Port0 Port1 Port2 Port3 Port4 Port5 Port6 Port7 Port0 Port1 Port2 Port3 Port4 Port5 Port6 Port7 Port0 Port1 Port2 Port3 Port4 Port5 Port6 Port7 Port0 Port1 Port2 Port3 Port4 Port5 Port6 Port7 15~8 NAME Dev3Map DESCRIPTION Port VLAN corresponding port7~port0 device with Dev_ID Non-member port. Member port.
Dev2Map
Port VLAN corresponding port7~port0 device with Dev_ID Non-member port. Member port.
15~8
Dev1Map
Port VLAN corresponding port7~port0 device with Dev_ID Non-member port. Member port.
Dev0Map
Port VLAN corresponding port7~port0 device with Dev_ID Non-member port. Member port.
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Port Trunk Port Assignment Registers (Registers Port Trunk Port assignment register assigns port trunk port-based load balancing trunking. Please example trunking section. port trunk port work sheet provided Appendix
PORT NUMBER
REGISTER
Table Port Trunk Port Assignment Registers (Registers
15~14 NAME Trunk Trunk Port Trunk Port Port Port Port Trunk Port Trunk Port Port Port Port Trunk Port Trunk Port Port Port Port Trunk Port Trunk Port Port Port Port Trunk Port Trunk Port Port Port Port Trunk Port Trunk Port Port Port Port DESCRIPTION
13~12
Trunk
11~10
Trunk
Trunk
Trunk
Trunk
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Table Port Trunk Port Assignment Registers (Registers
NAME Trunk Trunk Port Trunk Port Port Port Port Trunk Port Trunk Port Port Port Port DESCRIPTION
Trunk
Table System Status Register (Register
NAME EPTimeOut DESCRIPTION EEPROM Time Out. EEPROM initialized device. Device ready programmed CPU. EEPROM Checksum Error. SGRAM Initialization Done. SRAM Initialization Done. Register Initialization Done. Traffic Counter.
10~7
CheckSumEr SGRAMinit SRAMinit REGinit Traffic Counter Reserved Chip
0000: AL116
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Port Operation Status Registers (Register Registers status indication port basis. These read only register. Port port status register Port register 3B.and port register
Table Port Operation Status Registers (Register
NAME LinkFail Port Link Status. Normal Fail Port Status. Normal Error Port Security Violation. Normal Violation Flow Control. port mode ([1:0]) 2'b01 2'b11: Pause disable. Pause enable. port mode ([1:0]) 2'b00 2'b10: Back pressure based CRS. Back pressure based collision. Port Broadcast Storm Status. Normal Stormed Port Input Buffer Full Status. Normal Input buffer full experienced. Table Entry Unavailability Learning. Normal Unavailability experienced. Port Jabber Status. Normal Jabber experienced. Port Late Collision Status. Normal Late collision experienced. Port Transmit Pause Status. transmit pause experienced. Transmit pause experienced. Port Carrier Sense Loss During Transmission Status. carrier sense loss experienced. Carrier sense loss experienced. DESCRIPTION
PHYError
Sviolation
FlowCtrl
Stormed
InBFull
TblUNAVL
Jabbered
LateCOL
TxPaused
CRSLoss
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Table Port Operation Status Registers (Register (Continued)
FalseCRS False Carrier Status. Normal False carrier experienced. Transmit Queue Underflow Status. Normal Underflow experienced. Frame Time Out. Normal Frame time experienced. Port Operating Mode. 10Mb half-duplex. 10Mb full-duplex. 100Mb half-duplex. 100Mb full-duplex.
Underflow
TimeOut
PortMode
Indirect Resource Access Command Register (Register This register used managing resource switch.
Table Indirect Resource Access Command Register (Register
NAME CmdDone Command Done. Execute command. Command done. Read/Write Operation Command. Read operation. Write operation. Type Accessed Resource. 000: registers. 001: EEPROM 010: SGRAM 011: address table Read: table address read. Write: address learn. 100: address table Read: address search. Write: address delete. 101-111: Reserved External Address Table Read. ResType Operation On-chip address table read. Off-chip address table read. Address Entry within Accessed Resource. DESCRIPTION
Operation
13~11
ResType
ExtRD
ResAddr
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Table Indirect Resource Access Data Register (Register
15~0 NAME IRAData DESCRIPTION Indirect Resource Access Data
Table Indirect Resource Access Data Register (Register
15~0 NAME IRAData DESCRIPTION Indirect Resource Access Data
Table Indirect Resource Access Data Register (Register
15~0 NAME IRAData DESCRIPTION Indirect Resource Access Data
Table Indirect Resource Access Data Register (Register
15~0 NAME IRAData DESCRIPTION Indirect Resource Access Data
Table Check (Register
15~8 NAME CheckSum Reserved DESCRIPTION Check value AL116 register contents.
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Timing Requirements
Table Transmit Timing
SYMBOL ttdv ttxev DESCRIPTION TXCLK valid time. TXCLK TXEN valid time. UNIT
Table RMII Transmit Timing
SYMBOL ttdv ttxev DESCRIPTION TXCLK valid time. TXCLK TXEN valid time. UNIT
Note: Delays assuming 10pf loading output pins.
TXCLK
ttxev ttxev
TXEN
ttdv
DATA
DATA
DATA
DATA
DATA
DATA
Figure
RMII/MII Transmit Timing Diagram
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Table Receive Timing
SYMBOL trxds trxdh DESCRIPTION RX_DV, RXD, RX_ER, setup time. RX_DV, RXD, RX_ER hold time. UNIT
Table RMII Receive Timing
SYMBOL trxds trxdh DESCRIPTION RX_DV, RXD, RX_ER, setup time. RX_DV, RXD, RX_ER hold time. UNIT
RXCLK
trxdh
RXDV
trxds trxdh
DATA
DATA
DATA
DATA
DATA
DATA
Figure
RMII/MII Receive Timing Diagram
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Table Timing
SYMBOL troxs troxh DESCRIPTION Setup time. Hold time. UNIT
RICLK troxs troxh
Figure
Timing
Table Management (MDIO) Read Timing
SYMBOL DESCRIPTION high time time period MDIO setup time MDIO hold time UNIT
MDIO
Figure
Management Read Timing
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Table Management Write Timing
SYMBOL DESCRIPTION high time time period MDIO output delay UNIT
MDIO
Figure
Management Write Timing
Table SGRAM Refresh Timing
SYMBOL tCHI tCKH tCKS DESCRIPTION Access hold time Access setup time PBCS#, PBRAS#, PBWE# hold time Clock high level width System clock cycle time hold time setup time Clock level width PBCS#, PBRAS#, PBWE# setup time Precharge command period Auto-refresh auto-refresh period UNIT
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PBCLK tCKS tCKH
tCHI
Command
Precharge
Auto Refresh
Auto Refresh
Active
BANK
BANK
Address
Don't Care
Figure
SGRAM Refresh Timing
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Table SGRAM Read Timing
SYMBOL tCHI tCKH tCKS tRAS tRCD DESCRIPTION Access time Access hold time Access setup time PBCS#, PBRAS#, PBWE# hold time Clock high level width System clock cycle time hold time setup time Clock level width PBCS#, PBRAS#, PBWE# setup time Data high impedance time Data impedance time Data hold time Active precharge command period Active read delay UNIT
Note: This timing requirement SGRAM running Latency Typically speed grade SGRAM needs used.
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tCHI
PBCLK
tCKS
tCKH
BURST TERM.
Command
Active
READ
A0-A7
column
PBBA
BANK BANK
tRCD (Bank tRAS (Bank Latency
Dout
Dout
Dout
Dout
Dout
Dout
location within same
Figure
SGRAM Read Timing
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Table SGRAM Write Timing
SYMBOL tCHI tCKH tCKS tRAS tRCD DESCRIPTION Access hold time Access setup time PBCS#, PBRAS#, PBWE# hold time Clock high level width System clock cycle time hold time setup time Clock level width PBCS#, PBRAS#, PBWE# setup time Data hold time Data setup time Active precharge command period Active read delay 100,000 UNIT
Note: This timing requirement SGRAM running Latency Typically speed grade SGRAM needs used.
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tCHI
PBCLK
tCKS
tCKH
Command Active write BURST TERM.
A0-A7
column
BANK
PBBA
BANK
tRCD (Bank tRAS (Bank
location within same
Don't Care
Undefined
Figure
SGRAM Write Timing
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Electrical Specifications
Note: Operation absolute maximum ratings could cause permanent damage device.
Table Maximum Ratings
Supply Voltage (Vcc) Input Voltage Output Voltage Supply Voltage Input Voltage Output Voltage Storage Temperature -0.3V 3.6V -0.3 0.3V -0.3 0.3V -0.6V 6.0V -0.6 Vcc5 0.3V -0.6 Vcc5 0.3V +150
Table Recommended Operation Conditions
Supply Voltage Operating Temperature Power Dissipation 3.3V 0.3V (typical)
Table Electrical Characteristics
PARAMETER DESCRIPTION Output Voltage-High, Ioh=4mA Output Voltage-Low, Ioh=4mA High Impedance State Output Current Input Current-high (With Pull-up Pull-down) Input Current-low (With Pull-up Pull-down) Input High Voltage Input Voltage Supply Current 0.7*Vcc 0.3*Vcc UNIT
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AL116 Mechanical Data
Figure
AL116 Mechanical Dimensions
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Appendix (VLAN Mapping Work Sheet)
PORT 6/REG.
PORT
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PORT 7/REG.
PORT 0/REG.
PORT 1/REG.
PORT 2/REG.
PORT 3/REG.
PORT 4/REG.
PORT 5/REG.
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Appendix (Port Trunk Port Assignment Work Sheet)
PORT 0/REG.
PORT 1/REG.
PORT 2/REG.
PORT 3/REG.
PORT 4/REG.
PORT 5/REG.
PORT 6/REG.
TRUNK PORT
BIT/ VALUE
TRUNK BITS TRUNK BITS
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PORT 7/REG.
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Appendix (Suggested Memory Components)
Note: This only partial list memory components that used Allayer devices. AL116 uses Frame Buffer SGRAM chips that require 32-bit wide SGRAM SDRAM, that faster with Latency AL116 uses Table Memory SSRAM chips that require Sync Burst pipelined SSRAM, faster.
DEVICE AL116 FREQ. Mbit SGRAM MoSys MG802C256Q-10 Etron EM635327Q-8 Mbit SGRAM MoSys MG802C512L-8 Etron EM636227Q-8 Hitachi HM5216326FP-8 Winbond W971632AF-8 SSRAM Micron MT58LC64K32D8LG-11 71V632S6PF
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Revision History Rev. (7/13/99) Added memory information appendix III. Rev. 1.4a (7/28/99) Reformatted document. Added management timing diagrams. Added RMII timing diagrams. Rev. (9/22/99) Switched numbers AF20 AC21 output interface table. Changed number EEPROM interface table. Added names TRST, TMS, TDO, TDI, TCLK miscellaneous pins table. Added AC15, M22, power interface table. Prelim. (11/8/99) Updated table pins 15-11 (system config. reg. III). Updated transmit timing diagram. Corrected tables reflect transmit signals clocked rising edge TX_CLK. Prelim. Rev. (5/00) Fully released document.
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Index
Address Aging Address Learning AL116 EEPROM Mapping AL116 Mechanical Data AL116 Overview AL116 Diagram Appendix (VLAN Mapping Work Sheet) Appendix (Port Trunk Port Assignment Work Sheet) Appendix (Suggested Memory Components) Broadcast Storm Control Data Reception Electrical Characteristics EEPROM Address Format EEPROM Interface EEPROM External Address Table SRAM Interface False Carrier Events Flow Control Frame Filtering Frame Forwarding Frame Generation Frame Transmission Functional Description Half Duplex Flow Control (Backpressure) Half Duplex Mode Operation Illegal Frame Length Indirect Resource Access Command Register (Register Interface Block Diagram Load Balancing Long Frames Based Load Balancing Example Based Load Balancing Maximum Ratings MDIO Interface Media Independent Interface (MII) Receive Timing Transmit Timing Miscellaneous Pins Auto-negotiation Mode Other Options Management Management Master Mode Management MDIO Management Slave Mode Descriptions Diagram (Top View) Port Aggregation (Trunking) Port Based Load Balancing Example Port Based Trunk Loading Port Configuration Register Port Configuration Register Port Configuration Registers (Registers Port Monitoring Port Monitoring Configuration Register (Register Port Operation Status Registers (Register Port Trunk Port Assignment Registers (Registers Port VLAN Registers (Registers Power Interface Product Description Programming EEPROM with Parallel Port Queue Management Recommended Operation Conditions Reduced Media Independent Interface (RMII) Reserved Register (Register RMII Receive Timing RMII Transmit Timing RMII/MII Interface (Port RMII/MII Interface (Port RMII/MII Interface (Port RMII/MII Interface (Port RMII/MII Signal (Port RMII/MII Signal (Port RMII/MII Signal (Port RMII/MII Signal (Port RMON Source Destination Registers (Registers Timing Input Interface Interface Output Interface Secure Mode Operation SGRAM Interface SGRAM Read Timing SGRAM Refresh Timing SGRAM Write Timing Spanning Tree Support Start Stop Summary Programmable Control Transmit Receive Summary Programmable Options Address Learning
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System Configuration Register (Register System Configuration Register (Register System Configuration Register (Register System Initialization Testing Register (Register Timing Requirements Trunk Port Assignment Trunk Port Numbering Trunking Port Assignment Typical Write Operation Uplink Port Vendor Specific Register (Register VLAN Mapping Based Load Balancing Trunk VLAN Mapping Port Based Load Balancing Trunk VLAN Example
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