SMALL-OUTLINE SDRAM MODULE PC100- PC133-compliant, 144-pin, small
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64MB, 128MB, 256MB (x64, 144-PIN SDRAM SODIMM
SMALL-OUTLINE SDRAM MODULE
PC100- PC133-compliant, 144-pin, smalloutline, dual in-line memory module (SODIMM) Utilizes SDRAM components Unbuffered 64MB 64), 128MB 64), 256MB Single +3.3V power supply Fully synchronous; signals registered positive edge system clock Internal pipelined operation; column address changed every clock cycle Internal SDRAM banks hiding access/ precharge Programmable burst lengths: full page Auto Precharge Auto Refresh Modes Self Refresh Mode: Standard Power 64MB 128MB: 64ms, 4,096-cycle (15.625µs) refresh interval; 256MB: 64ms, 8,192-cycle (7.8125µs) refresh interval LVTTL-compatible inputs outputs Serial Presence-Detect (SPD) Gold edge contacts
MT8LSDT864(L)H(I) 64MB MT8LSDT1664(L)H(I) 128MB MT8LSDT3264(L)H(I) 256MB
latest data sheet, please refer Micron® site: www.micron.com/products/modules
Figure 144-Pin SODIMM (MO-190)
Standard 1.25in. (31.75mm)
Options
Self Refresh Current Standard Low-Power Operating Temperature Range Commercial (0°C +70°C) Industrial (-40°C +85°C) Package 144-pin SODIMM (standard) 144-pin SODIMM (lead-free) Memory Clock/CAS Latency 7.5ns (133 MHz)/CL 7.5ns (133 MHz)/CL 10ns (100 MHz)/CL
NOTE:
Marking
None None
-13E -133 -10E
Table
Timing Parameters
(READ) latency ACCESS TIME MODULE CLOCK MARKING FREQUENCY -13E -133 -10E 5.4ns 5.4ns SETUP HOLD TIME TIME 1.5ns 1.5ns 0.8ns 0.8ns
Contact Micron product availability. Power Industrial Temperature options available concurrently; Industrial Temperature option available -133 speed only.
Table
Address Table
64MB 128MB (BA0, BA1) 128Mb (A0-A11) (A0-A8) (S0#, S1#) 256MB (BA0, BA1) 256Mb (A0-A12) (A0-A8) (S0#, S1#) (BA0, BA1) 64Mb x16) (A0-A11) (A0-A7) (S0#, S1#)
Refresh Count Device Banks Device Configuration Addressing Column Addressing Module Ranks
09005aef8077d63a SD8C8_16_32x64HG.fm Rev. 6/04
©2004 Micron Technology, Inc. rights reserved.
PRODUCTS SPECIFICATIONS DISCUSSED HEREIN SUBJECT CHANGE MICRON WITHOUT NOTICE.
64MB, 128MB, 256MB (x64, 144-PIN SDRAM SODIMM
Table Part Numbers
MODULE DENSITY 64MB 64MB 64MB 64MB 64MB 64MB 128MB 128MB 128MB 128MB 128MB 128MB 256MB 256MB 256MB 256MB 256MB 256MB CONFIGURA-TION SYSTEM SPEED
PART NUMBER1 MT8LSDT864(L)HG-13E_ MT8LSDT864(L)HY-13E_ MT8LSDT864(L)H(I)G-133_ MT8LSDT864(L)H(I)Y-133_ MT8LSDT864(L)HG-10E_ MT8LSDT864(L)HY-10E_ MT8LSDT1664(L)HG-13E_ MT8LSDT1664(L)HY-13E_ MT8LSDT1664(L)H(I)G-133_ MT8LSDT1664(L)H(I)Y-133_ MT8LSDT1664(L)HG-10E_ MT8LSDT1664(L)HY-10E_ MT8LSDT3264(L)HG-13E_ MT8LSDT3264(L)HY-13E_ MT8LSDT3264(L)H(I)G-133_ MT8LSDT3264(L)H(I)Y-133_ MT8LSDT3264(L)HG-10E_ MT8LSDT3264(L)HY-10E_
NOTE:
designators component revision last characters each part number. Consult factory current revision codes. Example: MT8LSDT1664HG-133B1
09005aef8077d63a SD8C8_16_32x64HG.fm Rev. 6/04
Micron Technology, Inc., reserves right change products specifications without notice. ©2004 Micron Technology, Inc. rights reserved.
64MB, 128MB, 256MB (x64, 144-PIN SDRAM SODIMM
Table Assignment (144-Pin SODIMM Front)
DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 RAS# DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQMB2 DQMB3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
Table
Assignment (144-Pin SODIMM Back)
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 CKE0 CAS# CKE1 NC/A121 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQMB6 DQMB7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
SYMBOL SYMBOL SYMBOL SYMBOL
NOTE:
SYMBOL SYMBOL SYMBOL SYMBOL DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQMB4 DQMB5
DQMB0 DQMB1
Connect 64MB and128MB modules, 256MB module.
Figure Locations (144-Pin SODIMM)
Front View
Back View
(all pins)
(all even pins)
Indicates VDDQ
Indicates
09005aef8077d63a SD8C8_16_32x64HG.fm Rev. 6/04
Micron Technology, Inc., reserves right change products specifications without notice. ©2004 Micron Technology, Inc. rights reserved.
64MB, 128MB, 256MB (x64, 144-PIN SDRAM SODIMM
Table Descriptions
SYMBOL RAS#, CAS#, CK0, TYPE Input DESCRIPTION numbers correlate with symbols; more information refer Assignment tables page NUMBERS
Command Inputs: RAS#, CAS#, (along with define command being entered. Input Clock: driven system clock. SDRAM input signals sampled positive edge also increments internal burst counter controls output registers. CKE0, CKE1 Input Clock Enable: activates (HIGH) deactivates (LOW) signal. Deactivating clock provides PRECHARGE, POWERDOWN, SELF REFRESH operation (all device banks idle), ACTIVE POWER-DOWN (row ACTIVE device bank), CLOCK SUSPEND operation (burst access progress). synchronous except after device enters power-down self refresh modes, where becomes asynchronous until after exiting same mode. input buffers, including disabled during power-down self refresh modes, providing standby power. S0#, Input Chip Select: enables (registered LOW) disables (registered HIGH) command decoder. commands masked when registered HIGH. considered part command code. 115, 116, 117, DQMB0-DQMB7 Input Input/Output Mask: DQMB input mask signal write accesses output enable signal read accesses. Input data masked when DQMB sampled HIGH during WRITE cycle. output buffers placed High-Z state (two-clock latency) when DQMB sampled HIGH during READ cycle. 106, BA0, Input Bank Address: define which device bank ACTIVE, READ, WRITE, PRECHARGE command being applied. 31,32, A0-A11 Input Address Inputs: Provide address ACTIVE commands, (256MB), 103, 104, 105, (64MB, 128MB) column address auto precharge (A10) READ/ 109, 111, A0-A12 WRITE commands, select location memory array (256MB) respective device bank. sampled during PRECHARGE command determines whether PRECHARGE applies device bank (A10 LOW, device bank selected BA0, BA1) device banks (A10 HIGH). Address inputs also provide op-code during MODE REGISTER command. Input Serial Clock Presence-Detect: used synchronize presence-detect data transfer from module. Input/ Serial Presence-Detect Data: bidirectional used Output transfer addresses data into presence-detect portion module. 3-10, 13-20, 47-54, DQ0-DQ63 Input/ Data I/O: Data bus. 93-100, 121-128, Output 131-138 Supply Power Supply: +3.3V ±0.3V. 101, 102, 113, 114, 129, 130, 143, Supply Ground. 107, 108, 119, 120, 139, (64MB, 128MB), Connected: These pins should left unconnected. Use: These pins connected these modules, assigned pins other modules this product family.
09005aef8077d63a SD8C8_16_32x64HG.fm Rev. 6/04
Micron Technology, Inc., reserves right change products specifications without notice. ©2004 Micron Technology, Inc. rights reserved.
64MB, 128MB, 256MB (x64, 144-PIN SDRAM SODIMM
Figure Functional Block Diagram
DQMB0 DQMB4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQML DQMH DQMH DQML DQMB6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQMB2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQMH DQML DQML DQMH
DQMB5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQMB1 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQMH DQML RAS# CAS# CKE0 CKE1 A0-A11 (64MB/128MB) A0-A12 (256MB) BA0-1
NOTE:
resistor values unless otherwise specified. industry standard, Micron modules various component speed grades referenced module part numbering guide
DQMB7 DQML DQMH RAS#: SDRAMs CAS#: SDRAMs CKE: SDRAMs U2-U5 CKE: SDRAMs U6-U9 WE#: SDRAMs A0-A11: SDRAMs A0-A12: SDRAMs BA0-1: SDRAMs
Standard modules following SDRAM devices: MT48LC4M16A2TG(IT) (64MB); MT48LC8M16A2TG(IT) (128MB); MT48LC16M16A2TG(IT) (256MB) Lead-free modules following SDRAM devices: MT48LC4M16A2P(IT) (64MB); MT48LC8M16A2P(IT) (128MB); MT48LC16M16A2P(IT) (256MB)
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQMB3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
DQMH DQML
DQML DQMH
SERIAL
U2-U5 U6-U9 SDRAMs, SDRAMs,
09005aef8077d63a SD8C8_16_32x64HG.fm Rev. 6/04
Micron Technology, Inc., reserves right change products specifications without notice. ©2004 Micron Technology, Inc. rights reserved.
64MB, 128MB, 256MB (x64, 144-PIN SDRAM SODIMM
General Description
Micron MT8LSDT864(L)H(I), MT8LSDT1664(L)H(I), MT8LSDT3264(L)H(I) high-speed CMOS, dynamic random-access, memory modules organized configuration. These modules SDRAM devices which internally configured quad-bank DRAMs with synchronous interface (all signals registered positive edge clock signals CK). Read write accesses SDRAM modules burst oriented; accesses start selected location continue programmed number locations programmed sequence. Accesses begin with registration ACTIVE command, which then followed READ WRITE command. address bits registered coincident with ACTIVE command used select device bank accessed (BA0, select device bank; device rows selected A0-A11 64MB 128MB; A0-A12 256MB). address bits registered coincident with READ WRITE command (A0-A7 64MB; A0-A8 128MB 256MB) used select starting device column location burst access. SDRAM modules provide programmable READ WRITE burst lengths locations, full page, with burst terminate option. auto precharge function enabled provide selftimed precharge that initiated burst sequence. These modules internal pipelined architecture achieve high-speed operation. This architecture compatible with rule prefetch architectures, also allows column address changed every clock cycle achieve high-speed, fully random access. Precharging device bank while accessing other three device banks will hide precharge cycles provide seamless, high-speed, random access operation. SDRAM modules designed operate 3.3V, low-power memory systems. auto refresh mode provided, along with power-saving, power-down mode. inputs, outputs, clocks LVTTL-compatible. SDRAM modules offer substantial advances DRAM operating performance, including ability synchronously burst data high data rate with automatic column-address generation, ability interleave between internal banks order hide precharge time, capability randomly change column addresses each clock cycle during burst access. more information regarding SDRAM operation, refer 64Mb, 128Mb, 256Mb SDRAM component data sheets.
Serial Presence-Detect Operation
SDRAM modules incorporate serial presence-detect (SPD). function implemented using 2,048-bit EEPROM. This nonvolatile storage device contains bytes. first bytes programmed Micron identify module type various SDRAM organizations timing parameters. remaining bytes storage available customer. System READ/WRITE operations between master (system logic) slave EEPROM device (DIMM) occur standard using DIMM's (clock) (data) signals. Write protect (WP) tied ground module, permanently disabling hardware write protect.
Initialization
SDRAM devices must powered initialized predefined manner. Operational procedures other than those specified result undefined operation. Once power applied VDDQ (simultaneously) clock stable (stable clock defined signal cycling within timing constraints specified clock pin), SDRAM requires 100µs delay prior issuing command other than COMMAND INHIBIT Starting some point during this 100µs period continuing least through this period, COMMAND INHIBIT commands should applied. Once 100µs delay been satisfied with least COMMAND INHIBIT command having been applied, PRECHARGE command should applied. device banks must then precharged, thereby placing device banks idle state. Once idle state, AUTO REFRESH cycles must performed. After AUTO REFRESH cycles complete, SDRAM ready mode register programming. Because mode register will power unknown state, should loaded prior applying operational command.
Mode Register Definition
mode register used define specific mode operation SDRAM. This definition includes selection burst length, burst type, latency, operating mode write burst mode, shown Figure Mode Register Definition Diagram, page mode register programmed LOAD MODE REGISTER command will retain stored information until programmed again device loses power.
09005aef8077d63a SD8C8_16_32x64HG.fm Rev. 6/04
Micron Technology, Inc., reserves right change products specifications without notice. ©2004 Micron Technology, Inc. rights reserved.
64MB, 128MB, 256MB (x64, 144-PIN SDRAM SODIMM
Mode register bits M0-M2 specify burst length, specifies type burst (sequential interleaved), M4-M6 specify latency, specify operating mode, specifies write burst mode, reserved future use. 64MB 128MB, Address (M12) undefined should driven during loading mode register. mode register must loaded when device banks idle, controller must wait specified time before initiating subsequent operation. Violating either these requirements will result unspecified operation. ordering accesses within burst determined burst length, burst type starting column address, shown Table Burst Definition Table, page
Figure Mode Register Definition Diagram
64MB Module 128MB Module
Address
Mode Register (Mx)
Reserved* Mode
Latency
Burst Length
Burst Length
Read write accesses SDRAM burst oriented, with burst length being programmable, shown Figure Mode Register Definition Diagram. burst length determines maximum number column locations that accessed given READ WRITE command. Burst lengths locations available both sequential interleaved burst types, full-page burst available sequential type. full-page burst used conjunction with BURST TERMINATE command generate arbitrary burst lengths. Reserved states should used, unknown operation incompatibility with future versions result. When READ WRITE command issued, block columns equal burst length effectively selected. accesses that burst take place within this block, meaning that burst will wrap within block boundary reached, shown Table Burst Definition Table, page block uniquely selected A1-Ai when burst length two; A2-Ai when burst length four; A3-Ai when burst length eight. Note Table Burst Definition Table, page values. remaining (least significant) address bit(s) (are) used select starting location within block. Full-page bursts wrap within page boundary reached, shown Table Burst Definition Table, page
*Should program ensure compatibility with future devices.
256MB Module
Address
Mode Register (Mx)
Reserved*
Mode
Latency
Burst Length
*Should program M12, M11, ensure compatibility with future devices.
Burst Length Reserved Reserved Reserved Full Page Reserved Reserved Reserved Reserved
Burst Type Sequential Interleaved
Latency Reserved Reserved Reserved Reserved Reserved Reserved
M6-M0 Defined
Operating Mode Standard Operation other states reserved
Burst Type
Accesses within given burst programmed either sequential interleaved; this referred burst type selected
Write Burst Mode Programmed Burst Length Single Location Access
09005aef8077d63a SD8C8_16_32x64HG.fm Rev. 6/04
Micron Technology, Inc., reserves right change products specifications without notice. ©2004 Micron Technology, Inc. rights reserved.
64MB, 128MB, 256MB (x64, 144-PIN SDRAM SODIMM
Table
BURST LENGTH
Burst Definition Table
STARTING COLUMN ORDER ACCESSES WITHIN ADDRESS BURST TYPE SEQUENTIAL TYPE INTERLEAVED 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 supported
Figure Latency Diagram
COMMAND
READ
DOUT
Full Page
(location 0-y)
0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6
Latency
COMMAND
READ
DOUT
Latency
DON'T CARE UNDEFINED
Latency
latency delay, clock cycles, between registration READ command availability first piece output data. latency three clocks. READ command registered clock edge latency clocks, data will available clock edge will start driving result clock edge cycle earlier and, provided that relevant access times met, data will valid clock edge example, assuming that clock cycle time such that relevant access times met, READ command registered latency programmed clocks, will start driving after data will valid shown Figure Latency Diagram. Table Latency Table, page indicates operating frequencies which each latency setting used. Reserved states should used, because unknown operation incompatibility with future versions result.
NOTE:
full-page accesses: (64MB), (128MB 256MB) burst length two, A1-Ai select block-oftwo burst; selects starting column within block. burst length four, A2-Ai select block-offour burst; A0-A1 select starting column within block. burst length eight, A3-Ai select block-ofeight burst; A0-A2 select starting column within block. full-page burst, full selected A0-Ai select starting column. Whenever boundary block reached within given sequence above, following access wraps within block. burst length one, A0-Ai select unique column accessed, mode register ignored. 64MB modules 128MB 256MB modules
Operating Mode
normal operating mode selected setting zero; other combinations values reserved future and/or test modes. programmed burst length applies both READ WRITE bursts.
Micron Technology, Inc., reserves right change products specifications without notice. ©2004 Micron Technology, Inc. rights reserved.
09005aef8077d63a SD8C8_16_32x64HG.fm Rev. 6/04
64MB, 128MB, 256MB (x64, 144-PIN SDRAM SODIMM
Test modes reserved states should used, because unknown operation incompatibility with future versions result.
Table
Latency Table
ALLOWABLE OPERATING CLOCK FREQUENCY (MHz)
Write Burst Mode
When burst length programmed M0M2 applies both READ WRITE bursts; when programmed burst length applies READ bursts, write accesses single-location (nonburst) accesses.
SPEED -13E -133 -10E
LATENCY
LATENCY
09005aef8077d63a SD8C8_16_32x64HG.fm Rev. 6/04
Micron Technology, Inc., reserves right change products specifications without notice. ©2004 Micron Technology, Inc. rights reserved.
64MB, 128MB, 256MB (x64, 144-PIN SDRAM SODIMM
Commands
Truth Table provides quick reference available commands. This followed written description each command. more detailed description commands operations, refer 64Mb, 128Mb, 256Mb SDRAM component data sheet.
Table
Truth Table SDRAM Commands DQMB Operation
RAS# CAS# DQMB L/H8 L/H8 ADDR Bank/Row Bank/Col Bank/Col Code Op-code Valid Active Active High-Z NOTES
HIGH commands shown except SELF REFRESH NAME (FUNCTION) COMMAND INHIBIT (NOP) OPERATION (NOP) ACTIVE (Select bank activate row) READ (Select bank column, start READ burst) WRITE (Select bank column, start WRITE burst) BURST TERMINATE PRECHARGE (Deactivate bank banks) AUTO REFRESH SELF REFRESH (Enter self refresh mode) LOAD MODE REGISTER Write Enable/Output Enable Write Inhibit/Output High-Z
NOTE:
A0-A11 (64MB 128MB) A0-A12 (256MB) provide device address, BA0, determine which device bank made active. A0-A7 (64MB) A0-A8 (128MB 256MB) provide device column address; HIGH enables auto precharge feature (nonpersistent), while disables auto precharge feature; BA0, determine which device bank being read from written LOW: BA0, determine which device bank being precharged. HIGH: device banks precharged BA0, "Don't Care." This command AUTO REFRESH HIGH, SELF REFRESH LOW. Internal refresh counter controls addressing; inputs I/Os "Don't Care" except CKE. A0-A11 define op-code written mode register; 64MB 128MB, should driven low. Activates deactivates during WRITEs (zero-clock delay) READs (two-clock delay).
09005aef8077d63a SD8C8_16_32x64HG.fm Rev. 6/04
Micron Technology, Inc., reserves right change products specifications without notice. ©2004 Micron Technology, Inc. rights reserved.
64MB, 128MB, 256MB (x64, 144-PIN SDRAM SODIMM
Absolute Maximum Ratings
Stresses greater than those listed cause permanent damage device. This stress rating only, functional operation device these other conditions above those indicated operaVoltage Supply Relative +4.6V Voltage Inputs, Pins Relative +4.6V tional sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
Operating Temperature TOPR (Commercial ambient) +65°C TOPR (Industrial ambient) -40°C +85°C Storage Temperature (plastic) -55°C +150°C
Table Electrical Characteristics Operating Conditions
Notes: notes appear page VDD, VDDQ +3.3V ±0.3V PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic inputs INPUT VOLTAGE: Logic inputs INPUT LEAKAGE CURRENT: input (All other pins under test OUTPUT LEAKAGE CURRENT: pins disabled; VOUT VDDQ OUTPUT LEVELS: Output High Voltage (IOUT -4mA) Output Voltage (IOUT 4mA) SYMBOL VDD, VDDQ Command Address Inputs DQMB -0.3 UNITS NOTES
Table Specifications Conditions 64MB
Notes: notes appear page VDD, VDDQ +3.3V ±0.3V; DRAM components only PARAMETER/CONDITION OPERATING CURRENT: Active Mode; Burst READ (MIN) STANDBY CURRENT: Power-Down Mode; device device banks idle; STANDBY CURRENT: Active Mode; HIGH; HIGH; device banks active after tRCD met; accesses progress OPERATING CURRENT: Burst Mode; Continuous burst; READ WRITE; device banks active tRFC tRFC (MIN) AUTO REFRESH CURRENT HIGH; HIGH SELF REFRESH CURRENT: 0.2V (Low power available with industrial temperature option)
NOTE:
tRFC
SYMBOL WRITE; IDD1a IDD2b IDD3a IDD4a IDD5b IDD6b IDD7b IDD7b
-13E 1,840
-133
-10E
UNITS
NOTES 29,30
1,680 1,520
15.625µs Standard
Power
Value calculated module rank this operating condition, other module ranks power-down mode. Value calculated reflects module ranks this operating condition.
09005aef8077d63a SD8C8_16_32x64HG.fm Rev. 6/04
Micron Technology, Inc., reserves right change products specifications without notice. ©2004 Micron Technology, Inc. rights reserved.
64MB, 128MB, 256MB (x64, 144-PIN SDRAM SODIMM
Table Specifications Conditions 128MB
Notes: notes appear page VDD, VDDQ +3.3V ±0.3V; DRAM components only PARAMETER/CONDITION OPERATING CURRENT: Active Mode; Burst READ WRITE; (MIN) STANDBY CURRENT: Power-Down Mode; device device banks idle; STANDBY CURRENT: Active Mode; HIGH; HIGH; device banks active after tRCD met; accesses progress OPERATING CURRENT: Burst Mode; Continuous burst; READ WRITE; device banks active tRFC tRFC (MIN) AUTO REFRESH CURRENT HIGH; HIGH SELF REFRESH CURRENT: 0.2V (Low power available with industrial temperature option)
NOTE:
SYMBOL IDD1
-13E 2,640
-133
-10E
UNITS
NOTES
IDD2b IDD3a IDD4a IDD5b IDD6b IDD7b IDD7b
2,480 2,160
15.625µs Standard Power
Value calculated module bank this operating condition, other module banks power-down mode. Value calculated reflects module banks this operating condition.
Table Specifications Conditions 256MB
Notes: notes appear page VDD, VDDQ +3.3V ±0.3V; DRAM components only PARAMETER/CONDITION OPERATING CURRENT: Active Mode; Burst READ WRITE; (MIN) STANDBY CURRENT: Power-Down Mode; device device banks idle; STANDBY CURRENT: Active Mode; HIGH; HIGH; device banks active after tRCD met; accesses progress OPERATING CURRENT: Burst Mode; Continuous burst; READ WRITE; device banks active tRFC tRFC (MIN) AUTO REFRESH CURRENT HIGH; HIGH SELF REFRESH CURRENT: 0.2V (Low power available with industrial temperature option)
NOTE:
tRFC
SYMBOL IDD1a IDD2b IDD3a
-13E
-133
-10E
UNITS
NOTES
IDD4a IDD5b IDD6b IDD7b IDD7b
2,280
2,160 2,160
7.8125µs Standard
Power
Value calculated module bank this operating condition, other module banks power-down mode. Value calculated reflects module banks this operating condition.
09005aef8077d63a SD8C8_16_32x64HG.fm Rev. 6/04
Micron Technology, Inc., reserves right change products specifications without notice. ©2004 Micron Technology, Inc. rights reserved.
64MB, 128MB, 256MB (x64, 144-PIN SDRAM SODIMM
Table Capacitance
Notes notes appear page PARAMETER Input Capacitance: Address Command Input Capacitance: CKE, Input Capacitance: DQMB Inuput/Output Capacitnance: SYMBOL UNITS
Table Electrical Characteristics Recommended Operating Conditions
Notes: notes appear page Module timing parameters comply with PC100 PC133 Design Specs, based component parameters CHARACTERISTICS PARAMETER Access time from (positive edge) Address hold time Address setup time high-level width low-level width Clock cycle time SYMBOL
-13E
-133
-10E UNITS NOTES
AC(3)
tAC(2)
tCK(3) tCK(2) tCKH tCKS tCMH tCMS tHZ(3) tHZ(2) tOHN tRAS
hold time setup time CS#, RAS#, CAS#, WE#, hold time CS#, RAS#, CAS#, WE#, setup time Data-in hold time Data-in setup time Data-out high-impedance time Data-out low-impedance time Data-out hold time (load) Data-out hold time load) ACTIVE PRECHARGE command ACTIVE ACTIVE command period ACTIVE READ WRITE delay Refresh period AUTO REFRESH period PRECHARGE command period ACTIVE bank ACTIVE bank command Transition time WRITE recovery time
120,000
120,000
120,000
tRCD tREF tRFC
7.5ns
Exit SELF REFRESH ACTIVE command
tXSR
09005aef8077d63a SD8C8_16_32x64HG.fm Rev. 6/04
Micron Technology, Inc., reserves right change products specifications without notice. ©2004 Micron Technology, Inc. rights reserved.
64MB, 128MB, 256MB (x64, 144-PIN SDRAM SODIMM
Table Functional Characteristics
Notes: notes appear page PARAMETER READ/WRITE command READ/WRITE command clock disable power-down entry mode clock enable power-down exit setup mode input data delay data mask during WRITEs data high-impedance during READs WRITE command input data delay Data-in ACTIVE command Data-in PRECHARGE command Last data-in burst STOP command Last data-in READ/WRITE command Last data-in PRECHARGE command LOAD MODE REGISTER command ACTIVE REFRESH command Data-out high-impedance from PRECHARGE command SYMBOL
-13E
-133
-10E
UNITS
NOTES
tCKED
tDWD tDAL tDPL tBDL tCDL tRDL tMRD tROH(3) tROH(2)
09005aef8077d63a SD8C8_16_32x64HG.fm Rev. 6/04
Micron Technology, Inc., reserves right change products specifications without notice. ©2004 Micron Technology, Inc. rights reserved.
64MB, 128MB, 256MB (x64, 144-PIN SDRAM SODIMM
Notes
voltages referenced VSS. This parameter sampled. VDD, VDDQ +3.3V; MHz; 25°C; under test biased 1.4V. dependent output loading cycle rates. Specified values obtained with minimum cycle time outputs open. Enables on-chip refresh address counters. minimum specifications used only indicate cycle time which proper operation over full temperature range ensured (Commercial temperature: +70°C Industrial Temperature: -40°C +85°C). initial pause 100µs required after powerup, followed AUTO REFRESH commands, before proper device operation ensured. (VDD VDDQ must powered simultaneously. VSSQ must same potential.) AUTO REFRESH command wake-ups should repeated time tREF refresh requirement exceeded. characteristics assume 1ns. addition meeting transition rate specification, clock must transit between between VIH) monotonic manner. Outputs measured 1.5V with equivalent load: Timing actually specified plus tRP; clock(s) specified reference only minimum cycle rate. Timing actually specified tWR. Required clocks specified JEDEC functionality dependent timing parameter. current will increase decrease proportionally according amount frequency alteration test condition. Address transitions average transition every clocks. must toggled minimum times during this period. Based 10ns -10E, 7.5ns -133 -13E. overshoot: (MAX) VDDQ pulse width 3ns, pulse width cannot greater than third cycle rate. undershoot: (MIN) pulse width 3ns. clock frequency must remain constant (stable clock defined signal cycling within timing constraints specified clock pin) during access precharge states (READ, WRITE, including tWR, PRECHARGE commands). used reduce data rate. Auto precharge mode only. precharge timing budget (tRP) begins -13E; 7.5ns -133 -10E after first clock delay, after last WRITE executed. exceed limit precharge mode. Precharge mode only. JEDEC PC100 specify three clocks. -133/-13E with load 4.6ns guaranteed design. Parameter guaranteed design. -13E, 7.5ns; -133, 7.5ns; -10E, 10ns. HIGH during refresh command period tRFC (MIN) else LOW. IDD6 limit actually nominal value does result fail value. Refer component datasheet timing wavfeforms. value tRAS used -13E speed grade module SPDs calculated from 45ns. Leakage number reflects worst case leakage possible through module pin, what each memory device contributes.
50pF
defines time which output achieves open circuit condition; reference VOL. last valid data element will meet before going High-Z. timing tests have with timing referenced 1.5V crossover point. input transition time longer than 1ns, then timing referenced (MAX) (MIN) longer 1.5V crossover point. Other input signals allowed transition more than once every clocks otherwise valid levels. specifications tested after device properly initialized. Timing actually specified tCKS; clock(s) specified reference only minimum cycle rate.
09005aef8077d63a SD8C8_16_32x64HG.fm Rev. 6/04
Micron Technology, Inc., reserves right change products specifications without notice. ©2004 Micron Technology, Inc. rights reserved.
64MB, 128MB, 256MB (x64, 144-PIN SDRAM SODIMM
Clock Data Conventions
Data states line change only during LOW. state changes during HIGH reserved indicating start stop conditions (Figure Data Validity, Figure Definition Start Stop).
Acknowledge
Acknowledge software convention used indicate successful data transfers. transmitting device, either master slave, will release after transmitting eight bits. During ninth clock cycle, receiver will pull line acknowledge that received eight bits data (Figure Acknowledge Response From Receiver). device will always respond with acknowledge after recognition start condition slave address. both device WRITE operation have been selected, device will respond with acknowledge after receipt each subsequent eight-bit word. read mode device will transmit eight bits data, release line monitor line acknowledge. acknowledge detected stop condition generated master, slave will continue transmit data. acknowledge detected, slave will terminate further data transmissions await stop condition return standby power mode.
Start Condition
commands preceded start condition, which HIGH-to-LOW transition when HIGH. device continuously monitors lines start condition will respond command until this condition been met.
Stop Condition
communications terminated stop condition, which LOW-to-HIGH transition when HIGH. stop condition also used place device into standby power mode.
Figure Data Validity
Figure Definition Start Stop
DATA STABLE DATA CHANGE DATA STABLE
START
STOP
Figure Acknowledge Response From Receiver
from Master
Data Output from Transmitter
Data Output from Receiver Acknowledge
09005aef8077d63a SD8C8_16_32x64HG.fm Rev. 6/04
Micron Technology, Inc., reserves right change products specifications without notice. ©2004 Micron Technology, Inc. rights reserved.
64MB, 128MB, 256MB (x64, 144-PIN SDRAM SODIMM
Table EEPROM Device Select code
most significant (b7) sent first DEVICE TYPE IDENTIFIER Memory Area Select Code (two arrays) Protection Register Select Code CHIP ENABLE
Table EEPROM Operating modes
MODE Current Address Read Random Address Read Sequential Read Byte Write Page Write BYTES INITIAL SEQUENCE START, Device Select, START, Device Select, Address reSTART, Device Select, Similar Current Random Address Read START, Device Select, START, Device Select,
Figure EEPROM Timing Diagram
HIGH
SU:STA HD:STA HD:DAT SU:DAT SU:STO
UNDEFINED
09005aef8077d63a SD8C8_16_32x64HG.fm Rev. 6/04
Micron Technology, Inc., reserves right change products specifications without notice. ©2004 Micron Technology, Inc. rights reserved.
64MB, 128MB, 256MB (x64, 144-PIN SDRAM SODIMM
Table Serial Presence-Detect EEPROM Operating Conditions
voltages referenced VSS; VDDSPD +2.3V +3.6V PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic inputs INPUT VOLTAGE: Logic inputs OUTPUT VOLTAGE: IOUT INPUT LEAKAGE CURRENT: OUTPUT LEAKAGE CURRENT: VOUT STANDBY CURRENT: 0.3V; other inputs 3.3V ±10% POWER SUPPLY CURRENT: clock frequency SYMBOL UNITS
Table Serial Presence-Detect EEPROM Operating Conditions
voltages referenced VSS; VDDSPD +2.3V +3.6V PARAMETER/CONDITION data-out valid Time must free before transition start Data-out hold time fall time Data-in hold time Start condition hold time Clock HIGH period Noise suppression time constant SCL, inputs Clock period rise time clock frequency Data-in setup time Start condition setup time Stop condition setup time WRITE cycle time
NOTE:
SYMBOL
tBUF tHD:DAT tHD:STA tHIGH tLOW fSCL tSU:DAT tSU:STA tSU:STO tWRC
UNITS
NOTES
avoid spurious START STOP conditions, minimum delay placed between falling rising edge SDA. This parameter sampled. reSTART condition, following WRITE cycle. EEPROM WRITE cycle time (tWRC) time from valid stop condition write sequence EEPROM internal erase/program cycle. During WRITE cycle, EEPROM interface circuit disabled, remains HIGH pull-up resistor, EEPROM does respond slave address.
09005aef8077d63a SD8C8_16_32x64HG.fm Rev. 6/04
Micron Technology, Inc., reserves right change products specifications without notice. ©2004 Micron Technology, Inc. rights reserved.
64MB, 128MB, 256MB (x64, 144-PIN SDRAM SODIMM
Table Serial Presence-Detect Matrix
"1"/"0": Serial Data, "driven HIGH"/"driven LOW"; notes appear Serial Presence-Detect Matrix BYTE DESCRIPTION Number Bytes Used Micron Total Number Memory Bytes Memory Type Number Addresses Number Column Addresses Number Module Ranks Module Data Width Module Data Width (Continued) Module Voltage Interface Levels SDRAM Cycle Time, (CAS Latency ENTRY (VERSION) SDRAM LVTTL (-13E) 7.5ns (-133) (-10E) 5.4ns (-13E/-133) (-10E) None 15.6µs 7.81µs/SELF PAGE Unbuffered 7.5ns (13E) 10ns (-133/-10E) 54ns (-13E) (-133/-10E) 15ns (-13E) 20ns (-133/-10E) 14ns (-13E) 15ns (-133) 20ns (-10E) 15ns (-13E)20ns (-133/-10E) 45ns (-13E) 44ns (133) 50ns (-10E) MT8LSDT864H MT8LSDT1664 MT8LSDT3264H
SDRAM Access from CLK, (CAS Latency Module Configuration Type Refresh Rate/Type SDRAM Width (Primary SDRAM) Error-checking SDRAM Data Width Minimum Clock Delay from Back-to-Back Random Column Addresses,tCCD Burst Lengths Supported Number Banks SDRAM Device Latencies Supported Latency Latency SDRAM Module Attributes SDRAM Device Attributes: General SDRAM Cycle Time, (CAS Latency (-133/-10E) SDRAM Access from CLK, (CAS Latency SDRAM Cycle Time, (CAS Latency SDRAM Access from CLK, (CAS Latency Minimum Precharge Time, Minimum Active Active, tRRD
Minimum RAS# CAS# Delay, tRCD Minimum RAS# Pulse Width, tRAS (See note
09005aef8077d63a SD8C8_16_32x64HG.fm Rev. 6/04
Micron Technology, Inc., reserves right change products specifications without notice. ©2004 Micron Technology, Inc. rights reserved.
64MB, 128MB, 256MB (x64, 144-PIN SDRAM SODIMM
Table Serial Presence-Detect Matrix
"1"/"0": Serial Data, "driven HIGH"/"driven LOW"; notes appear Serial Presence-Detect Matrix BYTE DESCRIPTION Module Rank Density Command Address Setup Time, tAS, tCMS Command Address Hold Time, tAH, tCMH Data Signal Input Setup Time, Data Signal Input Hold Time, ENTRY (VERSION) 32MB, 64MB, 128MB 1.5ns (-13E/-133) (-10E) 0.8ns (-13E/-133) (-10E) 1.5ns (-13E/-133) (-10E) 0.8ns (-13E/-133) (-10E) MT8LSDT864H 01-0C Variable Data 01-09 Variable Data Variable Data Variable Data MT8LSDT1664 MT8LSDT3264H 01-0C Variable Data 01-09 Variable Data Variable Data Variable Data 01-0C Variable Data 01-09 Variable Data Variable Data Variable Data
Reserved Device Minimum Active/Auto-Refresh Time,
66ns (-13E) 71ns (-133) 66ns (-10E)
Reserved Revision Checksum Bytes 0-62
65-71 73-90 95-98 99-125
Manufacturer's JEDEC Code Manufacturer's JEDEC Code (Cont.) Manufacturing Location Module Part Number (ASCII) Identification Code Identification Code (Cont.) Year Manufacture Week Manufacture Module Serial Number Manufacturer-specific Data (RSVD) System Frequency
REV. (-13E) (-133) (-10E) MICRON
(-13E/-133/-10E)
SDRAM Component Clock Detail
NOTE:
value tRAS used -13E modules calculated from tRP. Actual device spec. value 37ns.
09005aef8077d63a SD8C8_16_32x64HG.fm Rev. 6/04
Micron Technology, Inc., reserves right change products specifications without notice. ©2004 Micron Technology, Inc. rights reserved.
64MB, 128MB, 256MB (x64, 144-PIN SDRAM SODIMM
Figure 144-Pin SODIMM
FRONT VIEW
2.666 (67.72) 2.656 (67.45) 0.150 (3.80)
0.079 (2.00) (2X)
0.071 (1.80) (2X)
1.255 (31.88) 1.245 (31.62) 0.787 (20.00)
0.236 (6.00) 0.100 (2.55) 0.157 (4.00)
0.079 (2.00) 0.13 (3.30)
0.059 (1.50) 0.024 (0.60) 2.386 (60.60) 2.504 (63.60)
0.0315 (0.80)
BACK VIEW
NOTE:
dimensions inches (millimeters);
typical where noted.
Data Sheet Designation
Released Mark): This data sheet contains minimum maximum limits specified over complete power supply temperature range production devices. Although considered final, these specifications subject change, further product development data characterization sometimes occur.
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09005aef8077d63a SD8C8_16_32x64HG.fm Rev. 6/04 Micron Technology, Inc., reserves right change products specifications without notice. ©2004 Micron Technology, Inc. rights reserved.
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