SPACE LEVEL MIL-STD-1553 BC/RT/MT ADVANCED COMMUNICATION ENGINE (SP'AC

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SPACE LEVEL MIL-STD-1553 BC/RT/MT ADVANCED COMMUNICATION ENGINE (SP'AC

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BU-61582
SPACE LEVEL MIL-STD-1553 BC/RT/MT ADVANCED COMMUNICATION ENGINE (SP'ACE) TERMINAL
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Radiation-Hardened MRad Fully Integrated 1553 Terminal Flexible Processor Interface Internal Automatic Retries Programmable Times Frame Auto-Repeat Intelligent Data Buffering Small Ceramic Package Available 5962-96887 Multiple Ordering Options; (Only) +5V/-15V +5V/-12V +5V/Transceiverless (Only, with Transmit Inhibits)
DESCRIPTION
DDC's BU-61582 Space Advanced Communication Engine (SP'ACE) radiation hardened version BU-61580 terminal. supplies BU-61582 with enhanced screening space other high reliability applications. BU-61582 provides complete integrated BC/RT/MT interface between host processor MIL-STD-1553 bus. BU-61582 maintains functional software compatibility with standard BU61580 product packaged same square-inch package footprint. option, supply BU-61582 with space level screening. This entails enhancements areas element evaluation screening procedures active passive elements, well manufacturing screening processes used producing terminals. BU-61582 integrates dual transceiver, protocol, memory management processor interface logic, words choice 70-pin flat pack packages. Transceiverless versions used with external electrical fiber optic transceiver. minimize board space `glue' logic, SP'ACE terminals provide ultimate flexibility interfacing host processor internal/external RAM.
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Data Device Corporation Wilbur Place Bohemia, York 11716 631-567-5600 Fax: 631-567-7358 www.ddc-web.com
Technical Support: 1-800-DDC-5757 ext. 7771
trademarks property their respective owners. 1998, 1999 Data Device Corporation
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SHARED TRANSCEIVER DATA DUAL ENCODER/DECODER, MULTIPROTOCOL MEMORY MANAGEMENT ADDRESS ADDRESS BUFFERS DATA BUFFERS D15-D0 PROCESSOR DATA A15-A0 PROCESSOR ADDRESS TRANSCEIVER TRANSPARENT/BUFFERED, STRBD, SELECT, RD/WR, MEM/REG, TRIGGER_SEL/MEMENA-IN, MSB/LSB/DTGRT IOEN, MEMENA-OUT, READYD ADDR_LAT/MEMOE, ZERO_WAIT/MEMWR, 8/16-BIT/DTREQ, POLARITY_SEL/DTACK PROCESSOR MEMORY CONTROL PROCESSOR MEMORY INTERFACE LOGIC INTERRUPT REQUEST
ADDRESS
RTAD4-RTAD0, RTADP
INCMD
MISCELLANEOUS
CLK_IN, TAG_CLK, MSTCLR,SSFLAG/EXT_TRG
BU-61582 M-08/04-0
FIGURE BU-61582 BLOCK DIAGRAM
TABLE SP'ACE SERIES SPECIFICATIONS
PARAMETER ABSOLUTE MAXIMUM RATING Supply Voltage Logic Transceiver -15V -12V Logic Voltage Input Range RECEIVER Differential Input Resistance (Notes 1-6) Differential Input Capacitance (Notes 1-6) Threshold Voltage, Transformer Coupled, Measured Stub Common Mode Voltage (Note TRANSMITTER Differential Output Voltage Direct Coupled Across Measured Transformer Coupled Across Measured Output Noise, Differential (Direct Coupled) Output Offset Voltage, Transformer Coupled Across ohms Rise/Fall Time LOGIC (VCC=5.5V, VIN=5.5V) (VCC=5.5V, VIN=0V) DB15-DB0, A15-A0 RTAD4-RTAD0, RTADP, MEMWR/ZEROWAIT, DTREQ/16/8, DTACK/POLARITY_SEL Other Inputs (VCC=4.5V, VIH=4.2V, VIL=1.0V, IOH=max) (VCC=4.5V, VIH=2.7V, VIL=0.2V, IOL=max) POWER SUPPLY REQUIREMENTS Voltages/Tolerances BU-61582X0 (Logic) BU-61582X1 (Logic) BU-61582X2 (Logic) BU-61582X3/X6 (+5V Only) (Logic) UNITS
TABLE SP'ACE SERIES SPECIFICATIONS (CONT)
PARAMETER POWER SUPPLY REQUIREMENTS (Cont'd) Current Drain (Total Hybrid) BU-61582X0 (Logic) BU-61582X1 (Note -15V Idle Transmitter Duty Cycle Transmitter Duty Cycle 100% Transmitter Duty Cycle BU-61582X2 (Note -12V Idle Transmitter Duty Cycle Transmitter Duty Cycle 100% Transmitter Duty Cycle BU-61582X3/X6 (+5V) (Logic, Idle Transmitter Duty Cycle Transmitter Duty Cycle 100% Transmitter Duty Cycle POWER DISSIPATION Total Hybrid BU-61582X0 BU-61582X1 Idle Transmitter Duty Cycle Transmitter Duty Cycle 100% Transmitter Duty Cycle BU-61582X2 Idle Transmitter Duty Cycle Transmitter Duty Cycle 100% Transmitter Duty Cycle BU-61582X3/X6 Idle Transmitter Duty Cycle Transmitter Duty Cycle 100% Transmitter Duty Cycle Hottest BU-61582X0 BU-61582X1 Idle Transmitter Duty Cycle Transmitter Duty Cycle 100% Transmitter Duty Cycle BU-61582X2 Idle Transmitter Duty Cycle Transmitter Duty Cycle 100% Transmitter Duty Cycle BU-61582X3/X6 Idle Transmitter Duty Cycle Transmitter Duty Cycle 100% Transmitter Duty Cycle UNITS
-0.5 -0.5 +0.5 +0.5 -0.5
-18.0 -18.0 Vcc+0.5
0.860
Vp-p Vpeak
Vp-p Vp-p mVp-p, diff nsec
-250 -550
0.250 0.875 1.22 1.475 0.86 1.16 1.46 2.06
0.750 2.97 3.77 1.92 2.35 2.84 3.71 1.34 1.57 1.79 2.23
-8.0
0.225 0.335 0.600 0.860 1.385 0.290 0.590 0.890 1.490
0.50 0.68 1.06 1.45 2.23 0.59 0.92 1.36 2.16 0.28 0.51 0.75 1.22
-15.75 -12.6 5.25 5.25
-14.25 -15.0 -11.4 4.75 4.75 -12.0
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BU-61582 M-08/04-0
TABLE SP'ACE SERIES SPECIFICATIONS (CONT)
PARAMETER CLOCK INPUT Frequency Nominal Value (programmable) Default Mode Option Long Term Tolerance 1553A Compliance 1553B Compliance Short Term Tolerance,1 second 1553A Compliance 1553B Compliance Duty Cycle UNITS
16.0 12.0 0.01 0.001 0.01
19.5 23.5 51.5
TABLE NOTES (cont) Software programmable options). Includes RT-to-RT Timeout (Mid-Parity Transmit Command Mid-Sync Transmitting Status). (10) both logic transceiver. channels (11) Measured from mid-parity crossing Command Word mid-sync crossing RT's Status Word.
INTRODUCTION
DDC's SP'ACE series Integrated BC/RT/MT hybrids provide complete, flexible interface between microprocessor MIL-STD-1553A, Notice McAir, STANAG 3838 bus, implementing Controller, Remote Terminal (RT) Monitor Terminal (MT) modes. Packaged single square inch 70pin DIP, surface mountable Flat Pack Gull Lead, SP'ACE series contains dual low-power transceivers encoder/decoders, complete BC/RT/MT multiprotocol logic, memory management interrupt logic, shared static direct, buffered interface host processor bus. BU-61582 contains internal address latches bidirectional data buffers provide direct interface host processor bus. BU-61582 interfaced directly both 16-bit 8-bit microprocessors buffered shared configuration. addition, SP'ACE connect 16-bit processor Direct Memory Access (DMA) interface. BU-61582 includes words buffered RAM. Alternatively, SP'ACE interfaced much words external either shared configurations. SP'ACE mode multiprotocol, supporting MIL-STD1553A, MIL-STD-1553B Notice STANAG 3838 (including EFAbus). memory management scheme mode provides option separation broadcast data, compliance with 1553B Notice Both double buffer circular buffer options programmable subaddress. These features serve ensure data consistency off-load host processor bulk data transfer applications. SP'ACE series implements three monitor modes: word monitor, selective message monitor, combined RT/selective monitor. Other features include options automatic retries programmable intermessage mode, internal Time Register, Interrupt Status Register internal command illegalization mode.
1553 MESSAGE TIMING Completion Write Start2.5 to-Start Next Message) Intermessage (Note 10.5 BC/RT/MT Response Timeout (Note 18.5 nominal 17.5 18.5 22.5 nominal 21.5 22.5 50.5 nominal 49.5 50.5 128.0 nominal 129.5 Transmitter Watchdog Timeout Response Timeout (Note THERMAL Thermal Resistance, Junction-to-Case, Hottest (JC) BU-61582X0 BU-61582X1 BU-61582X2 BU-61582X3/X6 Operating Junction Temperature Storage Temperature Lead Temperature (soldering, sec.) PHYSICAL CHARACTERISTICS Size 70-pin DIP, Flat Pack J-Lead, Gull Leads Weight 70-pin DIP, Flat Pack J-Lead, Gull Leads
+300
°C/W °C/W °C/W °C/W
0.215 (48.26 25.4 5.46
(mm)
TABLE NOTES: Notes through applicable Receiver Differential Resistance Differential Capacitance specifications: Specifications include both transmitter receiver (tied together internally). Measurement impedance directly between pins TX/RX A(B) TX/RX A(B) SP'ACE Series hybrid. Assuming connection power ground inputs hybrid. specifications applicable both unpowered powered conditions. specifications assume volt balanced, differential, sinusoidal input. applicable frequency range MHz. Minimum resistance maximum capacitance parameters guaranteed, tested, over operating range. Assumes common mode voltage within frequency range MHz, applied pins isolation transformer stub side (either direct transformer coupled), referenced hybrid ground. recommended transformer other transformer that provides equivalent minimum CMRR. Typical value minimum intermessage time. Under software control, lengthened (65,535 minus message time), increments
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BU-61582 M-08/04-0
FUNCTIONAL OVERVIEW
TRANSCEIVERS V/-12 front end, BU-61582X1(X2) uses low-power bipolar analog monolithic thin-film hybrid technology. transceiver requires (-12 only (requiring V/+12 includes voltage source transmitters. voltage source transmitters provide superior line driving capability long cables heavy amounts loading.
receiver sections BU-61582 fully compliant with MIL-STD-1553B terms front overvoltage protection, threshold, common mode rejection, word error rate. addition, receiver filters have been designed optimal operation with J-Rad chip's Manchester decoders.
interfacing fiber optic transceivers MIL-STD-1773 applications, transceiverless version SP'ACE used. These versions provide register programmable option direct interface single-ended outputs fiber optic receiver. external logic needed.
TIME TAGGING SP'ACE includes internal read/writable Time Register. This register read/writable 16-bit counter with programmable resolution either LSB. Also, Time Register clocked from external oscillator. Another option allows software controlled incrementing Time Register. This supports self-test Time Register. each message processed, value Time register loaded into second location respective descriptor stack entry ("TIME WORD") both modes.
Additional provided options will: clear Time Register following Synchronize (without data) mode command load Time Register following Synchronize (with data) mode command; enable interrupt request setting Interrupt Status Register when Time Register rolls over from FFFF 0000. Assuming Time Register loaded reset, this will occur approximately second time intervals, µs/LSB resolution, down intervals, µs/LSB resolution. Another programmable option mode automatic clearing Service Request Status Word following BU-61582's response Transmit Vector Word mode command.
J-RAD DIGITAL MONOLITHIC J-Rad digital monolithic represents cornerstone element BU-61582 SP'ACE family terminals. J-Rad chip actually radiation hardened version DDC's (J-prime) monolithic which building block behind DDC's non-radiation hardened BU-61580 series terminals. such, J-Rad possesses enhanced hardware software features which have made BU-61580 industry standard 1553 interface component.
J-Rad chip consists dual encoder/decoder, complete protocol Controller (BC), 1553A/B/McAir Remote Terminal (RT), Monitor (MT) modes; memory management interrupt logic; flexible, buffered interface host processor optional external RAM; separate buffered interface external RAM. Reference region within dotted line FIGURE Besides realizing protocol, memory management, interface functions earlier AIM-HY series, J-Rad chip includes large number enhancements facilitate hardware software design, further off-load 1553 terminal's host processor.
DECODERS default mode operation BU-61582 BC/RT/MT requires clock input. needed, software programmable option allows device operated from clock input. Most current 1553 decoders sample using clock. mode (default following hardware software reset), decoders sample 1553 serial data using clock. mode MHz), decoders programmed sample using both clock edges; this provides sampling rate MHz. faster sampling rate J-Rad's Manchester decoders provides superior performance terms error rate zero-crossing distortion tolerance.
INTERRUPTS SP'ACE series components provide many programmable options interrupt generation handling. interrupt output three software programmable modes operation: pulse, level output cleared under software control, level output automatically cleared following read Interrupt Status Register. Individual interrupts enabled Interrupt Mask Register. host processor easily determine cause interrupt using Interrupt Status Register. Interrupt Status Register provides current state interrupt conditions. Interrupt Status Register updated ways. standard interrupt handling mode, particular Interrupt Status Register will updated only condition exists corresponding Interrupt Mask Register enabled. enhanced interrupt handling mode, particular Interrupt Status Register will updated condition exists regardless contents corresponding Interrupt Mask Register bit. case, respective Interrupt Mask Register enables interrupt particular condition.
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BU-61582 M-08/04-0
RADIATION HARDNESS BU-61582 combines analog bipolar transceivers with logic fabricated Honeywell Solid State Electronics Center's (SSEC) micron Radiation Insensitive CMOS (RICMOS-4) process provide radiation survivability.
summarize, BU-61582 total gamma dose immunity MRad threshold MeV/mg/cm2, providing soft error rate 10-5 errors/device-day. Since transceiver bipolar digital logic implemented Honeywell's RICMOS process, hybrids inherently immune latchup.
TABLE SP'ACE SERIES RADIATION SPECIFICATIONS
PART NUMBER TOTAL DOSE SINGLE EVENT UPSET SINGLE EVENT LATCHUP
BU-61582(3)X0 BU-61582(3)X1 BU-61582(3)X2 MRad
10-5 errors/device-day, (LET Threshold MeV/mg/cm2) 10-5 errors/device-day, (LET Threshold MeV/mg/cm2)
Immune
BU-61582(3)X3 BU-61582(3)X6
KRad
Immune
HIGH-REL SCREENING committed design manufacture hybrids transformers with enhanced processing screening spaceborne applications other systems requiring highest levels reliability. These platforms include launch vehicles, satellites International Space Station.
tailored design methodologies optimize fabrication space level hybrids. intent design guidelines minimize number wirebonds, minimize number substrate layers, maximize space between components. DDC's space grade products combine analog bipolar hard CMOS technology provide various levels radiation tolerance. BU-61582 packaged 70-pin ceramic package. contrast Kovar (metal) packages, ceramic eliminates hermeticity problems associated with glass beads used metal packages. addition, ceramic packages provide more rigid leads, better thermal properties, easier wirebonding, lower weight. production space level hybrids entail enhanced screening steps beyond DDC's standard flow. This includes Condition visual inspection, analysis, element evaluation integrated circuit die. hybrids, additional screening includes Particle Impact Noise Detection (PIND), 320hour burn-in, 100% non-destructive wirebond pull, X-ray analysis, well Destructive Physical Analysis (DPA) testing, extended temperature cycling testing, moisture content limit 5000 PPM. TABLE summarizes procurement screening, element evaluation, hybrid screening used production BU-61582.
TABLE HIGH RELIABILITY SCREENING OPTIONS
ELEMENT EVALUATION Visual Inspection: Integrated Circuits Transistors Diodes Passive Components METHOD MIL-STD-883, Method 2010 Condition MIL-STD-750, Method 2072 2073 MIL-STD-883, Method 2032 Class
Analysis Integrated MIL-STD-883, Method 2018 Circuits Element Evaluation: Visual, Electrical, Wire Bondability, 24-Hour Stabilization Bake, Temperature Cycles 5000 constant acceleration MIL-H-38534 240-Hour Powered Burn-In 1000-Hour Life Test (Burn-In 1000-Hour Life Test Only Required Active Components.) ASSEMBLY TEST Particle Impact Noise Detection (PIND) 320-Hour Burn-In 100% Non-Destructive Wirebond Pull Radiographic (X-Ray) Analysis TESTING Extended Temperature Cycling: Cycles Including Radiographic (X-Ray) Testing Moisture Content Limit 5000 MIL-STD-883, Method 1010 Condition MIL-STD-883, Method 2012 MIL-STD-883, Method 2020 Condition MIL-STD-883, Method 1015 MIL-STD-883, Method 2023 MIL-STD-883, Method 2012
MIL-STD-883, Method 1018
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BU-61582 M-08/04-0
ADDRESSING, INTERNAL REGISTERS, MEMORY MANAGEMENT software interface BU-61582 host processor consists internal operational registers normal operation, additional test registers, plus shared memory address space. BU-61582's internal resides this address space. Reference TABLE
Definition address mapping accessibility SP'ACE's nontest registers, test registers, follows:
TABLE ADDRESS MAPPING
ADDRESS LINES reserved Test Mode Register reserved Interrupt Mask Register (RD/WR) Configuration Register (RD/WR) Configuration Register (RD/WR) Start/Reset Register (WR) BC/RT Command Stack Pointer Register (RD) Control Word/RT Subaddress Control Word Register (RD/WR) Time Register (RD/WR) Interrupt Status Register (RD) Configuration Register (RD/WR) Configuration Register (RD/WR) Configuration Register (RD/WR) Data Stack Address Register (RD/WR) Frame Time Remaining Register (RD/WR) Time Remaining Next Message Register (RD/WR) Frame Time/RT Last Command Trigger Word Register (RD/WR) Status Word Register (RD) Word Register (RD) Test Mode Register REGISTER DESCRIPTION/ACCESSIBILITY
Interrupt Mask Register: Used enable disable interrupt requests various conditions. Configuration Registers Used select BU-61582's mode operation, software control Status Word bits, Active Memory Area, Stop-on-Error, Memory Management mode selection, control Time operation. Start/Reset Register: Used "command" type functions, such software reset, BC/MT Start, Interrupt Reset, Time Reset, Time Register Test. Start/Reset Register includes provisions stopping auto-repeat mode, either current message current frame. BC/RT Command Stack Pointer Register: Allows host determine pointer location current most recent message when BU-61582 modes. Control Word/RT Subaddress Control Word Register: mode, allows host access current most recent Control Word. Control Word contains bits that select active message format, enable off-line self-test, masking Status Word bits, enable retries interrupts, specify MIL-STD-1553A -1553B error handling. mode, this register allows host access current most recent Subaddress Control Word. Subaddress Control Word used select memory management scheme enable interrupts current message. read/write accessibility used testing SP'ACE hybrid. Time Register: Maintains value real-time clock. resolution this register programmable from among µs/LSB. TAG_CLK input signal also cause external
oscillator clock Time Register. Start-of-Message (SOM) End-of-Message (EOM) sequences Message Monitor modes cause write current value Time Register stack area RAM.
Interrupt Status Register: Mirrors Interrupt Mask Register contains Master Interrupt bit. allows host processor determine cause interrupt request means single READ operation.
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BU-61582 M-08/04-0
Configuration Registers Used enable many BU-61582's advanced features. These include enhanced mode features; that functionality beyond that previous generation product, BUS-61559 Advanced Integrated Hybrid with Enhanced Features (AIM-HY'er). mode, enhanced mode features include expanded Control Word Block Status Word, additional Stop-On-Error Stop-On-Status functions, frame auto-repeat, programmable intermessage times, automatic retries, expanded Status Word Masking, capability generate interrupts following completion selected message. mode, enhanced mode features include expanded Block Status Word, combined RT/Selective Message Monitor mode, internal wrapping RTFAIL output signal (from J-Rad chip) RTFLAG Status Word bit, double buffering scheme individual receive (broadcast) subaddresses, alternate (fully software programmable) Status Word. mode, enhanced mode enables Selective Message Monitor, combined RT/Selective Monitor modes, monitor triggering capability. Data Stack Address Register: Used point current address location shared used storing message words (second Command Words, Data Words, Status Words) Selective Word Monitor mode. Frame Time Remaining Register: Provides read only indication time remaining current frame. resolution this register 100, µs/LSB. Message Time Remaining Register: Provides read only indication time remaining before start next message frame. resolution this register µs/LSB. Frame/RT Last Command/MT Trigger Word Register: mode, programs frame time, frame auto-repeat mode. resolution this register µs/LSB,
TABLE INTERRUPT MASK REGISTER (READ/WRITE 00H)
15(MSB) RESERVED 0(LSB) PARITY ERROR BC/RT TRANSMITTER TIMEOUT BC/RT COMMAND STACK ROLLOVER COMMAND STACK ROLLOVER DATA STACK ROLLOVER FAIL RETRY ADDRESS PARITY ERROR TIME ROLLOVER CIRCULAR BUFFER ROLLOVER BC/RT SELECTED MESSAGE FRAME FORMAT ERROR STATUS SET/RT MODE CODE/MT PATTERN TRIGGER MESSAGE DESCRIPTION
with range 6.55 seconds; mode, this register stores current most previous) 1553 Command Word processed SP'ACE Word Monitor mode, this register specifies 16-bit Trigger (Command) Word. Trigger Word used start stop monitor, generate interrupts.
Status Word Register Word Registers: Provide read-only indications BU-61582's Status Words. Test Mode Registers 0-7: These registers used facilitate production maintenance testing SP'ACE systems incorporating SP'ACE hybrid.
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BU-61582 M-08/04-0
TABLE CONFIGURATION REGISTER (READ/WRITE 01H)
FUNCTION (BITS 11-0 ENHANCED MODE ONLY) WITHOUT ALTERNATE STATUS (logic (logic CURRENT AREA MESSAGE MONITOR ENABLED (MMT) DYNAMIC CONTROL ACCEPTANCE WITH ALTERNATE STATUS (logic (logic CURRENT AREA MESSAGE MONITOR ENABLED (MMT) MONITOR FUNCTION (logic (logic CURRENT AREA MESSAGE MONITOR ENABLED (MMT) TRIGGER ENABLED WORD START-ON-TRIGGER STOP-ON-TRIGGER USED EXTERNAL TRIGGER ENABLED USED USED USED USED MONITOR ENABLED (Read Only) MONITOR TRIGGERED (Read Only) MONITOR ACTIVE (Read Only)
(MSB) RT/BC-MT (logic (LSB) MT/BC-RT (logic CURRENT AREA MESSAGE STOP-ON-ERROR FRAME STOP-ON-ERROR
STATUS STOP-ON-MESSAGE BUSY STATUS STOP-ON-FRAME FRAME AUTO-REPEAT EXTERNAL TRIGGER ENABLED INTERNAL TRIGGER ENABLED INTERMESSAGE TIMER ENABLED RETRY ENABLED DOUBLED/SINGLE RETRY ENABLED (Read Only) FRAME PROGRESS (Read Only) MESSAGE PROGRESS (Read Only) SERVICE REQUEST SUBSYSTEM FLAG RTFLAG USED USED USED USED USED USED
MESSAGE PROGRESS MESSAGE (Read Only) PROGRESS (Read Only)
TABLE CONFIGURATION REGISTER (READ/WRITE 02H)
15(MSB) 0(LSB) DESCRIPTION ENHANCED INTERRUPTS LOGIC BUSY LOOKUP TABLE ENABLE DOUBLE BUFFER ENABLE OVERWRITE INVALID DATA 256-WORD BOUNDARY DISABLE TIME RESOLUTION (TTR2) TIME RESOLUTION (TTR1) TIME RESOLUTION (TTR0) CLEAR TIME SYNCHRONIZE LOAD TIME SYNCHRONIZE INTERRUPT STATUS AUTO CLEAR LEVEL/PULSE INTERRUPT REQUEST CLEAR SERVICE REQUEST ENHANCED MEMORY MANAGEMENT SEPARATE BROADCAST DATA
TABLE START/RESET REGISTER (WRITE 03H)
15(MSB) RESERVED RESERVED BC/MT STOP-ON-MESSAGE STOP-ON-FRAME TIME TEST CLOCK TIME RESET INTERRUPT RESET BC/MT START RESET DESCRIPTION
0(LSB)
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BU-61582 M-08/04-0
TABLE BC/RT COMMAND STACK POINTER REG. (READ 03H)
0(LSB) COMMAND STACK POINTER DESCRIPTION 15(MSB) COMMAND STACK POINTER
TABLE TIME REGISTER (READ/WRITE 05H)
15(MSB) TIME 0(LSB) TIME DESCRIPTION
TABLE CONTROL WORD REGISTER (READ/WRITE 04H)
15(MSB) RESERVED 0(LSB) M.E. MASK SERVICE REQUEST MASK SUBSYS BUSY MASK SUBSYS FLAG MASK TERMINAL FLAG MASK RESERVED BITS MASK RETRY ENABLED CHANNEL LINE SELF TEST MASK BROADCAST INTERRUPT ENABLE 1553A/B SELECT MODE CODE FORMAT BROADCAST FORMAT RT-RT FORMAT DESCRIPTION
TABLE INTERRUPT STATUS REGISTER (READ 06H)
PARITY ERROR BC/RT TRANSMITTER TIMEOUT BC/RT COMMAND STACK ROLLOVER COMMAND STACK ROLLOVER DATA STACK ROLLOVER FAIL RETRY ADDRESS PARITY ERROR TIME ROLLOVER CIRCULAR BUFFER ROLLOVER BC/RT SELECTIVE MESSAGE FRAME FORMAT ERROR STATUS SET/RT MODE CODE PATTERN TRIGGER MESSAGE DESCRIPTION 15(MSB) MASTER INTERRUPT
0(LSB)
TABLE SUBADDRESS CONTROL WORD (READ/WRITE 04H)
DESCRIPTION 15(MSB) DOUBLE BUFFER ENABLE 0(LSB) CIRC MEMORY MANAGEMENT (MM2) MEMORY MANAGEMENT (MM1) MEMORY MANAGEMENT (MM0) CIRC MEMORY MANAGEMENT (MM2) MEMORY MANAGEMENT (MM1) MEMORY MANAGEMENT (MM0) BCST: BCST: CIRC BCST: MEMORY MANAGEMENT (MM2) BCST: MEMORY MANAGEMENT (MM1) BCST: MEMORY MANAGEMENT (MM0)
TABLE CONFIGURATION REGISTER (READ/WRITE 07H)
DESCRIPTION 15(MSB) ENHANCED MODE ENABLE 0(LSB) BC/RT COMMAND STACK SIZE BC/RT COMMAND STACK SIZE COMMAND STACK SIZE COMMAND STACK SIZE DATA STACK SIZE DATA STACK SIZE DATA STACK SIZE ILLEGALIZATION DISABLED OVERRIDE MODE ERROR ALTERNATE STATUS WORD ENABLE ILLEGAL TRANSFER DISABLE BUSY TRANSFER DISABLE RTFAIL-FLAG WRAP ENABLE 1553A MODE CODES ENABLE ENHANCED MODE CODE HANDLING
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BU-61582 M-08/04-0
TABLE CONFIGURATION REGISTER (READ/WRITE 08H)
DESCRIPTION 15(MSB) EXTERNAL WORD ENABLE 0(LSB) INHIBIT WORD BUSY MODE COMMAND OVERRIDE BUSY EXPANDED CONTROL WORD ENABLE BROADCAST MASK ENABLE/XOR RETRY M.E. RETRY STATUS RETRY ALT/SAME RETRY ALT/SAME VALID M.E./NO DATA VALID BUSY/NO DATA OPTION LATCH ADDRESS WITH CONFIG TEST MODE TEST MODE TEST MODE
TABLE FRAME TIME REMAINING REGISTER (READ/WRITE 0BH)
DESCRIPTION 15(MSB) FRAME TIME REMAINING 0(LSB) FRAME TIME REMAINING
Note: resolution
TABLE MESSAGE TIME REMAINING REGISTER (READ/WRITE 0CH)
DESCRIPTION 15(MSB) MESSAGE TIME REMAINING 0(LSB) MESSAGE TIME REMAINING
Note: resolution
TABLE CONFIGURATION REGISTER (READ/WRITE 09H)
DESCRIPTION 15(MSB) 12MHZ CLOCK SELECT 0(LSB) SINGLE ENDED SELECT EXTERNAL INHIBIT read only EXTERNAL INHIBIT read only EXPANDED CROSSING ENABLED RESPONSE TIMEOUT SELECT RESPONSE TIMEOUT SELECT CHECK ENABLED BROADCAST DISABLED ADDRESS LATCH/TRANSPARENT (see Note) ADDRESS ADDRESS ADDRESS ADDRESS ADDRESS ADDRESS PARITY
TABLE FRAME TIME/RT LAST COMMAND/ TRIGGER REGISTER (READ/WRITE 0DH)
15(MSB) 0(LSB) DESCRIPTION
TABLE STATUS WORD REGISTER (READ/WRITE 0EH)
15(MSB) LOGIC LOGIC LOGIC LOGIC LOGIC MESSAGE ERROR INSTRUMENTATION SERVICE REQUEST RESERVED RESERVED RESERVED BROADCAST COMMAND RECEIVED BUSY SUBSYSTEM FLAG DYNAMIC CONTROL ACCEPT TERMINAL FLAG DESCRIPTION
Note: Read only, logic 61582, logic 61583.
TABLE MONITOR DATA STACK ADDRESS REGISTER (READ/WRITE 0AH)
0(LSB) MONITOR DATA STACK ADDRESS DESCRIPTION 15(MSB) MONITOR DATA STACK ADDRESS
0(LSB)
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BU-61582 M-08/04-0
TABLE WORD REGISTER (WRITE 0FH)
0(LSB) DESCRIPTION LOOP TEST FAILURE LOOP TEST FAILURE HANDSHAKE FAILURE TRANSMITTER SHUTDOWN TRANSMITTER SHUTDOWN TERMINAL FLAG INHIBITED CHANNEL HIGH WORD COUNT WORD COUNT INCORRECT SYNC RECEIVED PARITY/MANCHESTER ERROR RECEIVED RT-RT GAP/SYNC/ADDRESS ERROR RT-RT RESPONSE ERROR RT-RT COMMAND WORD ERROR COMMAND WORD CONTENTS ERROR 15(MSB) TRANSMITTER TIMEOUT
TABLE MODE BLOCK STATUS WORD
15(MSB) 0(LSB) CHANNEL ERROR FLAG RT-RT FORMAT FORMAT ERROR RESPONSE TIMEOUT LOOP TEST FAIL DATA STACK ROLLOVER ILLEGAL COMMAND WORD WORD COUNT ERROR INCORRECT SYNC INVALID WORD RT-RT GAP/SYNC/ADDRESS ERROR RT-RT COMMAND ERROR COMMAND WORD CONTENTS ERROR DESCRIPTION
TABLE WORD MONITOR IDENTIFICATION WORD
15(MSB) TIME NOTE: TABLES REGISTERS, THEY WORDS STORED RAM. 0(LSB) TIME WORD FLAG THIS BROADCAST ERROR COMMAND/DATA CHANNEL CONTIGUOUS DATA/GAP MODE CODE DESCRIPTION
TABLE MODE BLOCK STATUS WORD
15(MSB) 0(LSB) CHANNEL ERROR FLAG STATUS FORMAT ERROR RESPONSE TIMEOUT LOOP TEST FAIL MASKED STATUS RETRY COUNT RETRY COUNT GOOD DATA BLOCK TRANSFER WRONG STATUS ADDRESS/NO WORD COUNT ERROR INCORRECT SYNC TYPE INVALID WORD DESCRIPTION
TABLE MESSAGE MONITOR MODE BLOCK STATUS WORD
15(MSB) CHANNEL ERROR FLAG RT-RT TRANSFER FORMAT ERROR RESPONSE TIMEOUT GOOD DATA BLOCK TRANSFER DATA STACK ROLLOVER RESERVED WORD COUNT ERROR INCORRECT SYNC INVALID WORD RT-RT GAP/SYNC/ADDRESS ERROR RT-RT COMMAND ERROR COMMAND WORD CONTENTS ERROR DESCRIPTION
0(LSB)
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BU-61582 M-08/04-0
CONTROLLER (BC) ARCHITECTURE
protocol BU-61582 implements MIL-STD1553B message formats. Message format programmable message-by-message basis means bits Control Word Command Word respective message. Control Word allows 1553 message format, 1553A/B type channel, self-test, Status Word masking specified individual message basis. addition, automatic retries and/or interrupt requests enabled disabled individual messages. performs error checking required MIL-STD-1553B. This includes validation response time, sync type sync encoding, Manchester encoding, parity, count, word count, Status Word Address field, various RT-to-RT transfer errors. BU-61582's response timeout value programmable with choices longer response timeout values allow operation over long buses and/or repeaters. FIGURE illustrates intermessage frame timing. BU-61582 programmed process frames messages with processor intervention. possible program either single frame frame auto-repeat operation. auto-repeat mode, frame repetition rate controlled either internally, using programmable frame timer, from external trigger input. internal frame time programmable 6.55 seconds increments addition frame time, intermessage time, defined start current message start subsequent message, programmable individual message basis. time between individual successive messages programmable 65.5 increments
TABLE TYPICAL MEMORY ORGANIZATION (SHOWN RAM)
ADDRESS (HEX) 0000-00FF Stack 0100 0101 0102 0103 0104 0105 0106 0107 Stack Pointer (fixed location) Message Count (fixed location) Initial Stack Pointer (see note) (Auto-Frame Repeat Mode) Initial Message Count (see note) (Auto-Frame Repeat Mode) Stack Pointer Message Count Initial Stack Pointer (see note) (Auto-Frame Repeat Mode) Initial Message Count (see note) (Auto-Frame Repeat Mode) DESCRIPTION
0108-012D Message Block 012E-0153 Message Block 0154-0179 Message Block
3EC8-3EED Message Block 3EEE-3EFF Used 3F00-3FFF Stack
Note: Used only Enhanced mode with Frame Auto-Repeat enabled.
MEMORY ORGANIZATION
TABLE illustrates typical memory mode. important note that only fixed locations BU-61582 Standard mode Stack Pointers (address locations 0100 (hex) 0104) Message Count locations (0101 0105). Enabling Frame Auto-Repeat mode will reserve four more memory locations Enhanced mode; these locations Initial Stack Pointers (address locations (hex) 106) Initial
Message Count locations (103 107). user free locate Stack Message Blocks anywhere else within (16K internal) shared address space. simplicity illustration, assume allocation maximum length message each message block typical memory TABLE maximum size message block words, RT-to-RT transfer Data Words (Control Commands Loopback Status Words Data Words). Note, however, that this example assumes disabling 256-word boundaries.
MESSAGE TIME MESSAGE INTERMESSAGE TIME
MESSAGE
MESSAGE
MESSAGE
FRAME TIME
FIGURE MESSAGE FRAME TIMING
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MEMORY MANAGEMENT
FIGURE illustrates BU-61582's memory management scheme. memory management features global double buffering mechanism. This provides sets various mode data structures: Stack Pointer Message Counter locations, Descriptor Stack areas, message blocks. Configuration Register selects current active area. point time, BU-61582's internal 1553 memory management logic access only various data structures within "active" area. FIGURE delineates "active" "inactive" areas nonshaded shaded areas, respectively; however, point time, both "active" "nonactive" areas accessible host processor. most applications, host processor will access "nonactive" area, while 1553 processes "active" area messages. programmed transmit multimessage frames messages. number messages processed programmable Active Area Message Count location shared RAM, initialized host processor. addition, host processor must initialize another location, Active Area Stack Pointer. Stack Pointer references four-word message block descriptor Stack area shared each message processed. Stack size programmable with choices 256, 512, 1024, 2048 words.
Frame Auto-Repeat mode, Initial Stack Pointer Initial Message Counter locations must loaded host prior processing first frame. single frame mode does these locations third fourth words block descriptor Intermessage Time Message Block Address respective message. These memory locations must written host processor prior start message processing. Intermessage Time optional. Block Address pointer specifies starting location each message block. first word each message block Control Word. start each message, Block Status Time Words write message block descriptor stack. Block Status Word includes indications message process message completion, channel, Status Set, response timeout, retry count, Status address mismatch, loop test (on-line self-test) failure, other error conditions. TABLE illustrates mapping Block Status word. 16-bit Time Word will reflect current contents internal Time Register. This read/writable register, which operates three modes, programmable resolution from µs/LSB. addition, Time register clocked from external source.
INITIAL STACK POINTERS (NOTE) MESSAGE BLOCKS
CONFIGURATION REGISTER
STACK POINTERS
DESCRIPTOR STACKS
CURRENT AREA INITIAL MESSAGE COUNTERS
BLOCK STATUS WORD TIME WORD MESSAGE TIME WORD MESSAGE BLOCK ADDR MESSAGE BLOCK
MESSAGE COUNTERS
MESSAGE BLOCK
FIGURE MODE MEMORY MANAGEMENT
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MESSAGE BLOCK FORMATS CONTROL WORD mode, BU-61582 supports MIL-STD-1553 message formats. each 1553 message format, BU-61582 mandates specific sequence words within Message Block. This includes locations Control, Command (transmitted) Data Words that read from
BC-to-RT Transfer Control Word Receive Command Word Data Word Data Word Last Data Word Last Data Word Looped Back Status Received RT-to-RT Transfer Control Word Receive Command Transmit Command Transmit Command Looped Back Status Word Data Data Last Data Status Word Mode Code; With Data Control Word Mode Command Data Word Data Word Looped Back Status Received Broadcast Control Word Broadcast Command Data Data Last Data Last Data Status Word RT-to-RTs (Broadcast) Transfer Control Word Broadcast Command Command Command Looped Back Status Word Data Data Last Data Broadcast Mode Code; Data Control Word Broadcast Mode Command Broadcast Mode Command Looped Back Broadcast Mode Code; With Data Control Word Broadcast Mode Command Data Word Data Word Looped Back Mode Code; Data Control Word Mode Command Mode Command Looped Back Status Received RT-to-BC Transfer Control Word Transmit Command Word Transmit Command Looped Back Status Received Data Word Data Word Last Data Word Mode Code; With Data Control Word Mode Command Mode Command Looped Back Status Received Data Word
protocol logic. addition, subsequent contiguous locations must allocated storage received Loopback, Status Data Words. FIGURE illustrates organization message blocks various MIL-STD-1553 message formats. Note that message formats, Control Word located first location message block. Control Word transmitted 1553 bus. Instead, contains bits that select active message format, enable off-line self-test, masking Status Word bits, enable retries interrupts, specify MIL-STD-1553A 1553B error handling. mapping definitions Control Word illustrated TABLE Control Word followed Command Word transmitted, subsequently second Command Word (for RT-to-RT transfer), followed Data Words transmitted (for Receive commands). location after last word transmitted reserved Loopback Word. loopback Word on-line self-test feature. subsequent locations after Loopback Word reserved received Status Words Data Words (for Transmit commands).
AUTOMATIC RETRIES
BU-61582 implements automatic message retries. When enabled, retries will occur, following response timeout format error conditions. additional options, retries enabled when Message Error Status Word 1553A following "Status Set" condition. failed message, either message retries will occur, channel (same alternate) independently programmable first second retry attempts. Retries enabled disabled individual message basis.
INTERRUPTS
interrupts enabled Interrupt Mask Register Stack Rollover, Retry, End-of-Message (global), End-ofMessage conjunction with Control Word individual messages), response timeout, message error, frame, Status conditions. definition "Status Set" programmable individual message basis means Control Word. This allows masking ("care/don't care") individual Status Word bits.
REMOTE TERMINAL (RT) ARCHITECTURE
protocol design BU-61582 represents DDC's fifth generation implementation 1553 salient features SP'ACE's architecture true multiprotocol functionality. This includes programmable options support MIL-STD-1553A, various McAir protocols, MIL-STD1553B Notice BU-61582 response time dead time 1553B), providing compliance 1553 protocols. Additional multiprotocol features BU61582 include options full software control Status Built-in-Test (BIT) words. Alternatively, 1553B applications, BU-61582 M-08/04-0
FIGURE MESSAGE BLOCK FORMATS
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these words formulated real time BU-61582 protocol logic. BU-61582 protocol design implements MIL-STD1553B message formats dual redundant mode codes. This design based largely previous generation products that have passed SEAFAC testing MIL-STD-1553B compliance. SP'ACE performs comprehensive error checking, word format validation, checks various RT-to-RT transfer errors. Other features BU-61582 include interrupt conditions, internal command illegalization, programmable busy subaddress.
TABLE TYPICAL MEMORY (SHOWN RAM)
ADDRESS (HEX) 0000-00FF 0100 0101-0103 0104 0105-0107 0108-010F 0110-013F 0140-01BF 01C0-023F 0240-0247 0248-025F 0260-027F 0280-02FF 0300-03FF 0400-041F 0420-043F 3FE0-3FFF DESCRIPTION Stack Stack Pointer (fixed location) RESERVED Stack Pointer (fixed location) RESERVED Mode Code Selective Interrupt Table (fixed area) Mode Code Data (fixed area) Lookup Table (fixed area) Lookup Table (fixed area) Busy Lookup Table (fixed area) (not used) Data Block Data Block Command Illegalizing Table (fixed area) Data Block Data Block Data Block
MEMORY ORGANIZATION
TABLE illustrates typical memory SP'ACE mode. mode, Stack Pointers reside fixed locations shared address space: address 0100 (hex) Area Stack Pointer address 0104 Area Stack Pointer. Besides Stack Pointer, mode there several other areas BU-61582 address space designated fixed locations. modes operation require Area Area Lookup Tables. Also allocated, several fixed locations optional features: Command Illegalization Lookup Table, Mode Code Selective Interrupt Table, Mode Code Data Table, Busy Lookup Table. should noted that unenabled optional fixed locations used general purpose storage (data blocks). Lookup tables, which provide mechanism mapping data blocks individual Tx/Rx/Bcst-subaddresses areas RAM, occupy address range locations 0140 01BF Area 01C0 023F Area lookup tables include Subaddress Control Words individual Data Block Pointers. used, address range 0300-03FF will dedicated illegalizing section RAM. actual Stack area individual data blocks located nonfixed areas shared address space.
fourth section each Lookup Tables stores Subaddress Control Words (refer TABLE TABLE 30). individual Subaddress Control Words used select memory management option interrupt scheme each transmit, receive, (optionally) broadcast subaddress. each transmit subaddress, there possible memory management schemes: single message; circular buffer. each receive (and optionally broadcast) subaddress,
TABLE LOOK-UP TABLES
AREA AREA 01C0 01DF 01E0 01FF 0200 021F 0220 023F DESCRIPTION Rx(/Bcst)_SA0 Rx(/Bcst)_SA31 Tx_SA0 Tx_SA31 Bcst_SA0 Bcst_SA31 SACW_SA0 SACW_SA31 COMMENT Receive (/Broadcast) Lookup Table 0140 015F 0160 017F 0180 019F 01A0 01BF
MEMORY MANAGEMENT
Another salient feature SP'ACE series products flexibility memory management architecture. architecture allows memory management scheme each transmit, receive, broadcast subaddress programmable subaddress basis. Also, compliance with MIL-STD-1553B Notice BU-61582 provides option separate data received from broadcast messages from nonbroadcast received data. Besides supporting global double buffering scheme mode), SP'ACE provides pair 128-word Lookup Tables memory management control, programmable subaddress basis (refer TABLE 29). 128-word tables include 32-word tables transmit message pointers receive message pointers. There also third, optional Lookup Table broadcast message pointers, providing Notice compliance, necessary. Data Device Corporation www.ddc-web.com
Transmit Lookup Table
Broadcast Lookup Table Optional
Subaddress Control Word Lookup Table (Optional)
BU-61582 M-08/04-0
TABLE SUBADDRESS CONTROL WORD MEMORY MANAGEMENT SUBADDRESS BUFFER SCHEME
DESCRIPTION 128-Word 256-Word 512-Word 1024-Word 2048-Word 4096-Word 8192-Word COMMENT Circular Buffer Specified Size Single Message Double Buffered
(default) mode, Single Message scheme implemented transmit, receive, broadcast subaddresses. Single Message mode (also Double Buffer Circular Buffer modes), there global double buffering scheme, controlled Configuration Register This selects from between sets various data structures shown figure: Stack Pointers (fixed addresses), Descriptor Stacks (user defined addresses), Lookup Tables (fixed addresses), Data Word blocks (user defined addresses). FIGURES delineate "active" "nonactive" areas nonshaded shaded areas, respectively. shown, SP'ACE stores Command Word from each message received, fourth location within message descriptor stack) respective message. bit, subaddress field, (optionally) broadcast/own address, index into active area Lookup Table, locate data block pointer current message. BU-61582 memory management logic then accesses data block pointer locate starting address Data Word block current message. maximum size Data Word block words. particular subaddress Single Message mode, there overwriting contents data blocks receive/broadcast subaddresses overreading, transmit subaddresses. single message mode, possible access multiple data blocks same subaddress. This, however, requires intervention host processor update respective Lookup Table pointer. implement data wraparound subaddress, required Notice MIL-STD-1553B, Single Message scheme should used wraparound subaddress. Notice recommends subaddress wraparound subaddress.
there three possible memory management schemes: single message; double buffered; circular buffer. each transmit, receive broadcast subaddress, there interrupt conditions programmable respective Subaddress Control Word: after every message subaddress; after circular buffer rollover. additional table used enable interrupts following selected mode code messages. When using circular buffer scheme given subaddress, size circular buffer programmable three bits Subaddress Control Word (see TABLE 30). options circular buffer size 128, 256, 512, 1024, 2048, 4096, 8192 Data Words.
SINGLE MESSAGE MODE
FIGURE illustrates Single Message memory management scheme. When operating BU-61582 "AIM-HY"
CONFIGURATION REGISTER
STACK POINTERS
DESCRIPTOR STACKS
LOOK-UP TABLE (DATA BLOCK ADDR)
DATA BLOCKS
CURRENT AREA
BLOCK STATUS WORD TIME WORD DATA BLOCK POINTER RECEIVED COMMAND WORD LOOK-UP TABLE ADDR (See note)
DATA BLOCK
DATA BLOCK
Note: Lookup table used mode commands when enhanced mode codes enabled.
FIGURE MEMORY MANAGEMENT: SINGLE MESSAGE MODE
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CONFIGURATION REGISTER
STACK POINTERS
DESCRIPTOR STACK
LOOK-UP TABLES
CIRCULAR DATA BUFFER* (128,256,.8192 WORDS)
CURRENT AREA BLOCK STATUS WORD TIME WORD DATA BLOCK POINTER RECEIVED COMMAND WORD LOOK-UP TABLE ADDRESS POINTER CURRENT DATA BLOCK LOOK-UP TABLE ENTRY POINTER NEXT DATA BLOCK
RECEIVED (TRANSMITTED) MESSAGE DATA (NEXT LOCATION)
CIRCULAR BUFFER ROLLOVER INTERRUPT
Notes:
TX/RX/BCST_SA look-up table entry updated following valid receive (broadcast) message following completion transit message
100% CIRCULAR BUFFER ROLLOVER INTERRUPT
FIGURE MEMORY MANAGEMENT: CIRCULAR BUFFER MODE
CIRCULAR BUFFER MODE
FIGURE illustrates circular buffer memory management scheme. circular buffer mode facilitates bulk data transfers. size circular buffer, shown right side figure, programmable from 8192 words even powers respective Subaddress Control Word. single message mode, host processor initially loads individual Lookup Table entries. start each message, SP'ACE stores Lookup Table entry third position respective message block descriptor stack area RAM, Single Message mode. SP'ACE transfers Receive Transmit Data Words (from) circular buffer, starting location referenced Lookup Table pointer. valid (or, optionally, invalid) message, value Lookup Table entry updates next location after last address accessed current message. result, Data Words next message directed same Tx/RX(/Bcst) subaddress will accessed from next contiguous block address locations within circular buffer. recommended option, Lookup Table pointers programmed update following invalid receive broadcast) message. This allows 1553 controller retry failed message, resulting valid (retried) data overwriting invalid data. This eliminates overhead RT's host processor. When pointer reaches lower boundary circular buffer (located 128, 256, 8192-word boundaries BU-61582 address space), pointer moves boundary circular buffer, FIGURE shows.
IMPLEMENTING BULK DATA TRANSFERS Circular Buffer scheme ideal bulk data transfers; that multiple messages to/from same subaddress. recommendation such applications enable circular buffer interrupt request. doing, routine transfer multiple messages selected subaddress, including errors retries, transparent RT's host processor. strategically initializing subaddress's Lookup Table pointer prior start bulk transfer, BU-61582 configured issue interrupt request only after received anticipated number valid Data Words designated subaddress.
SUBADDRESS DOUBLE BUFFERING MODE
receive (and broadcast) subaddresses, BU-61582 offers third memory management option, Subaddress Double Buffering. Subaddress double buffering provides means ensuring data consistency. FIGURE illustrates Subaddress Double Buffering scheme. Like Single Message Circular Buffer modes, Double Buffering mode selected subaddress basis means Subaddress Control Word. purpose Double Buffering mode provide host processor convenient means accessing most recent, valid data received given subaddress. This serves ensure highest possible degree data consistency allocating 32-bit Data Word blocks each individual receive (and/or broadcast) subaddress. given point time, blocks will designated "active" 1553 data block while other will designated "inactive" block. Data Words from next receive message that subaddress will stored "active" block. BU-61582 M-08/04-0
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CONFIGURATION REGISTER
STACK POINTERS
DESCRIPTOR STACK
LOOK-UP TABLES
DATA BLOCKS
CURRENT AREA BLOCK STATUS WORD YYYYY TIME WORD DATA BLOCK POINTER RECEIVED COMMAND WORD DATA BLOCK POINTER YYYYY DATA BLOCK DATA BLOCK
RECEIVE DOUBLE BUFFER ENABLE SUBADDRESS CONTROL WORD
FIGURE MEMORY MANAGEMENT: SUBADDRESS DOUBLE BUFFERING MODE
Upon completion message, provided that message valid Subaddress Double Buffering enabled, BU61582 will automatically switch "active" "inactive" blocks respective subaddress. SP'ACE accomplishes this toggling subaddress's Lookup Table Pointer rewriting pointer. result, most recent valid block received Data Words will always readily accessible host processor. means ensuring data consistency, host processor able reliably access most recent valid, received Data Word block performing following sequence: Disable double buffering respective subaddress Subaddress Control Word. That temporarily switch subaddress's memory management scheme Single Message mode. Read current value receive broadcast) subaddress's Lookup Table pointer. This points current "active" Data Word block. inverting this pointer value, possible locate start "inactive" Data Word block. This block will contain Data Words received during most recent valid message subaddress. Read words from "inactive" (most recent) Data Word Block. Re-enable Double Buffering mode respective subaddress Subaddress Control Word.
INTERRUPTS
mode, BU-61582 provides many maskable interrupts. interrupt conditions include (every) Message, Message Error, Selected Subaddress (Subaddress Control Word) Interrupt, Circular Buffer Rollover, Selected Mode Code Interrupt, Stack Rollover.
DESCRIPTOR STACK
beginning each message, BU-61582 stores four-word message descriptor active area stack. stack size programmable, with choices 256, 512, 1024, 2048 words. FIGURES show four words: Block Status Word, Time Word, Data Block Pointer, 1553 received Command Word. Block Status Word includes indications message in-progress message complete, channel, RT-to-RT transfer RT-to-RT transfer errors, message format error, loop test (self-test) failure, circular buffer rollover, illegal command, other error conditions. TABLE shows mapping Block Status Word. mode, Time Word stores current contents BU-61582's read/writable Time Register. resolution Time Register programmable from among µs/LSB. Also, incrementing Time counter from external clock source software command. SP'ACE stores contents accessed Lookup Table location current message, indicating starting location Data Word block, Data Block Pointer. This serves convenience locating stored message data blocks. BU-61582 M-08/04-0
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SP'ACE stores full 16-bit 1553 Command Word fourth location message descriptor.
following should noted with regards command illegalization: illegalize particular word count given broadcast/own address-T/R subaddress, appropriate position respective illegalization word should logic value logic designates respective Command Word legal command. BU-61582 will respond illegalized nonbroadcast command with Message Error Status Word. subaddresses 00001 through 11110, "WC/MC" field specifies Word Count field respective Command Word. subaddresses 00000 11111, "WC/MC" field specifies Mode Code field respective Command Word. Since nonmode code broadcast transmit messages defined MIL-STD-1553B, sixty (60) words illegalization RAM, addresses 0342 through 037D, corresponding these commands need initialized. BU-61582 will respond nonmode code broadcast transmit command, will automatically Message Error internal Status Register, regardless whether corresponding illegalization been set. next message Transmit Status Transmit Last Command mode code, BU-61582 will respond with Message Error set.
COMMAND ILLEGALIZATION
BU-61582 provides internal mechanism command illegalization. addition, there means allowing setting Busy Status Word only programmed subset transmit/receive/broadcast subaddresses. illegalization scheme uses 256-word area BU61582's address space. benefit this feature reduction printed circuit board requirements, eliminating need external PROM, PLD, device that does illegalizing function. BU-61582's illegalization scheme provides maximum flexibility, allowing subset 4096 possible combinations broadcast/own address, bit, subaddress, word count/mode code illegalized. Another advantage RAM-based illegalization technique that provides high degree self-testability.
ADDRESSING ILLEGALIZATION TABLE TABLE illustrates addressing scheme illegalization RAM. shown, base address illegalizing 0300 (hex). SP'ACE formulates index into Illegalizing Table based values BROADCAST/OWNADDRESS ADDRESS, bit, Subaddress, Word Count/Mode Code field (WC/MC4) current Command Word.
internal words reserved command illegalization. Broadcast commands illegalized separately from nonbroadcast receive commands mode commands. Commands illegalized down word count level. example, one-word receive command subaddress legal, while two-word receive command subaddress illegalized. first words Illegalization Table refer broadcast receive commands (two words subaddress). next words refer broadcast transmit commands. Since nonmode code broadcast transmit commands definition invalid, this section table (except subaddresses does need initialized user. next words correspond nonbroadcast receive commands. final words refer nonbroadcast transmit commands. Messages with Word Count/ Mode Code (WC/MC) fields between illegalized setting corresponding data bits respective evennumbered address locations illegalization table. Likewise, messages with WC/MC fields between illegalized setting corresponding data bits respective oddnumbered address locations illegalization table.
TABLE ILLEGALIZATION ADDRESS DEFINITION
15(MSB) 0(LSB) BROADCAST/OWN_ADDRESS WC4/MC4 DESCRIPTION
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BU-61582 M-08/04-0
PROGRAMMABLE BUSY
means providing compliance with Notice MIL-STD1553B, BU-61582 provides software controllable means setting Busy Status Word function subaddress. Busy Lookup Table BU-61582 address space, possible Busy based command broadcast/own address, bit, subaddress. Another programmable option allows received Data Words either stored stored messages when Busy set.
words circular buffer shared address space. TABLE shows mapping Monitor word.
MONITOR TRIGGER WORD
There Trigger Word Register that provides additional flexibility Word Monitor mode. BU-61582 stores value 16-bit Trigger Word Trigger Word Register. contents this register represent value Trigger Command Word. BU-61582 programmable options start stop Word Monitor, and/or issue interrupt request following receipt Trigger Command Word from 1553 bus.
OTHER FUNCTIONS
BU-61582 allows hardwired Address read host processor. Also, there options FLAG Status Word under software control and/or automatically following failure loopback self-test. Other software controllable options include software programmable Status words, automatic clearing Service Request Status Word following Transmit Vector Word mode command, capabilities clear and/or load Time Register following receipt Synchronize mode commands, options regarding Data Word transfers Busy and/or Message Error (Illegal) Status Word bits, handling 1553A reserved mode codes.
SELECTIVE MESSAGE MONITOR MODE
BU-61582 Selective Message Monitor provides features greatly reduce software processing burden host CPU. Selective Message Monitor implements selective monitoring messages from dual 1553 bus, with monitor filtering based Address, bit, Subaddress fields received 1553 Command Words. Selective Message Monitor mode greatly simplifies host processor software distinguishing between Command Status Words. Selective Message Monitor maintains stacks BU-61582 RAM: Command Stack Data Stack.
MONITOR (MT) ARCHITECTURE
BU-61582 provides three monitor (MT) modes: "AIM-HY" (default) "AIM-HY'er" Word Monitor mode. Selective Message Monitor mode. Simultaneous Remote Terminal/Selective Message Monitor mode. strong recommendation applications Selective Message Monitor, rather than Word Monitor. Besides providing monitor filtering based Address,T/R bit, Subaddress, Message Monitor eliminates need determine start messages software. development such software tends tedious task. Moreover, time, tends entail high degree overhead.
SIMULTANEOUS RT/MESSAGE MONITOR MODE Selective Message Monitor function purely passive monitor programmed function simultaneous RT/Monitor. RT/Monitor mode provides complete Remote Terminal (RT) operation BU-61582's strapped address monitor capability other non-broadcast addresses. This allows BU-61582 simultaneously operate full function "snoop" subset activity involving other bus. This type operation sometimes needed implement backup controller. combined RT/Selective Monitor maintains three stack areas BU-61582 address space: Command Stack, Monitor Command Stack, Monitor Data Stack. pointers various stacks have fixed locations BU-61582 address space. SELECTIVE MESSAGE MONITOR MEMORY ORGANIZATION TABLE illustrates typical memory SP'ACE Selective Message Monitor mode. This mode operation defines several fixed locations RAM. These locations allocate manner that compatible with combined RT/Selective Message Monitor mode. fixed memory consists Monitor Command Stack Pointers (location 102h 106h), Monitor Data Stack Pointers (locations 103h 107h), Selective Message Monitor Lookup Table (028002FFh) based Address T/R, subaddress. Assume Monitor Command Stack size words, Monitor Data Stack size words.
WORD MONITOR
Word Monitor mode, BU-61582 monitors both 1553 buses. After initializing Word Monitor putting on-line BU-61582 stores Command, Status, Data Words received from both buses. each word received from either bus, BU-61582 stores pair words RAM. first word bits data from received word. second word Monitor Identification (ID), "Tag" word. Word contains information relating channel, sync type, word validity, interword time gaps. BU-61582 stores data
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BU-61582 M-08/04-0
TABLE TYPICAL SELECTIVE MESSAGE MONITOR MEMORY (SHOWN RAM)
ADDRESS (HEX) 0000-0101 0102 0103 0104-0105 0106 0107 0108-027F 0280-02FF 0300-03FF 0400-07FF 0800-3FFF 0C00-0FFF1000-1FFF 2000-2FFF 3000-3FFF DESCRIPTION Used Monitor Command Stack Pointer (fixed location) Monitor Data Stack Pointer (fixed location) Used Monitor Command Stack Pointer (fixed location) Monitor Data Stack Pointer (fixed location) Used Selective Monitor Lookup Table (fixed area) Used Monitor Command Stack words) Monitor Command Stack words) Used words) Monitor Data Stack words) Monitor Data Stack words) Used words)
61582 will ignore (and store) current message; enabled, BU-61582 will create entry Monitor Command Stack address location referenced Monitor Command Stack Pointer. Similar mode, SP'ACE stores Block Status Word, 16-bit Time Word, Data Block Pointer Message Descriptor, along with received 1553 Command Word following reception Command Word. SP'ACE writes Block Status Time Words both start message. Monitor Block Status Word contains indications message in-progress message complete, channel, Monitor Data Stack Rollover, RT-to-RT transfer RT-to-RT transfer errors, message format error, other error conditions. TABLE shows Message Monitor Block Status Word. Data Block Pointer references first word stored Monitor Data Stack (the first word following Command Word) current message. BU-61582 will then proceed store subsequent words from message [possible second Command Word, Data Word(s), Status Word(s)] into consecutive locations Monitor Data Stack. size Monitor Command Stack programmable 256, words. Monitor Data Stack size programmable 512, 16K, 32K, words. Monitor interrupts enabled Monitor Command Stack Rollover, Monitor Data Stack Rollover, and/or End-of-Message conditions. addition, Word Monitor mode there interrupt enabled Monitor Trigger condition.
Refer FIGURE illustration Selective Message Monitor operation. Upon receipt valid Command Word, BU-61582 will reference Selective Monitor Lookup Table fixed block addresses) check condition (disabled/enabled) current command. disabled,
CONFIGURATION REGISTER
MONITOR COMMAND STACK POINTERS
MONITOR COMMAND STACKS
MONITOR DATA STACKS
CURRENT AREA BLOCK STATUS WORD TIME WORD CURRENT COMMAND WORD DATA BLOCK POINTER RECEIVED COMMAND WORD
MONITOR COMMAND STACK ROLLOVER INTERRUPT
MONITOR DATA BLOCK MONITOR DATA BLOCK
MONITOR DATA STACK ROLLOVER INTERRUPT
MONITOR COMMAND STACK 100% ROLLOVER INTERRUPT
NOTE
THIS (NOT SELECTED) WORDS STORED EITHER COMMAND STACK DATA STACK. ADDITION, COMMAND DATA STACK POINTERS WILL UPDATED.
MONITOR DATA STACK 100% ROLLOVER INTERRUPT
MONITOR DATA SELECTIVE MONITOR STACK POINTERS LOOKUP TABLES
OFFSET BASED RTA4-RTA0, T/R, SELECTIVE MONITOR ENABLE (SEE NOTE)
FIGURE SELECTIVE MESSAGE MONITOR OPERATION
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PROCESSOR MEMORY INTERFACE
SP'ACE terminals provide much flexibility interfacing host processor optional external memory. FIGURE shows that there control signals, which dual purpose, processor/memory interface. FIGURES through illustrate configurations that used interfacing BU-61582 host processor bus. various possible configurations serve reduce absolute minimum amount glue logic required interface 16-, 32-bit processor buses. Also included features facilitate interfacing processors that have "wait state" type handshake acknowledgment. Finally, SP'ACE supports reliable interface external dual port RAM. This type interface minimizes portion available processor bandwidth required access 1553 RAM. 16-bit buffered mode (FIGURE most common configuration used. provides direct, shared interface 16-bit 32-bit microprocessor. this mode, SP'ACE's internal address data buffers provide necessary isolation between host processor's address data buses corresponding internal memory buses. buffered mode, 1553 shared address space limit BU-61582's words internal RAM. 16-bit buffered mode provides pair pin-programmable options: logic sense RD/WR control input selectable POLARITY_SEL input; example, write when RD/WR Motorola 680X0 processors; write when RD/WR high Intel i960 series microprocessors. strapping input signal ZERO WAIT logic "1", SP'ACE terminals interface processors that have acknowledge type handshake input accommodate hardware controlled wait states; most current processor chips have such input. this case, BU-61582 will assert READY output only after latched WRITE data internally presented READ data D15-D0. strapping ZERO WAIT logic "0", possible easily interface BU-61582 processors that have acknowledge type handshake input. example such processor Analog Device's ADSP2101 chip. this configuration, processor clear strobe output before completion access BU-61582 internal register. this case, READY goes high following rising edge STRBD will stay high until completion transfer. READY will normally when ZERO WAIT low. Similar 16-bit buffered mode, 16-bit transparent mode (FIGURE supports shared interface host CPU. transparent mode offers advantage allowing buffer size expanded words, using external
RAM. disadvantage transparent mode that requires external address data buffers isolate processor buses from memory/BU-61582 buses. modified version transparent mode involves dual port RAM, rather than conventional static RAM. Refer FIGURE This allows host access very quickly, only limitation being access time dual port RAM. This configuration eliminates BU-61582 arbitration delays memory accesses. worst case delay time occurs only during simultaneous access host BU-61582 1553 logic same memory address. general, this will occur very rarely SP'ACE limits delay approximately FIGURE illustrates connections 16-bit Direct Memory Access (DMA) mode. this configuration host processor, rather than SP'ACE terminal, arbitrates address data buses. arbitration involves output signals Request (DTREQ), Acknowledge (DTACK), input signal Grant (DTGRT). interface allows SP'ACE components interface large amounts system while eliminating need external buffers. system address spaces larger than words, necessary host processor provide page register upper address bits (above A15) when BU-61582 accesses (while asserting (DTACK) low). internal accessible through standard SP'ACE interface (SELECT, STRBD, READYD, etc). host access external SP'ACE's arbitration logic output control signals, illustrated FIGURE Alternatively, control shared both host processor SP'ACE, illustrated FIGURE latter requires external logic, allows processor access directly full access speed RAM, rather than waiting SP'ACE handshake acknowledge output READY. FIGURE illustrates 8-bit buffered mode. This interface allows direct connection 8-bit microprocessors 8-bit microcontrollers. 16-bit buffered configuration, buffer limit BU-61582's words internal RAM. 8-bit mode, host accesses BU-61582's internal registers pair 8-bit registers embedded SP'ACE interface. 8-bit interface further configured three strappable inputs: ZEROWAIT, POLARITY_SEL, TRIGGER_SEL. connecting ZEROWAIT logic "0", BU-61582 interfaced with minimal "glue" logic 8-bit microcontrollers, such Intel 8051 series, that have Acknowledge type handshake input. programmable inputs POLARITY_SEL TRIGGER_SEL allow BU-61582 accommodate different byte ordering conventions "A0" logic sense utilized different 8-bit processor families.
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BU-61582 M-08/04-0
PROCESSOR INTERFACE TIMING
FIGURES illustrate timing host processor access SP'ACE's internal registers 16-bit, nonzero wait buffered mode. FIGURE illustrates 16-bit, buffered, nonzero wait state mode read cycle timing while FIGURE shows 16-bit, buffered, nonzero wait state mode write cycle timing. During transfer cycle, signals STRB SELECT must sampled rising edge system clock request access BU-61582's internal shared RAM. transfer will begin first rising system clock edge when SELECT STRBD 1553 protocol/memory management unit accessing internal RAM. falling edge output signal IOEN indicates start transfer. SP'ACE latches signals MEM/REG RD/WR internally first falling clock edge after start transfer cycle. address inputs latch internally first rising clock edge after signal IOEN goes low. Note that address lines latched time using ADDR_LAT input signal. output signal READYD will asserted third it's internal read) rising system clock edge after IOEN goes low. assertion READYD indicates host processor that read data available parallel data bus, that write data been stored. this time, should bring signal STRBD high, completing transfer cycle.
SP'ACE's internal memory bus) track state address inputs A00. When low, internal memory remains latched state just prior falling edge ADDR_LAT.
MISCELLANEOUS
SELF-TEST BU-61582 products incorporate several self-test features. These features include on-line wraparound self-test messages modes, off-line wraparound self-test mode, several other internal self-test features.
BC/RT on-line loop test involves wraparound test encoder/decoder transceiver. off-line self-test involves encoder/decoder, transceiver. These tests entail checking received version every transmitted word validity (sync, encoding, count, parity) checking received version last transmitted word bit-by-bit comparison with encoded word. loopback test also fails there timeout internal transmitter watchdog timer. failure loop test results setting message's Block Status Word and, enabled, will result interrupt request. With appropriate host processor software, offline test able exercise parallel serial data paths, encoder, decoder, substantial portion protocol memory management logic. There additional built-in self-test features, involving three configuration register bits eight test registers. This allows test approximately J-Rad chip's internal logic. These tests include encoder test, decoder test, register test, protocol test, test fail-safe (transmitter timeout) timer. There also test mode. test mode, host processor emulate arbitrary activity 1553 buses writing pair test registers. test mode operated conjunction with Word Monitor mode facilitate end-to-end selftests.
ADDRESS LATCH TIMING
FIGURE illustrates operation timing address input latches buffered interface mode. transparent mode, address buffers always transparent. Since transparent mode requires external buffers, external address latches would required demultiplex multiplexed address bus. buffered mode however, SP'ACE's internal address latches used perform demultiplexing function. ADDR_LAT input signal controls address latch operation. When ADDR_LAT high, outputs latch (which drive
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BU-61582 M-08/04-0
-12V/-15V CLOCK OSCILLATOR
D15-D0 TX/RXA A15-A12 A11-A0 TX/RXA
ADDRESS LATCH (NOTE ADDR_LAT
TRANSPARENT/BUFFERED 16/8_BIT TRIGGER_SEL
(NOTE
TX/RXB
MSB/LSB POLARITY_SEL
HOST
(NOTE
ZERO_WAIT
SP'ACE
TX/RXB
SELECT ADDRESS DECODER MEM/REG
RD/WR STROBE ACKNOWLEDGE
(NOTE
RD/WR STRBD READYD TAG_CLK RTAD4-RTAD0 RTADP ADDRESS, PARITY
RESET
MSTCLR
SSFLAG/EXT_TRIG
INTERRUPT REQUEST
NOTES:
ADDRESS LATCH SIGNAL PROVIDED PROCESSORS WITH MULTIPLEXED ADDRESS/DATA BUSES. POLARITY_SEL "1", RD/WR HIGH READ, WRITE. POLARITY_SEL "0", RD/WR READ, HIGH WRITE. ZERO_WAIT SHOULD STRAPPED LOGIC NON-ZERO WAIT INTERFACE LOGIC ZERO WAIT INTERFACE. ACKNOWLEDGE PROCESSOR INPUT ONLY NON-ZERO WAIT TYPE INTERFACE.
FIGURE 16-BIT BUFFERED MODE
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-12V/-15V CLOCK OSCILLATOR
D15-D0
'245
D15-D0 TX/RXA TX/RXA IOEN DTREQ DTGRT MEMWR MEMOE
A15-A0 '244 ADDRESS DECODER A15-A0 TX/RXB MEMENA-IN
HOST
MEMENA-OUT TRANSPARENT/BUFFERED
SP'ACE
TX/RXB
SELECT ADDRESS DECODER MEM/REG
RD/WR STROBE ACKNOWLEDGE STRBD READYD TAG_CLK RESET MSTCLR RTAD4-RTAD0 RTADP ADDRESS, PARITY
SSFLAG/EXT_TRIG
INTERRUPT REQUEST
FIGURE 16-BIT TRANSPARENT MODE
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CS-L
CS-R
MEMENA-OUT
WR-L DUAL PORT
WR-R
MEMWR
OE-L BUSY-L
OE-R BUSY-R
MEMOE
D15-D0
D15-D0
ADDRESS
A15-A0
RD/WR
RD/WR
MEMENA-IN MEM/REG
HOST
1553 SELECT ADDRESS DECODER 1553 SELECT A4-A0
'245
SP'ACE
IOEN
A4-A0 '244
DTREQ DTGRT
DTACK SELECT
DATA STROBE
STRBD
TRANSPARENT/BUFFERED READY READYD RESET MSTCLR
INTERRUPT REQUEST
FIGURE 16-BIT TRANSPARENT MODE USING DUAL PORT
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-12V/-15V CLOCK OSCILLATOR
D15-D0 RD/WR
D15-D0 TX/RXA RD/WR DTREQ DTGRT DTACK MEMWR MEMOE TX/RXA
A15-A0
A15-A0
TX/RXB
HOST
ADDRESS DECODER
MEMENA-IN
SP'ACE
TX/RXB
MEMENA-OUT
SELECT ADDRESS DECODER TRANSPARENT/BUFFERED MEM/REG
STROBE ACKNOWLEDGE
STRBD READYD TAG_CLK RTAD4-RTAD0 RTADP ADDRESS, PARITY
RESET
MSTCLR SSFLAG/EXT_TRIG
INTERRUPT REQUEST
FIGURE 16-BIT DIRECT MEMORY ACCESS (DMA) MODE
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-12V/-15V CLOCK OSCILLATOR D15-D0 RD/WR
D15-D0 RD/WR TX/RXA MEMWR MEMOE TX/RXA
DTREQ DTGRT DTACK TX/RXB A15-A0 A15-A0 MEMENA-IN MEMENA-OUT MEM/REG 1553 SELECT ADDRESS DECODER 1553 SELECT TRANSPARENT/BUFFERED SELECT
HOST
SP'ACE
TX/RXB
STROBE ACKNOWLEDGE
STRBD READYD TAG_CLK RTAD4-RTAD0 RTADP ADDRESS, PARITY
RESET
MSTCLR SSFLAG/EXT_TRIG
INTERRUPT REQUEST
FIGURE 16-BIT MODE WITH EXTERNAL LOGIC REDUCE PROCESSOR ACCESS TIME EXTERNAL
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CLOCK OSCILLATOR D7-D0
(NOTE
-12V/-15V
D15-D8
D7-D0 TX/RXA A15-A12 A12-A0 A12-A1 ADDRESS LATCH (NOTE A11-A0 ADDR_LAT MSB/LSB 16/8_BIT TRANSPARENT/BUFFERED TX/RXA
(NOTE
POLARITY_SEL
TX/RXB
(NOTE
ZERO_WAIT
HOST
(NOTE
TRIGGER_SEL
SP'ACE
TX/RXB
SELECT ADDRESS DECODER MEM/REG
RD/WR STROBE ACKNOWLEDGE
(NOTE
RD/WR STRBD READYD TAG_CLK RTAD4-RTAD0 RTADP ADDRESS, PARITY
RESET
MSTCLR
SSFLAG/EXT_TRIG
INTERRUPT REQUEST
NOTES:
D7-D0 CONNECTS BOTH D15-D8 D7-D0. ADDRESS LATCH SIGNAL PROVIDED PROCESSORS WITH MULTIPLEXED ADDRESS/DATA BUFFERS. POLARITY_SEL "1", THEN MSB/LSB SELECTS MOST SIGNIFICANT BYTE WHEN LOW, LEAST SIGNIFICANT BYTE WHEN HIGH. POLARITY_SEL "0", THEN MSB/LSB SELECTS LEAST SIGNIFICANT BYTE WHEN LOW, MOST SIGNIFICANT BYTE WHEN HIGH. ZERO WAIT SHOULD STRAPPED LOGIC NON-ZERO WAIT INTERFACE LOGIC ZERO WAIT INTERFACE. OPERATION TRIGGER_SELECT INPUT FOLLOWS: NON-ZERO WAIT INTERFACE (ZERO WAIT "1"): TRIGGER_SEL "1", THEN INTERNAL 16-BIT TRANSFERS TRIGGERED MOST SIGNIFICANT BYTE TRANSFER READ ACCESSES LEAST SIGNIFICANT BYTE TRANSFER WRITE ACCESSES. TRIGGER_SEL "0", THEN INTERNAL 16-BIT TRANSFERS TRIGGERED LEAST SIGNIFICANT BYTE TRANSFER READ ACCESSES MOST SIGNIFICANT BYTE TRANSFER WRITE ACCESSES. ZERO WAIT INTERFACE (ZERO WAIT "0"): TRIGGER_SEL "1", THEN INTERNAL 16-BIT TRANSFERS TRIGGERED LEAST SIGNIFICANT BYTE TRANSFER, BOTH READ WRITE ACCESSES. TRIGGER_SEL "0", THEN INTERNAL 16-BIT TRANSFERS TRIGGERED MOST SIGNIFICANT BYTE TRANSFER, BOTH READ WRITE ACCESSES. ACKNOWLEDGE PROCESSOR INPUT ONLY NON-ZERO WAIT TYPE INTERFACE.
FIGURE 8-BIT BUFFERED MODE
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SELECT
MSB/LSB
INPUT SIGNALS
MEM/REG
A15-A0
ADDRESS_LAT
SELECT
INTERNAL VALUES
MSB/LSB
MEM/REG
A15-A0
Notes FIGURE associated table. Applicable buffered mode only. Address SELECT MEM/REG latches always transparent transparent mode operation. Latches transparent when ADDR_LAT high. Internal values update when ADDR_LAT low. MSB/LSB input signal applicable 8-bit mode only (16/8 input logic "0"). MSB/LSB input "don't care" 16-bit operation.
TABLE FIGURE ADDRESS LATCH TIMING
ADDR_LAT pulse width ADDR_LAT high delay internal signals valid Propagation delay from external input signals internal signals valid Input setup time prior falling edge ADDR_LAT Input hold time following falling edge ADDR_LAT DESCRIPTION UNITS
FIGURE ADDRESS LATCH TIMING
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CLOCK
SELECT
(Note 2,7)
STRBD
(Note
(Note 3,4,7)
RD/WR
(Note 4,5)
IOEN
(Note 2,6)
READYD
(Note
A15-A0
VALID
(Note
D15-D0
(Note
FIGURE READING (SHOWN 16-BIT, BUFFERED, NONZERO WAIT MODE)
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VALID
MEM/REG
VALID
BU-61582 M-08/04-0
TABLE FIGURE READING REGISTERS (SHOWN 16-BIT, BUFFERED, NONZERO WAIT MODE)
DESCRIPTION SELECT STRBD setup time prior clock rising edge SELECT STRBD delay IOEN (uncontended access MHz) SELECT STRBD delay IOEN (contended access MHz) SELECT STRBD delay IOEN (uncontended access MHz) SELECT STRBD delay IOEN (contended access MHz) MEM/REG, RD/WR setup time following SELECT STRBD low(@ MHz) MEM/REG, RD/WR setup time following SELECT STRBD low(@ MHz) Address valid setup time following SELECT STRBD MHz) Address valid setup time following SELECT STRBD MHz) CLOCK rising edge delay IOEN falling edge SELECT hold time following IOEN falling MEM/REG, RD/WR setup time prior CLOCK falling edge MEM/REG, RD/WR hold time prior CLOCK falling edge Address valid setup time prior CLOCK rising edge Address hold time following CLOCK rising edge IOEN falling delay READYD falling (reading MHz) IOEN falling delay READYD falling (reading MHz) IOEN falling delay READYD falling (reading registers MHz) IOEN falling delay READYD falling (reading registers MHz) Output Data valid prior READYD falling MHz) Output Data valid prior READYD falling MHz) CLOCK rising edge delay READYD falling READYD falling STRBD rising release time STRBD rising edge delay IOEN rising edge READYD rising edge Output Data hold time following STRBD rising edge STRBD rising delay output Data tri-state STRBD high hold time from READYD rising 437.5 583.3 187.5 107.5 5.24 128.3 6.97 UNITS NOTE REFERENCE note note note note note note note note note note notes notes note notes notes notes notes
Notes FIGURE associated table. 16-bit buffered configuration, inputs TRIGGER_SEL MSB/LSB connected GND. nonzero wait interface ZEROWAIT, must connected logic "1". SELECT STRBD tied together. IOEN goes first rising edge when SELECT STRBD sampled (satisfying BU-61582's protocol/memory management logic accessing internal RAM. When this occurs, IOEN goes low, starting transfer cycle. After IOEN goes low, SELECT released high. MEM/REG must presented high memory access, register access. MEM/REG RD/WR buffered transparently until first falling edge after IOEN goes low. After this edge, MEM/REG RD/WR become latched internally. logic sense RD/WR diagram assumes that POLARITY_SEL connected logic "1". POLARITY_SEL connected logic "0", RD/WR must asserted read. timing IOEN, READYD D15-D0 assumes load. loading above validity IOEN, READYD, D15D0 delayed additional 0.14 ns/pf typ, 0.28 ns/pf max. Timing A15-A0 assumes ADDR-LAT connected logic "1". Refer Address Latch timing additional details Internal accessed through Registers accessed through address A15-A0 internally buffered transparently until first rising edge after IOEN, goes low. After this edge, A15-A0 become latched internally.
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BU-61582 M-08/04-0
CLOCK
SELECT
(Note 2,7)
STRBD
(Note
MEM/
(Note 3,4,7)
VALID
(Note 4,5)
IOEN
(Note 2,6)
READYD
(Note
VALID
A15-A0
(Notes 7,8,9)
VALID
(Notes
D15-D0
FIGURE WRITING (SHOWN 16-BIT, BUFFERED, NONZERO WAIT MODE)
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BU-61582 M-08/04-0
TABLE FIGURE WRITING REGISTERS (SHOWN 16-BIT, BUFFERED, NONZERO WAIT MODE)
SYMBOL DESCRIPTION SELECT STRBD setup time prior CLOCK rising edge SELECT STRBD delay IOEN (uncontended access MHz) SELECT STRBD delay IOEN (contended access MHz) SELECT STRBD delay IOEN (uncontended access MHz) SELECT STRBD delay IOEN (contended access MHz) MEM/REG RD/WR setup time following SELECT STRBD MHz) MEM/REG RD/WR setup time following SELECT STRBD MHz) Address valid setup following SELECT STRBD MHz) Address valid setup following SELECT STRBD MHz) Input Data valid setup following SELECT STRBD MHz) Input Data valid setup following SELECT STRBD MHz) CLOCK rising edge delay IOEN falling edge SELECT hold time following IOEN falling edge MEM/REG, RD/WR setup time prior CLOCK falling edge MEM/REG, RD/WR hold time following CLOCK falling edge Address valid setup prior CLOCK rising edge Input Data valid setup prior CLOCK rising edge Address hold time following CLOCK rising edge Input Data valid hold time following CLOCK rising edge IOEN falling delay READYD falling MHz) IOEN falling delay READYD falling MHz) CLOCK rising edge delay READYD falling edge READYD falling STRBD rising release time STRBD rising delay IOEN rising, READYD rising STRBD high hold time following READYD rising 187.5 107.5 5.24 128.3 6.97 UNITS note note note note note notes notes NOTE REFERENCE note notes notes
Notes FIGURE associated table. 16-bit buffered configuration, inputs TRIGGER_SEL MSB/LSB connected GND. nonzero wait interface, ZEROWAIT must connected logic "1." SELECT STRBD tied together. IOEN goes first rising edge when SELECT STRBD sampled (satisfying BU-61582's protocol/memory management logic accessing internal RAM. When this occurs, IOEN goes low, starting transfer cycle. After IOEN goes low, SELECT released high. MEM/REG must presented high memory access, register access. MEM/REG RD/WR buffered transparently until first falling edge after IOEN goes low. After this edge, MEM/REG RD/WR become latched internally. logic sense RD/WR diagram assumes that POLARITY_SEL connected logic "1". POLARITY_SEL connected logic "0", RD/WR must asserted high read. timing IOEN READYD outputs assumes load. loading above validity IOEN READYD delayed additional 0.14 ns/pf typ, 0.28 ns/pf max. Timing A15-A0 assumes ADDR-LAT connected logic "1". Refer Address Latch timing additional details. Internal accessed through Registers accessed through address A15-A0 data D15-D0 internally buffered transparently until first rising edge after IOEN goes low. After this edge, A15-A0 become latched internally.
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TRANSFORMER CONSIDERATIONS BU-61582X3 (+5V ONLY VERSIONS)
selecting isolation transformers used BU61582X3 (+5V only) versions, there limitation maximum amount leakage inductance. this limit exceeded, transmitter rise fall times increase, possibly causing amplitude fall below minimum level required MILSTD-1553. addition, excessive leakage imbalance result transformer dynamic offset that exceeds 1553 specifications. maximum allowable leakage inductance measured follows: side transformer that connects Hybrid defined "primary" winding. side primary shorted primary center-tap, inductance should measured across "secondary" (stub side) winding. This inductance must less than Similarly, other side primary shorted primary center-tap, inductance measured across "secondary" (stub side) winding must also less than difference between these measurements "differential" leakage inductance. This value must less than Beta Transformer Technology Corporation (BTTC), subsidiary DDC, manufactures transformers variety mechanical configurations with required turns ratios 1:2.5 direct coupled, 1:1.79 transformer coupled. Table provides listing many these transformers. further information, contact BTTC 631-244-7393 www.bttc-beta.com.
TABLE BTTC TRANSFORMERS WITH BU-61582X3/X6
TRANSFORMER CONFIGURATION Single epoxy transformer, through-hole, 0.625" 0.625", 0.250" height Single epoxy transformer, through-hole, 0.625" 0.625", 0.220" height Single epoxy transformer, flat pack, 0.625" 0.625", 0.275" height Single epoxy transformer, surface mount, 0.625" 0.625", 0.275" height Single epoxy transformer, surface mount, hi-temp solder, 0.625" 0.625", 0.220" height. Single epoxy transformer, flat pack, 0.625" 0.625", 0.150" height Single epoxy transformer, surface mount, 0.625" 0.625", 0.150" height
Single epoxy transformer, through hole, transformer coupled only, 0.500" 0.350", 0.250" height.
BTTC PART B-3067 B-3226 B-3818 B-3231 B-3227 B-3819 LPB-5014 LPB-5015 B-3229 TST-9007 TST-9017 TST-9027 TLP-1205 TLP-1105 TLP-1005 DLP-7115 (see note HLP-6014 HLP-6015 DLP-7014 SLP-8007 SLP-8024
Dual epoxy transformer, twin stacked, 0.625" 0.625", 0.280" height Dual epoxy transformer, twin stacked, surface mount, 0.625" 0.625", 0.280" height Dual epoxy transformer, twin stacked, flat pack, 0.625" 0.625", 0.280" height Dual epoxy transformer, side side, through-hole, 0.930" 0.630", 0.155" height Dual epoxy transformer, side side, flat pack, 0.930" 0.630", 0.155" height Dual epoxy transformer, side side, surface mount, 0.930" 0.630", 0.155" height Dual epoxy transformer, side side, surface mount, 1.410" 0.750", 0.130" height Single metal transformer, hermetically sealed, flat pack, 0.630" 0.630", 0.175" height Single metal transformer, hermetically sealed, surface mount, 0.630" 0.630", 0.175" height
RECOMMENDED
Notes: DLP-7115 operates +105°C max.
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BU-61582 M-08/04-0
INTERFACE MIL-STD-1553
FIGURE illustrates interface from various versions SP'ACE series terminals 1553 bus. figure also indicates connections both direct (short stub) transformer (long stub) coupling, plus peak-to-peak voltage levels that appear various points (when transmitting). TABLE lists characteristics required isolation transformers various SP'ACE terminals, Beta Transformer Technology Corporation corresponding part number, (DESC) drawing number applicable). Beta Transformer Technology Corporation direct subsidiary DDC. both coupling configurations, isolation transformer transformer that interfaces directly SP'ACE component. transformer (long stub) coupling configuration, transformer that interfaces stub coupling transformer. turns ratio isolation transformer varies, depending upon peak-to-peak output voltage specific SP'ACE terminal. transmitter voltage each model BU-61582 varies directly function power supply voltage. turns ratios respective transformers will yield secondary voltage approximately volts peak-to-peak outer taps (used direct coupling) volts peak-to-peak inner taps (used stub coupling). accordance with MIL-STD-1553B, turns ratio coupling transformer 1.4. Both coupling configurations require isolation resistor series with each connecting 1553 bus; this protects against short circuit conditions transformers, stubs, terminal components.
TABLE ISOLATION TRANSFORMER GUIDE
SP'ACE PART NUMBER TURNS RATIO DIRECT XFORMER COUPLED COUPLED RECOMMENDED XFORMER PLUG-IN SURFACE MOUNT B-2387 M21038/27 -12, M21038/27 LPB-5002 LPB-5009 LPB-6002 LPB-6009 LPB-5001 LPB-5008 LPB-6001 LPB-6008 B-2388 M21038/27 -13, B-2334, M21038/27
BU-61582X1
1.41:1
BUS-25679, B-2203, M21038/27
1:0.83
BUS-29854
BU-61582X2 1.25:1 (Note
1:0.67 B-2204, M21038/27
Notes TABLE FIGURE Shown redundant buses that interface BU61582. Transmitted voltage level 1553 Vp-p min, Vp-p nominal, Vp-p max. Required tolerance isolation resistors Instantaneous power dissipation (when transmitting) approximately (typ), (max). Transformer numbering correct (e.g., BUS25679) transformers. Beta transformers (e.g., B-2203) QPL-21038-31 transformers (e.g., M21038/27-02), winding sense turns ratio mechanically same, with reversed numbering; therefore, necessary reverse pins pins Beta transformers (Note: transformer part numbers begin with BUS- prefix, while Beta transformer part numbers begin with prefix). B-2204, B-2388, B-2344 transformers have slightly different turns ratio direct coupled taps then turns ratio BUS-29854 direct coupled taps. They however, have same transformer coupled ratio. transformer coupled applications, either transformer used. transceiver BU-61582 designed work with 1:0.83 ratio direct coupled applications. direct coupled applications, 1.20:1 turns ration recommended, 1.25:1 used. 1.25:1 turns ratio will result slightly lower transmitter amplitude. (Approximately 3.6% lower) slight shift SP'ACE's receiver threshold.
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BU-61582 M-08/04-0
DIRECT COUPLED (SHORT STUB) 1.4:1
DATA
-15V
BU-61582X1 BU-61583X1
ISOLATION TRANSFORMER
TRANSFORMER COUPLED (LONG STUB) 1:1.4
0.75 0.75
ISOLATION TRANSFORMER
COUPLING TRANSFORMER
DIRECT COUPLED (SHORT STUB) 1:0.83
-12V
BU-61582X2 BU-61583X2
ISOLATION TRANSFORMER
TRANSFORMER COUPLED (LONG STUB) 1:0.67 1:1.4
0.75 0.75
ISOLATION TRANSFORMER
COUPLING TRANSFORMER
DIRECT COUPLED (SHORT STUB) 1:2.5
BU-61582X3 BU-61583X3 BU-61582X6 BU-61582X6
11.6
ISOLATION TRANSFORMER
TRANSFORMER COUPLED (LONG STUB) 1:1.79 1:1.4
0.75 0.75
11.6VPP
ISOLATION TRANSFORMER
COUPLING TRANSFORMER
FIGURE INTERFACE 1553
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TABLE SIGNAL DESCRIPTIONS, PROCESSOR/MEMORY INTERFACE CONTROL (15)
SIGNAL NAME TRANSPARENT/ BUFFERED STRBD SELECT MEM/REG RD/WR DESCRIPTION Used select between Transparent/ mode (when strapped logic Buffered mode (when strapped logic host processor interface. Strobe Data. Used with SELECT initiate control data transfer cycle between host processor BU-61582. Generally connected address decoder output select BU-61582 transfer to/from either register. tied STRBD Memory/Register. Generally connected either address line address decoder output. Selects between memory access MEM/REG register access MEM/REG Read/Write. host processor access, selects either reading writing. 16-bit buffered mode, polarity select logic (0), then RD/WR (logic read accesses high (logic write accesses. polarity select logic configuration interface mode other than 16-bit buffered mode, then RD/WR high (logic read accesses (logic write accesses.
IOEN READYD
Tri-state control external address data buffers. Generally needed buffered mode. When low, external buffers should enabled allow host processor access BU-61582's registers. Handshake output host processor. nonzero wait state read access, signals that data available read through nonzero wait state write cycle, signals completion data transfer register location. buffered zero wait state mode, active high output signal (following rising edge STRBD used indicate latching address data (write only) that internal transfer between address/data latches RAM/registers on-going. Interrupt request output. LEVEL/PULSE interrupt (bit Configuration Register low, negative pulse approximately width output INT. high, level interrupt request output will asserted INT. Data Transfer Request 16-bit/8-bit Transfer Mode Select. transparent mode, active output signal used request access processor interface (address, data, control buses). buffered mode, input signal used select between 16-bit data transfer mode (16/8 logic data transfer mode (16/8 logic Data Transfer Grant Most Significant Byte/Least Significant Byte. transparent mode, active input signal asserted, response DTREQ output, indicate that access processor buses been granted BU-61582. 8-bit buffered mode, input signal used indicate which byte being transferred (MSB LSB). POLARITY_SEL input controls logic sense MSB/LSB. (Note: only 8-bit buffered mode uses MSB/LSB.) description POLARITY_SEL signal. Data Transfer Acknowledge Polarity Select. transparent mode, active output signal used indicate acceptance processor interface response data transfer grant (DTGR). 16-bit buffered mode (TRANSPARENT/BUFFERED logic 16/8 logic input signal used control logic sense RD/WR signal. When POLARITY_SEL logic RD/WR must asserted high (logic read operation (logic write operation. When POLARITY_SEL logic RD/WR must asserted (logic read operation high (logic write operation. 8-bit buffered mode (TRANSPARENT/BUFFERED logic 16/8 logic input signal used control logic sense MSB/LSB signal. When POLARITY_SEL logic MSB/LSB must asserted (logic indicate transfer least significant byte high (logic indicate transfer most significant byte. When POLARITY_SEL logic MSB/LSB must asserted high (logic indicate transfer least significant byte (logic indicate transfer most significant byte. Memory Enable Output. Asserted during both host processor 1553 protocol/memory management memory transfer cycles. Used memory chip select (CS) signal external transparent mode.
DTREQ /16/8 DTGRT /MSB/LSB
DTACK (O)/ POLARITY_SEL
MEMENA-OUT
MEMENA-IN Memory Enable Input Trigger Select. transparent mode, MEMENA_IN active Chip Select (CS) input /TRIGGER_SEL internal shared RAM. When only using internal RAM, connect directly MEMENA_OUT. 8-bit buffered mode, input signal (TRIGGER_SEL) indicates order byte pairs transferred from BU-61582 host processor. This signal operation (can N/C) 16-bit buffered mode. 8-bit buffered mode, TRIGGER_SEL should asserted high (logic byte order both read operations write operations followed LSB. TRIGGER_SEL should asserted (logic byte order both read operations write operations followed MSB. MEMOE (O)/ ADDR_LAT MEMWR /ZERO_WAIT Memory Output Enable Address Latch. transparent mode, MEMOE output will used enable data outputs external read cycles (normally connected signal external chips). buffered mode, ADDR_LAT input will used configure internal address latches latched mode (when low) transparent mode (when high). Memory Write Zero Wait State. transparent mode, active output signal (MEMWR) will asserted during memory write transfers strobe data into internal external (normally connected signal external chips). buffered mode, input signal (ZERO WAIT) will used select between zero wait mode (ZERO WAIT= logic nonzero wait mode (ZERO WAIT logic
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BU-61582 M-08/04-0
TABLE SIGNAL DESCRIPTIONS, MISCELLANEOUS
SIGNAL NAME CLOCK MSTCLR INCMD 16MHz 12MHz) clock input. Master Clear. Negative true Reset input, normally asserted following power turn-on. Requires minimum 100ns negative pulse reset internal logic "power turn-on" state. Command. mode, asserted throughout processing cycle each message. mode Message Monitor mode, asserted following receipt Command Word kept until completion current message sequence. Word Monitor mode, goes following MONITOR START command, kept while monitor on-line, goes high following RESET command. Subsystem Flag External Trigger input. Remote Terminal mode, asserting this input will Subsystem Flag BU-61582's Status Word. SSFLAG input overrides logic respective (bit Configuration Register Controller mode, enabled external Start option (bit Configuration Register low-to-high transition this input will issue Start command, starting execution current frame. Word Monitor mode, enabled external trigger (bit Configuration Register low-to-high transition this input will issue monitor trigger. External Time Clock input. designated bits Configuration Register When used increments internal Time Register/Counter. used, should connected ground. DESCRIPTION
SSFLAG (I)/ EXT_TRIG
TAG_CLK
TABLE SIGNAL DESCRIPTIONS, ADDRESS
SIGNAL NAME RTAD4 (MSB) RTAD3 RTAD2 RTAD1 RTAD0 (LSB) RTADP Remote Terminal Address Inputs Remote Terminal Address Parity. Must provide parity with RTAD4-RTAD0 order respond nonbroadcast commands. DESCRIPTION
TABLE SIGNAL DESCRIPTIONS, POWER GROUND
SIGNAL NAME LOGIC LOGIC +5VA GNDA +5VB GNDB Logic Supply Logic Ground -15V(-12V) Supply Supply Transceiver Ground -15V(-12V) Supply Supply Transceiver Ground X1/X2* DESCRIPTION
Note: *Pin X1/X2, refer package option(X) Voltage Transceiver option ordering information. X1/X2 versions logic GND, GNDA GNDB internally connected.
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TABLE SIGNAL DESCRIPTIONS, 1553 ISOLATION TRANSFORMER INTERFACE
SIGNAL NAME TX/RX-A (I/O) TX/RX-A (I/O) TX/RX-B (I/O) TX/RX-B (I/O) X1/X2* DESCRIPTION Analog Transmit/Receive Input/Outputs. Connect directly 1553 isolation transformers.
Note: *Pin X1/X2, refer package option(X) Voltage Transceiver option ordering information.
TABLE SIGNAL DESCRIPTIONS, ADDRESS (16)
SIGNAL NAME (MSB) DESCRIPTION 16-bit bidirectional address bus. both buffered transparent modes, host accesses BU-61582 registers words internal through host performs register selection through buffered mode, A15-A0 inputs only. transparent mode, A15-A0 inputs during accesses drive outward (towards CPU) when 1553 protocol/memory management logic accesses external RAM. address drives outward only transparent mode when signal DTACK (indicating that 61582 control processor interface bus) IOEN high (indicating that this access). Most time, including imme12 diately after power turn-on RESET, A15-A0 outputs will their disabled (high impedance) state.
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TABLE SIGNAL DESCRIPTIONS, DATA (16)
SIGNAL NAME (MSB) DESCRIPTION 16-bit bidirectional data bus. This interfaces host processor internal registers words RAM. addition, transparent mode, this allows data transfers take place between internal protocol/memory man61 agement logic external RAM. Most time, outputs through their high impedance state. They drive outward buffered transparent mode when host reads internal registers. transparent mode, when protocol/memory management logic accessing (either reading writ59 ing) internal writing external RAM.
TABLE SIGNAL DESCRIPTIONS, TRANSMITTER/RECEIVERS (14)
SIGNAL NAME TX_INH_A_IN TX_INH_B_IN TX_INH_A_OUT TX_INH_B_OUT Transmitter inhibit inputs Channel Channel MIL-STD-1553 transmitters. normal operation, these inputs should connected logic "0". force shutdown Channel and/or Channel value logic should applied respective TX_INH input. Digital Transmit Inhibit outputs. Connect TX_INH_OUT inputs MIL-STD-1553 transceiver. Asserted high inhibit when transmitting respective bus. User Connections Digital manchester biphase receive data inputs. Connect directly corresponding outputs MILSTD-1553 MIL-STD-1773 transceiver. X1/X2* DESCRIPTION Digital manchester biphase transmit data outputs. Connect directly corresponding inputs MILSTD-1553 MIL-STD-1773 (fiber optic) transceiver.
Note: *Pin X1/X2, refer package option(X) Voltage Transceiver option ordering information.
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BU-61582 M-08/04-0
TABLE BU-61582 LISTING (70-PIN DIP, FLAT PACK)
RX-B RX-B SIGNAL NAME TX/RX-A TX/RX-A SELECT STRBD MEM/REG RD/WR MSTCLR LOGIC CLOCK_IN DTGRT/MSB/LSB SSFLAG/EXT_TRIG MEMENA_OUT MEMOE/ADDR_LAT MEMWR/ZERO_WAIT DTREQ/16/8 DTACK/POLARITY_SEL MEMENA_IN/TRIGGER_SEL TX/RX-B TX/RX-B TX_INH_OUT_A (Note TX_INH_OUT_B RTAD0 RTAD1 RTAD2 RTAD3 RTAD4 RTADP INCMD Logic TAG_CLK TRANSPARENT/BUFFERED READYD IOEN +5VA GNDA TX_INH_IN_A SIGNAL NAME (Note GNDB +5VB TX_INH_IN_B
Notes: X1/X2, refer package option(X) Voltage Transceiver option ordering information. -15V BU-61582X1 -12V BU-61582X2.
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BU-61582 M-08/04-0
0.215 (5.46) 0.180 ±0.010 (4.57 ±0.25) 0.100 (2.54)
1.900 (48.26)
0.400 (10.16)
0.600 (15.24)
BOTTOM VIEW
0.018 ±0.002 (0.46 ±0.05)
SIDE VIEW
0.100 (2.54) 0.050 (1.27) 1.700 (43.18) 1.900 (48.26)
INDEX DENOTES
1.000 (25.4)
VIEW
INDEX DENOTES
NOTES: DIMENSIONS INCHES (MILLIMETERS). PACKAGE MATERIAL: ALUMINA (AL2O3). LEAD MATERIAL: KOVAR, PLATED 150µ MINIMUM NICKEL, PLATED MINIMUM GOLD.
FIGURE BU-61582DX, 70-PIN CERAMIC MECHANICAL OUTLINE
Data Device Corporation www.ddc-web.com BU-61582 M-08/04-0
1.900 (48.26) 1.760 0.020 (44.70) 0.018 0.002 (0.46 0.05) CERAMIC PLACES) 0.035 (TYP) (0.89) 0.215 (5.46)
INDEX DENOTES
1.000 (25.4)
1.024 (26.0)
0.595 (TYP) (15.11) 0.405 (TYP) (10.29)
0.012 (0.31) 0.010 0.002 (0.254 0.051) 0.050 1.700 NONCUM NUMBERS ONLY 0.070 0.010 (1.78)
0.100 (2.54)
0.050 (TYP) (1.27)
VIEW
NOTES: DIMENSIONS INCHES (MILLIMETERS). PACKAGE MATERIAL: ALUMINA (AL2O3). LEAD MATERIAL: KOVAR, PLATED 150µ MINIMUM NICKEL, PLATED MINIMUM GOLD.
SIDE VIEW
FIGURE BU-61582FX, 70-PIN FLAT PACK CERAMIC MECHANICAL OUTLINE
Data Device Corporation www.ddc-web.com BU-61582 M-08/04-0
DENOTED INDEX MARK
1.000 (25.4)
0.018 ±0.002 (0.46 ±0.05)
VIEW
1.900 (48.26)
0.050 1.700 1.27 43.18) (TOL. NONCUM) 0.050 (1.27)
INDEX DENOTES
NUMBERS REF. ONLY 0.215 (5.461) 0.065 (1.651) 0.190 ±0.010 (4.826 ±0.254) 0.080 (2.032)
0.012 (0.305) 0.010 ±0.002 (0.254 ±0.051) 1.024 (26.0) 1.38 ±0.02 0.050 (1.27)
0.040 (1.016)
NOTES: (35.05 ±0.51) DIMENSIONS INCHES (MILLIMETERS). PACKAGE MATERIAL: ALUMINA (AL2O3). LEAD MATERIAL: KOVAR, PLATED 150µ MINIMUM NICKEL, PLATED MINIMUM GOLD.
FIGURE BU-61582GX, 70-PIN GULL LEAD CERAMIC MECHANICAL OUTLINE
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ORDERING INFORMATION
BU-61582XX-XXXX Supplemental Process Requirements: Pre-Cap Source Inspection 100% Pull Test 100% Pull Test Pre-Cap Source Inspection Date Code Date Code Pre-Cap Source Inspection Date Code 100% Pull Test Date Code, Pre-Cap Source Inspection 100% Pull Test Blank None Above Other Criteria: Process Requirements: Standard Processing, Burn-In MIL-PRF-38534 Compliant (notes (note MIL-PRF-38534 Compliant (notes with PIND Testing MIL-PRF-38534 Compliant (notes with Solder MIL-PRF-38534 Compliant (notes with PIND Testing Solder (note with PIND Testing (note with Solder (note with PIND Testing Solder Standard Processing with Solder Dip, Burn-In Temperature Grade/Data Requirements: -55°C +125°C -40°C +85°C +70°C -55°C +125°C with Variables Test Data -40°C +85°C with Variables Test Data +70°C with Variables Test Data Voltage Transceiver Option: Transceiver +5/-15 +5/-12 +5/+5 +5/+5 with Transmit Inhibit (TX_INHIBIT) Package: Flat Pack Gull Leads (Above "Process Requirements" must include solder dip.) Product Type: 61582 70-Pin BC/RT/MT with Internal 61583 70-Pin BC/RT/MT with Internal with Address Latch
Notes: MIL-PRF-38534 Compliant products include hours burn-in 100% non-destruct pull-test. (See Table Standard Processing with burn-in full temperature (-55°C +125°C) test. MIL-PRF-38534 product grading designated with following dash numbers: Class -11X, 13X, 14X, 15X, 41X, 43X, 44X, Class -21X, 23X, 24X, 25X, 51X, 53X, 54X, Class -31X, 33X, 34X, 35X, 81X, 83X, 84X,
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BU-61582 M-08/04-0
information this data sheet believed accurate; however, responsibility assumed Data Device Corporation use, license rights granted implication otherwise connection therewith. Specifications subject change without notice. Please visit site www.ddc-web.com latest information.
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ERED
DATA DEVICE CORPORATION REGISTERED 9001 FILE A5976
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SPACE LEVEL MIL-STD-1553 BC/RT/MT ADVANCED COMMUNICATION ENGINE (SP'AC

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