Full militarized RM5261 microprocessor Dual Issue superscalar micropro

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

Full militarized RM5261 microprocessor Dual Issue superscalar micropro

Datasheet Thumbnail

Top Searches for this datasheet

5261 64-Bit Superscaler Microprocessor
Full militarized RM5261 microprocessor Dual Issue superscalar microprocessor issue integer floating-point instruction cycle
133,
High-performance floating point unit: MFLOPS
cycle repeat rate common single precision operations some double precision operations cycle repeat rate double precision multiply double precision combined multiply-add operations Single cycle repeat rate single precision combined multiplyadd operation
Single
150, 200, operating frequencies Consult Factory latest speeds Dhrystone MIPS SPECInt95 7.3, SPECfp95
Pinout compatible with popular RM5260 High performance system interface compatible with RM5260, 5270, RM5271, RM7000, R4600, R4700 R5000
multiplexed system address/data optimum price/ performance High performance write protocols maximize uncached write bandwidth Supports clock divisors 2.5, 3.5, 4.5, IEEE 1149.1 JTAG boundary scan
64-bit
MIPS instruction
Floating
point multiply-add instruction increases performance signal processing graphics applications Conditional moves reduce branch frequency Index address modes (register register)
Embedded application enhancements
Specialized
Integrated on-chip caches
32KB 32KB
integer Multiply-Accumulate instruction operand multiply instruction cache locking Optional dedicated exception vector interrupts
instruction associative data associative Virtually indexed, physically tagged Write-back write-through page basis Pipeline restart first double data cache misses
Fully static CMOS design with power down logic
reduced power mode with WAIT instruction Watts typical power 200MHz 2.5V core with 3.3V IO's
Standby
208-lead CQFP, cavity-up package (F17) 208-lead CQFP, inverted footprint (F24), Intended duplicate commercial footprint 179-pin package (Future Product) (P10)
Integrated memory management unit
Fully
associative joint (shared translations) dual entries pages Variable page size (4KB 16MB increments)
Block Diagram
Preliminary
eroflex Circuit Technology RISC TurboEngines Future SCD5261 12/22/98
DESCRIPTION
Aeroflex ACT5261 highly integrated superscalar microprocessor that implements superset MIPS Instruction Architecture(ISA). high performance 64-bit integer unit, high throughput, fully pipelined 64-bit floating point unit, operating system friendly memory management unit with 48-entry fully associative TLB, KByte 2-way associative instruction cache, KByte 2-way associative data cache, high-performance 64-bit system interface. ACT5261 issue both integer floating point instruction same cycle. ACT5261 ideally suited high-end embedded control applications such internetworking, high performance image manipulation, high speed printing, visualization.
Integer Unit
Like ACT5260, ACT5261 implements MIPS Instruction Architecture, therefore fully upward compatible with applications that processors implementing earlier generation MIPS I-III instruction sets. Additionally, ACT5261 includes implementation specific instructions found baseline MIPS that useful embedded market place. Described detail RM5261 datasheet, these instructions integer multiply-accumulate 3-operand integer multiply. ACT5261 integer unit includes thirty-two general purpose 64-bit registers, load/store architecture with single cycle operations (add, sub, logical, shift) autonomous multiply/ divide unit. Additional register resources include: HI/LO result registers two-operand integer multiply/divide operations, program counter(PC).
HARDWARE OVERVIEW
ACT5261 offers high-level integration targeted high-performance embedded applications. elements ACT5261 briefly described below.
Register File
ACT5261 thirty-two general purpose registers with register location hard wired zero. These registers used scalar integer operations address calculation. register file read ports write port fully bypassed minimize operation latency pipeline.
Superscalar Dispatch
ACT5261 efficient asymmetric superscalar dispatch unit which allows issue integer instruction floating-point computation instruction simultaneously. With respect superscalar issue, integer instructions include alu, branch, load/store, floating-point load/ store, while floating-point computation instructions include floating-point add, subtract, combined multiply-add, converts, etc. combination with high throughput fully pipelined floating-point execution unit, superscalar capability ACT5261 provides unparalleled price/performance computationally intensive embedded applications.
ACT5261 consists integer adder/ subtractor, logic unit, shifter. adder performs address calculations addition arithmetic operations, logic unit performs logical zero shift data moves, shifter performs shifts store alignment operations. Each these units optimized perform operations single processor cycle.
Registers
Like MIPS processors, ACT5261 simple, clean user visible state consisting general purpose registers, special purpose registers integer multiplication division, program counter, condition code bits. additional Detail Information regarding operation Quantum Effect Design (QED) RISCMarkRM 5261TM, 64-Bit Superscalar Microprocessor latest datasheet (Revision July 1998).
Pipeline
integer operations, loads, stores, other non-floating-point operations, ACT5261 uses simple 5-stage pipeline also found RM52xx family, 4600, R4700, R5000. addition this standard pipeline, ACT5261 uses extended seven stage pipeline floating-point operations. Like ACT5260, ACT5261 does virtual physical translation parallel with cache access.
Aeroflex Circuit Technology
SCD5261 12/22/98 Plainview (516) 694-6700
Package Information "F17" CQFP Leads
1.131 (28.727) 1.109 (28.169)
.0236 (.51) .0158 (.49)
.010R .010R .015 (.381) .009 (.229) .130 (3.302) 0°±5° .100 (2.540) .080 (2.032) .035 (.889) .025 (.635) .009 (.253) .007 (.178)
1.009 (25.63) .9998 (25.37) Spaces .0197 Spaces .50)
Detail
Chamfer
Detail
.960 (24.384)
.055 (1.397)
.115 (2.921)
.005 (.127) .008 (.258)
1.331 (33.807) 1.269 (32.233)
.055 (1.397) .045 (1.143)
Units: Inches (Millimeters)
Note: rotation opposite QEDs PQUAD cavity-up construction.
Future Package "P10" Pins (Advanced)
Bottom View
Side View
.100
1.700 1.840 1.880
.018
1.700 1.840 1.880
Aeroflex Circuit Technology
.050 .221
SCD5261 12/22/98 Plainview (516) 694-6700
ACT5261 Microprocessor CQFP Pinouts "F17"
Aeroflex Circuit Technology
Function (3.3V) (3.3V) SysAD4 SysAD36 SysAD5 SysAD37 (2.5V) SysAD6 SysAD38 (3.3V) SysAD7 SysAD39 SysAD8 SysAD40 (2.5V) SysAD9 SysAD41 (3.3V) SysAD10 SysAD42 SysAD11 SysAD43 (2.5V) SysAD12 SysAD44 (3.3V) SysAD13 SysAD45 SysAD14 SysAD46 (2.5V) SysAD15 SysAD47 (3.3V) ModeClock JTDO JTDI JTCK JTMS (3.3V)
Function (3.3V) ModeIn RdRdy* WrRdy* ValidIn* ValidOut* Release* VccP VssP SysClock (2.5V) (3.3V) (2.5V) SysCmd0 SysCmd1 SysCmd2 SysCmd3 (3.3V) SysCmd4 SysCmd5 (3.3V) SysCmd6 SysCmd7 SysCmd8 SysCmdP (2.5V) (2.5V) (3.3V) Int0* Int1* Int2* Int3* Int4* Int5* (3.3V)
Function (3.3V) NMI* ExtRqst* Reset* ColdReset* VccOK BigEndian (3.3V) SysAD16 SysAD48 (2.5V) SysAD17 SysAD49 SysAD18 SysAD50 (3.3V) SysAD19 SysAD51 (2.5V) SysAD20 SysAD52 SysAD21 SysAD53 (3.3V) SysAD22 SysAD54 (2.5V) SysAD23 SysAD55 SysAD24 SysAD56 (3.3V) SysAD25 SysAD57 (2.5V) SysAD26 SysAD58 SysAD27 SysAD59 (3.3V)
Function (3.3V) SysAD28 SysAD60 SysAD29 SysAD61 (2.5V) SysAD30 SysAD62 (3.3V) SysAD31 SysAD63 SysADC2 SysADC6 (2.5V) SysADC3 SysADC7 (3.3V) SysADC0 SysADC4 (2.5V) SysADC1 SysADC5 SysAD0 SysAD32 (3.3V) SysAD1 SysAD33 (2.5V) SysAD2 SysAD34 SysAD3 SysAD35 (3.3V) (3.3V)
SCD5261 12/22/98 Plainview (516) 694-6700
CIRCUIT TECHNOLOGY
Sample Ordering Information
Part Number ACT- 5261PC-133F17I ACT- 5261PC-150F17C ACT- 5261PC-200F17T ACT-5261PC-250F17M Screening Industrial Temperature Commercial Temperature Military Temperature Military Screening Speed (MHz) Package Lead CQFP Lead CQFP Lead CQFP Lead CQFP
Part Number Breakdown
ACT- 5261
Aeroflex Circuit Technology
Base Processor Type Cache Style
Primary Cache
Screening
Commercial Temp, +70°C Industrial Temp, -40°C +85°C Military Temp, -55°C +125°C Military Temp, -55°C +125°C, Screened MIL-PRF-38534 Compliant/SMD applicable Package Type Size
Maximum Pipeline Freq.
133MHz 150MHz 200MHz 250MHz 266MHz (Future Option)
Surface Mount Package 1.120" Lead CQFP 1.120" Inverted Lead CQFP Thru-Hole Package 1.86"SQ pins with shoulder (Advanced)
Screened individual test methods MIL-STD-883
Specifications subject change without notice.
Aeroflex Circuit Technology South Service Road Plainview York 11803 www.aeroflex.com/act1.htm
Aeroflex Circuit Technology
Telephone: (516) 694-6700 FAX: (516) 694-6715 Toll Free Inquiries: (800) 843-1553 E-Mail: sales-act@aeroflex.com
SCD5261 12/22/98 Plainview (516) 694-6700

Full militarized RM5261 microprocessor Dual Issue superscalar micropro

Top Searches for this datasheet

Other recent searches