4519G Sound Processor Digital Analog Surround Systems Edition Oct
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4519G Sound Processor Digital Analog Surround Systems
Edition Oct. 2000 6251-512-1PD
4519G
Contents Page Section 1.1. 1.2. 2.1. 2.2. 2.3. 2.4. 2.5. 2.5.1. 2.6. 2.6.1. 2.6.1.1. 2.6.1.2. 2.6.1.3. 2.6.1.4. 2.6.2. 2.6.3. 2.6.3.1. 2.6.3.2. 2.6.3.3. 2.6.3.4. 2.6.4. 2.7. 2.7.1. 2.7.2. 2.8. 2.8.1. 2.8.2. 2.8.3. 2.8.4. 2.9. 2.10. 3.1. 3.1.1. 3.1.2. 3.1.3. 3.1.4. 3.1.5. 3.1.5.1. 3.1.5.2. 3.1.5.3. 3.1.5.4. 3.2. Title Introduction Features 4519G Application Fields 4519G Functional Description Architecture 4519G Family Preprocessing Input Signals Selection Internal Processed Surround Signals Source Selection Output Channel Matrix Audio Baseband Processing Main Outputs Surround Processing Surround Processing Mode Decoder Matrix Surround Reproduction Center Modes Useful Combinations Surround Processing Modes Examples Application Tips using 3D-PANORAMA Sweet Spot Clipping Loudspeaker Requirements Cabinet Requirements Input Output Levels Dolby Surround Logic SCART Signal Routing SCART Select Stand-by Mode Interfaces Synchronous I2S-Interface(s) Asynchronous I2S-Interface Multichannel I2S-Output Asynchronous Multichannel I2S-Input Digital Control Pins Clock Oscillator Crystal Specifications Control Interface Interface Device Subaddresses Internal Hardware Error Handling Description CONTROL Register Protocol Description Proposals General 4519G Telegrams Symbols Write Telegrams Read Telegrams Examples Start-Up Sequence: Power-Up Controlling
Micronas
4519G
Contents, continued Page Section 3.3. 3.3.1. 3.3.2. 3.3.2.1. 3.3.2.2. 3.3.2.3. 3.3.2.4. 3.4. 3.5. 3.5.1. 4.1. 4.2. 4.3. 4.4. 4.5. 4.6. 4.6.1. 4.6.2. 4.6.2.1. 4.6.2.2. 4.6.2.3. 4.6.3. 4.6.3.1. 4.6.3.2. 4.6.3.3. 4.6.3.4. 4.6.3.5. 4.6.3.6. 4.6.3.7. 4.6.3.8. 5.1. 5.2. Title 4519G Programming Interface User Registers Overview Description User Registers Write Registers Subaddress 10hex Read Registers Subaddress 11hex Write Registers Subaddress 12hex Read Registers Subaddress 13hex Programming Tips Examples Minimum Initialization Codes Micronas Dolby Digital chipset (with 3528E) Specifications Outline Dimensions Connections Short Descriptions Descriptions Configurations Circuits Electrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions General Recommended Operating Conditions Analog Input Output Recommendations Crystal Recommendations Characteristics General Characteristics Digital Inputs, Digital Outputs Reset Input Power-Up I2C-Bus Characteristics I2S-Bus Characteristics Analog Baseband Inputs Outputs, AGNDC Power Supply Rejection Analog Performance Appendix Application Information Phase Relationship Analog Outputs Application Circuit Data Sheet History
License Notice: "Dolby Logic" "Dolby Digital" trademarks Dolby Laboratories. Supply this implementation Dolby Technology does convey license imply right under patent, other industrial intellectual property right Dolby Laboratories, this implementation finished end-user ready-to-use final product. Companies planning this implementation products must obtain license from Dolby Laboratories Licensing Corporation before designing such products.
Micronas
4519G
Sound Processor Digital Analog Surround Systems hardware software description this document valid 4519G version following versions.
application together with Dolby Digital decoder 3528E, eight channels (left, right, surround left, surround right, center, subwoofer, Logic encoded left, Logic encoded right) processed 4519G. Similar multichannel input interface, provided with 8-channel output interface, which connected 44x0G. Therefore channels routed each output both ICs. baseband processing including e.g. balance, bass, treble, loudness performed fixed sample rate kHz. Fig. shows simplified functional block diagram 4519G. 4519G pin-compatible members 34xx family. This speeds development customers using MSPs. software interface 4519G also largely same members family. produced submicron CMOS technology available PQFP80, PLQFP64 PSDIP64 packages.
Introduction 4519G processor designed part Micronas chip digital analog Surround Systems Dolby Digital, MPEG Audio, Dolby ProLogic. combination 3528E, 4519G, 44x0G complete channel Dolby Digital decoder playback solution, while 4519G 44x0G alone, represent complete Dolby Surround Logic system. 4519G receives incoming data highly flexible interfaces. three input interfaces configured three asynchronous inputs synchronous asynchronous interface. latter case, asynchronous interface allows reception channels with arbitrary sample rate ranging from kHz. synchronization performed means adaptive high-quality sample rate converter.
I2S1
Prescale
Main Sound Processing
Main Subwoofer
I2S2
Source Select
(2.8-channel)
Sound Processing
(8-channel) SCART Output Select SCART1
SCART1 SCART2 SCART3 SCART4 MONO
ProLogic processing
SCART2
Fig. 1-1: Simplified block diagram 4519G
Micronas
4519G
1.1. Features 4519G 8-channel asynchonous input interface (multichannel mode) synchronous input channels (e.g. ADR) asynchronous two-channel input interfaces Main channel with balance, bass, treble, loudness, volume 5-band graphic equalizer Main channel Dolby Surround Logic Adaptive Matrix Micronas Effect Matrix Micronas "3D-Panorama" virtualizer compliant "Virtual Dolby Surround" technology Micronas Panorama sound mode Surround sound loudspeakers) Noise Generator Spatial Effect Surround 30-ms Surround delay Surround matrix control: Adaptive/Passive/Effect Center mode control: Normal/Phantom/Wide/Off Surround reproduction control: Rear speaker, Front speaker, Panorama, 3D-Panorama digital input/output pins controlled Fig. shows typical Dolby Digital application using 4519G, 4450G, 3528E.
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4519G
1.2. Application Fields 4519G
S/PDI1 AC-3, MPEG other Format S/PDI2 Input Buffer Deemphasis
S/PDIF
S/PDIF
PCM-Format (Lt/Rt Lo/Ro) Loop-through (e.g. DTS) Post Processing Delay Lines
SPDO
MPEG
SID* SII* SIC*
AC-3
SOD3 SOD2 SOD1
Multipl.
I2S-In: Slave
Noise Gen.
Dolby Digital Logic Configurations Example internal internal woofer freq. (C), ext. Surround speakers ext. Subwoofer channel.
18.432
Amp./ Osc.
Synth.
CLKO
3528E Dolby Digital Decoder MPEG-L2 Decoder
Example internal Left Right used internal woofer freq. ext. ext. Surround speakers ext. Subwoofer channel.
Configuration Examples I2S-Mode:Multichannel Mode Channels, fs=32, 44.1 kHz, 16,18,.32 Bit) Main analog Volume analog Volume -Cint SUBext (Cint) Lext SUBext Rext normal Dolby Digital Logic
I2S_Inputs I2S_WS3 I2S_CL3
I2S_1_L I2S_1_R I2S_2_L I2S_2_R
Bass Treble Balance Volume Bass Treble Balance Volume
AUDIO_ CL_OUT
Input (LT, RT,L, SR,C, SUB)
I2S_3_Lt I2S_3_Rt
18.432 Channel Loop-through Dolby Logic Decoder Dolby Digital Upgrade Module I2S_WS I2S_CL
SCART1 I2S_Out_L/R -Volume
4519G
Logic Decoder
Basic TVSound System I2S_WS3 I2S_CL3 I2S_WS I2S_CL
Dolby Digital: SUB) Logic: SubW) I2S_Inputs I2S_1_L I2S_1_R I2S_2_L I2S_2_R
I2S_3_Lt I2S_3_Rt I2S_3_L I2S_3_R I2S_3_SL I2S_3_SR I2S_3_C I2S_3_SUB
SoundProcess. Balance Volume Bass Treble Balance Volume Volume
analog Volume
Main
Subw
Lint Subwint Rint
Cint Subwint Cint
18.432
analog Volume
SCART1
Channel Serial Input
SCART2
Volume
SIF-IN SCART1_In
Demod
I2S_Out_L/R
4450G
Multistandard Sound Processor
SCART4_In
Fig. 1-2: Typical 4519G application
Micronas
(01hex)
Volume Balance DACM_R
Subwoofer Level Adjust
DACM_L
Source Select
I2S_3 Resorting Matrix
(36hex (11hex (36hex)
Internal/External Switch
SC3_IN_L
SC3_IN_R SC2_OUT_L
SC4_IN_L
SC4_IN_R
MONO_IN SC2_OUT_R
4519G
Fig. 2-1: Signal flow block diagram 4519G (input output names correspond names)
SCART Output Select
Micronas
Main Channel Matrix Bass/ Treble/ Loudness/ Equalizer
DACM_SUB
(00hex)
I2S_DA_IN1 (sync. 48kHz)
Prescale
(16hex) (14hex) (2Chex)
Interface Beeper
Prescale
(12hex)
I2S1
(08hex) (02/03/04hex (20.25hex
I2S_CL I2S_WS
I2S_DA_IN2 (sync. 48kHz) Volume Balanc DACA_R
(31/32/33hex (30hex) (06hex)
Channel Matrix
(09hex)
I2S2 Bass/ Treble/ Loudness
Functional Description
Interface
DACA_L
I2S_CL3 I2S_WS3
I2S_DA_IN3 (async. 8-48 kHz)
(0Bhex)
Interface
synchronization
Interface
Channel Matrix
I2S_DA_OUT (sync. 48kHz)
2.1. Architecture 4519G Family
I2S3
Prescale
Fig. shows simplified block diagram
Volume
SCART1_L/R
(07hex
SCART1 Channel Matrix Noise Generator Surround Processing
(0Ahex)
(4Dhex) (49hex (4Ahex) (4Bhex) (4Chex)
Surround Channel Matrix
(48hex
SC1_IN_L
SC1_OUT_L
SC1_IN_R
SC2_IN_L
SC2_IN_R
SC1_OUT_R
4519G
2.2. Preprocessing Input Signals inputs adjusted level means prescale registers. I2S_3 interface able receive more than channels (see Section 2.6. page incoming signals resorted programmable matrix order obtain certain order, which means unified postprocessing afterwards. Since I2S_3 interface asynchronous, incoming sound signals with arbitrary sample rates range 8-48 interpolated means adaptive high quality sample rate converter. Therefore subsequent processing calculated fixed sampling rate, which even synchronized I2S_WS e.g. 4450 being locked incoming NICAM signal.
2.6. Surround Processing 2.6.1. Surround Processing Mode Surround sound processing controlled three functions: "Decoder Matrix" defines which method used create multichannel signal stereo input. "Surround Reproduction" determines whether surround signal surround speakers. surround speaker actually connected, defines method that used create surround effects. "Center Mode" determines center signal processed. left unmodified, distributed left right, discarded high pass filtered, whereby pass signals distributed left right.
2.3. Selection Internal Processed Surround Signals Instead having multichannel input I2S_3 interface, multichannel signal created internal Dolby Logic decoder. that case channels multichannel input replaced internally generated signals. 2.6.1.1. Decoder Matrix Decoder Matrix allows three settings: ADAPTIVE: Adaptive Matrix used Dolby Surround Logic. Even sound material encoded Dolby Surround will produce good surround effects this mode. Adaptive Matrix requires license from Dolby Laboratories (See License Notice page PASSIVE: simple fixed matrix used surround sound. EFFECT: fixed matrix that used mono sound special effects. With Adaptive Passive Matrix surround signal present case mono, moreover Adaptive mode even left right output channels carry signal just frequency signals case Center Mode NORMAL). surround sound still required mono signals, Effect Matrix used. This forces surround channel active. Effect Matrix used together with 3D-PANORAMA. result will pseudo stereo effect broadened stereo image respectively.
2.4. Source Selection Output Channel Matrix Source Selector makes possible distribute source signals (I2S input signals) desired output channels (Main, Aux, etc.). input output signals processed simultaneously. Each source channel identified unique source address. each output channel, output channel matrix sound (left mono), sound (right mono), stereo, mono (sound left right).
2.5. Audio Baseband Processing 2.5.1. Main Outputs following baseband features implemented Main output channels: bass/treble, loudness, balance, volume. square wave beeper added these outputs. Main channel additionally supports equalizer function (this simultaneously available with bass/treble).
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4519G
2.6.1.4. Useful Combinations Surround Processing Modes principle, "Decoder Matrix", "Surround Reproduction", "Center Modes" independent settings (all "Decoder Matrix" settings used with "Surround Reproduction" "Center Modes") there some combinations that create "good" sound. Useful combinations
2.6.1.2. Surround Reproduction Surround sound reproduced with four choices: REAR_SPEAKER: there surround speakers connected system, this mode should used. Useful loudspeaker combinations FRONT_SPEAKER: there surround speaker connected, this mode used. Surround information mixed left right output without creating illusion virtual speaker. similar stereo additional center speaker used. This mode should used with Adaptive decoder Matrix only. Useful loudspeaker combinations (Note: surround output channel muted). PANORAMA: surround information mixed left right order create illusion virtual surround speaker. Useful loudspeaker combinations (Note: surround output channel muted). 3D-PANORAMA: Like PANORAMA with improved effect. This algorithm been approved Dolby Laboratories compliance with "Virtual Dolby Surround" technology. Useful loudspeaker combinations (Note: surround output channel muted).
Surround Reproduction Center Modes REAR_SPEAKER: This mode used surround speakers available. Useful center modes NORMAL, WIDE, PHANTOM, OFF. FRONT_SPEAKER: This mode used surround speaker center speaker connected. Useful center modes NORMAL WIDE. PANORAMA 3D-PANORAMA: surround speaker used. three loudspeakers used. Useful center modes NORMAL, WIDE, PHANTOM, OFF.
Center Modes Decoder Matrix PHANTOM: Should only used together with ADAPTIVE Decoder Matrix. NORMAL WIDE: used together with Surround Decoder Matrix. OFF: This mode used together with PASSIVE EFFECT Decoder Matrix center speaker connected).
2.6.1.3. Center Modes Four center modes supported: NORMAL: small center speaker connected, speakers have better bass capability. Center signal high pass filtered. WIDE: speakers have good bass capability. PHANTOM: center speaker used. Center signal distributed (Note: center output channel muted). OFF: center speaker used. Center signal discarded (Note: center output channel muted).
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4519G
2.6.2. Examples Table shows some examples these modes used configure list intended complete, more modes possible.
Table 2-1: Examples Surround Configurations
Configurations
Speaker Configuration1)
Surround Processing Mode
Register (4Bhex) Decoder Matrix [15:8] Surround Reproduction [7:4] Center Mode [3:0]
Stereo Stereo
(L,R)
Surround Modes defined Dolby Laboratories Dolby Surround Logic
(L,C,R,S) ADAPTIVE REAR_ SPEAKER REAR_ SPEAKER FRONT_ SPEAKER 3D_PANORAMA NORMAL WIDE PHANTOM
(L,R,S)
ADAPTIVE
Dolby Stereo Virtual Dolby Surround
(L,C,R)
ADAPTIVE
NORMAL WIDE PHANTOM
(L,R)
ADAPTIVE
Surround Modes that Dolby Adaptive Matrix2) 3-Channel Virtual Surround Passive Matrix Surround Sound 4-Channel Surround 3-Channel Surround 2-Channel Micronas Surround Sound (MSS) 3-Channel Micronas Surround Sound (MSS) Special Effects Surround Sound 4-Channel Surround mono 2-Channel Virtual Surround mono 3-Channel Virtual Surround mono
(L,C,R)
ADAPTIVE
3D_PANORAMA
NORMAL WIDE
(L,C,R,S)
PASSIVE
REAR_ SPEAKER REAR_ SPEAKER 3D_PANORAMA 3D_PANORAMA
NORMAL WIDE
(L,R,S)
PASSIVE
(L,R) (L,C,R)
PASSIVE PASSIVE
NORMAL WIDE
(L,C,R,S)
EFFECT
REAR_ SPEAKER 3D_PANORAMA 3D_PANORAMA
NORMAL WIDE NORMAL WIDE
(L,R) (L,C,R)
EFFECT EFFECT
Speakers muted automatically. implementation products requires license from Dolby Laboratories Licensing Corporation (see note page
Micronas
4519G
Great care taken with systems that common subwoofer: single loudspeaker cannot reproduce virtual sound locations. crossover frequency must lower than
2.6.3. Application Tips using 3D-PANORAMA 2.6.3.1. Sweet Spot Good results only obtained rather close area along middle axis between loudspeakers: sweet spot. Moving away from this position degrades effect.
2.6.3.4. Cabinet Requirements During listening tests Dolby Laboratories, resonances cabinet should occur.
2.6.3.2. Clipping test Dolby Labs, very important have clipping effects even with worst case signals. I2S-prescale register values 10hex (16dec). This sufficient terms clipping. However, found, that reducing prescale value lower than 16dec more convincing effects generated case very high dynamic signals. value 10dec good compromise between overall volume additional headroom. Test signals: sine sweep with dBFS; only, only, equal phase, anti phase. Listening tests: Dolby Trailers (train trailer, city trailer, canyon trailer.) Good material check resonances Dolby Trailers other dynamic sound tracks.
2.6.4. Input Output Levels Dolby Surround Logic nominal input level (input sensitivity) I2SInputs dBFS. highest possible input level dBFS accepted without internal overflow. I2Sprescale value should values (16dec). With higher prescale values lower input sensitivities accommodated. higher input sensitivity possible, because least headroom required every input according Dolby specifications. full-scale left only input dBFS) will produce fullscale left only output volume). typical output level 1.37 Vrms DACM_L. same holds true right only signals (1.37 Vrms DACM_R). full-scale input level both inputs (Lin=Rin=0 dBFS) will give center only output with maximum level. full-scale input level both inputs (but with inverted phases) will give surround-only signal with maximum level. reproducing Dolby Logic according specifications, center surround outputs must amplified with respect output signals. This done ways: implementing more amplification center surround loudspeaker outputs. always selecting volume lower than center surround. Method preferable, method lowers achievable left right signals
2.6.3.3. Loudspeaker Requirements loudspeakers used their positioning inside will greatly influence performance virtualizer. algorithm works with direct sound path. Reflected sound waves reduce effect. it's most important have much direct sound possible, compared indirect sound. obtain approval set, Dolby Laboratories require mounting loudspeakers front set. Loudspeakers radiating side will produce convincing effects. Good directionality loudspeakers towards listener optimal. virtualizer specially developed implementation sets. Even rather small stereo TV's, sufficient sound effects obtained. small sets, loudspeaker placement should side CRT; large screen sets 16:9 sets), mounting loudspeakers below acceptable (large separation preferred, frequency speakers should outmost avoid cancellation effects). Using external loudspeakers with large stereo base will create optimal effects. loudspeakers should able reproduce wide frequency range. most important frequency range starts from ranges kHz.
2.7. SCART Signal Routing 2.7.1. SCART Select SCART Output Select block includes full matrix switching facilities. switches controlled user register (see page page 30).
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4519G
2.7.2. Stand-by Mode 4519G switched first pulling STANDBYQ then (after delay) switching DVSUP AVSUP, keeping AHVSUP (`Standby'-mode), SCART switches maintain their position function. This allows copying from selected SCART-inputs SCART-outputs set's stand-by mode. case power starting from stand-by (see details power-up sequence Fig. 4-19 page 52), internal registers except register (page reset default configuration (see Table page 17). reset position register becomes active after first transmission into Baseband Processing part (subaddress 12hex). transmitting register first, reset state redefined. 2.8. Interfaces 4519G kinds interfaces: synchron master/slave input/output interfaces running asynchron slave interface. interfaces accept variety formats with different sample width, bit-orientation, wordstrobe timing. options means MODUS I2S_CONFIG register. 2.8.1. Synchronous I2S-Interface(s) synchronous interface consists pins: I2S_DA_IN1, I2S_DA_IN2/3 (I2S_DA_IN2 PQFP80 package): serial data input, 18.32 bits sample. I2S_DA_OUT: serial data output, 18.32 bits sample. I2S_CL: serial clock. I2S_WS: word strobe signal defines left right sample. 4519G serves master interface, clock word strobe lines driven 4519G. this mode, only bits sample selected. slave mode, these lines input 4519G 4519G clock synchronized times I2S_WS rate kHz). timing diagram shown Fig. 4-21 page
2.8.2. Asynchronous I2S-Interface asynchronous slave interface allows reception digital audio signals with arbitrary sample rates from kHz. synchronization performed means adaptive sample rate converter. oversampling clock required. following pins used asynchronous interface (serve only input): I2S_WS3 I2S_CL3 I2S_DA_IN2/3 (I2S_DA_IN3 PQFP80 package). interface accepts I2S-input streams with first with sample widths 16,18.32 bits. With left/ right alignment wordstrobe timing polarity, there additional parameters available adaption variety formats CONFIGURATION register. 2.8.3. Multichannel I2S-Output Bit[0:1] CONFIGURATION register (see page switches output channel multichannel output mode. resolution channel master mode. While first channels selected source select matrix, channels always connected I2S_3 input channels 3-8. Both, master slave mode possible, long wordstrobe only positive edge frame slave mode. 2.8.4. Asynchronous Multichannel I2S-Input 4519G supports kinds asynchronous multichannel input: asynchronous I2S_3 interface switched multichannel mode (bit CONFIGURATION register number channels must even less equal eight. input lines (I2S_DA_IN1, I2S_DA_IN2 I2S_DA_IN3 PQFP80 package) switched asynchronous channel mode (bit[2] CONFIGURATION register). common clock I2S_WS3 I2S_CL3. synchronous interfaces available this mode.
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4519G
2.9. Digital Control Pins static level digital input/output pins D_CTR_I/O_0/1 switchable between HIGH I2C-bus means register (see page 30). This enables controlling external hardware switches other devices I2C-bus. Modus Register digital input/output pins high impedance (see page 19). pins used input. current state read STATUS register (see page page 21).
2.10. Clock Oscillator Crystal Specifications 4519G derives internal system clocks from 18.432 oscillator. I2S-slave mode synchronous interface, clock phase-locked corresponding source. proper performance, clock oscillator requires 18.432-MHz crystal. Note that phase-locked modes (I2S-slave), crystals with tighter tolerance required. asynchronous I2S3 slave interface uses different locking mechanism does require tighter crystal tolerances.
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4519G
Control Interface 3.1. Interface 3.1.1. Device Subaddresses 4519G controlled slave interface. selected transmitting 4519G device addresses. order allow three connected single bus, address select (ADR_SEL) been implemented. With ADR_SEL pulled high, low, left open, 4519G responds different device addresses. device address pair defined write address read address (see Table 3-1). Writing done sending device write address, followed subaddress byte, address bytes, data bytes. Reading done sending write device address, followed subaddress byte address bytes. Without sending stop condition, reading addressed data completed sending device read address reading bytes data. Refer Section 3.1.4. protocol Section 3.4. "Programming Tips" page proposals 4519G telegrams. Table list available subaddresses. Besides possibility hardware reset, also reset means RESET CONTROL register controller bus. internal architecture 4519G, cannot react immediately request. Table 3-1: Device Addresses
ADR_SEL Mode device address (connected DVSS) Write 80hex Read 81hex High (connected DVSUP) Write 84hex Read 85hex
typical response time about cannot accept another complete byte data until performed some other function (for example, servicing internal interrupt), will hold clock line I2C_CL force transmitter into wait state. positions within transmission where this happen indicated "Wait" Section 3.1.4. maximum wait period during normal operation mode less than
3.1.2. Internal Hardware Error Handling case internal hardware error (e.g. interruption power supply DPL), DPL's wait period extended After this time period elapses, releases data clock lines.
Indicating solving error status: indicate error status, remaining acknowledge bits actual I2C-protocol will left high. Additionally, bit[14] CONTROL one. then reset transmitting reset condition CONTROL.
Indication reset: reset, even caused unstable reset line etc., indicated bit[15] CONTROL. general timing diagram shown Fig. 4-21 page
Left Open Write 88hex Read 89hex
Table 3-2: Subaddresses
Name CONTROL WR_DEM RD_DEM WR_DSP RD_DSP Binary Value 0000 0000 0001 0000 0001 0001 0001 0010 0001 0011 Value Mode Read/Write Write Write Write Write Function Write: Software reset (see Table 3-3) Read: Hardware error status write address demodulator read address demodulator write address read address
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4519G
3.1.3. Description CONTROL Register
Table 3-3: CONTROL Write Register
Name CONTROL Subaddress Bit[15] (MSB) RESET normal Bits[14:0]
Table 3-4: CONTROL Read Register (only 4519G-versions from
Name CONTROL Subaddress Bit[15] (MSB) Reset status after last reading CONTROL: reset occured reset occured Bit[14] Internal hardware status: error occured internal error occured Bits[13:0] interest
Reading CONTROL will reset bits[15,14] CONTROL. After Power-on, bit[15] CONTROL will set; must read once resetted.
3.1.4. Protocol Description Write
Wait write device address sub-addr addr-byte addr-byte data-byte- data-byte high high
Read from
Wait write device address sub-addr addr-byte addr-byte high read device address Wait data-byte- data-byte high
Write Control
Wait write device address sub-addr data-byte data-byte high
Read from Control
Wait write device address 00hex read device address Wait data-byte- data-byte high
Note: Wait
I2C-Bus Start Condition from master I2C-Bus Stop Condition from master Acknowledge-Bit: I2C_DA from slave DPL, light gray) master controller dark gray) Acknowledge-Bit: HIGH I2C_DA from master (dark gray) indicate `End Read' from indicating internal error state I2C-Clock line held low, while processing command. This waiting time max.
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4519G
I2C_DA I2C_CL
Fig. 3-1: protocol (MSB first; data must stable while clock high)
3.1.5. Proposals General 4519G Telegrams 3.1.5.1. Symbols write device address (80hex, 84hex 88hex) read device address (81hex, 85hex 89hex) Start Condition Stop Condition Address Byte Data Byte
3.2. Start-Up Sequence: Power-Up Controlling After POWER RESET (see Fig. 4-21), inactive state. registers reset position, analog outputs muted. controller initialize registers which non-default setting necessary.
3.3. 4519G Programming Interface 3.3.1. User Registers Overview
3.1.5.2. Write Telegrams
<daw <daw <daw
write CONTROL register write data into demodulator write data into
4519G controlled means user registers. complete list user registers given following tables. registers partitioned into sections: Subaddress 10hex writing, 11hex reading
3.1.5.3. Read Telegrams
read data from CONTROL register <daw <dar read data from demodulator <daw <dar read data from
<daw <dar
Subaddress 12hex writing, 13hex reading. Write read registers 16-bit wide, whereby denoted bit[15]. Transmissions have take place 16-bit words (two byte transfers, with most significant byte transferred first). write registers, except MODUS CONFIGURATION, readable. Unused parts 16-bit write registers must zero. Addresses given this table must accessed.
3.1.5.4. Examples
RESET statically Clear RESET Main channel source I2S3 Main volume
More examples typical application protocols listed Section 3.4. "Programming Tips" page
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4519G
Table 3-5: List 4519G Write Registers
Write Register Address (hex) Bits Description Adjustable Range Reset Page
Subaddress 10hex Registers readable MODUS CONFIGURATION [15:0] [15:0] options, D_CTR_I/O modes Configuration format
Subaddress 12hex Registers readable using Subaddress 13hex Volume Main channel [15:8] [7:5] [4:0] Balance Main channel [L/R] Balance mode Main Bass Main channel Treble Main channel Loudness Main channel Loudness filter characteristic Volume channel [15:8] [7:0] [15:8] [15:8] [15:8] [7:0] [15:8] [7:5] [4:0] Volume SCART1 output channel Main source select Main channel matrix source select channel matrix SCART1 source select SCART1 channel matrix source select channel matrix Prescale I2S3
[+12 -114 MUTE] Steps must [0.100 100% 0.100%] [-127.0 -127.0 [Linear logarithmic mode] [+20 [+15 [NORMAL, SUPER_BASS] [+12 -114 MUTE] Steps must [+12 -114 MUTE] ch1&2, ch3&4,.] [SOUNDA, SOUNDB, STEREO, MONO] [I2S1, I2S2, I2S3 ch1&2, I2S3 ch3&4,.] [SOUNDA, SOUNDB, STEREO, MONO] [I2S1, I2S2, I2S3 ch1&2, I2S3 ch3&4,.] [SOUNDA, SOUNDB, STEREO, MONO] ch1&2, ch3&4,.] [SOUNDA, SOUNDB, STEREO, MONO] [00hex 7Fhex] [00hex 7Fhex] Bits [15:0] [00hex 7Fhex]/[00hex 7Fhex] [00hex 7Fhex] [BASS/TREBLE, EQUALIZER] [+12 [+12 [+12 [+12 [+12 mute]
MUTE 000bin 00000bin 100%/100% linear mode NORMAL MUTE 000bin 00000bin MUTE undefined SOUNDA undefined SOUNDA undefined SOUNDA undefined SOUNDA 10hex 10hex 00hex 00/00hex 10hex BASS/TREB
[15:8] [15:8] [7:0]
[15:8] [7:0]
[15:8] [7:0]
[15:8] [7:0] [15:8] [15:8] [15:0] [15:0] [15:8] [15:8] [15:8] [15:8] [15:8] [15:8] [15:8] [15:8]
Prescale I2S2 ACB: SCART Switches D_CTR_I/O Beeper Prescale I2S1 Mode tone control Equalizer Main band Equalizer Main band Equalizer Main band Equalizer Main band Equalizer Main band Subwoofer level adjust
Micronas
4519G
Table 3-5: List 4519G Write Registers, continued
Write Register Balance channel [L/R] Balance mode Bass channel Treble channel Loudness channel Loudness filter characteristic Resorting Surround source select Surround channel matrix Spatial effect surround processing Virtual surround effect strength Decoder matrix Surround reproduction Center mode Surround delay Noise Generator
Address (hex)
Bits [15:8] [7:0]
Description Adjustable Range [0.100 100% 0.100%] [-127.0 -127.0 [Linear mode logarithmic mode] [+20 [+15 [NORMAL, SUPER_BASS] through, straight eight, eight, six, four, through [I2S1, I2S2, I2S3 ch1&2, I2S3 ch3&4,.] [SOUNDA, SOUNDB, STEREO, MONO] 100%] 100%] [ADAPTIVE/PASSIVE/EFFECT] 3D_PANORAMA] [PHANTOM/NORMAL/WIDE/OFF] [5.31ms] [NOISEL, NOISEC, NOISER, NOISES]
Reset %/100 linear mode NORMAL 00hex undefined SOUNDA 00hex 00hex 00hex 0hex 0hex 00hex 00hex
Page
[15:8] [15:8] [15:8] [7:0]
[15:8] [15:8] [7:0] [15:8] [15:8] [15:8] [7:4] [3:0] [15:0] [15:0]
Table 3-6: List 4519G Read Registers
Read Register Address (hex) Bits Description Adjustable Range Page
Subaddress 11hex Registers writable STATUS
[15:0]
Monitoring settings e.g. D_CTR_I/O
Subaddress 13hex Registers writable hardware version code major revision code product code version code [15:8] [7:0] [15:8] [7:0] [00hex FFhex] [00hex FFhex] [00hex FFhex] [00hex FFhex]
Micronas
4519G
3.3.2. Description User Registers 3.3.2.1. Write Registers Subaddress 10hex Table 3-7: Write Registers Subaddress 10hex Register Address MODUS 30hex MODUS Register bit[15:8] bit[7] bit[6] bit[5] bit[4] bit[3] bit[2:0] undefined, must active/tristate state audio clock output AUD_CL_OUT word strobe alignment (synchronous I2S) changes data word boundary changes clock cycle advance master/slave mode interface active/tristate state output pins state digital output pins D_CTR_I/O_0 active: D_CTR_I/O_0 output pins (can means register) tristate: D_CTR_I/O_0 input pins (level read STATUS[4,3]) undefined, must MODUS Function Name
Micronas
4519G
Table 3-7: Write Registers Subaddress 10hex, continued Register Address Function
Name
CONFIGURATION 40hex CONFIGURATION Register I2S31) bit[11] bit[10] data alignment (must bit[2] left/right aligned wordstrobe polarity (must bit[2] right, left right, left wordstrobe alignment (asynchronous I2S_3) changes data word boundary changes clock cycle advance Sample Mode Two/Multi sample Word length each data packet (n-2)/2 bit[3]=0, bit[8]=1 (multi-sample input mode) 0111 1000 1111 bit[3]=0, bit[8]=0 (two-sample input mode) xxxx 16.32 bit, 18-bit valid bit[3]=1, bit[8]=1 (multi-sample output mode) 1111 bit[3]=1, bit[8]=0 (two-sample output mode) 0111 1111 bit[3] I2S3 Mode output (I2S3 CL/WS active) input (I2S3 CL/WS tristate) I2S3_MODE I2S3_ALIGN I2S3_WS_POL I2S_CONFIG
bit[9]
I2S3_WS_MODE
bit[8] bit[7:4]
I2S3_MSAMP I2S3_MBIT
I2S1/2/3 bit[2] I2S1/2/3 Timing I2S3 timing inputs (1/2/3) default mode I2S_TIMING
bit[1:0] I2S_CL frequency I2S_DA_OUT sample length (1.536 Clk) (3.072 Clk) (12.288 Clk)
I2S_CL3 frequency depends bit[8] bits[7:4] follows: [7:4] 0111 fs*(2*16) [7:4] else fs*(2*32) fs*(8*32)
Micronas
4519G
3.3.2.2. Read Registers Subaddress 11hex Table 3-8: Read Registers Subaddress 11hex Register Address 00hex Function STATUS Register Contains status D_CTR_I/O pins bit[15:5] bit[4] bit[3] bit[2:0] undefined low/high level digital D_CTR_I/O_1 low/high level digital D_CTR_I/O_0 undefined Name STATUS
3.3.2.3. Write Registers Subaddress 12hex Table 3-9: Write Registers Subaddress 12hex Register Address Function Name
PREPROCESSING 16hex 12hex 11hex I2S1 Prescale I2S2 Prescale I2S3 Prescale Defines prescale value digital input signals bit[15:8] 00hex 10hex 7Fhex gain (recommendation) gain (maximum gain) PRE_I2S1 PRE_I2S2 PRE_I2S3
Micronas
4519G
Table 3-9: Write Registers Subaddress 12hex, continued Register Address Function
Name
I2S3 RESORTING MATRIX 36hex
I2S3 Resorting Matrix (not mentioned combinations must used) Resorting multichannel inputs bit[15:8] 0000hex channel, "through" 1,2,3,4,5,6,7,8 Lt,Rt Lt,Rt,Lvirtual,Rvirtual 1,2,3,4,5,6,7,8 Lt,Rt,L,R,SL,SR,C,LFE I2S3_Sort
0001hex channel, "straight eight" 1,2,3,4,5,6,7,8 L,R,SL,SR,C,LFE,Lt,Rt
0002hex channel, "left/right eight", "MAS 3528E" 1,2,3,4,5,6,7,8 4,8,1,5,2,6,3,7 Lt,Rt,L,R,SL,SR,C,LFE L,SL,C,Lt,R,SR,LFE,Rt 0003hex channel, "left/right six" 1,2,3,4,5,6 L,SL,C,R,SR,LFE -,-,1,4,2,5,3,6 -,-,L,R,SL,SR,C,LFE
0004hex channel, "left/right four", "External ProLogic" 1,2,3,4 -,-,1,3,4,4,2,L,C,R,S -,-,L,R,SL,SR,C,-0010hex channel, "through"; "Internal ProLogic" 1,2,+,+,+,+,+,+ Lt,Rt,LPL,RPL,SPL,SPL,CPL,SUBPL Lt,Rt
"+": channel will replaced internally generated signal "XPL": internally generated signal
Micronas
4519G
Table 3-9: Write Registers Subaddress 12hex, continued Register Address Function Name
SOURCE SELECT OUTPUT CHANNEL MATRIX 08hex 09hex 0Ahex 0Bhex 48hex Source for: Main Output Output SCART1 Output Output Surround Processing bit[15:8]
SRC_MAIN SRC_AUX SRC_SCART1 SRC_I2S SRC_DPL
I2S1 input I2S2 input I2S3 input channels (e.g. Lt,Rt)1) I2S3 input channels (e.g. L,R)1) Logic processed I2S3 input channels (e.g. SL,SR)1) Logic processed (both channels same signal) I2S3 input channels (e.g. C,SUB)1) Logic processed
exemplary channel assignment Micronas digital multichannel sound system with 3528E 4450G. 08hex 09hex 0Ahex 0Bhex 48hex Channel Matrix for: Main Output Output SCART1 Output Output Surround Processing bit[7:0] 00hex 10hex 20hex 30hex Sound Mono Left Mono) Sound Mono Right Mono) Stereo (transparent mode) Mono (L+R)/2 MAT_MAIN MAT_AUX MAT_SCART1 MAT_I2S MAT_DPL
Usually matrix modes should "Stereo" (transparent).
Micronas
4519G
Table 3-9: Write Registers Subaddress 12hex, continued Register Address Function
Name
MAIN PROCESSING 00hex 06hex Volume Main Volume bit[15:8] volume table with step size (maximum volume) 7Fhex 7Ehex 74hex 73hex 72hex -113 02hex -114 01hex Mute (reset condition) 00hex Fast Mute FFhex higher resolution volume table +0.125 increase addition volume table +0.875 increase addition volume table used must VOL_MAIN VOL_AUX
bit[7:5]
bit[4:0]
With large scale input signals, positive volume settings lead signal clipping. 4519G Main Volume function divided into digital analog section. With Fast Mute, volume reduced mute position digital volume only. Analog volume changed. This reduces audible plops. turn volume again, volume step that been used before Fast Mute activated must transmitted.
Micronas
4519G
Table 3-9: Write Registers Subaddress 12hex, continued Register Address 01hex 30hex Function Balance Main Channel Balance Channel bit[15:8] Linear Mode Left muted, Right 100% 7Fhex Left 0.8%, Right 100% 7Ehex Left 99.2%, Right 100% 01hex Left 100%, Right 100% 00hex Left 100%, Right 99.2% FFhex Left 100%, Right 0.8% 82hex Left 100%, Right muted 81hex Logarithmic Mode Left -127 Right 7Fhex Left -126 Right 7Ehex Left Right 01hex Left Right 00hex Left Right FFhex Left Right -127 81hex Left Right -128 80hex Balance Mode linear 0hex logarithmic 1hex Name BAL_MAIN BAL_AUX
bit[15:8]
bit[3:0]
Positive balance settings reduce left channel without affecting right channel; negative settings reduce right channel leaving left channel unaffected.
Micronas
4519G
Table 3-9: Write Registers Subaddress 12hex, continued Register Address 20hex Function Tone Control Mode Main Channel bit[15:8] 00hex FFhex bass treble active equalizer active
Name TONE_MODE
Defines whether Bass/Treble Equalizer activated Main channel. Bass/Treble Equalizer cannot work simultaneously. Equalizer used, Bass Treble coefficients must zero vice versa. 02hex 31hex Bass Main Channel Bass Channel bit[15:8] normal range 60hex 58hex 08hex 00hex F8hex A8hex A0hex extended range 7Fhex 78hex 70hex 68hex BASS_MAIN BASS_AUX
bit[15:8]
Higher resolution possible: step normal range results gain step about extended range about With positive bass settings, internal clipping occur even with overall volume less than This will lead clipped output signal. Therefore, recommended bass value that, conjunction with volume, would result overall positive gain.
Micronas
4519G
Table 3-9: Write Registers Subaddress 12hex, continued Register Address 03hex 32hex Function Treble Main Channel Treble Channel bit[15:8] 78hex 70hex 08hex 00hex F8hex A8hex A0hex Name TREB_MAIN TREB_AUX
Higher resolution possible: step results gain step about With positive treble settings, internal clipping occur even with overall volume less than This will lead clipped output signal. Therefore, recommended treble value that, conjunction with volume, would result overall positive gain. 21hex 22hex 23hex 24hex 25hex Equalizer Main Channel Band (below Equalizer Main Channel Band (center: Equalizer Main Channel Band (center: kHz) Equalizer Main Channel Band (center: kHz) Equalizer Main Channel Band (above: kHz) bit[15:8] 60hex 58hex 08hex 00hex F8hex A8hex A0hex EQUAL_BAND1 EQUAL_BAND2 EQUAL_BAND3 EQUAL_BAND4 EQUAL_BAND5
Higher resolution possible: step results gain step about With positive equalizer settings, internal clipping occur even with overall volume less than This will lead clipped output signal. Therefore, recommended equalizer bands value that, conjunction with volume, would result overall positive gain.
Micronas
4519G
Table 3-9: Write Registers Subaddress 12hex, continued Register Address 04hex 33hex Function Loudness Main Channel Loudness Channel bit[15:8] Loudness Gain 44hex 40hex 04hex 00hex Loudness Mode normal (constant volume kHz) 00hex Super Bass (constant volume kHz) 04hex
Name LOUD_MAIN LOUD_AUX
bit[7:0]
Higher resolution Loudness Gain possible: step results gain step about Loudness increases volume low- high-frequency signals, while keeping amplitude 1-kHz reference frequency constant. intended loudness according actual volume setting. Because loudness introduces gain, recommended loudness value that, conjunction with volume, would result overall positive gain. corner frequency bass amplification different values. Super Bass mode, corner frequency shifted point constant volume shifted from kHz.
Micronas
4519G
Table 3-9: Write Registers Subaddress 12hex, continued Register Address 2Chex Function Subwoofer Level Adjustment bit[15:8] 00hex FFhex E3hex E2hex 80hex Mute Name SUBW_LEVEL
SCART OUTPUT CHANNEL 07hex Volume SCART1 Output Channel bit[15:8] volume table with step size (maximum volume) 7Fhex 7Ehex 74hex 73hex 72hex -113 02hex -114 01hex Mute (reset condition) 00hex higher resolution volume table +0.125 increase addition volume table +0.875 increase addition volume table 01hex this must 01hex VOL_SCART1
bit[7:5]
bit[4:0]
Micronas
4519G
Table 3-9: Write Registers Subaddress 12hex, continued Register Address Function
Name
SCART SWITCHES DIGITAL PINS 13hex Register Defines level digital output pins position SCART switches bit[15] bit[14] bit[13:5] low/high digital output D_CTR_I/O_1 (MODUS[3]=0) low/high digital output D_CTR_I/O_0 (MODUS[3]=0) ACB_REG
SCART1 Output Select xx00xx SCART3 input SCART1 output (RESET position) xx01xx SCART2 input SCART1 output xx10xx MONO input SCART1 output xx11xx SCART1 SCART1 output xx01xx SCART1 input SCART1 output xx10xx SCART4 input SCART1 output xx11xx mute SCART1 output SCART2 Output Select 00xxxx SCART1 SCART2 output (RESET position) 01xxxx SCART1 input SCART2 output 10xxxx MONO input SCART2 output 01xxxx SCART2 input SCART2 output 10xxxx SCART3 input SCART2 output 11xxxx SCART4 input SCART2 output 11xxxx mute SCART2 output
bit[13:5]
RESET position becomes active time first write transmission control audio processing part. writing register first, RESET state redefined. BEEPER 14hex Beeper Volume Frequency bit[15:8] Beeper Volume 00hex maximum volume 7Fhex Beeper Frequency (lowest) 01hex 40hex FFhex BEEPER
bit[7:0]
Micronas
4519G
Table 3-9: Write Registers Subaddress 12hex, continued Register Address Function Name
SURROUND PROCESSING 49hex Spatial Effects Surround Processing bit[15:8] Spatial Effect Strength Enlargement 100% 7Fhex Enlargement 3Fhex Enlargement 1.5% 01hex Effect 00hex 00hex must SUR_SPAT
bit[7:0]
Increases perceived basewidth reproduced left right front channels. Recommended value: 40hex. 4Ahex Virtual Surround Effect Strength bit[15:8] Virtual Surround Effect Strength Effect 100% 7Fhex Effect 3Fhex 01hex 00hex bit[7:0] 00hex Effect 1.5% Effect must SUR_3DEFF
Strength surround effect PANORAMA 3D-PANORAMA mode. other Surround Reproduction Modes this value must Recommended value: 54hex.
Micronas
4519G
Table 3-9: Write Registers Subaddress 12hex, continued Register Address 4Bhex Function Surround Processing Mode bit[15:8]
Name SUR_MODE DEC_MAT
Decoder Matrix ADAPTIVE (for Dolby Surround Logic Virtual 00hex Surround) PASSIVE (for MSS, Micronas Surround Sound) 10hex EFFECT (used special effects monophonic 20hex signals) Surround Reproduction 0hex 3hex REAR_SPEAKER: surround signal reproduced rear speakers. FRONT_SPEAKER: surround signal redirected front channels. There physical rear speaker connected. PANORAMA: surround signal processed redirected left right front speakers order create illusion virtual rear speaker, although physical rear speaker connected. 3D-PANORAMA: surround signal processed redirected left right front speakers order create illusion virtual rear speaker, although physical rear speaker connected.
bit[7:4]
SUR_REPRO
5hex
6hex
bit[3:0]
Center Mode 0hex 1hex 2hex 3hex PHANTOM mode Center speaker connected) NORMAL mode (small Center speaker) WIDE mode (large Center speaker) mode (Center output Surround Decoder discarded. Useful only special effect modes)
C_MODE
4Chex
Surround Delay bit[15:8] 05hex 06hex 1Fhex 00hex delay surround path (lowest) delay surround path delay surround path (highest)) must
SUR_DELAY
bit[7:0]
Dolby Surround Logic designs, only fixed 15-30 variable delay must used. This register effect 3D-PANORAMA PANORAMA mode. 4Dhex Noise Generator bit[15:8] bit[7:0] 00hex 80hex A0hex B0hex C0hex D0hex Noise generator Noise generator Noise left channel Noise center channel Noise right channel Noise surround channel SUR_NOISE
Determines active channel noise generator.
Micronas
4519G
3.3.2.4. Read Registers Subaddress 13hex Table 3-10: Read Registers Subaddress 13hex Register Address Function Name
4519G VERSION READOUT Registers 1Ehex Hardware Version Code bit[15:8] 01hex 4519G-A1 DPL_HARD
change hardware version code defines hardware optimizations that have influence chip's behavior. readout this register identical hardware version code chip's imprint. Family Code bit[7:4] 3hex 4519G-A1 DPL_REVISION DPL_FAMILY
Major Revision Code bit[3:0] 1Fhex 7hex 4519G-A1
Product Code bit[15:8] 13hex 4519G
DPL_PRODUCT
means DPL-Product Code, control processor able decide which sound standards have considered. Version Code bit[7:0] 41hex 42hex 4519G 4519G DPL_ROM
change version code defines internal software optimizations, that have influence chip's behavior, e.g. features have been included. While software change intended create compatibility problems, customers that want functions identify 4519G versions according this number.
Micronas
4519G
3.4. Programming Tips This section describes preferred method initializing 4519G. initialization grouped into four sections: analog signal path, input processing I2S, output processing. Fig. page complete signal flow.
3.5. Examples Minimum Initialization Codes Initialization 4519G according these listings reproduces sound selected standard Main output. numbers hexadecimal. examples have following structure: Perform controlled reset Write MODUS register
SCART Signal Path Select source each analog SCART output with register. Inputs Select preferred prescale inputs (set after RESET). Select I2S3 Resorting matrix according channel order your decoding device (e.g. 3528E chose mode 02hex) Output Channels Select source channel matrix each output. audio baseband features Select volume each output.
Source Selection Main channel (with matrix STEREO). Volume Main channel
3.5.1. Micronas Dolby Digital chipset (with 3528E)
MODUS-Register: slave I2S-config-Register I2S3 Resorting matrix, Mode Source Sel. I2S_out I2S3 Lt/Rt Source Sel. Main_out I2S3 Main Volume Softreset
Micronas
4519G
Specifications 4.1. Outline Dimensions
18.4
0.17 0.04
23.2 0.15
0.05 ±0.2
SPGS705000-3(P80)/1E
Fig. 4-1: 80-Pin Plastic Quad Flat Pack (PQFP80) Weight approximately 1.61 Dimensions
0.145
0.055
1.75
1.75
0.05
0.22 0.05
D0025/3E
Fig. 4-2: 64-Pin Plastic Low-Profile Quad Flat Pack (PLQFP64) Weight approximately 0.35 Dimensions
Micronas
12.0
17.2 0.15
0.37 0.04
4519G
SPGS703000-1(P64)/1E
57.7 ±0.1
±0.2 ±0.1
19.3 ±0.1 ±0.05
0.28 ±0.06 ±0.2 ±0.05 1.778 0.48 ±0.06 1.778 55.1 ±0.1 20.3 ±0.5
Fig. 4-3: 64-Pin Plastic Shrink Dual-Inline Package (PSDIP64) Weight approximately Dimensions
Micronas
4519G
4.2. Connections Short Descriptions connected (leave vacant future compatibility reasons) Test (leave vacant used production test only) leave vacant obligatory; connect described application circuit diagram AHVSS: connect AHVSS
PQFP 80-pin PLQFP 64-pin PSDIP 64-pin
Name
Type
Connection
used)
Short Description
I2C_CL I2C_DA I2S_CL I2S_WS I2S_DA_OUT I2S_DA_IN1 DVSUP DVSUP DVSUP DVSS DVSS DVSS I2S_DA_IN2/3 I2S_DA_IN2 I2S_CL3 I2S_WS3 RESETQ I2S_DA_IN3 DACA_R DACA_L IN/OUT IN/OUT IN/OUT IN/OUT
connected clock data clock word strobe data output I2S1 data input Test Test Test Digital power supply Digital power supply Digital power supply Digital ground Digital ground Digital ground I2S2/3-data input
PQFP80: separate I2S_DA_IN3
connected I2S3 clock I2S3 word strobe Power-on-reset I2S3-data input connected out, right out, left
Micronas
4519G
PQFP 80-pin PLQFP 64-pin PSDIP 64-pin
Name
Type
Connection
used)
Short Description
VREF2 DACM_R DACM_L DACM_SUB SC2_OUT_R SC2_OUT_L VREF1 SC1_OUT_R SC1_OUT_L CAPL_A AHVSUP CAPL_M AHVSS AHVSS AGNDC SC4_IN_L SC4_IN_R SC3_IN_L SC3_IN_R SC2_IN_L SC2_IN_R SC1_IN_L
AHVSS AHVSS AHVSS
Reference ground Loudspeaker out, right Loudspeaker out, left connected Subwoofer output connected connected SCART output right SCART output left Reference ground SCART output right SCART output left Volume capacitor Analog power supply Volume capacitor MAIN connected connected Analog ground Analog ground Analog reference voltage connected SCART input, left SCART input, right Analog Shield Ground SCART input, left SCART input, right Analog Shield Ground SCART input, left SCART input, right Analog Shield Ground SCART input, left
Micronas
4519G
PQFP 80-pin PLQFP 64-pin PSDIP 64-pin
Name
Type
Connection
used)
Short Description
SC1_IN_R MONO_IN AVSS AVSS AVSUP AVSUP TESTEN XTAL_IN XTAL_OUT AUD_CL_OUT D_CTR_I/O_1 D_CTR_I/O_0 ADR_SEL STANDBYQ
SCART input, right connected connected Mono input Analog ground Analog ground connected connected Analog power supply Analog power supply connected connected connected Test Crystal oscillator Crystal oscillator (See also 4.3.
descriptions)
AVSS
Test Audio clock output (18.432 MHz) connected connected connected D_CTR_I/O_1 D_CTR_I/O_0 address select Stand-by (low-active)
IN/OUT IN/OUT
Micronas
4519G
4.3. Descriptions numbers refer 80-pin PQFP package connected. I2C_CL Clock Input/Output (Fig. 4-8) this pin, I2C-bus clock signal supplied. signal pulled down case wait conditions. I2C_DA Data Input/Output (Fig. 4-8) this pin, I2C-bus data written read from DPL. I2S_CL Clock Input/Output (Fig. 4-11) Clock line bus. master mode, this line driven DPL; slave mode, external clock supplied. I2S_WS Word Strobe Input/Output (Fig. 4-11) Word strobe line bus. master mode, this line driven DPL; slave mode, external word strobe supplied. I2S_DA_OUT1 Data Output (Fig. 4-7) Output digital serial sound data bus. I2S_DA_IN1 Data Input (Fig. 4-9) First input digital serial sound data bus. Test pins Pins DVSUP* Digital Supply Voltage Power supply digital circuitry DPL. Must connected power supply. Pins DVSS* Digital Ground Ground connection digital circuitry DPL. I2S_DA_IN2 Data Input (Fig. 4-9) Second input digital serial sound data bus. packages except PQFP-80-pin this also connected asynchronous interface Pins connected. Pins I2S_CL3 Clock Input (Fig. 4-9) Clock line bus. Since only slave mode available external clock supplied. Pins I2S_WS3 Word Strobe Input (Fig. 4-9) Word strobe line bus. Since only slave mode available external word strobe supplied.
RESETQ Reset Input (Fig. 4-9) steady state, high level required. level resets 4519G. I2S_DA_IN3 Data Input (Fig. 4-9) Asynchronous input digital serial sound data bus. Pins connected. Pins DACA_R/L Outputs (Fig. 4-16) Output signal. capacitor AHVSS must connected these pins. offset these pins depends selected volume. VREF2 Reference Ground Reference analog ground. This must connected separately ground (AHVSS). VREF2 serves clean ground should used reference analog connections Main outputs. Pins DACM_R/L Main Outputs (Fig. 4-16) Output Main signal. capacitor AHVSS must connected these pins. offset these pins depends selected Main volume. connected. DACM_SUB Subwoofer Output (Fig. 4-16) Output subwoofer signal. 1-nF capacitor AHVSS must connected this pin. frequency content subwoofer output, value capacitor increased better suppression high-frequency noise. offset this depends selected Main volume. Pins connected. Pins SC2_OUT_R/L SCART2 Outputs (Fig. 4-18) Output SCART2 signal. Connections these pins must 100- series resistor intended AC-coupled. VREF1 Reference Ground Reference analog ground. This must connected separately ground (AHVSS). VREF1 serves clean ground should used reference analog connections SCART outputs. Pins SC1_OUT_R/L SCART1 Outputs (Fig. 4-18) Output SCART1 signal. Connections these pins must 100- series resistor intended AC-coupled.
Micronas
4519G
ASG* Analog Shield Ground Analog ground (AHVSS) should connected this reduce cross-coupling between SCART inputs. Pins SC1_IN_L/R SCART1 Inputs (Fig. 4-15) analog input signal SCART1 this pin. Analog input connection must AC-coupled. connected
CAPL_A Volume Capacitor (Fig. 4-13) 10-µF capacitor AHVSUP must connected this pin. serves smoothing filter volume changes order suppress audible plops. value capacitor lowered 1-µF faster response required. area encircled trace lines should minimized; keep traces short possible. This input sensitive magnetic induction. AHVSUP* Analog Power Supply High Voltage Power supplied this analog circuitry DPL. This must connected supply. V-operation possible with restrictions performance) CAPL_M Volume Capacitor Loudspeakers (Fig. 4-13) 10-µF capacitor AHVSUP must connected this pin. serves smoothing filter volume changes order suppress audible plops. value capacitor lowered faster response required. area encircled trace lines should minimized; keep traces short possible. This input sensitive magnetic induction. Pins Pins connected.
connected. MONO_IN Mono Input (Fig. 4-15) analog mono input signal this AC-coupled. Pins AVSS* Analog Power Supply Voltage Ground connection analog input circuitry DPL. Pins Pins connected. Pins AVSUP* Analog Power Supply Voltage Power supplied this analog input circuitry DPL. This must connected supply. connected.
Pins AHVSS* Ground Analog Power Supply High Voltage Ground connection analog circuitry DPL. AGNDC Internal Analog Reference Voltage This serves internal ground connection analog circuitry. must connected VREF pins with 3.3-µF 100-nF capacitor parallel. This pins shows level typically 3.73 connected. Pins SC4_IN_L/R SCART4 Inputs (Fig. 4-15) analog input signal SCART4 this pin. Analog input connection must AC-coupled. ASG* Analog Shield Ground Analog ground (AHVSS) should connected this reduce cross-coupling between SCART inputs. Pins SC3_IN_L/R SCART3 Inputs (Fig. 4-15) analog input signal SCART3 this pin. Analog input connection must AC-coupled. ASG* Analog Shield Ground Analog ground (AHVSS) should connected this reduce cross-coupling between SCART inputs. Pins SC2_IN_L/R SCART2 Inputs (Fig. 4-15) analog input signal SCART2 this pin. Analog input connection must AC-coupled.
TESTEN Test Enable (Fig. 4-9) This enables factory test modes. normal operation, must connected ground. Pins XTAL_IN, XTAL_OUT Crystal Input Output Pins (Fig. 4-12) These pins connected 18.432 crystal oscillator which digitally tuned integrated capacitances. external clock into XTAL_IN (leave XTAL_OUT vacant this case). audio clock output signal AUD_CL_OUT derived from oscillator. External capacitors each crystal ground (AVSS) required. should verified layout, that supply current digital circuitry flowing through ground connection point. This needed factory tests. normal operation, must left vacant. AUD_CL_OUT Audio Clock Output (Fig. 4-12) This 18.432 main clock output. Pins Pins connected. Pins D_CTR_I/O_1/0 Digital Control Input/ Output Pins (Fig. 4-11) General purpose input/output pins.
Micronas
4519G
ADR_SEL Address Select (Fig. 4-10) This selects device address DPL. (see Table 3-1). STANDBYQ Stand-by normal operation, this must High. switched `Stand-by'-mode, SCART switches maintain their position function. (see Section 2.7.2.)
Application Note: ground pins should connected low-resistive ground plane. supply pins should connected separately with short low-resistive lines power supply. Decoupling capacitors from DVSUP DVSS, AVSUP AVSS, AHVSUP AHVSS recommended closely possible these pins. Decoupling DVSUP DVSS most important. recommend using more than capacitor. choosing different values, frequency range active decoupling extended. application boards use: capacitor with lowest value should placed nearest pins. pins should connected closely possible ground. They intended leading with SCART signals shield lines should connected ground SCART-connector again.
Micronas
4519G
4.4. Configurations
SC2_IN_L SC2_IN_R SC1_IN_L SC1_IN_R MONO_IN AVSS AVSS
SC3_IN_R SC3_IN_L SC4_IN_R SC4_IN_L AGNDC AHVSS AHVSS
AVSUP AVSUP TESTEN XTAL_IN XTAL_OUT AUD_CL_OUT D_CTR_I/O_1 D_CTR_I/O_0 ADR_SEL STANDBYQ
CAPL_M AHVSUP CAPL_A SC1_OUT_L SC1_OUT_R VREF1 SC2_OUT_L SC2_OUT_R DACM_SUB DACM_L DACM_R VREF2 DACA_L
4519G
I2C_CL I2C_DA I2S_CL I2S_WS I2S_DA_OUT I2S_DA_IN1 DVSUP DVSUP I2S_DA_IN2 DVSS DVSS DVSS DVSUP
DACA_R
I2S_DA_IN3 RESETQ I2S_WS3 I2S_CL3
Fig. 4-4: 80-pin PQFP package
Micronas
4519G
SC2_IN_L SC2_IN_R SC1_IN_L SC1_IN_R MONO_IN AVSS
SC3_IN_R SC3_IN_L SC4_IN_R SC4_IN_L AGNDC AHVSS
AVSUP TESTEN XTAL_IN XTAL_OUT AUD_CL_OUT D_CTR_I/O_1 C_CTR_I/O_0 ADR_SEL STANDBYQ I2C_CL I2C_DA I2S_CL I2S_WS I2S_DA_OUT I2S_DA_IN1 I2S_DA_IN2/3 DVSS DVSUP RESETQ I2S_WS3 I2S_CL3 CAPL_M AHVSUP CAPL_A SC1_OUT_L SC1_OUT_R VREF1 SC2_OUT_L SC2_OUT_R DACM_SUB DACM_L DACM_R VREF2 DACA_L DACA_R
4519G
Fig. 4-5: 64-pin PLQFP package
Micronas
4519G
4.5. Circuits
AUD_CL_OUT D_CTR_I/O_1 D_CTR_I/O_0 ADR_SEL STANDBYQ I2C_CL I2C_DA I2S_CL I2S_WS I2S_DA_OUT I2S_DA_IN1 DVSUP DVSS I2S_DA_IN2/3 I2S_CL3 I2S_WS3 RESETQ DACA_R DACA_L VREF2 DACM_R DACM_L DACM_SUB
XTAL_OUT XTAL_IN TESTEN AVSUP AVSS MONO_IN SC1_IN_R SC1_IN_L SC2_IN_R SC2_IN_L SC3_IN_R SC3_IN_L SC4_IN_R SC4_IN_L AGNDC AHVSS CAPL_M AHVSUP CAPL_A SC1_OUT_L SC1_OUT_R VREF1 SC2_OUT_L SC2_OUT_R
numbers refer PQFP80 package. DVSUP Fig. 4-7: Output (I2S_DA_OUT)
4519G
Fig. 4-8: Input/Output Pins (I2C_CL, I2C_DA)
Fig. 4-6: 64-pin PSDIP package
Fig. 4-9: Input Pins (I2S_DA_IN1.3, RESETQ, TESTEN, STANDBYQ)
DVSUP
ADR_SEL Fig. 4-10: Input (ADR_SEL)
Micronas
4519G
DVSUP Fig. 4-11: Input/Output Pins (I2S_CL, I2S_WS, D_CTR_I/O_1, D_CTR_I/O_0)
AHVSUP
0.1.2
Fig. 4-16: Output Pins (DACA_R/L, DACM_R/L, DACM_SUB)
Gain=0.5
3.75
3-30
Fig. 4-17: (AGNDC)
3-30
Fig. 4-12: Output/Input Pins (XTALIN, XTALOUT, AUD_CL_OUT)
3.75
Fig. 4-18: Output Pins (SC_2_OUT_R/L, SC_1_OUT_R/L) Fig. 4-13: Capacitor Pins (CAPL_A, CAPL_M)
3.75
Fig. 4-14: Input (MONO_IN)
3.75
Fig. 4-15: Input Pins (SC4-1_IN_L/R)
Micronas
4519G
4.6. Electrical Characteristics 4.6.1. Absolute Maximum Ratings Symbol VSUP1 VSUP2 VSUP3 dVSUP23 PTOT Parameter Ambient Operating Temperature Storage Temperature First Supply Voltage Second Supply Voltage Third Supply Voltage Voltage between AVSUP DVSUP Package Power Dissipation PSDIP64 PQFP80 PLQFP64 Input Voltage, Digital Inputs Input Current, Digital Pins Input Voltage, Analog Inputs Input Current, Analog Inputs Output Current, SCART Outputs Output Current, Analog Outputs except SCART Outputs Output Current, other pins connected capacitors SCn_IN_s,3) MONO_IN SCn_IN_s,3) MONO_IN SCn_OUT_s3) DACp_s3) CAPL_p,3) AGNDC -0.3 -0.3
Name AHVSUP DVSUP AVSUP AVSUP, DVSUP
Min. -0.3 -0.3 -0.3 -0.5
Max. 701)
Unit
1300 1000 9601) VSUP2+0.3 VSUP1+0.3
VIdig IIdig VIana IIana IOana IOana ICana
mA2) mA2)
PLQFP64: positive value means current flowing into circuit means "1", "2", "3", "4", means "R", means analog outputs short circuit proof with respect First Supply Voltage ground. Total chip power dissipation must exceed absolute maximum rating.
Stresses beyond those listed "Absolute Maximum Ratings" cause permanent damage device. This stress rating only. Functional operation device these other conditions beyond those indicated "Recommended Operating Conditions/Characteristics" this specification implied. Exposure absolute maximum ratings conditions extended periods affect device reliability.
Micronas
4519G
4.6.2. Recommended Operating Conditions 4.6.2.1. General Recommended Operating Conditions Symbol VSUP1 Parameter First Supply Voltage (8-V Operation) First Supply Voltage (5-V Operation) VSUP2 VSUP3 tSTBYQ1 Second Supply Voltage Third Supply Voltage STANDBYQ Setup Time before Turn-off Second Supply Voltage DVSUP AVSUP STANDBYQ, DVSUP Name AHVSUP Min. 4.75 4.75 4.75
Typ.
Max. 5.25 5.25 5.25
Unit
4.6.2.2. Analog Input Output Recommendations Symbol CAGNDC Parameter AGNDC-Filter-Capacitor Ceramic Capacitor Parallel CinSC VinSC VinMONO RLSC CLSC CVMA CFMA
Name AGNDC
Min. -20% -20%
Typ.
Max.
Unit
DC-Decoupling Capacitor front SCART Inputs SCART Input Level Input Level, Mono Input SCART Load Resistance SCART Load Capacitance Main/AUX Volume Capacitor Main/AUX Filter Capacitor
SCn_IN_s1)
-20%
MONO_IN SCn_OUT_s1) CAPL_M, CAPL_A DACM_s, DACA_s1) -10% +10%
VRMS VRMS
means "1", "2", "3", means "R", means
Micronas
4519G
4.6.2.3. Crystal Recommendations Symbol Parameter Name Min. Typ. Max. Unit
General Crystal Recommendations Crystal Parallel Resonance Frequency Load Capacitance Crystal Series Resistance Crystal Shunt (Parallel) Capacitance External Load Capacitance1) XTAL_IN, XTAL_OUT 18.432
PSDIP approx. P(L)QFP approx.
Crystal Recommendations Master-Slave Applications (DPL Clock must perform synchronization clock) fTOL DTEM Accuracy Adjustment Frequency Variation versus Temperature Motional (Dynamic) Capacitance Required Open Loop Clock Frequency (Tamb AUD_CL_OUT 18.431 18.433
Crystal Recommendations other Applications synchronization clock possible) fTOL DTEM Accuracy Adjustment Frequency Variation versus Temperature Required Open Loop Clock Frequency (Tamb AUD_CL_OUT -100 18.429 +100 18.435
Amplitude Recommendation Operation with External Clock Input (Cload after reset typ. VXCA
External Clock Amplitude
XTAL_IN
External capacitors each crystal ground required. They necessary tune open-loop frequency internal stabilize frequency closed-loop operation. different layouts, accurate capacitor size should determined with customer PCB. suggested values (1.5.3.3 figures based experience should serve "start value". define capacitor size, reset without transmitting further telegrams. Measure frequency AUD_CL_OUT-pin. Change capacitor size until free running frequency matches 18.432 closely possible. higher capacity, lower resulting clock frequency.
Micronas
4519G
4.6.3. Characteristics
fCLOCK 18.432 MHz, VSUP1 VSUP2 4.75 5.25 min./max. values fCLOCK 18.432 MHz, VSUP1 VSUP2 typical values, Junction Temperature Main Main Channel, Channel
4.6.3.1. General Characteristics
Symbol Supply ISUP1A First Supply Current (active) (AHVSUP AHVSUP First Supply Current (active) (AHVSUP ISUP2A ISUP3A ISUP1S Second Supply Current (active) (DVSUP Third Supply Current (active) First Supply Current (AHVSUP First Supply Current (AHVSUP Clock fCLOCK DCLOCK tJITTER VxtalDC tStartup VACLKAC VACLKDC routHF_ACL Clock Input Frequency Clock High Ratio Clock Jitter (Verification provided Production Test) DC-Voltage Oscillator Oscillator Startup Time Slew-rate V/µs Audio Clock Output Voltage Audio Clock Output Voltage Output Resistance XTAL_IN, XTAL_OUT AUD_CL_OUT XTAL_IN 18.432 VSUP3 load Imax DVSUP AVSUP AHVSUP Standby Mode STANDBYQ Volume Main Volume Main Volume Main Volume Main Parameter Name Min. Typ. Max. Unit Test Conditions
Micronas
4519G
4.6.3.2. Digital Inputs, Digital Outputs
Symbol Parameter Name Min. Typ. Max. Unit Test Conditions
Digital Input Levels VDIGIL VDIGIH ZDIGI IDLEAK VDIGIL VDIGIH IADRSEL Digital Input Voltage Digital Input High Voltage Input Impedance Digital Input Leakage Current ADR_SEL Input Voltage ADR_SEL Input High Voltage Input Current ADR_SEL -500 -220 Digital Output Levels VDCTROL VDCTROH Digital Output Voltage Digital Output High Voltage D_CTR_I/O_0 D_CTR_I/O_1 VSUP2 IDDCTR IDDCTR STANDBYQ D_CTR_I/O_0/1 VSUP2 VSUP2 VSUP2 VSUP2 UADR_SEL= DVSS UADR_SEL= DVSUP UINPUT< DVSUP D_CTR_I/O_0/1: tri-state
Micronas
4519G
4.6.3.3. Reset Input Power-Up
Symbol Parameter Name Min. Typ. Max.
Unit
Test Conditions
RESETQ Input Levels VRHL VRLH ZRES IRES Reset High-Low Transition Voltage Reset Low-High Transition Voltage Input Impedance Input Leakage Current RESETQ 0.45 0.55 VSUP2 VSUP2 UINPUT< DVSUP
DVSUP AVSUP
VSUP2
t/ms
RESETQ
Low-to-High Threshold
Note: reset should reach high level before oscillator started. This requires reset delay
High-to-Low Threshold
VSUP2 means Volt with VSUP2 t/ms
Reset Delay
Internal Reset
High
t/ms Fig. 4-19: Power-up sequence
Micronas
4519G
4.6.3.4. I2C-Bus Characteristics
Symbol VI2CIL VI2CIH tI2C1 tI2C2 tI2C5 tI2C6 tI2C3 tI2C4 fI2C VI2COL II2COH tI2COL1 tI2COL2 Parameter I2C-BUS Input Voltage I2C-BUS Input High Voltage Name I2C_CL, I2C_DA I2C_CL I2C_CL, I2C_DA Min. Typ. Max. Unit VSUP2 VSUP2 fI2C II2COL VI2COH Test Conditions
START Condition Setup Time STOP Condition Setup Time C-Data Setup Time before Rising Edge Clock I2C-Data Hold Time after Falling Edge Clock I2C-Clock Pulse Time I2C-Clock High Pulse Time
I2C-BUS Frequency I2C-Data Output Voltage C-Data Output High Leakage Current I2C-Data Output Hold Time after Falling Edge Clock I2C-Data Output Setup Time before Rising Edge Clock
1/FI2C I2C_CL TI2C4 TI2C3
TI2C1 I2C_DA input
TI2C5
TI2C6
TI2C2
TI2COL2 I2C_DA output
TI2COL1
Fig. 4-20: timing diagram
Micronas
4519G
4.6.3.5. I2S-Bus Characteristics
Symbol VI2SIL VI2SIH ZI2SI ILEAKI2S VI2SOL VI2SOH fI2SOWS fI2SOCL RI2S10/I2S20 Parameter Input Voltage Input High Voltage Input Impedance Input Leakage Current Output Voltage Output High Voltage I2S-Word Strobe Output Frequency I2S-Clock Output Frequency I2S-Clock Output High/Low-Ratio
Name I2S_CL I2S_WS I2S_CL3 I2S_WS3 I2S_DA_IN1.3
Min.
Typ.
Max.
Unit VSUP2 VSUP2
Test Conditions
VSUP2 48.0 1.536 3.072 12.288
UINPUT< DVSUP II2SOL II2SOH
I2S_CL I2S_WS I2S_DA_OUT I2S_WS I2S_CL
Synchronous Interface ts_I2S Input Setup Time before Rising Edge Clock Input Hold Time after Rising Edge Clock Output Delay Time after Falling Edge Clock I2S-Word Strobe Input Frequency I2S-Clock Input Frequency S-Clock Input Ratio
I2S_DA_IN1/2 I2S_CL
details Fig. 4-21 "I2S timing diagram (synchronous interface)"
th_I2S td_I2S
I2S_CL I2S_WS I2S_DA_OUT I2S_WS I2S_CL 1.536 48.0 3.072 12.288
CL=30
fI2SWS fI2SCL RI2SCL
Asynchronous Interface ts_I2S3 th_I2S3 fI2S3WS fI2S3CL RI2S3CL I2S3 Input Setup Time before Rising Edge Clock I2S3 Input Hold Time after Rising Edge Clock I2S3-Word Strobe Input Frequency I2S3-Clock Input Frequency I2S3-Clock Input Ratio I2S_CL3 I2S_WS3 I2S_DA_IN3 I2S_WS3 I2S_CL3 details Fig. 4-22 "I2S timing diagram (asynchronous interface)"
Micronas
4519G
1/FI2SWS I2S_WS
MODUS[6] MODUS[6]
Detail
I2S_CL Detail I2S_DA_IN*)
16/32 left channel Detail I2S_DA_OUT
16/32 right channel
16/32 left channel
16/32 right channel
Data: first, synchronous master
1/FI2SWS I2S_WS
MODUS[6] MODUS[6]
Detail
I2S_CL Detail I2S_DA_IN*)
16,18.32 left channel Detail I2S_DA_OUT
18.32 right channel
18.32 left channel
18.32 right channel
Data: first, synchronous slave
Note:
I2S_DA_IN I2S_DA_IN1, I2S_DA_IN2, I2S_DA_IN2/3
Detail
I2S_CL
1/FI2SCL
Detail
I2S_CL
Ts_I2S Ts_I2S I2S_DA_IN1) I2S_WS INPUT
Th_I2S
Td_I2S
Td_I2S
I2S_WS OUTPUT
I2S_DA_OUT
Fig. 4-21: timing diagram (synchronous interface)
Micronas
4519G
I2S_CL3 1/FI2S3WS
Left sample (I2S_CONFIG[10] Right sample (I2S_CONFIG[10] Right sample (I2S_CONFIG[10] Left aligned (I2S_CONFIG[9] 16,18.32 data clocks allowed Left aligned (I2S_CONFIG[9] 16,18.32 data clocks allowed
I2S_WS3
Left sample S_CONFIG[10]
I2S_DA_IN3
I2S_DA_IN3
Right aligned (I2S_CONFIG[11] I2S_CONFIG[9] data 16.32 clocks allowed
I2S_DA_IN3
1/FI2S3CL I2S_CL3
Ts_I2S3 Th_I2S3
I2S_DA_IN3 Ts_I2S3
I2S_WS3
Fig. 4-22: timing diagram (asynchronous interface)
4.6.3.6. Analog Baseband Inputs Outputs, AGNDC
Symbol Parameter Name Min. Typ. Max. Unit Test Conditions
Analog Ground VAGNDC0 AGNDC Open Circuit Voltage AHVSUP AHVSUP RoutAGN AGNDC Output Resistance AHVSUP AHVSUP Analog Input Resistance RinSC RinMONO
AGNDC
Rload
VAGNDC
SCART Input Resistance from MONO Input Resistance from
SCn_IN_s1) MONO_IN
fsignal kHz, 0.05 fsignal kHz,
means "1", "2", "3", "4";
means
Micronas
4519G
Symbol
Parameter
Name
Min.
Typ.
Max.
Unit
Test Conditions
Audio Analog-to-Digital-Converter VAICL Analog Input Clipping Level Analog-to-Digital-Conversion (AHVSUP=8 Analog Input Clipping Level Analog-to-Digital-Conversion (AHVSUP=5 SCART Outputs RoutSC dVOUTSC ASCtoSC frSCtoSC VoutSC SCART Output Resistance Deviation DC-Level SCART Output from AGNDC Voltage Gain from Analog Input SCART Output Frequency Response from Analog Input SCART Output Signal Level SCART-Output (AHVSUP=8 Signal Level SCART-Output (AHVSUP=5 Main Outputs RoutMA Main/Aux Output Resistance DACp_s1) 1.80 1.12 1.23 0.76 means 2.28 1.60 1.51 1.04 VRMS VRMS fsignal kHz, 27°C from 70°C Volume Volume Volume Volume fsignal full scale Digital Input from Volume SCn_IN_s,1) MONO_IN SCn_OUT_s1) SCn_OUT_s1) SCn_OUT_s1) -1.0 -0.5 1.17 1.27 +0.5 +0.5 1.37 VRMS VRMS fsignal with resp. fsignal full scale Digital Input from fsignal kHz, 27°C, 70°C SCn_IN_s,1) MONO_IN 2.00 2.25 VRMS fsignal
1.13
1.51
VRMS
VoutDCMA
DC-Level Main/Aux-Output (AHVSUP=8 DC-Level Main/Aux-Output (AHVSUP=5
2.04 1.36 1.37 0.90
VoutMA
Signal Level Main/Aux-Output (AHVSUP=8 Signal Level Main/Aux-Output (AHVSUP=5
means "1", "2", "3", "4";
means "R";
Micronas
4519G
4.6.3.7. Power Supply Rejection
Symbol Parameter Name Min. Typ. Max.
Unit
Test Conditions
PSRR: Rejection Noise AHVSUP PSRR AGNDC From Analog Input Output From Analog Input SCART Output From Input SCART Output From
AGNDC MONO_IN, SCn_IN_s1) MONO_IN, SCn_IN_s1) SCn_OUT_s1) SCn_OUT_s1) DACp_s1) means
Input Main/Aux Output
means "1", "2", "3", "4";
means "R";
4.6.3.8. Analog Performance
Symbol Parameter Name Min. Typ. Max. Unit Test Conditions
Specifications AHSUP=8 Signal-to-Noise Ratio from Analog Input Output MONO_IN, SCn_IN_s1) Input Level with resp. VAICL, fsig kHz, A-weighted Hz.20 Input Level fsig kHz, A-weighted Hz.20 Volume
from Analog Input SCART Output
MONO_IN, SCn_IN_s1) SCn_OUT_s1) SCn_OUT_s1) DACp_s1)
from Input SCART Output from Input Main/Aux-Output Total Harmonic Distortion from Analog Input Output
MONO_IN, SCn_IN_s1)
0.01
0.03
Input Level with resp. VAICL, fsig kHz, unweighted Hz.20 Input Level dBr, fsig kHz, unweighted Hz.20
from Analog Input SCART Output
MONO_IN, SCn_IN_s SCn_OUT_s1) SCn_OUT_s1) DACA_s, DACM_s1) means
0.01
0.03
from Input SCART Output from
0.01 0.01
0.03 0.03
Input Main Out-
means "1", "2", "3", "4";
means "R";
Micronas
4519G
Symbol
Parameter
Name
Min.
Typ.
Max.
Unit
Test Conditions
Specifications AHSUP=5 Signal-to-Noise Ratio from Analog Input Output MONO_IN, SCn_IN_s1) Input Level with resp. VAICL, fsig kHz, A-weighted Hz.20 Input Level fsig kHz, A-weighted Hz.20 Volume
from Analog Input SCART Output
MONO_IN, SCn_IN_s1) SCn_OUT_s1) SCn_OUT_s1) DACp_s1)
from Input SCART Output from Input Main/Aux-Output Analog Volume Analog Volume Total Harmonic Distortion from Analog Input Output
MONO_IN, SCn_IN_s1)
0.03
Input Level with resp. VAICL, fsig kHz, unweighted Hz.20 Input Level dBr, fsig kHz, unweighted Hz.20
from Analog Input SCART Output
MONO_IN, SCn_IN_s SCn_OUT_s1) SCn_OUT_s1) DACA_s, DACM_s1) means
from Input SCART Output from Input Main Output
means "1", "2", "3", "4";
means "R";
Micronas
4519G
Symbol
Parameter
Name
Min.
Typ.
Max.
Unit
Test Conditions
Crosstalk Specifications XTALK Crosstalk Attenuation Input Level fsig kHz, unused analog inputs connected ground unweighted Hz.20 unweighted Hz.20
between left right channel within SCART Input/Output pair (LR, SCn_IN SCn_OUT1) SC1_IN SC2_IN Output
SC3_IN Output Input SCn_OUT1)
between left right channel within Main Output pair Input DACp1) between SCART Input/Output pairs disturbing program observed program MONO/SCn_IN SCn_OUT MONO/SCn_IN SCn_OUT1) MONO/SCn_IN SCn_OUT unsel. MONO/SCn_IN Output MONO/SCn_IN SCn_OUT Input SCn_OUT1) MONO/SCn_IN unselected Input SC1_OUT1) Crosstalk between Main Output pairs Input DACp1)
(unweighted Hz.20 kHz) same signal source left right disturbing channel, effect each observed output channel
(unweighted Hz.20 kHz) same signal source left right disturbing channel, effect each observed output channel (unweighted Hz.20 kHz) same signal source left right disturbing channel, effect each observed output channel
XTALK
Crosstalk from Main Output SCART Output vice versa disturbing program observed program MONO/SCn_IN/DSP SCn_OUT Input DACp1) MONO/SCn_IN/DSP SCn_OUT Input DACp1) Input DACp MONO/SCn_IN SCn_OUT1) Input DACM Input SCn_OUT1) means
SCART output load resistance SCART output load resistance
means "1", "2", "3", "4";
means "R";
Micronas
4519G
Appendix Application Information 5.1. Phase Relationship Analog Outputs analog output signals: Main, Aux, SCART2 have same phases. SCART1 output opposite phase. Using I2S-outputs other DSPs converters, care must taken adjust correct phase.
I2S_IN1/2/3
I2S_OUT1/2
Main
SCART1-Ch. Audio Baseband Processing SCART1 SCART2 SCART3 SCART4 MONO MONO, SCART1.4 SCART Output Select SCART2 SCART1
Fig. 5-1: Phase diagram 4519G
Micronas
4519G
5.2. Application Circuit
section 4.6.2.
18.432
XTAL_IN (62)
AGNDC (42)
XTAL_OUT (63)
CAPL_M (40)
CAPL_A (38)
DACM_L (29) DACM_R (28)
left
(55) MONO_IN
right
AHVSS AHVSS AHVSS
(52) SC1_IN_L (53) SC1_IN_R (51) (49) SC2_IN_L (50) SC2_IN_R (48) (46) SC3_IN_L (47) SC3_IN_R (45) (43) SC4_IN_L (44) SC4_IN_R DACA_R (25) DACA_L (26) DACM_SUB (31)
Subwoofer
Center
Surround
DVSS
4519G
SC1_OUT_L (37)
STANDBYQ ADR_SEL
SC1_OUT_R (36)
DVSS (10) I2C_DA I2C_CL SC2_OUT_L (34)
SC2_OUT_R (33) D_CTR_I/O_0 (12) I2S_WS (11) I2S_CL (14) I2S_DA_IN1 (20) I2S_DA_IN2 (13) I2S_DA_OUT (39) AHVSUP (24) RESETQ (18) DVSUP (57) AVSUP (19) DVSS (56) AVSS TESTEN (61) (41) AHVSS (35) VREF1 (27) VREF2 AUD_CL_OUT D_CTR_I/O_1
AHVSS
RESETQ (from Controller, section 4.6.3.3.)
Note:
Decoupling capacitors from DVSUP DVSS, AVSUP AVSS, AHVSUP AHVSS recommended closely possible supply pins (see application note page 42).
AHVSS
AHVSS
Note: numbers refer PQFP80 package, numbers brackets refer PSDIP64 package.
AHVSS
AVSS
Micronas
4519G
Micronas
4519G
Data Sheet History Preliminary data sheet: "DPL 4519G Sound Processor Digital Analog Surround Systems", Oct. 2000, 6251-512-1PD. First release preliminary data sheet.
Micronas GmbH Hans-Bunte-Strasse D-79108 Freiburg (Germany) P.O. D-79008 Freiburg (Germany) Tel. +49-761-517-0 +49-761-517-2174 E-mail: docservice@micronas.com Internet: www.micronas.com Printed Germany Order 6251-512-1PD
information data contained this data sheet without commitment, considered offer conclusion contract, shall they construed create liability. issue this data sheet invalidates previous issues. Product availability delivery exclusively subject respective order confirmation form; same applies orders based development samples delivered. this publication, Micronas GmbH does assume responsibility patent infringements other rights third parties which result from use. Further, Micronas GmbH reserves right revise this publication make changes content, time, without obligation notify person entity such revisions changes. part this publication reproduced, photocopied, stored retrieval system, transmitted without express written consent Micronas GmbH.
Micronas
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