34x0G Multistandard Sound Processor Family Edition 2003 6251-476-
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34x0G Multistandard Sound Processor Family
Edition 2003 6251-476-1DS
34x0G
Contents Page Section 1.1. 1.2. 1.3. 2.1. 2.2. 2.2.1. 2.2.2. 2.2.3. 2.2.4. 2.2.5. 2.3. 2.4. 2.5. 2.5.1. 2.5.2. 2.5.3. 2.5.4. 2.5.5. 2.5.6. 2.5.7. 2.5.8. 2.5.8.1. 2.5.8.2. 2.5.8.3. 2.6. 2.6.1. 2.6.2. 2.7. 2.8. 2.9. 2.10. 3.1. 3.1.1. 3.1.2. 3.1.3. 3.1.4. 3.1.4.1. 3.1.4.2. 3.1.4.3. 3.1.4.4. 3.2. 3.3. Title Introduction Features 34x0G Family 34x0G Version List 34x0G Versions their Application Fields Functional Description Architecture 34x0G Family Sound Processing Analog Sound Input Demodulator: Standards Features Preprocessing Demodulator Signals Automatic Sound Select Manual Mode Preprocessing SCART Input Signals Source Selection Output Channel Matrix Audio Baseband Processing High Definition Sound Micronas VOICE Automatic Volume Correction (AVC) Loudspeaker Headphone Outputs Subwoofer Output Quasi-Peak Detector Micronas BASS (MB) Dynamic Amplification Adding Harmonics Micronas BASS Parameters SCART Signal Routing SCART SCART Select Stand-by Mode Interface Interface Digital Control Pins Status Change Indication Clock Oscillator Crystal Specifications Control Interface Interface Internal Hardware Error Handling Description CONTROL Register Protocol Description Proposals General 34x0G Telegrams Symbols Write Telegrams Read Telegrams Examples Start-Up Sequence: Power-Up I2C-Controlling 34x0G Programming Interface
2003; 6251-476-1DS
Micronas
34x0G
Contents, continued Page Section 3.3.1. 3.3.2. 3.3.2.1. 3.3.2.2. 3.3.2.3. 3.3.2.4. 3.3.2.5. 3.3.2.6. 3.3.2.7. 3.4. 3.5. 3.5.1. 3.5.2. 3.5.3. 3.5.4. 3.5.5. 3.5.6. 4.1. 4.2. 4.3. 4.4. 4.5. 4.6. 4.6.1. 4.6.2. 4.6.2.1. 4.6.2.2. 4.6.2.3. 4.6.2.4. 4.6.3. 4.6.3.1. 4.6.3.2. 4.6.3.3. 4.6.3.4. 4.6.3.5. 4.6.3.6. 4.6.3.7. 4.6.3.8. 4.6.3.9. 4.6.3.10. Title User Registers Overview Description User Registers STANDARD SELECT Register Refresh STANDARD SELECT Register STANDARD RESULT Register Write Registers Subaddress 10hex Read Registers Subaddress 11hex Write Registers Subaddress 12hex Read Registers Subaddress 13hex Programming Tips Examples Minimum Initialization Codes B/G-FM NICAM) BTSC-Stereo BTSC-SAP with Loudspeaker Channel FM-Stereo Radio Automatic Standard Detection Software Flow Interrupt driven STATUS Check Specifications Outline Dimensions Connections Short Descriptions Descriptions Configurations Circuits Electrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions General Recommended Operating Conditions Analog Input Output Recommendations Recommendations Analog Sound Input Signal Crystal Recommendations Characteristics General Characteristics Digital Inputs, Digital Outputs Reset Input Power-Up I2C-Bus Characteristics I2S-Bus Characteristics Analog Baseband Inputs Outputs, AGNDC Sound Inputs Power Supply Rejection Analog Performance Sound Standard Dependent Characteristics
Micronas
2003; 6251-476-1DS
34x0G
Contents, continued Page Section 5.1. 5.2. 5.3. 5.4. 5.5. 5.6. 6.1. 6.2. 6.3. 6.3.1. 6.3.1.1. 6.3.1.2. 6.3.2. 6.3.3. 6.3.4. 6.3.5. 6.3.6. 6.3.7. 6.4. 6.4.1. 6.4.2. 6.4.3. 6.4.4. 6.4.5. 6.4.6. 6.4.7. 6.5. 6.5.1. 6.5.2. 6.5.3. 6.5.4. 6.5.5. 6.5.6. 6.5.7. 6.6. 6.6.1. 6.6.2. 6.7. 6.7.1. 6.7.2. 6.8. 6.9. Title Appendix Overview TV-Sound Standards NICAM A2-Systems BTSC-Sound System Japanese Stereo System (EIA-J) Satellite Sound FM-Stereo Radio Appendix Manual/Compatibility Mode Demodulator Write Read Registers Manual/Compatibility Mode Write Read Registers Manual/Compatibility Mode Manual/Compatibility Mode: Description Demodulator Write Registers Automatic Switching between NICAM Analog Sound Function Automatic Sound Select Mode Function Manual Mode Threshold Carrier-Mute Threshold Register AD_CV Register MODE_REG FIR-Parameter, Registers FIR1 FIR2 DCO-Registers Manual/Compatibility Mode: Description Demodulator Read Registers NICAM Mode Control/Additional Data Bits Register Additional Data Bits Register Bits Register NICAM Error Rate Register PLL_CAPS Readback Register AGC_GAIN Readback Register Automatic Search Function FM-Carrier Detection Satellite Mode Manual/Compatibility Mode: Description Write Registers Additional Channel Matrix Modes Volume Modes SCART1/2 Outputs Fixed Deemphasis Adaptive Deemphasis NICAM Deemphasis Identification Mode Stereo Systems Notch Manual/Compatibility Mode: Description Read Registers Stereo Detection Register Stereo Systems Level Register Demodulator Source Channels Manual Mode Terrestric Sound Standards Sound Standards Exclusions Audio Baseband Features Compatibility Restrictions 34x0D
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34x0G
Contents, continued Page Section 7.1. 7.2. Title Appendix Application Information Phase Relationship Analog Outputs Application Circuit Appendix 34x0G Version History Data Sheet History
License Notice: "Dolby Logic" trademark Dolby Laboratories. Supply this implementation Dolby Technology does convey license imply right under patent, other industrial intellectual property right Dolby Laboratories, this implementation finished end-user ready-to-use final product. Companies planning this implementation products must obtain license from Dolby Laboratories Licensing Corporation before designing such products.
Micronas
2003; 6251-476-1DS
34x0G
Multistandard Sound Processor Family Release Note: Revision bars indicate significant changes previous edition. hardware software description this document valid 34x0G version following versions.
Current have perform adjustment procedures order achieve good stereo separation BTSC EIA-J. 34x0G optimum stereo performance without adjustments. 34xxG versions compatible 34xxD. Only minor modifications necessary adapt 34xxD controlling software 34xxG. 34x0G further simplifies controlling software. Standard selection requires single transmission only. 34x0G built-in automatic functions: able detect actual sound standard automatically (Automatic Standard Detection). Furthermore, pilot levels identification signals evaluated internally with subsequent switching between mono/ stereo/bilingual; interaction necessary (Automatic Sound Selection). 34x0G handle very high deviations even conjunction with NICAM processing. This especially important introduction NICAM China. produced submicron CMOS technology. 34x0G available following packages: PSDIP64-1, PSDIP52-1/-2, PMQFP80-11, PMQFP64-2.
Introduction 34x0G family single-chip Multistandard Sound Processors covers sound processing analog TV-Standards worldwide, well NICAM digital sound standards. full sound processing, starting with analog sound signal-in, down processed analog AF-out, performed single chip. Figure shows simplified functional block diagram 34x0G. These sound processing include versions processing multichannel television sound (MTS) signal conforming standard recommended Broadcast Television Systems Committee (BTSC). noise reduction, alternatively, Micronas Noise Reduction (MNR) performed alignment free. Other processed standards Japanese FM-FM multiplex standard (EIA-J) Stereo Radio standard.
Sound Sound
Demodulator
Preprocessing
Loudspeaker Sound Processing
Loudspeaker Subwoofer
Source Select
I2S2 SCART1
Headphone Sound Processing
Headphone
Prescale
SCART2 SCART3 SCART4 MONO
SCART Input Select
SCART1 Prescale SCART Output Select SCART2
Fig. 1-1: Simplified functional block diagram 34x0G
2003; 6251-476-1DS
Micronas
34x0G
1.1. Features 34x0G Family
Feature Standard Selection with single transmission Automatic Standard Detection terrestrial standards/Automatic Carrier Mute function Automatic Sound Selection (mono/stereo/bilingual), registers MODUS, STATUS selectable sound (SIF) inputs Automatic Carrier Mute function Interrupt output programmable (indicating status change) Loudspeaker Headphone channel with volume, balance, bass, treble, loudness AVC: Automatic Volume Correction Subwoofer output with programmable low-pass complementary high-pass filter Micronas BASS (MB) 5-band graphic equalizer loudspeaker channel Spatial effect loudspeaker channel Four Stereo SCART (line) inputs, Mono input; Stereo SCART outputs Complete SCART in/out switching matrix inputs; output analog Mono sound carriers including AM-SECAM Korean FM-Stereo standard analog FM-Stereo satellite standards Simultaneous demodulation (very) high-deviation FM-Mono NICAM Adaptive deemphasis satellite (Wegener-Panda, acc. ASTRA specification) ASTRA Digital Radio (ADR) together with 3510A NICAM standards Demodulation BTSC multiplex signal channel Alignment free digital noise reduction BTSC Stereo Alignment free digital Micronas Noise Reduction (MNR) BTSC Stereo BTSC stereo separation (MSP 3420/40G also EIA-J) significantly better than spec. stereo detection BTSC system Alignment-free Japanese standard EIA-J Demodulation FM-Radio multiplex signal 3400 3410 3420 3440 3450 3460
1.2. 34x0G Version List
Version 3400G 3410G 3420G 3440G 3450G 3460G Status available available available available available available Description Stereo (A2) Version NICAM Stereo (A2) Version NTSC Version Korea, BTSC with Micronas Noise Reduction (MNR), Japanese EIA-J system) NTSC Version Korea, BTSC with noise reduction, Japanese EIA-J system) Global Version (all sound standards) Global Mono Version (all sound standards)
Micronas
2003; 6251-476-1DS
34x0G
1.3. 34x0G Versions their Application Fields Table provides overview sound standards that processed 34x0G family. addition, 34x0G able handle FM-Radio standard. With 34x0G, complete
multimedia receiver covering sound standards together with terrestrial/cable satellite radio sound built; even ASTRA Digital Radio processed (with 3510A coprocessor).
Table 1-1: Stereo Sound Standards covered 34x0G Family (details Appendix
Version 3400 TVSystem 5.5/5.85 6.5/5.85 6.0/6.552 6.5/6.2578125 3400 3410 6.5/6.7421875 6.5/5.7421875 3450 6.5/5.85 7.02/7.2 7.38/7.56 etc. 4.5/4.724212 3420, 3440 FM-Radio 3460 10.7 FM-Stereo (A2, D/K3) FM-Mono/NICAM (D/K, NICAM) FM-Mono FM-Stereo ASTRA Digital Radio (ADR) with 3510A FM-Stereo (A2) FM-FM (EIA-J) BTSC-Stereo FM-Stereo Radio SECAM-East Poland China, Hungary FM-Mono/NICAM AM-Mono/NICAM FM-Mono/NICAM FM-Stereo (A2, D/K1) FM-Stereo (A2, D/K2) SECAM-L SECAM-East Scandinavia, Spain France Hong Kong Slovak. Rep. currently broadcast Position Sound Carrier /MHz 5.5/5.7421875 Sound Modulation FM-Stereo (A2) Color System Broadcast e.g. Germany
3400
Satellite
Europe Sat. ASTRA
NTSC NTSC NTSC,
Korea Japan USA, Argentina USA, Europe
Standards above Mono demodulation only.
Filter Tuner Sound Mixer
Loudspeaker
Mono Vision Demodulator SCART1
Subwoofer
34x0G
Headphone
Composite Video
SCART Inputs
SCART2 SCART3 SCART4
SCART1 SCART2
SCART Outputs
I2S1
I2S2
Dolby Logic Processor 351xA
Decoder 3510A
Fig. 1-2: Typical 34x0G application
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Micronas
Functional Description
ANA_IN1+ ANA_IN2+ DEMODULATOR (incl. Carrier Mute) Standard Selection Deemphasis: 50/75 DBX/MNR Panda1 FM/AM Automatic Sound Select
FM/AM
Source Select
SCART Input Select
(13hex)
SC1_IN_L SC1_IN_R SC2_IN_L SC2_IN_R SC3_IN_L SC3_IN_R SC4_IN_L SC4_IN_R MONO_IN
(41hex)
(40hex)
SCART Output Select
Micronas
2003; 6251-476-1DS
Prescale
(0Ehex)
Stereo
Loudspeaker Channel Matrix
(08hex)
(29hex)
Bass/ Treble Equalize
(02hex) (03hex)
Loudness
(04hex)
Complementary Spatial Balance Highpass Effects
(2Dhex) (05hex) (01hex)
Volume
DACM_L
DACM_R
(00hex)
ADR-Bus Interface
Decoded Standards: NICAM BTSC EIA-J FM-Radio
NICAM Deemphasis Prescale
(10hex)
Stereo
Lowpass Beeper
(14hex) (2Dhex)
Level Adjust
hex)
DACM_SUB
Stereo
Standard Sound Detection
Read Register
I2S_DA_IN1 Interface Prescale
(16hex)
Headphone Channel Matrix
(09hex)
Volume Bass/ Treble
(31/32hex)
Loudness
Balance
DACA_L
(33hex)
(30hex)
(06hex)
DACA_R
I2S_DA_IN2 Interface Prescale
(12hex)
Channel Matrix
(0Bhex)
Interface
I2S_DA_OUT
Quasi-Peak Channel Matrix
(0Chex)
Quasi-Peak Detector
Read Register
(19hex) (1Ahex)
SCART Prescale
(0Dhex)
SCART1 Channel Matrix
(0Ahex)
Volume
SCART1_L/R
(07hex)
SCART2 Channel Matrix
Volume
SCART2_L/R
SC1_OUT_L
SC1_OUT_R
34x0G
SC2_OUT_L
SC2_OUT_R
(13hex)
Fig. 2-1: Signal flow block diagram 34x0G (input output names correspond names)
34x0G
2.1. Architecture 34x0G Family Fig. page shows simplified block diagram block diagram contains features 3450G. Other members 34x0G family have complete features: demodulator handles only subset standards presented demodulator block; NICAM processing only possible 3410G 3450G.
BTSC-Mono SAP: Detection demodulation aural carrier resulting MTS/MPX signal. Detection evaluation pilot carrier, detection demodulation subcarrier. Processing noise reduction Micronas Noise Reduction (MNR). Japan Stereo: Detection demodulation aural carrier resulting signal. Demodulation evaluation identification signal demodulation (L-R)-carrier. FM-Satellite Sound: Demodulation carriers. Processing high-deviation mono narrow bandwidth mono, stereo, bilingual satellite sound according ASTRA specification. FM-Stereo-Radio: Detection demodulation aural carrier resulting signal. Detection evaluation pilot carrier demodulation (L-R)-carrier. demodulator blocks 34x0G versions have identical user interfaces. Even completely different systems like BTSC NICAM systems controlled same way. Standards selected means Standard Codes. Automatic processes handle standard detection identification without controller interaction. features 34x0G demodulator blocks are: Standard Selection: controlling demodulator minimized: parameters, such tuning frequencies filter bandwidth, adjusted automatically transmitting single value STANDARD SELECT register. standards, specific standard codes defined. Automatic Standard Detection: sound standard unknown, 34x0G automatically detect actual standard, switch that standard, respond actual standard code. Automatic Carrier Mute: prevent noise effects identification problems absence carrier, 34x0G offers configurable carrier mute feature, which activated automatically sound standard selected means STANDARD SELECT register. carrier detected demodulator channels, corresponding demodulator output muted. This indicated STATUS register.
2.2. Sound Processing 2.2.1. Analog Sound Input input pins ANA_IN1+, ANA_IN2+, ANA_IN- offer possibility connect different sound (SIF) sources 34x0G. analog-to-digital conversion preselected sound signal done A/D-converter. analog automatic gain circuit (AGC) allows wide range input levels. highpass filters formed coupling capacitors pins ANA_IN1+ ANA_IN2+ Section 7.2. "Application Circuit" page sufficient most cases suppress video components. Some combinations filters sound mixer ICs, however, show large picture components their outputs. this case, further filtering recommended.
2.2.2. Demodulator: Standards Features 34x0G able demodulate TV-sound standards worldwide including digital NICAM system. Depending 34x0G version, following demodulation modes performed: Systems: Detection demodulation separate carriers (FM1 FM2), demodulation evaluation identification signal carrier FM2. NICAM Systems: Demodulation decoding NICAM carrier, detection demodulation analog carrier. D/K-NICAM, carrier have maximum deviation kHz. Very high deviation FM-Mono: Detection robust demodulation carrier with maximum deviation kHz. BTSC-Stereo: Detection demodulation aural carrier resulting MTS/MPX signal. Detection evaluation pilot carrier, demodulation (L-R)-carrier detection subcarrier. Processing noise reduction Micronas Noise Reduction (MNR).
2003; 6251-476-1DS
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34x0G
"Stereo channel: Analog digital mono sound, stereo available. case bilingual broadcast, contains language left right). "Stereo channel: Analog digital mono sound, stereo available. case bilingual broadcast, contains language left right). Fig. Table show source channel assignment demodulated signals case Automatic Sound Select mode sound standards. Note: analog primary input channel contains signal mono FM/AM carrier signal carrier. secondary input channel contains signal carrier, signal carrier, signal.
2.2.3. Preprocessing Demodulator Signals NICAM signals must processed deemphasis filter adjusted level. analog demodulated signals must processed deemphasis filter, adjusted level, dematrixed. correct deemphasis filters already selected setting standard STANDARD SELECT register. level adjustment done means NICAM prescale registers. necessary dematrix function depends selected sound standard actual broadcasted sound mode (mono, stereo, bilingual). manually Matrix Mode register automatically Automatic Sound Selection.
2.2.4. Automatic Sound Select Automatic Sound Select mode, dematrix function automatically selected based identification information STATUS register. interaction necessary when broadcasted sound mode changes (e.g. from mono stereo). demodulator supports identification check switching between mono-compatible standards (standards that have same FM-Mono carrier) automatically non-audible. B/G-FM B/G-NICAM selected, will switch between these standards. same action performed standards: D/K1-FM, D/K2-FM, D/K3-FM D/K-NICAM. Switching only done absence stereo bilingual identification. identification found, keeps detected standard. case high bit-error rates, 34x0G automatically falls back from digital NICAM sound analog mono. Table summarizes actions that take place when Automatic Sound Select switched
primary channel primary channel secondary channel
FM/AM Prescale
FM/AM
Matrix Source Select
NICAM
NICAM
Automatic Sound Select
Stereo
Stereo
Output-Ch. matrices must once stereo.
NICAM
Prescale
Stereo
Fig. 2-2: Source channel assignment demodulated signals Automatic Sound Select Mode
2.2.5. Manual Mode Fig. shows source channel assignment demodulated signals case manual mode. manual mode required, more information found Section 6.7. "Demodulator Source Channels Manual Mode" page 101.
FM/AM FM-Matrix
FM/AM
Matrix Source Select
provide more flexibility, Automatic Sound Select block prepares four different source channels demodulated sound (Fig. 2-2). choosing four demodulator channels, preferred sound mode selected each output channels (loudspeaker, headphone, etc.). This done means Source Select registers. following source channels demodulated sound defined: "FM/AM" channel: Analog mono sound, stereo available. case NICAM, analog mono only mono). "Stereo A/B" channel: Analog digital mono sound, stereo available. case bilingual broadcast, contains both languages (left) (right).
secondary channel
Prescale
NICAM
NICAM
NICAM (Stereo A/B)
Output-Ch. matrices must according standard.
NICAM
Prescale
Fig. 2-3: Source channel assignment demodulated signals Manual Mode
2.3. Preprocessing SCART Input Signals SCART inputs need only adjusted level means SCART prescale registers.
Micronas
2003; 6251-476-1DS
34x0G
Table 2-1: Performed actions Automatic Sound Selection
Selected Sound Standard B/G-FM, D/K-FM, M-Korea, M-Japan B/G-NICAM, L-NICAM, I-NICAM, D/K-NICAM Performed Actions
Evaluation identification signal automatic switching mono, stereo, bilingual. Preparing four demodulator source channels according Table 2-2. Evaluation NICAM-C-bits automatic switching mono, stereo, bilingual. Preparing four demodulator source channels according Table 2-2. case NICAM reception, switches automatically FM/AM mono switches back NICAM possible. hysteresis prevents periodical switching.
B/G-FM, B/G-NICAM D/K1-FM, D/K2-FM, D/K3-FM, D/K-NICAM
Automatic searching stereo/bilingual-identification case mono transmission. Automatic nonaudible changes between Dual-FM FM-NICAM standards while listening basic FM-mono sound carrier. Example: starting with B/G-FM-Stereo, there will periodical alternation B/G-NICAM absence FM-Stereo/Bilingual NICAM-identification. Once identification detected, keeps corresponding standard. Evaluation pilot signal automatic switching mono stereo. Preparing four demodulator source channels according Table 2-2. Detection carrier. absence SAP, switches BTSC-stereo available. detected, switches automatically (see Table 2-2).
BTSC-STEREO, Radio M-BTSC-SAP
Table 2-2: Sound modes demodulator source channels with Automatic Sound Select
Source Channels Automatic Sound Select Mode Broadcasted Sound Standard M-Korea B/G-FM D/K-FM M-Japan Selected Standard Code3) 081) 0B1) Broadcasted Sound Mode MONO STEREO BILINGUAL: Languages B/G-NICAM L-NICAM I-NICAM D/K-NICAM D/K-NICAM
(with high deviation
FM/AM
(source select:
Stereo
(source select:
Stereo
(source select:
Stereo
(source select:
Mono Stereo Left Right analog Mono analog Mono analog Mono analog Mono Mono Stereo Mono Stereo Left Mono Right Left Mono Right Mono Stereo
Mono Stereo Left Right analog Mono NICAM Mono NICAM Stereo Left NICAM Right NICAM Mono Stereo Mono Stereo Left Mono Right Left Mono Right Mono Stereo
Mono Stereo analog Mono NICAM Mono NICAM Stereo NICAM Mono Stereo Mono Stereo Mono Mono Mono Stereo
Mono Stereo analog Mono NICAM Mono NICAM Stereo NICAM Mono Stereo Mono Stereo Mono Stereo
032) 042), 052)
NICAM available error rate high MONO STEREO BILINGUAL: Languages
MONO STEREO
BTSC
MONO STEREO MONO STEREO
Radio
MONO STEREO
Automatic Sound Select process will automatically switch mono compatible analog standard. Automatic Sound Select process will automatically switch mono compatible digital standard. Standard Codes defined (see Table page 23).
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34x0G
2.5.2. High Definition Sound License Notice: registered trademark Sound Inc., Logo trademark Sound Inc. license from Sound Inc. required before BBE-version 34x0G purchased. High Definition Sound also called, Sonic Maximizer technology improves clarity music when played back loudspeakers. more "life like" feeling created BBE. BBE-approved Micronas implementation works digital domain thus needs external components does suffer from tolerances aging effects. 34x0G shipped without except otherwise ordered. When BBE-version 34x0G ordered, carries special marking chip identification. Sonic Maximizer functionality must enabled writing "license key" into 34x0G. information obtain this license from Micronas, please contact your Micronas sales representative.
2.4. Source Selection Output Channel Matrix Source Selector makes possible distribute source signals (one demodulator source channels, SCART, input) desired output channels (loudspeaker, headphone, etc.). input output signals processed simultaneously. Each source channel identified unique source address. each output channel, sound mode sound sound stereo, mono means output channel matrix. Automatic Sound Select output channel matrix stay fixed stereo (transparent) demodulated signals.
2.5. Audio Baseband Processing 2.5.1. License Notice: SRS, WOW, Logo trademarks Labs, Inc. license from Labs, Inc. required before SRS-version 34x0G purchased. Labs' technology enlarges sound image field improves bass performance television speakers. Manufacturers save costs licensing while utilizing smaller speakers still provide higher quality audio experience. consists three sections: Clarity Improvement, 3D-Audio (SRS, Sound Retrieval System), Bass Enhancement (TruBass).
2.5.3. Micronas VOICE Micronas VOICE developed following improvements speech signals: Increase speech signal over background noise increase intelligibility noisy environments Move voice foreground, closer listener, while other sounds moved back Improve voices that hard understand, leave clear voices largely undisturbed Micronas VOICE dynamically enhances those portions speech that important intelligibility while same time decreasing portions signal that disturb intelligibility. average amplitude signal changed. According speech theory, there main effects that affect intelligibility speech. Micronas VOICE combines both effects achieve maximum enhancement intelligibility. Forward backward masking: intelligibility, consonants more important than vowels, amplitude consonants much lower than that vowels. consonants masked vowels. Therefore, amplitude consonants increased amplitude vowels decreased. Phonemes formants: Most important intelligibility second fourth formants speech. These formants detected increased, while other parts signal decreased.
features include: Wider taller sound image field Larger sweet spot Deep, rich bass tones Quality improvements audio listening experience Improved clarity speech 34x0G shipped without except otherwise ordered. When SRS-version 34x0G ordered, carries special marking chip identification. functionality must enabled writing "license key" into 34x0G. information obtain this license from Micronas, please contact your Micronas sales representative.
Micronas
2003; 6251-476-1DS
34x0G
34x0G shipped without Micronas VOICE except otherwise ordered. When Micronas VOICE version 34x0G ordered, carries special marking chip identification. Micronas VOICE functionality must enabled writing "license key" into 34x0G. information obtain this license from Micronas, please contact your Micronas sales representative.
2.5.5. Loudspeaker Headphone Outputs following baseband features implemented loudspeaker headphone output channels: bass/treble, loudness, balance, volume. square wave beeper added loudspeaker headphone channel. loudspeaker channel additionally performs: equalizer (not simultaneously with bass/treble), spatial effects, subwoofer crossover filter.
2.5.4. Automatic Volume Correction (AVC) Different sound sources (e.g. terrestrial channels, channels, SCART) fairly often have same volume level. Advertisements during movies usually have higher volume level than movie itself. This results annoying volume changes. Automatic Volume Correction (AVC) solves this problem equalizing volume level. prevent clipping, AVC's gain decreases quickly dynamic boost conditions. suppress oscillation effects, gain increases rather slowly level inputs. decay time programmable means register (see page 33). input signals ranging from dBr, maintains fixed output level dBr. Fig. shows output level versus input level. prescale volume registers level corresponds full scale input/output. This SCART input/output Vrms Loudspeaker output Vrms output level [dBr]
2.5.6. Subwoofer Output subwoofer signal created combining left right channels directly behind loudness block using formula (L+R)/2. division converter will overloaded, even with full scale input signals. subwoofer signal filtered third-order low-pass with programmable corner frequency followed level adjustment. loudspeaker channels, complementary high-pass filter switched Subwoofer loudspeaker output same volume (Loudspeaker Volume Register).
Amplitude @dBD
input level [dBr]
2000
Fig. 2-4: Simplified characteristics
Fig. 2-5: Frequency response subwoofer filter sharp edge medium edge soft edge very soft edge
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34x0G
2.5.8.2. Adding Harmonics Micronas BASS exploits psychoacoustic phenomenon `missing fundamental'. Adding harmonics frequency components below cutoff frequency gives impression actually hearing frequency fundamental. other words: listener impression that loudspeaker system seems reproduce frequencies although physically possible.
Amplitude (db)
2.5.7. Quasi-Peak Detector quasi-peak readout register used read quasi-peak level input source. feature based following filter time constants: attack time: decay time:
2.5.8. Micronas BASS (MB) Micronas Bass system extends frequency range loudspeakers headphones. After adaption loudspeakers cabinet, further customizing allows individual fine tuning sound. Micronas BASS placed subwoofer path. applications without subwoofer, enhanced bass signal added back onto Left/Right channels (see Fig. page combines effects: dynamic amplification adding harmonics.
Frequency MB_HP
Fig. 2-7: Adding harmonics
2.5.8.1. Dynamic Amplification frequency signals boosted while output signal amplitude measured. amplitude comes close definable limit, gain reduced automatically dynamic Volume mode. Therefore, system adapts signal amplitude which really present output device. Clipping effects avoided.
Amplitude (db)
2.5.8.3. Micronas BASS Parameters Several parameters allow tuning characteristics Micronas BASS according loudspeaker, cabinet, personal preferences (see Table 3-11). more detailed information please refer corresponding application note.
2.6. SCART Signal Routing 2.6.1. SCART SCART Select SCART Input Select SCART Output Select blocks include full matrix switching facilities. design with four pairs SCART-inputs pairs SCART-outputs, external switching hardware required. switches controlled user register (see page 41).
Frequency MB_HP MB_LP SUBW_FREQ
Fig. 2-6: Dynamic amplification
Micronas
Signal Level
MB_LIMIT
2003; 6251-476-1DS
34x0G
2.6.2. Stand-by Mode 34x0G switched first pulling STANDBYQ then (after delay) switching DVSUP AVSUP, keeping AHVSUP (`Stand-by'-mode), SCART switches maintain their position function. This allows copying from SCART-input SCART-output set's stand-by mode. case power starting from stand-by (switching DVSUP AVSUP, RESETQ going high later), internal registers except register (see page reset default configuration (see Table page 20). reset position register becomes active after first transmission into Baseband Processing part. transmitting register first, reset state redefined. 2.7. Interface 34x0G synchronous master/slave input/output interface running kHz. interface accepts formats: I2S_WS changes word boundary I2S_WS changes I2S-clock period before word boundaries. options means MODUS I2S_CONFIGURATION registers. interface consists five pins: I2S_DA_IN1, I2S_DA_IN2: serial data input: 18.32 bits sample I2S_DA_OUT: serial data output: 18.32 bits sample I2S_CL: serial clock I2S_WS: word strobe signal defines left right sample 34x0G serves master interface, clock word strobe lines driven this mode, only bits sample selected. slave mode, these lines input clock synchronized times I2S_WS rate kHz). NICAM operation possible slave mode. timing diagram shown Fig. 4-27 page 2.9. Digital Control Pins Status Change Indication 2.8. Interface
ASTRA Digital Radio System (ADR), 3400G, 3410G, 3450G performs preprocessing such carrier selection filtering. 3-line ADR-bus, resulting signals transferred 3510A coprocessor, where source decoding performed. prepared upgrade with additional board, following lines 34x0G should provided feature connector: AUD_CL_OUT I2S_DA_IN1 I2S_DA_IN2 I2S_DA_OUT I2S_WS I2S_CL ADR_CL, ADR_WS, ADR_DA more details, please refer 3510A data sheet.
static level digital input/output pins D_CTR_I/O_0/1 switchable between HIGH I2C-bus means register (see page 41). This enables controlling external hardware switches other devices I2C-bus. digital input/output pins high impedance means MODUS register (see page 26). this mode, pins used input. current state read STATUS register (see page 28). Optionally, D_CTR_I/O_1 used interrupt request signal controller, indicating changes read register STATUS. This makes polling unnecessary, interactions reduced minimum (see STATUS register page MODUS register page 26).
2.10. Clock Oscillator Crystal Specifications 34x0G derives internal system clocks from 18.432 oscillator. NICAM I2SSlave mode, clock phase-locked corresponding source. Therefore, possible NICAM I2S-Slave mode same time. proper performance, clock oscillator requires 18.432 crystal. Note that phase-locked modes (NICAM, I2S-Slave), crystals with tighter tolerance required.
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response time about cannot accept another byte data (e.g. while servicing internal interrupt), holds clock line I2C_CL force transmitter into wait state. Master must read back clock line detect when ready receive next transmission. positions within transmission where this happen indicated 'Wait' Section 3.1.3. maximum wait period during normal operation mode less than
Control Interface 3.1. Interface 34x0G controlled slave interface. selected transmitting 34x0G device addresses. order allow three connected single bus, address select (ADR_SEL) been implemented. With ADR_SEL pulled high, low, left open, 34x0G responds different device addresses. device address pair defined write address read address (see Table 3-1). Writing done sending write device address, followed subaddress byte, address bytes, data bytes. Reading done sending write device address, followed subaddress byte address bytes. Without sending stop condition, reading addressed data completed sending device read address reading bytes data. Refer Section 3.1.3. protocol Section 3.4. "Programming Tips" page proposals 34x0G telegrams. Table list available subaddresses. Besides possibility hardware reset, also reset means RESET CONTROL register controller bus. architecture 34x0G, cannot react immediately request. typical Table 3-1: Device Addresses
ADR_SEL Mode device address (connected DVSS) Write 80hex Read 81hex
3.1.1. Internal Hardware Error Handling case hardware problems (e.g. interruption power supply MSP), MSP's wait period extended After this time period elapses, releases data clock lines.
Indication solving error status: indicate error status, remaining acknowledge bits actual I2C-protocol will left high. Additionally, bit[14] CONTROL one. then reset transmitting RESET condition CONTROL.
Indication reset: reset, even caused unstable reset line etc., indicated bit[15] CONTROL. general timing diagram shown Fig. 4-25 page
High (connected DVSUP) Write 84hex Read 85hex Write 88hex
Left Open Read 89hex
Table 3-2: Subaddresses
Name CONTROL WR_DEM RD_DEM WR_DSP RD_DSP Binary Value 0000 0000 0001 0000 0001 0001 0001 0010 0001 0011 Value Mode Read/Write Write Write Write Write Function Write: Software reset (see Table 3-3) Read: Hardware error status write address demodulator read address demodulator write address read address
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3.1.2. Description CONTROL Register
Table 3-3: CONTROL Write Register
Name CONTROL Subaddress 00hex Bit[15] (MSB) RESET normal Bits[14:0]
Table 3-4: CONTROL Read Register
Name CONTROL Subaddress 00hex %LW>@ RESET status after last reading CONTROL: reset occured reset occured Bit>@ Internal hardware status: error occured internal error occured BitV>@ interest
Reading CONTROL will reset bits[15,14] CONTROL. After Power-on, bit[15] CONTROL will set; must read once reset.
3.1.3. Protocol Description Write Demodulator
Wait write device address sub-addr addr-byte addr-byte data-byte data-byte high high
Read from Demodulator
Wait write device address sub-addr addr-byte addr-byte high read device address Wait data-byte- data-byte high
Write Control Register
Wait write device address sub-addr data-byte data-byte high
Read from Control Register
Wait write device address 00hex read device address Wait data-byte- data-byte high
Note:
I2C-Bus Start Condition from master I2C-Bus Stop Condition from master Acknowledge-Bit: I2C_DA from slave MSP, light gray) master controller, dark gray) Acknowledge-Bit: HIGH I2C_DA from master (dark gray) indicate `End Read' from indicating internal error state Wait I2C-Clock line held low, while processing command. This waiting time max.
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I2C_DA I2C_CL
Fig. 3-1: protocol (MSB first; data must stable while clock high)
3.1.4. Proposals General 34x0G Telegrams 3.1.4.1. Symbols write device address (80hex, 84hex 88hex) read device address (81hex, 85hex 89hex) Start Condition Stop Condition Address Byte Data Byte
3.2. Start-Up Sequence: Power-Up I2C-Controlling After POWER-ON RESET (see Fig. 4-24), inactive state. registers Reset position (see Table Table 3-6), analog outputs muted. controller initialize registers which non-default setting necessary.
3.3. 34x0G Programming Interface 3.3.1. User Registers Overview
3.1.4.2. Write Telegrams
<daw <daw <daw
write CONTROL register write data into demodulator write data into
3.1.4.3. Read Telegrams
read data from CONTROL register <daw <dar read data from demodulator <daw <dar read data from
<daw <dar
34x0G controlled means user registers. complete list user registers given Table Table 3-6. registers partitioned into Demodulator section (Subaddress 10hex writing, 11hex reading) Baseband Processing sections (Subaddress 12hex writing, 13hex reading). Write read registers wide, whereby denoted bit[15]. Transmissions have take place 16-bit words (two byte transfers, with most significant byte transferred first). write registers, except demodulator write registers readable. Unused parts 16-bit write registers must zero. Addresses given this table must accessed. reasons software compatibility 34xxD, Manual/Compatibility Mode available. More read write registers together with detailed description found "Appendix Manual/Compatibility Mode" page
3.1.4.4. Examples
RESET statically Clear RESET Automatic Sound Select demodulator stand. 03hex Read STATUS loudspeaker channel
source Stereo Matrix Stereo (transparent mode)
More examples typical application protocols listed Section 3.4. "Programming Tips" page
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Table 3-5: List 34x0G Write Registers
Write Register Address (hex) Bits Description Adjustable Range Reset Page
Subaddress 10hex Registers readable STANDARD SELECT MODUS CONFIGURATION [15:0] [15:0] [15:0] Initial Programming Demodulator Demodulator, Automatic Configuration options options
Subaddress 12hex Registers readable using Subaddress 13hex Volume loudspeaker channel Volume Mode loudspeaker channel [15:8] [7:0] [+12 -114 MUTE] Steps, Reduce Volume Tone Control Compromise/ Dynamic [0.100 100% 0.100%] [-127.0 -128.0 [Linear logarithmic mode] [+20 [+15 [NORMAL, SUPER_BASS] [-100%.OFF.+100%] [SBE, SBE+PSE] [+12 -114 MUTE] Steps, Reduce Volume Tone Control Compromise/ Dynamic [+12 -114 MUTE] [FM/AM, NICAM, SCART, [SOUNDA, SOUNDB, STEREO, MONO.] [FM/AM, NICAM, SCART, I2S1, I2S2]
MUTE 00hex
Balance loudspeaker channel [L/R] Balance mode loudspeaker Bass loudspeaker channel Treble loudspeaker channel Loudness loudspeaker channel Loudness filter characteristic Spatial effect strength loudspeaker Spatial effect mode/customize Volume headphone channel Volume Mode headphone channel
[15:8] [7:0]
100%/100% linear mode NORMAL SBE+PSE MUTE 00hex
[15:8] [15:8] [15:8] [7:0]
[15:8] [7:0]
[15:8] [7:0]
Volume SCART1 output channel Loudspeaker source select Loudspeaker channel matrix Headphone source select Headphone channel matrix SCART1 source select SCART1 channel matrix source select channel matrix Quasi-peak detector source select Quasi-peak detector matrix Prescale SCART input Prescale FM/AM matrix Prescale NICAM Prescale I2S2 SCART Switches D_CTR_I/O Beeper
[15:8] [15:8] [7:0]
MUTE FM/AM SOUNDA FM/AM SOUNDA FM/AM SOUNDA FM/AM SOUNDA FM/AM SOUNDA 00hex 00hex NO_MAT 00hex 10hex 00hex 00/00hex
[15:8] [7:0]
[SOUNDA, SOUNDB, STEREO, MONO.] [FM/AM, NICAM, SCART, I2S1, I2S2] [SOUNDA, SOUNDB, STEREO, MONO.] [FM/AM, NICAM, SCART, I2S1, I2S2] [SOUNDA, SOUNDB, STEREO, MONO.] [FM/AM, NICAM, SCART, [SOUNDA, SOUNDB, STEREO, MONO.] [00hex 7Fhex] [00hex 7Fhex] [NO_MAT, GSTEREO, KSTEREO] [00hex 7Fhex] (MSP 3410G, 3450G only) [00hex 7Fhex] Bits [15.0] [00hex 7Fhex]/[00hex 7Fhex]
[15:8] [7:0]
[15:8] [7:0]
[15:8] [7:0]
[15:8] [15:8] [7:0]
[15:8] [15:8] [15:0] [15:0]
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Table 3-5: List 34x0G Write Registers, continued
Write Register Prescale I2S1 Tone control mode Equalizer loudspeaker band Equalizer loudspeaker band Equalizer loudspeaker band Equalizer loudspeaker band Equalizer loudspeaker band Automatic Volume Correction Address (hex) Bits [15:8] [15:8] [15:8] [15:8] [15:8] [15:8] [15:8] [15:12] [11:8] Subwoofer level adjust Subwoofer corner frequency Subwoofer characteristics Subwoofer complementary high-pass Balance headphone channel [L/R] Balance mode headphone Bass headphone channel Treble headphone channel Loudness headphone channel Loudness filter characteristic Volume SCART2 output channel SCART2 source select SCART2 channel matrix Micronas BASS Effect Strength Micronas BASS Amplitude Limit Micronas BASS Harmonic Content Micronas BASS Pass Corner Frequency Micronas BASS High Pass Corner Frequency [15:8] [15:8] [7:4] [3:0] [15:8] [7:0] [15:8] [15:8] [15:8] [7:0] [15:8] [15:8] [7:0] [15:8] [15:8] [15:8] [15:8] [15:8] Description Adjustable Range [00hex 7Fhex] [Bass/Treble, Equalizer] [+12 [+12 [+12 [+12 [+12 [off, [decay time] [+12 mute] [sharp, medium, soft, very soft] [off, Micronas BASS Main] [0.100 100% 0.100%] [-127.0 -128.0 dB]] [Linear mode logarithmic mode] [+20 [+15 [NORMAL, SUPER_BASS] [+12 -114 MUTE] [FM, NICAM, SCART, I2S1, I2S2] [SOUNDA, SOUNDB, STEREO, MONO.] off] dBFS. dBFS] 100%] Reset 10hex Bass/Treble 00hex 00hex sharp %/100 linear mode NORMAL 00hex SOUNDA dBFS Page
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Table 3-6: List 34x0G Read Registers
Read Register Address (hex) Bits Description Adjustable Range Page
Subaddress 11hex Registers writable STANDARD RESULT STATUS [15:0] [15:0] Result Automatic Standard Detection (see Table page Monitoring internal settings e.g. Stereo, Mono, Mute etc.
Subaddress 13hex Registers writable Quasi peak readout left Quasi peak readout right hardware version code major revision code product code version code [15:0] [15:0] [15:8] [7:0] [15:8] [7:0] [00hex 7FFFhex]16 two's complement [00hex 7FFFhex]16 two's complement [00hex FFhex] [00hex FFhex] [00hex FFhex] [00hex FFhex]
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3.3.2. Description User Registers Table 3-7: Standard Codes STANDARD SELECT register
Standard Code (Data hex) Sound Standard Automatic Standard Detection Start Automatic Standard Detection sets detected standards Standard Selection M-Dual FM-Stereo -Dual FM-Stereo1) D/K1-Dual FM-Stereo2) 4.5/4.724212 5.5/5.7421875 6.5/6.2578125 6.5/6.7421875 3400, -10, -20, -40, 3400, -10, Sound Carrier Frequencies 34x0G Version
D/K2-Dual FM-Stereo2) -FM-Mono with HDEV33), detectable Automatic Standard Detection, HDEV33) SAT-Mono (i.e. Eutelsat, Table 6-18) D/K3-Dual FM-Stereo -NICAM-FM -NICAM-AM -NICAM-FM -NICAM-FM
6.5/5.7421875 5.5/5.85 6.5/5.85 6.0/6.552 6.5/5.85 6.5/5.85 6.5/5.85 3420, -40, 3410,
-NICAM-FM with HDEV24), detectable Automatic Standard Detection, China -NICAM-FM with HDEV33), detectable Automatic Standard Detection, China BTSC-Stereo BTSC-Mono M-EIA-J Japan Stereo FM-Stereo Radio with Deemphasis SAT-Mono Table 6-18) SAT-Stereo Table 6-18) (Astra Digital Radio)
10.7 7.02/7.20 6.12 3400, -10,
case Automatic Sound Select, B/G-codes 3hex 8hex equivalent. case Automatic Sound Select, D/K-codes 4hex, 5hex, 7hex Bhex equivalent. HDEV3: Max. deviation must exceed HDEV2: Max. deviation must exceed
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3.3.2.1. STANDARD SELECT Register sound standard 34x0G demodulator determined STANDARD SELECT register. There ways STANDARD SELECT register: Setting demodulator sound standard sending corresponding standard code with single transmission. Starting Automatic Standard Detection terrestrial standards. This most comfortable demodulator. Within detection setup actual sound standard performed. detected standard read STANDARD RESULT register control processor. This feature recommended primary setup set. Outputs should muted during Automatic Standard Detection. Standard Codes listed Table 3-7. 3.3.2.3. STANDARD RESULT Register Selecting sound standard STANDARD SELECT register initializes demodulator. This includes: AGC-settings carrier mute, tuning frequencies, FIR-filter settings, demodulation mode (FM, NICAM), deemphasis identification mode. stereo sound standards that unavailable specific version processed analog mono sound standard. that case, stereo bilingual processing will possible. complete setup sound processing from analog input source selection, transmissions shown Section 3.5. necessary. reasons software compatibility 34xxD, Manual/Compatibility mode available. detailed description this mode found page
3.3.2.2. Refresh STANDARD SELECT Register general refresh STANDARD SELECT register allowed. However, following method enables watching 34x0G "alive" status detection accidental resets (only versions later): After Power-on, bit[15] CONTROL will set; must read once enable reset-detection feature. Reading CONTROL register checking reset indicator bit[15] bit[15] "0", refresh STANDARD SELECT register allowed. bit[15] "1", indicating reset, refresh STANDARD SELECT register other MSPG registers required.
Automatic Standard Detection selected STANDARD SELECT register, status result Automatic Standard Detection process read STANDARD RESULT register. possible results based mentioned Standard Code listed Table 3-8. cases where sound standard been detected standard present, much noise, strong interferers, etc.) STANDARD RESULT register contains 00hex. that case, controller start further actions (for example standard according preference list manual input). long STANDARD RESULT register contains value greater than FFhex, Automatic Standard Detection still active. During this period, MODUS STANDARD SELECT register must written. STATUS register will updated when Automatic Standard Detection finished. present sound standard unavailable specific MSP-version, detects switches analog mono sound this standard. Example: MSPs 3420G 3440G will detect B/G-NICAM signal standard will switch analog FMMono sound.
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Table 3-8: Results Automatic Standard Detection
Broadcasted Sound Standard Automatic Standard Detection could find sound standard B/G-FM B/G-NICAM FM-Radio M-Korea M-Japan M-BTSC STANDARD RESULT Register Read 007Ehex 0000hex
0003hex 0008hex 000Ahex 0040hex 0002hex MODUS[14,13]=00) 0020hex MODUS[14,13]=01) 0030hex MODUS[14,13]=10)
L-AM D/K1 D/K2 D/K3 L-NICAM D/K-NICAM Automatic Standard Detection still active
0009hex MODUS[12]=0) 0004hex MODUS[12]=1) 0009hex MODUS[12]=0) 000Bhex MODUS[12]=1) >07FFhex
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3.3.2.4. Write Registers Subaddress 10hex Table 3-9: Write registers subaddress 10hex Register Address 20hex Function STANDARD SELECTION Register Defines TV-Sound FM-Radio Standard bit[15:0] 01hex 02hex 60hex start Automatic Standard Detection Standard Codes (see Table 3-7) Name
STANDARD_SEL
30hex
MODUS Register Preference Automatic Standard Detection: bit[15] bit[14:13] bit[12] undefined, must detected carrier interpreted as:1) standard (Korea) standard (BTSC) standard (Japan) chroma carrier (M/N standards ignored) detected carrier interpreted as:1) standard (SECAM) standard D/K1, D/K2, D/K3, NICAM
MODUS
General 34x0G Options bit[11:9] bit[8] bit[7] bit[6] bit[5] bit[4] bit[3] undefined, must ANA_IN1+/ANA_IN2+; select analog sound input active/tristate state audio clock output AUD_CL_OUT word strobe alignment changes data word boundary changes clock cycle advance master/slave mode interface (must Master) case NICAM mode) active/tristate state output pins state digital output pins D_CTR_I/O_0 active: D_CTR_I/O_0 output pins (can means register. also: MODUS[1]) tristate: D_CTR_I/O_0 input pins (level read STATUS[4,3]) undefined, must disable/enable STATUS change indication means digital D_CTR_I/O_1 Necessary condition: MODUS[3] (active) off/on: Automatic Sound Select
bit[2] bit[1]
bit[0]
Valid next start Automatic Standard Detection.
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Table 3-9: Write registers subaddress 10hex, continued Register Address 40hex Function CONFIGURATION Register bit[15:1] bit[0] used, must I2S_CL frequency data sample length master mode (1.024 MHz) (2.048 MHz) Name I2S_CONFIG
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3.3.2.5. Read Registers Subaddress 11hex Table 3-10: Read Registers Subaddress 11hex Register Address 7Ehex Function STANDARD RESULT Register Readback detected sound FM-Radio Standard bit[15:0] 00hex Automatic Standard Detection could find sound standard Standard Codes (see Table page Name
STANDARD_RES
02hex 40hex FFhex Automatic Standard Detection still active 00hex STATUS Register
STATUS
Contains user relevant internal information about status bit[15:10] bit[8] undefined indicates bilingual sound mode present (internally evaluated from received analog digital identification signals) indicates independent mono sound (only NICAM) mono/stereo indication (internally evaluated from received analog digital identification signals) analog sound standard active this pattern will occur digital sound (NICAM) available reception condition digital sound (NICAM) high error rate unimplemented sound code data transmission only low/high level digital D_CTR_I/O_1 low/high level digital D_CTR_I/O_0 detected secondary carrier (2nd sub-carrier) secondary carrier detected detected primary carrier (Mono carrier) primary carrier detected undefined
bit[7] bit[6]
bit[5,9]
bit[4] bit[3] bit[2] bit[1] bit[0]
STATUS change indication activated means MODUS[1]: Each change STATUS register sets digital D_CTR_I/O_1 high level. Reading STATUS register resets D_CTR_I/O_1.
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3.3.2.6. Write Registers Subaddress 12hex Table 3-11: Write Registers Subaddress 12hex Register Address Function Name
PREPROCESSING 0Ehex FM/AM Prescale bit[15:8] 00hex 7Fhex 00hex Defines input prescale gain demodulated signal (RESET condition) PRE_FM
modes except satellite AM-mode, combinations prescale value deviation listed below lead internal full scale with test signal emphasis. mode bit[15:8] 7Fhex 48hex 30hex 24hex 18hex 13hex deviation deviation deviation deviation deviation deviation (limit)
high deviation mode (HDEV2, Standard Code Chex) bit[15:8] 30hex 14hex deviation deviation (limit)
very high deviation mode (HDEV3, Standard Code Dhex) bit[15:8] 20hex 1Ahex deviation deviation (limit)
Satellite with adaptive deemphasis bit[15:8] 10hex recommendation
mode (MSP Standard Code bit[15:8] 7Chex recommendation input levels from (Due being switched AM-output level remains stable independent actual SIF-level mentioned input range)
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Table 3-11: Write Registers Subaddress 12hex, continued Register Address
(continued)
Function Matrix Modes Defines dematrix function demodulated signal bit[7:0] 00hex 01hex 02hex 03hex 04hex matrix (used bilingual unmatrixed stereo sound) German stereo (Standard B/G) Korean stereo (also used BTSC, EIA-J Radio) sound mono (left right channel contain mono sound FM/AM mono carrier) sound mono
Name FM_MATRIX
0Ehex
case Automatic Sound Select Matrix Mode automatically. Writing FM/AM prescale register 0Ehex high part) still allowed. order disturb automatic process, part transmission this register ignored. Therefore, FM-Matrix readback values differ from data written previously. case Automatic Sound Select off, Matrix Mode must shown Table 6-17 Appendix enable Forced Mono Mode THRESHOLD described Section 6.3.2.on page 10hex NICAM Prescale Defines input prescale value digital NICAM signal bit[15:8] 00hex 7Fhex prescale gain examples: 00hex gain 20hex gain (recommendation) 5Ahex gain (maximum gain) 7Fhex 16hex 12hex I2S1 Prescale I2S2 Prescale Defines input prescale value digital input signals bit[15:8] 00hex 7Fhex prescale gain examples: 00hex gain (recommendation) 10hex gain (maximum gain) 7Fhex 0Dhex SCART Input Prescale Defines input prescale value analog SCART input signal bit[15:8] 00hex 7Fhex prescale gain examples: 00hex gain VRMS input leads digital full scale) 19hex 7Fhex gain (400 mVRMS input leads digital full scale) PRE_SCART PRE_I2S1 PRE_I2S2 PRE_NICAM
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Table 3-11: Write Registers Subaddress 12hex, continued Register Address Function Name
SOURCE SELECT OUTPUT CHANNEL MATRIX 08hex 09hex 0Ahex 41hex 0Bhex 0Chex Source for: Loudspeaker Output Headphone Output SCART1 Output SCART2 Output Output Quasi-Peak Detector bit[15:8] 00hex 01hex "FM/AM": demodulated mono signal "Stereo A/B": demodulator Stereo signal manual mode, this source identical NICAM source 3410D) "Stereo demodulator Stereo Sound Language (only defined Automatic Sound Select) "Stereo demodulator Stereo Sound Language (only defined Automatic Sound Select) SCART input I2S1 input I2S2 input SRC_MAIN SRC_AUX SRC_SCART1 SRC_SCART2 SRC_I2S SRC_QPEAK
03hex 04hex 02hex 05hex 06hex
demodulator sources, Table 2-2. 08hex 09hex 0Ahex 41hex 0Bhex 0Chex Matrix Mode for: Loudspeaker Output Headphone Output SCART1 Output SCART2 Output Output Quasi-Peak Detector bit[7:0] Sound Mono Left Mono) 00hex Sound Mono Right Mono) 10hex Stereo (transparent mode) 20hex 30hex Mono (sum left right inputs divided special modes available (see Section 6.5.1. page MAT_MAIN MAT_AUX MAT_SCART1 MAT_SCART2 MAT_I2S MAT_QPEAK
Automatic Sound Select mode, demodulator source channels according Table 2-2. Therefore, matrix modes corresponding output channels should "Stereo" (transparent).
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Table 3-11: Write Registers Subaddress 12hex, continued Register Address Function
Name
LOUDSPEAKER HEADPHONE PROCESSING 00hex 06hex Volume Loudspeaker Volume Headphone bit[15:8] volume table with step size (maximum volume) 7Fhex 7Ehex 74hex 73hex 72hex -113 02hex -114 01hex Mute (reset condition) 00hex FFhex Fast Mute (needs about until signal completely ramped down) higher resolution volume table +0.125 increase addition volume table +0.875 increase addition volume table must VOL_MAIN VOL_AUX
bit[7:5]
bit[4] bit[3:0]
clipping mode reduce volume reduce tone control compromise dynamic
With large scale input signals, positive volume settings lead signal clipping. 34x0G loudspeaker headphone volume function divided into digital analog section. With Fast Mute, volume reduced mute position digital volume only. Analog volume changed. This reduces audible plops. turn volume again, volume step that been used before Fast Mute activated must transmitted. clipping mode "reduce volume", following rule used: prevent severe clipping effects with bass, treble, equalizer boosts, internal volume automatically limited level where, combination with either bass, treble, equalizer setting, amplification does exceed clipping mode "reduce tone control", bass treble value reduced amplification exceeds equalizer switched gain those bands reduced, where amplification together with volume exceeds clipping mode "compromise", bass treble value volume reduced half half amplification exceeds equalizer switched gain those bands reduced half half, where amplification together with volume exceeds clipping mode "dynamic", volume reduced automatically signal amplitudes would exceed dBFS within operation Micronas BASS, dynamic mode must switched
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Table 3-11: Write Registers Subaddress 12hex, continued Register Address 29hex Function Automatic Volume Correction (AVC) Loudspeaker Channel bit[15:12] 00hex 08hex bit[11:8] 08hex 04hex 02hex 01hex (and reset internal variables) decay time decay time decay time decay time (should used approx. after channel change) Name
Note: should used Dolby Prologic mode (with 35xx), except PANORAMA 3D-PANORAMA mode, when only loudspeaker output active. 01hex 30hex Balance Loudspeaker Channel Balance Headphone Channel bit[15:8] Linear Mode Left muted, Right 100% 7Fhex Left 0.8%, Right 100% 7Ehex Left 99.2%, Right 100% 01hex Left 100%, Right 100% 00hex FFhex Left 100%, Right 99.2% Left 100%, Right 0.8% 82hex Left 100%, Right muted 81hex Logarithmic Mode 7Fhex Left -127 Right 7Ehex Left -126 Right Left Right 01hex Left Right 00hex Left Right FFhex 81hex Left Right -127 Left Right -128 80hex Balance Mode 00hex linear logarithmic 01hex BAL_MAIN BAL_AUX
bit[15:8]
bit[7:0]
Positive balance settings reduce left channel without affecting right channel; negative settings reduce right channel leaving left channel unaffected.
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Table 3-11: Write Registers Subaddress 12hex, continued Register Address 20hex Function Tone Control Mode Loudspeaker Channel bit[15:8] 00hex FFhex bass treble active equalizer active
Name TONE_MODE
Defines whether Bass/Treble Equalizer activated loudspeaker channel. Bass Equalizer cannot work simultaneously. Equalizer used, Bass, Treble coefficients must zero vice versa. 02hex 31hex Bass Loudspeaker Channel Bass Headphone Channel bit[15:8] extended range 7Fhex 78hex 70hex 68hex normal range 60hex 58hex 08hex 00hex F8hex A8hex A0hex Higher resolution possible: step normal range results gain step about extended range about With positive bass settings, internal clipping occur even with overall volume less than This will lead clipped output signal. Therefore, recommended bass value that, conjunction with volume, would result overall positive gain. BASS_MAIN BASS_AUX
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34x0G
Table 3-11: Write Registers Subaddress 12hex, continued Register Address 03hex 32hex Function Treble Loudspeaker Channel Treble Headphone Channel bit[15:8] 78hex 70hex 08hex 00hex F8hex A8hex A0hex Name TREB_MAIN TREB_AUX
Higher resolution possible: step results gain step about With positive treble settings, internal clipping occur even with overall volume less than This will lead clipped output signal. Therefore, recommended treble value that, conjunction with volume, would result overall positive gain. 21hex 22hex 23hex 24hex 25hex Equalizer Loudspeaker Channel Band (below Equalizer Loudspeaker Channel Band (center: Equalizer Loudspeaker Channel Band (center: kHz) Equalizer Loudspeaker Channel Band (center: kHz) Equalizer Loudspeaker Channel Band (above: kHz) bit[15:8] 60hex 58hex 08hex 00hex F8hex A8hex A0hex EQUAL_BAND1 EQUAL_BAND2 EQUAL_BAND3 EQUAL_BAND4 EQUAL_BAND5
Higher resolution possible: step results gain step about With positive equalizer settings, internal clipping occur even with overall volume less than This will lead clipped output signal. Therefore, recommended equalizer bands value that, conjunction with volume, would result overall positive gain.
Micronas
2003; 6251-476-1DS
34x0G
Table 3-11: Write Registers Subaddress 12hex, continued Register Address 04hex 33hex Function Loudness Loudspeaker Channel Loudness Headphone Channel bit[15:8] Loudness Gain 44hex 40hex 04hex +0.75 03hex +0.5 02hex +0.25 01hex 00hex Loudness Mode 00hex normal (constant volume kHz) 04hex Super Bass (constant volume kHz)
Name LOUD_MAIN LOUD_AUX
bit[7:0]
Higher resolution Loudness Gain possible: step results gain step about Loudness increases volume low- high-frequency signals, while keeping amplitude reference frequency constant. intended loudness according actual volume setting. Because loudness introduces gain, recommended loudness value that, conjunction with volume, would result overall positive gain. corner frequency bass amplification different values. Super Bass mode, corner frequency shifted point constant volume shifted from kHz.
2003; 6251-476-1DS
Micronas
34x0G
Table 3-11: Write Registers Subaddress 12hex, continued Register Address 05hex Function Spatial Effects Loudspeaker Channel bit[15:8] Effect Strength 7Fhex Enlargement 100% Enlargement 3Fhex Enlargement 0.78% 01hex 00hex Effect reduction 0.78% FFhex reduction C0hex reduction 100% 80hex Spatial Effect Mode 0hex Stereo Basewidth Enlargement (SBE) Pseudo Stereo Effect (PSE). (Mode 2hex Stereo Basewidth Enlargement (SBE) only. (Mode Spatial Effect High-Pass Gain max. high-pass gain 0hex high-pass gain 2hex high-pass gain 4hex 6hex min. high-pass gain automatic 8hex Name SPAT_MAIN
bit[7:4]
bit[3:0]
There several spatial effect modes available: mode (low byte 00hex), spatial effect depends source mode. incoming signal mono, Pseudo Stereo Effect active; stereo signals, Pseudo Stereo Effect Stereo Basewidth Enlargement effective. strength effect controllable upper byte. negative value reduces stereo image. strong spatial effect recommended small sets where loudspeaker spacing rather close. large screen sets, more moderate spatial effect recommended. mode only Stereo Basewidth Enlargement effective. mono input signals, Pseudo Stereo Effect switched worth mentioning, that spatial effects affect amplitude phase response. With lower bits, frequency response customized. value 0hex yields flat response center signals high-pass function only signals. value 6hex flat response only signals, low-pass function center signals. using 8hex, frequency response automatically adapted sound material choosing optimal high-pass gain.
Micronas
2003; 6251-476-1DS
34x0G
Table 3-11: Write Registers Subaddress 12hex, continued Register Address Function
Name
SUBWOOFER OUTPUT CHANNEL 2Chex Subwoofer Level Adjustment bit[15:8] 0Chex 01hex 00hex FFhex E3hex E2hex 80hex 00hex (default) Mute must zero SUBW_LEVEL
bit[7:0]
Micronas BASS added onto main channel, this register should 00hex 2Dhex Subwoofer Corner Frequency bit[15:8] 5.40dec corner frequency steps (range: 50.400 SUBW_FREQ
Micronas BASS active, SUBW_FREQ must value higher than Lowpass Frequency (MB_LP). Choosing corner frequency subwoofer closer MB_LP results narrower frequency range. Recommended value: Subwoofer Characteristics bit[7:4] 0hex 1hex 2hex 3hex sharp edge Subwoofer characteristics (default) medium edge Subwoofer characteristics soft edge Subwoofer characteristics very soft edge Subwoofer characteristics SUBW_CHAR
adjustable subwoofer filter characterisitic with four different filter sets selected. complementary filter design, output high- lowpass filter crossover region filter sets. Subwoofer Complementary High-Pass Filter bit[3:0] 0hex 1hex 2hex loudspeaker channel unfiltered complementary high-pass processed loudspeaker output channel Micronas BASS added onto main channel SUBW_HP
MICRONAS BASS (MB) CONTROL REGISTERS 68hex Micronas BASS Effect Strength bit[15:8] bit[7:0] 00hex 7Fhex 00hex Micronas BASS (default) maximum Micronas BASS must zero MB_STR
Micronas BASS effect strength adjusted steps. value 44hex will yield medium Micronas BASS effect.
2003; 6251-476-1DS
Micronas
34x0G
Table 3-11: Write Registers Subaddress 12hex, continued Register Address 69hex Function Micronas BASS Amplitude Limit bit[15:8] 00hex FFhex E0hex 00hex dBFS (default limitation) dBFS dBFS must zero Name MB_LIM
bit[7:0]
Micronas BASS Amplitude Limit defines maximum allowed amplitude output relative dbFS. amplitude exceeds MB_LIM, gain automatically reduced. Note that Volume Clipping Mode must "dynamic" (see page 32). 6Ahex Micronas BASS Harmonic Content bit[15:8] 00hex 3Fhex 7Fhex 00hex harmonics added (default) fundamentals harmonics 100% harmonics must zero MB_HMC
bit[7:0]
creates harmonics frequencies below highpass frequency (MB_HP). variable MB_HMC describes ratio harmonics towards original signal. 6Bhex Micronas BASS Pass Corner Frequency bit[15:8] 5dec 6dec 30dec 00dec must zero MB_LP
bit[7:0]
lowpass corner frequency (range 50.300 defines upper corner frequency bandpass filter. Recommended values same highpass corner frequency (MB_HP). 6Chex Micronas BASS High Pass Corner Frequency bit[15:8] 3dec 4dec 30dec 00hex must zero MB_HP
bit[7:0]
highpass corner frequency defines lower corner frequency bandpass filter. highpass filter avoids loading loudspeakers with frequency components that below speakers' frequency. Recommended values subwoofer systems around 5dec (=50 Hz), regular sets around 10dec (=100 Hz).
Micronas
2003; 6251-476-1DS
34x0G
Table 3-11: Write Registers Subaddress 12hex, continued Register Address Function
Name
SCART OUTPUT CHANNEL 07hex 40hex Volume SCART1 Output Channel Volume SCART2 Output Channel bit[15:8] volume table with step size (maximum volume) 7Fhex 7Ehex 74hex 73hex 72hex -113 02hex -114 01hex Mute (reset condition) 00hex higher resolution volume table +0.125 increase addition volume table +0.875 increase addition volume table 01hex this must 01hex VOL_SCART1 VOL_SCART2
bit[7:5]
bit[4:0]
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Micronas
34x0G
Table 3-11: Write Registers Subaddress 12hex, continued Register Address Function Name
SCART SWITCHES DIGITAL PINS 13hex Register Defines level digital output pins position SCART switches bit[15] bit[14] bit[13:5] low/high digital output D_CTR_I/O_1 (MODUS[3]=0) low/high digital output D_CTR_I/O_0 (MODUS[3]=0) ACB_REG
SCART Input Select xxxx00xx0 SCART1 input (RESET position) xxxx01xx0 MONO input (set Sound Mono channel matrix mode corresponding output channels) xxxx10xx0 SCART2 input xxxx11xx0 SCART3 input xxxx00xx1 SCART4 input xxxx11xx1 mute input
xx00xxx0x
bit[13:5]
SCART1 Output Select SCART3 input SCART1 output (RESET position) xx01xxx0x SCART2 input SCART1 output xx10xxx0x MONO input SCART1 output xx11xxx0x SCART1 SCART1 output xx00xxx1x SCART2 SCART1 output xx01xxx1x SCART1 input SCART1 output xx10xxx1x SCART4 input SCART1 output xx11xxx1x mute SCART1 output SCART2 Output Select SCART1 SCART2 output (RESET position) SCART1 input SCART2 output MONO input SCART2 output SCART2 SCART2 output SCART2 input SCART2 output SCART3 input SCART2 output SCART4 input SCART2 output mute SCART2 output
bit[13:5]
00xxxx0xx 01xxxx0xx 10xxxx0xx 00xxxx1xx 01xxxx1xx 10xxxx1xx 11xxxx1xx 11xxxx0xx
bit[4:0]
must zero
RESET position becomes active time first write transmission control audio processing part. writing register first, RESET state redefined. BEEPER 14hex Beeper Volume Frequency bit[15:8] Beeper Volume 00hex maximum volume 7Fhex Beeper Frequency 01hex (lowest) 40hex FFhex BEEPER
bit[7:0]
Micronas
2003; 6251-476-1DS
34x0G
3.3.2.7. Read Registers Subaddress 13hex Table 3-12: Read Registers Subaddress 13hex Register Address Function
Name
QUASI-PEAK DETECTOR READOUT 19hex 1Ahex Quasi-Peak Detector Readout Left Quasi-Peak Detector Readout Right bit[15:0] 0hex. 7FFFhex QPEAK_L QPEAK_R
Values two's complement (only positive). value 4000hex corresponds internal full scale. 34x0G VERSION READOUT Registers 1Ehex Hardware Version Code bit[15:8] 03hex 34x0G MSP_HARD
change hardware version code defines hardware optimizations that have influence chip's behavior. readout this register identical hardware version code chip's imprint. Major Revision Code bit[7:0] 07hex 34x1G MSP_REVISION
major revision code 34x0G 1Fhex Product Code bit[15:8] 00hex 0Ahex 14hex 28hex 32hex 3Chex 3400G 3410G 3420G 3440G 3450G 3460G MSP_PRODUCT
means MSP-Product Code, control processor able decide which sound standards have considered. Version Code bit[7:0] 4Chex 34x0G MSP_ROM
change version code defines internal software optimizations, that have influence chip's behavior, e.g. features have been included. While software change intended create compatibility problems, customers that want functions identify 34x0G versions according this number. avoid compatibility problems with 3410B 34x0D, offset 40hex added version code chip's imprint.
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34x0G
3.5. Examples Minimum Initialization Codes Initialization 34x0G according these listings reproduces sound selected standard loudspeaker output. numbers hexadecimal. examples have following structure: Perform controlled reset Write MODUS register (with Automatic Sound Select). Source Selection loudspeaker channel (with matrix STEREO). Prescale and/or NICAM dummy matrix).
3.4. Programming Tips This section describes preferred method initializing 34x0G. initialization grouped into four sections: SCART Signal Path (analog signal path) Demodulator SCART Inputs Output Channels Fig. page complete signal flow.
SCART Signal Path Select analog input SCART baseband processing (SCART Input Select) means register. Select source each analog SCART output (SCART Output Select) means register.
Write STANDARD SELECT register. Volume loudspeaker channel
3.5.1. B/G-FM NICAM)
MODUS-Register: Automatic Source Sel. Matr. FM/AM-Prescale 24hex, FM-Matrix MONO/SOUNDA NICAM-Prescale 5Ahex Standard Select: NICAM Softreset
Demodulator complete setup sound processing from analog input source selection, following steps must performed: MODUS register preferred mode Sound input. Choose preferred prescale NICAM) values. Write STANDARD SELECT register. Automatic Sound Select active: Choose matrix repeatedly according sound mode indicated STATUS register. SCART Inputs Select preferred prescale SCART. Select preferred prescale inputs (set after RESET).
Loudspeaker Volume
3.5.2. BTSC-Stereo
MODUS-Register: Automatic Source Sel. Matr. FM/AM-Prescale 24hex, FM-Matrix Sound Mono Standard Select: BTSC-STEREO Loudspeaker Volume Softreset
3.5.3. BTSC-SAP with Loudspeaker Channel
Softreset MODUS-Register: Automatic Source Sel. Matr. FM/AM-Prescale 24hex, FM-Matrix Sound Mono Standard Select: BTSC-SAP Loudspeaker Volume
Output Channels Select source channel matrix each output channel. audio baseband processing. Select volume each output channel.
Micronas
2003; 6251-476-1DS
34x0G
3.5.4. FM-Stereo Radio
MODUS-Register: Automatic Source Sel. Matr. FM/AM-Prescale 24hex, FM-Matrix Sound Mono Standard Select: FM-STEREO-RADIO Loudspeaker Volume Softreset
3.5.5. Automatic Standard Detection detailed software flow diagram shown Fig. page
MODUS-Register: Automatic Source Sel. Matr. FM/AM-Prescale 24hex, FM-Matrix Sound Mono NICAM-Prescale 5Ahex Standard Select: Automatic Standard Detection Softreset
Wait till STANDARD RESULT contains value 07FF STANDARD RESULT contains 0000 some error handling ELSE Loudspeaker Volume
3.5.6. Software Flow Interrupt driven STATUS Check detailed software flow diagram shown Fig. page D_CTR_I/O_1 34x0G connected interrupt input controller, following interrupt handler applied automatically called with each status change 34x0G. interrupt handler adjust display according status information.
Interrupt Handler: Read STATUS adjust display with given status information Return from Interrupt
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34x0G
@hyr essential bits:
Enable interrupt STATUS changes ANA_IN1+ selected Define Preference Automatic Standard Detection: [12] MHz, SECAM-L [14:13] Ignore carrier
:ULWH 02'86 5HJLVWHU:
@hyr)
:ULWH 6285&( 6(/(&7 6HWWLQJV
loudspeaker Source Select "Stereo headphone Source Select "Stereo SCART_Out Source Select "Stereo A/B" Channel Matrix mode outputs "Stereo"
Write FM/AM-Prescale Write NICAM-Prescale
:ULWH LQWR 67$1'$5' 6(/(&7 5HJLVWHU
(Start Automatic Standard Detection)
previous standard standard manually according picture information
Result
expecting MSPG-interrupt
FDVH 063* ,QWHUUXSW &RQWUROOHU
Read STATUS
Adjust TV-Display
Bilingual, adjust Source Select setting required
Fig. 3-2: Software flow diagram Minimum demodulator setup European Multistandard applying Automatic Sound Select feature
Micronas
2003; 6251-476-1DS
34x0G
Specifications 4.1. Outline Dimensions
Fig. 4-1: PSDIP64-1: Plastic Shrink Dual In-line Package, leads, Ordering code: Weight approximately 8.77
2003; 6251-476-1DS
Micronas
34x0G
Fig. 4-2: PSDIP52-1: Plastic Shrink Dual In-line Package, leads, Ordering code: PO1) Weight approximately 5.13
Micronas delivers types PSDIP52 packages (-1, -2). packages have slightly different outline dimensions, considered identical. logistics reasons, customer cannot choose package delivered.
Micronas
2003; 6251-476-1DS
34x0G
Fig. 4-3: PSDIP52-2: Plastic Shrink Dual In-line Package, leads, Ordering code: PO1) Weight approximately 5.92
Micronas delivers types PSDIP52 packages (-1, -2). packages have slightly different outline dimensions, considered identical. logistics reasons, customer cannot choose package delivered.
2003; 6251-476-1DS
Micronas
34x0G
Fig. 4-4: PMQFP80-11: Plastic Metric Quad Flat Package, leads, mm3, high standoff Ordering code: Weight approximately 1.68
Micronas
2003; 6251-476-1DS
34x0G
Fig. 4-5: PMQFP64-2: Plastic Metric Quad Flat Package, leads, Ordering code: Weight approximately
2003; 6251-476-1DS
Micronas
34x0G
4.2. Connections Short Descriptions connected; leave vacant used, leave vacant obligatory; connect described circuit diagram DVSS: used, connect DVSS AHVSS: connect AHVSS
PMQFP 80-11 PMQFP 64-2 PSDIP 64-1 PSDIP 52-1/-2
Name
Type
Connection
used)
Short Description
I2C_CL I2C_DA I2S_CL I2S_WS I2S_DA_OUT I2S_DA_IN1 ADR_DA ADR_WS ADR_CL DVSUP DVSUP DVSUP DVSS DVSS DVSS I2S_DA_IN2 RESETQ DACA_R DACA_L VREF2 DACM_R IN/OUT IN/OUT IN/OUT IN/OUT
connected clock data clock word strobe data output I2S1 data input data output word strobe clock Digital power supply Digital power supply Digital power supply Digital ground Digital ground Digital ground I2S2-data input connected connected connected Power-on-reset connected connected Headphone out, right Headphone out, left Reference ground Loudspeaker out, right
Micronas
2003; 6251-476-1DS
34x0G
PMQFP 80-11 PMQFP 64-2 PSDIP 64-1 PSDIP 52-1/-2
Name
Type
Connection
used)
Short Description
DACM_L DACM_SUB SC2_OUT_R SC2_OUT_L VREF1 SC1_OUT_R SC1_OUT_L CAPL_A AHVSUP CAPL_M AHVSS AHVSS AGNDC SC4_IN_L SC4_IN_R SC3_IN_L SC3_IN_R SC2_IN_L SC2_IN_R SC1_IN_L SC1_IN_R VREFTOP
Loudspeaker out, left connected Subwoofer output connected connected SCART output right SCART output left Reference ground SCART output right SCART output left Volume capacitor Analog power supply Volume capacitor MAIN connected connected Analog ground Analog ground Analog reference voltage connected SCART input, left SCART input, right Analog Shield Ground SCART input, left SCART input, right Analog Shield Ground SCART input, left SCART input, right Analog Shield Ground SCART input, left SCART input, right Reference voltage converter
AHVSS
AHVSS
AHVSS
AHVSS
2003; 6251-476-1DS
Micronas
34x0G
PMQFP 80-11 PMQFP 64-2 PSDIP 64-1 PSDIP 52-1/-2
Name
Type
Connection
used)
Short Description
MONO_IN AVSS AVSS AVSUP AVSUP ANA_IN1+ ANA_IN-
AVSS AVSS IN/OUT IN/OUT
connected Mono input Analog ground Analog ground connected connected Analog power supply Analog power supply input common (can left vacant, only input also use) input (can left vacant, only input also use) Test Crystal oscillator Crystal oscillator Test Audio clock output (18.432 MHz) connected connected D_CTR_I/O_1 D_CTR_I/O_0 address select Stand-by (low-active)
ANA_IN2+ TESTEN XTAL_IN XTAL_OUT AUD_CL_OUT D_CTR_I/O_1 D_CTR_I/O_0 ADR_SEL STANDBYQ
Micronas
2003; 6251-476-1DS
34x0G
4.3. Descriptions numbers refer PMQFP80-11 package. connected. I2C_CL Clock Input/Output (Fig. 4-17) this pin, I2C-bus clock signal supplied. signal pulled down case wait conditions. I2C_DA Data Input/Output (Fig. 4-17) this pin, I2C-bus data written read from MSP. I2S_CL Clock Input/Output (Fig. 4-18) Clock line bus. master mode, this line driven MSP; slave mode, external clock supplied. I2S_WS Word Strobe Input/Output (Fig. 4-18) Word strobe line bus. master mode, this line driven MSP; slave mode, external word strobe supplied. I2S_DA_OUT Data Output (Fig. 4-22) Output digital serial sound data bus. I2S_DA_IN1 Data Input (Fig. 4-14) First input digital serial sound data bus. ADR_DA Data Output (Fig. 4-22) Output digital serial data 3510A bus. ADR_WS Word Strobe Output (Fig. 4-22) Word strobe output bus. ADR_CL Clock Output (Fig. 4-22) Clock line bus. Pins DVSUP* Digital Supply Voltage Power supply digital circuitry MSP. Must connected +3.3 power supply. Pins DVSS* Digital Ground Ground connection digital circuitry MSP. I2S_DA_IN2 Data Input (Fig. 4-14) Second input digital serial sound data bus. Pins Pins connected. RESETQ Reset Input (Fig. 4-10) steady state, high level required. level resets 34x0G. Pins Pins connected.
Pins DACA_R/L Headphone Outputs (Fig. 4-20) Output headphone signal. 1-nF capacitor AHVSS must connected these pins. offset these pins depends selected headphone volume. VREF2 Reference Ground Reference analog ground. This must connected separately ground (AHVSS). VREF2 serves clean ground should used reference analog connections loudspeaker headphone outputs. Pins DACM_R/L Loudspeaker Outputs (Fig. 4-20) Output loudspeaker signal. 1-nF capacitor AHVSS must connected these pins. offset these pins depends selected loudspeaker volume. connected. DACM_SUB Subwoofer Output (Fig. 4-20) Output subwoofer signal. 1-nF capacitor AHVSS must connected this pin. frequency content subwoofer output, value capacitor increased better suppression high-frequency noise. offset this depends selected loudspeaker volume. Pins connected. Pins SC2_OUT_R/L SCART2 Outputs (Fig. 4-21) Output SCART2 signal. Connections these pins must 100- series resistor intended AC-coupled. VREF1 Reference Ground Reference analog ground. This must connected separately ground (AHVSS). VREF1 serves clean ground should used reference analog connections SCART outputs. Pins SC1_OUT_R/L SCART1 Outputs (Fig. 4-21) Output SCART1 signal. Connections these pins must 100- series resistor intended AC-coupled.
2003; 6251-476-1DS
Micronas
34x0G
Pins SC2_IN_L/R SCART2 Inputs (Fig. 4-13) analog input signal SCART2 this pin. Analog input connection must AC-coupled. Analog Shield Ground Analog ground (AHVSS) should connected this reduce cross-coupling between SCART inputs. Pins SC1_IN_L/R SCART1 Inputs (Fig. 4-13) analog input signal SCART1 this pin. Analog input connection must AC-coupled. VREFTOP Reference Voltage Converter (Fig. 4-15) this pin, reference voltage converter decoupled. must connected AVSS pins with 10-µF 100-nF capacitor parallel. Traces must kept short. connected. MONO_IN Mono Input (Fig. 4-13) analog mono input signal this pin. Analog input connection must AC-coupled. Pins AVSS* Ground Analog Power Supply Voltage Ground connection analog input circuitry MSP. Pins Pins connected. Pins AVSUP* Analog Power Supply Voltage Power supplied this analog input circuitry MSP. This must connected supply. ANA_IN1+ Input (Fig. 4-15) analog sound signal supplied this pin. Inputs must AC-coupled. This designed symmetrical input: ANA_IN1+ internally connected input symmetrical amp, ANA_IN- other. ANA_IN- Common (Fig. 4-15) This pins serves common reference ANA_IN1/ inputs. ANA_IN2+ Input (Fig. 4-15) analog sound signal supplied this pin. Inputs must AC-coupled. This designed symmetrical input: ANA_IN2+ internally connected input symmetrical amp, ANA_IN- other. TESTEN Test Enable (Fig. 4-11) This enables factory test modes. normal operation, must connected ground.
CAPL_A Volume Capacitor Headphone (Fig. 4-23) 10-µF capacitor AHVSUP must connected this pin. serves smoothing filter headphone volume changes order suppress audible plops. value capacitor lowered 1-µF faster response required. area encircled trace lines should minimized; keep traces short possible. This input sensitive magnetic induction. AHVSUP* Analog Power Supply High Voltage Power supplied this analog circuitry (except input). This must connected supply. CAPL_M Volume Capacitor Loudspeaker (Fig. 4-23) 10-µF capacitor AHVSUP must connected this pin. serves smoothing filter loudspeaker volume changes order suppress audible plops. value capacitor lowered faster response required. area encircled trace lines should minimized; keep traces short possible. This input sensitive magnetic induction. Pins Pins connected. Pins AHVSS* Ground Analog Power Supply High Voltage Ground connection analog circuitry (except input). AGNDC Internal Analog Reference Voltage This serves internal ground connection analog circuitry (except input). must connected VREF pins with 3.3-µF 100-nF capacitor parallel. This pins shows level typically 3.73 (with AHVSUP connected. Pins SC4_IN_L/R SCART4 Inputs (Fig. 4-13) analog input signal SCART4 this pin. Analog input connection must AC-coupled. Analog Shield Ground Analog ground (AHVSS) should connected this reduce cross-coupling between SCART inputs. Pins SC3_IN_L/R SCART3 Inputs (Fig. 4-13) analog input signal SCART3 this pin. Analog input connection must AC-coupled. Analog Shield Ground Analog ground (AHVSS) should connected this reduce cross-coupling between SCART inputs.
Micronas
2003; 6251-476-1DS
34x0G
Pins XTAL_IN, XTAL_OUT Crystal Input Output Pins (Fig. 4-19) These pins connected 18.432 crystal oscillator which digitally tuned integrated shunt capacitances. external clock into XTAL_IN. audio clock output signal AUD_CL_OUT derived from oscillator. External capacitors each crystal ground (AVSS) required. should verified layout, that supply current digital circuitry flowing through ground connection point. This enables factory test modes. normal operation, must left vacant. AUD_CL_OUT Audio Clock Output (Fig. 4-19) This 18.432 main clock output. Pins Pins connected. Pins D_CTR_I/O_1/0 Digital Control Input/ Output Pins (Fig. 4-18) General purpose input/output pins. D_CTR_I/O_1 used interrupt request controller. ADR_SEL Address Select (Fig. 4-16) means this pin, three device addresses selected. connected ground (I2C device addresses 80/81hex), supply (84/85hex), left open (88/89hex). STANDBYQ Stand-by normal operation, this must high. 34x0G switched first pulling STANDBYQ then (after >1µs delay) switching DVSUP AVSUP, keeping AHVSUP (`Standby'-mode), SCART switches maintain their position function. Application Note: ground pins should connected low-resistive ground plane. supply pins should connected separately with short low-resistive lines power supply. Decoupling capacitors from DVSUP DVSS, AVSUP AVSS, AHVSUP AHVSS recommended closely possible these pins. Decoupling DVSUP DVSS most important. recommend using more than capacitor. choosing different values, frequency range active decoupling extended. application boards use: capacitor with lowest value should placed nearest DVSUP DVSS pins. pins should connected closely possible ground. they lead with SCART-inputs shielding lines, they should connected ground SCART connector.
2003; 6251-476-1DS
Micronas
34x0G
4.4. Configurations
AUD_CL_OUT D_CTR_I/O_1 D_CTR_I/O_0 ADR_SEL STANDBYQ I2C_CL I2C_DA I2S_CL I2S_WS I2S_DA_OUT I2S_DA_IN1 ADR_DA ADR_WS ADR_CL DVSUP DVSS I2S_DA_IN2 RESETQ DACA_R DACA_L VREF2 DACM_R DACM_L DACM_SUB
XTAL_OUT XTAL_IN TESTEN ANA_IN2+ ANA_IN- ANA_IN+ AVSUP AVSS MONO_IN VREFTOP SC1_IN_R SC1_IN_L SC2_IN_R SC2_IN_L SC3_IN_R SC3_IN_L SC4_IN_R SC4_IN_L AGNDC AHVSS CAPL_M AHVSUP CAPL_A SC1_OUT_L SC1_OUT_R VREF1 SC2_OUT_L SC2_OUT_R
AUD_CL_OUT D_CTR_I/O_1 D_CTR_I/O_0 ADR_SEL STANDBYQ I2C_CL I2C_DA I2S_CL I2S_WS I2S_DA_OUT I2S_DA_IN1 ADR_DA ADR_WS ADR_CL DVSUP DVSS I2S_DA_IN2 RESETQ DACA_R DACA_L VREF2 DACM_R DACM_L DACM_SUB
XTAL_OUT XTAL_IN TESTEN ANA_IN2+ ANA_IN- ANA_IN1+ AVSUP AVSS MONO_IN VREFTOP SC1_IN_R SC1_IN_L SC2_IN_R SC2_IN_L SC3_IN_R SC3_IN_L AGNDC AHVSS CAPL_M AHVSUP CAPL_A SC1_OUT_L SC1_OUT_R VREF1 SC2_OUT_L SC2_OUT_R
34x0G
34x0G
Fig. 4-7: PSDIP52-1/-2 package
Fig. 4-6: PSDIP64-1 package
Micronas
2003; 6251-476-1DS
34x0G
SC2_IN_L SC2_IN_R SC1_IN_L SC1_IN_R VREFTOP MONO_IN AVSS AVSS
SC3_IN_R SC3_IN_L SC4_IN_R SC4_IN_L AGNDC AHVSS AHVSS
AVSUP AVSUP ANA_IN1+ ANA_IN- ANA_IN2+ TESTEN XTAL_IN XTAL_OUT AUD_CL_OUT D_CTR_I/O_1 D_CTR_I/O_0 ADR_SEL STANDBYQ
CAPL_M AHVSUP CAPL_A SC1_OUT_L SC1_OUT_R VREF1 SC2_OUT_L SC2_OUT_R DACM_SUB DACM_L DACM_R VREF2 DACA_L
34x0G
I2C_CL I2C_DA I2S_CL I2S_WS I2S_DA_OUT I2S_DA_IN1 ADR_DA ADR_WS ADR_CL DVSUP DVSUP I2S_DA_IN2 DVSS DVSS DVSS DVSUP RESETQ
DACA_R
Fig. 4-8: PMQFP80-11 package
2003; 6251-476-1DS
Micronas
34x0G
SC2_IN_L SC2_IN_R SC1_IN_L SC1_IN_R VREFTOP MONO_IN AVSS
SC3_IN_R SC3_IN_L SC4_IN_R SC4_IN_L AGNDC AHVSS
AVSUP ANA_IN1+ ANA_IN- ANA_IN2+ TESTEN XTAL_IN XTAL_OUT AUD_CL_OUT D_CTR_I/OUT1 D_CTR_I/OUT0 ADR_SEL STANDBYQ I2C_CL I2C_DA I2S_CL I2S_WS I2S_DA_OUT I2S_DA_IN1 ADR_DA ADR_WS I2S_DA_IN2 DVSS DVSUP ADR_CL RESETQ CAPL_M AHVSUP CAPL_A SC1_OUT_L SC1_OUT_R VREF1 SC2_OUT_L SC2_OUT_R DACM_SUB DACM_L DACM_R VREF2 DACA_L DACA_R
34x0G
Fig. 4-9: PMQFP64-2 package
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2003; 6251-476-1DS
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4.5. Circuits DVSUP
>300
DVSS Fig. 4-10: Input Pin: RESETQ ADR_SEL Fig. 4-16: Input Pin: ADR_SEL AVSUP
Fig. 4-11: Input TESTEN
Fig. 4-17: Input/Output Pins: I2C_CL, I2C_DA
3.75
DVSUP Fig. 4-12: Input Pin: MONO_IN
3.75
Fig. 4-18: Input/Output Pins: I2S_CL, I2S_WS, D_CTR_I/O_1, D_CTR_I/O_0
Fig. 4-13: Input Pins: SC4-1_IN_L/R
Fig. 4-14: Input Pins: I2S_DA_IN1, I2S_DA_IN2, STANDBYQ
3-30
ANA_IN1+ ANA_IN2+
3-30
Fig. 4-19: Input/Output Pins: XTAL_IN, XTAL_OUT, AUD_CL_OUT
ANA_IN- VREFTOP
Fig. 4-15: Input Pins: VREFTOP, ANA_IN1+, ANA_IN-, ANA_IN2+
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AHVSUP
0.1.2
Fig. 4-20: Output Pins: DACA_R/L, DACM_R/L, DACM_SUB
3.75
Fig. 4-21: Output Pins: SC_2_OUT_R/L, SC_1_OUT_R/L
DVSUP Fig. 4-22: Output Pins: I2S_DA_OUT, ADR_DA, ADR_WS, ADR_CL
Fig. 4-23: Capacitor Pins: CAPL_A, CAPL_M
3.75
Fig. 4-24: Pin: AGNDC
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2003; 6251-476-1DS
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4.6. Electrical Characteristics Abbreviations: defined vacant applicable positive current values mean current flowing into chip
4.6.1. Absolute Maximum Ratings Stresses beyond those listed "Absolute Maximum Ratings" cause permanent damage device. This stress rating only. Functional operation device these conditions implied. Exposure absolut maximum rating conditions extended periods will affect device reliability. voltages listed referenced ground except where noted. grounds must externally connected ohmic. This device contains circuitry protect inputs outputs against damage high static voltages electric fields; however, advised that normal precautions taken avoid application voltage higher than absolut maximum-rated voltages this high-impedance circuit. Table 4-1: Absolute Maximum Ratings Symbol Parameter Name Min. TA1) Ambient Operating Temperature PSDIP64-1 PSDIP52-1/-2 PMQFP80-11 PMQFP64-2 Case Operating Temperature PSDIP64-1 PSDIP52-1/-2 PMQFP80-11 PMQFP64-2 Storage Temperature Maximum Power Dissipation PSDIP64-1 PSDIP52-1/-2 PMQFP80-11 PMQFP64-2 Supply Voltage Supply Voltage Supply Voltage Input Voltage, Digital Inputs Input Current, Digital Pins AHVSUP DVSUP AVSUP -0.3 -0.3 -0.3 -0.3 1300 1200 1000 VSUP2+0.3 Limit Values Max. Unit
PMAX
VSUP1 VSUP2 VSUP3 VIdig IIdig
Measured standard board according JESD Standard with maximum power consumption allowed this package.
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Table 4-1: Absolute Maximum Ratings, continued Symbol Parameter Name Min. VIana IIana IOana IOana ICana
Limit Values Max. VSUP1+0.3
Unit
Input Voltage, Analog Inputs Input Current, Analog Inputs Output Current, SCART Outputs Output Current, Analog Outputs except SCART Outputs Output Current, other pins connected capacitors
SCn_IN_s,1) MONO_IN SCn_IN_s,1) MONO_IN SCn_OUT_s1) DACp_s1) CAPL_p,1) AGNDC
-0.3
means "1", "2", "3", "4", means "R", means analog outputs short-circuit proof with respect Supply Voltage ground.
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4.6.2. Recommended Operating Conditions
Functional operation device beyond those indicated "Recommended Operating Conditions/Characteristics" implied will result unpredictable behaviour device result device destruction. voltages listed referenced ground (VSS except where noted. grounds must externally connected ohmic. insert device into live socket. Instead, apply power switching external power supply. power-up/-down sequences, instructions Section 4.6.3.3. this document.
4.6.2.1. General Recommended Operating Conditions Symbol Parameter Name Min. Ambient Operating Temperature PSDIP64-1 PSDIP52-1/-2 PMQFP80-11 PMQFP64-2 Case Operating Temperature PSDIP64-1 PSDIP52-1/-2 PMQFP80-11 PMQFP64-2 Supply Voltage (AHVSUP Supply Voltage (AHVSUP VSUP2 Supply Voltage (DVSUP Supply Voltage (DVSUP VSUP3 tSTBYQ1
Limit Values Typ. Max.
Unit
AHVSUP 4.75 DVSUP 4.75 3.15 AVSUP STANDBYQ, DVSUP 4.75 5.25 5.25 3.45 5.25
VSUP1
Supply Voltage STANDBYQ Setup Time before Turn-off Second Supply Voltage
power-optimized board layout recommended. Case Operating Temperatures mentioned Recommended Operating Conditions must exceeded worst case conditions application.
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4.6.2.2. Analog Input Output Recommendations Symbol Parameter Name Min. CAGNDC AGNDC-Filter-Capacitor Ceramic Capacitor Parallel CinSC VinSC VinMONO RLSC CLSC CVMA CFMA
Limit Values Typ. Max.
Unit
AGNDC
-20% -20%
VRMS VRMS +10%
DC-Decoupling Capacitor front SCART Inputs SCART Input Level Input Level, Mono Input SCART Load Resistance SCART Load Capacitance Main/AUX Volume Capacitor Main/AUX Filter Capacitor
SCn_IN_s1)
-20%
MONO_IN SCn_OUT_s1)
CAPL_p DACp_s1) -10%
means "1", "2", "3", "4", means "R", means
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4.6.2.3. Recommendations Analog Sound Input Signal Symbol Parameter Name Min. CVREFTOP VREFTOP-Filter-Capacitor Ceramic Capacitor Parallel FIF_FMTV FIF_FMRADIO VIF_FM VIF_AM RFMNI Analog Input Frequency Range Applications Analog Input Frequency FM-Radio Applications Analog Input Range FM/NICAM Analog Input Range AM/NICAM Ratio: NICAM Carrier/FM Carrier (unmodulated carriers) Ratio: NICAM Carrier/AM Carrier (unmodulated carriers) Ratio: FM-Main/FM-Sub Satellite Ratio: FM1/FM2 German FM-System Ratio: Main Carrier/ Color Carrier Ratio: Main Carrier/ Luma Components Passband Ripple Suppression Spectrum above (not Radio) Maximum FM-Deviation (approx.) normal mode HDEV2: high deviation mode HDEV3: very high deviation mode ANA_IN1+, ANA_IN2+, ANA_IN- VREFTOP -20% -20% 10.7 0.45 Limit Values Typ. Max.
Unit
RAMNI RFM1/FM2 PRIF SUPHF FMMAX
±180 ±360 ±540
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4.6.2.4. Crystal Recommendations Symbol Parameter Name Min. Typ. Max. Unit
General Crystal Recommendations Crystal Parallel Resonance Frequency Load Capacitance Crystal Series Resistance Crystal Shunt (Parallel) Capacitance External Load Capacitance1) XTAL_IN, XTAL_OUT 18.432
PSDIP approx. PMQFP approx.
Crystal Recommendations Master-Slave Applications (MSP-clock must perform synchronization clock) fTOL DTEM Accuracy Adjustment Frequency Variation versus Temperature Motional (Dynamic) Capacitance Required Open Loop Clock Frequency (Tamb AUD_CL_OUT 18.431 18.433
Crystal Recommendations NICAM Applications MSP-clock synchronization clock possible) fTOL DTEM Accuracy Adjustment Frequency Variation versus Temperature Motional (Dynamic) Capacitance Required Open Loop Clock Frequency (Tamb AUD_CL_OUT
18.4305 18.4335
Crystal Recommendations analog FM/AM Applications MSP-clock synchronization clock possible) fTOL DTEM Accuracy Adjustment Frequency Variation versus Temperature Required Open Loop Clock Frequency (Tamb AUD_CL_OUT -100 18.429 +100 18.435
Amplitude Recommendation Operation with External Clock Input (Cload after reset typ. VXCA
External Clock Amplitude
XTAL_IN
External capacitors each crystal ground required. They necessary tune open-loop frequency internal stabilize frequency closed-loop operation. different layouts, accurate capacitor value should determined with customer PCB. suggested values (1.5.3.3 figures based experience should serve "start value". adjust capacitor value, reset MSP. After reset, telegrams should transmitted. Measure frequency AUD_CL_OUT-pin. Change capacitor value until free running frequency matches 18.432 closely possible. higher capacity, lower resulting clock frequency.
Note: minimize adjustment tolerances MSP-generations, strongly recommended socalled MSP-XTAL-REF (available packages) capacitor adjustment.
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4.6.3. Characteristics Min./Max. values: fCLOCK 18.432 VSUP1 (4.75 5.25 VSUP1 VSUP2 4.75 5.25 (3.15 3.45 VSUP2 VSUP3 4.75 fCLOCK 18.432 VSUP1 noted) VSUP2 (3.3 noted) VSUP3
typical values:
Junction Temperature MAIN Loudspeaker Channel, Headphone Channel
4.6.3.1. General Characteristics
Symbol Parameter Name Min. Supply ISUP1A First Supply Current (active) (AHVSUP First Supply Current (active) (AHVSUP ISUP2A Second Supply Current (active) (DVSUP Second Supply Current (active) (DVSUP ISUP3A ISUP1S Third Supply Current (active) First Supply Current (AHVSUP First Supply Current (AHVSUP Clock fCLOCK DCLOCK tJITTER VxtalDC tStartup VACLKAC VACLKDC routHF_ACL Clock Input Frequency Clock High Ratio Clock Jitter (Verification provided Production Test) DC-Voltage Oscillator Oscillator Startup Time Slew-rate Audio Clock Output Voltage Audio Clock Output Voltage Output Resistance XTAL_IN, XTAL_OUT AUD_CL_OUT XTAL_IN 18.432 VSUP3 load Imax AVSUP AHVSUP DVSUP AHVSUP STANDBYQ Vol. Main Vol. Main -30dB Vol. Main Vol. Main Limit Values Typ. Max. Unit Test Conditions
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4.6.3.2. Digital Inputs, Digital Outputs
Symbol Parameter Name Min. Digital Input Levels VDIGIL VDIGIH ZDIGI IDLEAK VDIGIL VDIGIH IADRSEL Digital Input Voltage Digital Input High Voltage Input Impedance Digital Input Leakage Current Digital Input Voltage Digital Input High Voltage Input Current Address Select ADR_SEL -500 -220 Digital Output Levels VDCTROL VDCTROH Digital Output Voltage Digital Output High Voltage D_CTR_I/O_0 D_CTR_I/O_1 VSUP2 -0.3 IDDCTR IDDCTR STANDBYQ D_CTR_I/O_0/1 VSUP2 VSUP2 VSUP2 VSUP2 UADR_SEL= DVSS UADR_SEL= DVSUP UINPUT< DVSUP D_CTR_I/O_0/1: tri-state Limit Values Typ. Max. Unit Test Conditions
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4.6.3.3. Reset Input Power-Up
Symbol Parameter Name Min. RESETQ Input Levels VRHL VRLH ZRES IRES Reset High-Low Transition Voltage Reset Low-High Transition Voltage Input Capacitance Input High Current RESETQ 0.45 VSUP2 VSUP2 Limit Values Typ. Max. Unit
Test Conditions
URESETQ DVSUP
DVSUP AVSUP
t/ms
RESETQ
Low-to-High Threshold High-to-Low Threshold
Note: reset should reach high level before oscillator started. This requires reset delay 0.45 DVSUP means 2.25 Volt with DVSUP t/ms
Reset Delay
Internal Reset
High
t/ms Fig. 4-25: Power-up sequence
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4.6.3.4. I2C-Bus Characteristics
Symbol Parameter Name Min. VI2CIL VI2CIH tI2C1 tI2C2 tI2C5 tI2C6 tI2C3 tI2C4 fI2C VI2COL II2COH tI2COL1 tI2COL2 I2C-Bus Input Voltage C-Bus Input High Voltage Start Condition Setup Time Stop Condition Setup Time
Limit Values Typ. Max.
Unit
Test Conditions
I2C_CL, I2C_DA
VSUP2 VSUP2
I2C-Data Setup Time before Rising Edge Clock I2C-Data Hold Time after Falling Edge Clock I2C-Clock Pulse Time C-Clock High Pulse Time C-BUS Frequency I2C-Data Output Voltage I2C-Data Output High Leakage Current I2C_CL, I2C_DA
I2C_CL
fI2C II2COL VI2COH
I2C-Data Output Hold Time after Falling Edge Clock I2C-Data Output Setup Time before Rising Edge Clock
1/FI2C I2C_CL TI2C4 TI2C3
TI2C1 I2C_DA input
TI2C5
TI2C6
TI2C2
TI2COL2 I2C_DA output
TI2COL1
Fig. 4-26: timing diagram
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4.6.3.5. I2S-Bus Characteristics
Symbol Parameter Name Min. VI2SIL VI2SIH ZI2SI ILEAKI2S VI2SOL VI2SOH fI2SOWS fI2SOCL RI2S10/I2S20 ts_I2S th_I2S td_I2S Input Voltage Input High Voltage Input Impedance Input Leakage Current Output Voltage Output High Voltage I2S-Word Strobe Output Frequency I2S-Clock Output Frequency I2S-Clock Output High/Low-Ratio Input Setup Time before Rising Edge Clock Input Hold Time after Rising Edge Clock Output Delay Time after Falling Edge Clock I2S-Word Strobe Input Frequency S-Clock Input Frequency I2S-Clock Input High/Low Ratio
Limit Values Typ. Max. VSUP2 32.0 1.024 2.048
Unit
Test Conditions
I2S_DA_IN1/2 I2S_CL I2S_WS
VSUP2 VSUP2 I2S_CONFIG[0] I2S_CONFIG[0] UINPUT< DVSUP II2SOL II2SOH
I2S_CL I2S_WS I2S_DA_OUT I2S_WS I2S_CL
I2S_CL I2S_DA_IN1/2
details Fig. 4-27 "I2S timing diagram"
I2S_CL I2S_WS I2S_DA_OUT I2S_WS I2S_CL 32.0 1.024
fI2SWS fI2SCL RI2SCL
2.048
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1/FI2SWS I2S_WS
MODUS[6] MODUS[6]
Detail
I2S_CL Detail I2S_DA_IN
16/32 left channel Detail I2S_DA_OUT
16/32 right channel
16/32 left channel
16/32 right channel
Data: first, master
1/FI2SWS I2S_WS
MODUS[6] MODUS[6]
Detail
I2S_CL Detail I2S_DA_IN
16,18.32 left channel Detail I2S_DA_OUT
18.32 right channel
18.32 left channel
18.32 right channel
Data: first, slave
Detail
I2S_CL
1/FI2SCL
Detail
I2S_CL
Ts_I2S Ts_I2S I2S_DA_IN1/2 I2S_WS INPUT
Th_I2S
Td_I2S
Td_I2S
I2S_WS OUTPUT
I2S_DA_OUT
Fig. 4-27: timing diagram
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4.6.3.6. Analog Baseband Inputs Outputs, AGNDC
Symbol Parameter Name Min. Analog Ground VAGNDC0 AGNDC Open Circuit Voltage (AHVSUP AGNDC Open Circuit Voltage (AHVSUP RoutAGN AGNDC Output Resistance (AHVSUP AGNDC Output Resistance (AHVSUP Analog Input Resistance RinSC RinMONO SCART Input Resistance from MONO Input Resistance from SCn_IN_s1) MONO_IN AGNDC 3.77 2.51 Limit Values Typ. Max. Unit
Test Conditions
Rload
VAGNDC
fsignal kHz, 0.05 fsignal kHz,
Audio Analog-to-Digital-Converter VAICL Analog Input Clipping Level Analog-to-DigitalConversion (AHVSUP Analog Input Clipping Level Analog-to-DigitalConversion (AHVSUP SCART Outputs RoutSC SCART Output Resistance SCn_OUT_s1) Deviation DC-Level SCART Output from AGNDC Voltage Gain from Analog Input SCART Output Frequency Response from Analog Input SCART Output Signal Level SCART Output (AHVSUP Signal Level SCART Output (AHVSUP
SCn_IN_s,1) MONO_IN
2.00
2.25
VRMS
fsignal
1.13
1.51
VRMS
+0.5 +0.5
VRMS VRMS
fsignal kHz,
dVOUTSC ASCtoSC frSCtoSC VoutSC
SCn_IN_s,1) MONO_IN SCn_OUT_s1) SCn_OUT_s1) -1.0 -0.5 1.17 1.27
fsignal with resp. Bandwidth: 20000 fsignal Volume Full Scale input from
1.37
means "1", "2", "3", "4";
means
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Symbol
Parameter
Name Min.
Limit Values Typ. Max.
Unit
Test Conditions
Main Outputs RoutMA Main/AUX Output Resistance DACp_s1) VoutDCMA DC-Level Main/AUX-Output (AHVSUP DC-Level Main/AUX-Output (AHVSUP VoutMA Signal Level Main/AUX-Output (AHVSUP Signal Level Main/AUX-Output (AHVSUP
2.04 1.36 1.37 0.90
2.28 1.60 1.51 1.04
VRMS VRMS
fsignal kHz, Volume Volume Volume Volume fsignal Volume Full scale input from
1.80 1.12 1.23 0.76
means "R";
means
4.6.3.7. Sound Inputs
Symbol Parameter Name Min. RIFIN Input Impedance ANA_IN1+, ANA_IN2+, ANA_IN- VREFTOP ANA_IN1+, ANA_IN2+, ANA_IN- ANA_IN1+, ANA_IN2+, ANA_IN- 2.45 Limit Values Typ. 2.65 Max. 11.4 2.75 Gain Gain Unit Test Conditions
DCVREFTOP DCANA_IN
Voltage VREFTOP Voltage Inputs
XTALKIF BWIF
Crosstalk Attenuation Bandwidth Step Width
0.85
fsignal Input Level
4.6.3.8. Power Supply Rejection
Symbol Parameter Name Min. PSRR: Rejection Noise AHVSUP PSRR AGNDC From Analog Input Output From Analog Input SCART Output From Input SCART Output From Input MAIN Output
Limit Values Typ. Max.
Unit
Test Conditions
AGNDC MONO_IN, SCn_IN_s1) MONO_IN, SCn_IN_s1) SCn_OUT_s1) SCn_OUT_s1) DACp_s
means "1", "2", "3", "4";
means "R";
means
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4.6.3.9. Analog Performance
Symbol Parameter Name Min. Specifications AHVSUP Dynamic Range Signal-to-Noise Ratio from Analog Input Output MONO_IN, SCn_IN_s1) Limit Values Typ. Max. Unit
Test Conditions
Input Level with resp. VAICL, fsig kHz, A-weighted Hz.16 Input Level fsig kHz, A-weighted Hz.20 Input Level fsig kHz, A-weighted Hz.16 Input Level fsig kHz, A-weighted Hz.16
from Analog Input SCART Output
MONO_IN, SCn_IN_s1) SCn_OUT_s1) SCn_OUT_s1)
from Input SCART Output
from Input Main/AUX-Output Analog Volume Analog Volume Total Harmonic Distortion from Analog Input Output
DACp_s1)
MONO_IN, SCn_IN_s1)
0.008
0.03
Input Level with resp. VAICL, fsig kHz, unweighted Hz.16 Input Level dBr, fsig kHz, unweighted Hz.20 Input Level dBr, fsig kHz, unweighted Hz.16 Input Level dBr, fsig kHz, unweighted Hz.16
from Analog Input SCART Output
MONO_IN, SCn_IN_s SCn_OUT_s1) SCn_OUT_s1)
0.008
0.03
from Input SCART Output
0.008
0.03
from Input Main Output
DACp_s1)
0.008
0.03
means "1", "2", "3", "4";
means "R";
means
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Symbol
Parameter
Name Min.
Limit Values Typ. Max.
Unit
Test Conditions
Specifications AHVSUP Dynamic Range Signal-to-Noise Ratio from Analog Input Output MONO_IN, SCn_IN_s1) Input Level with resp. VAICL, fsig kHz, A-weighted Hz.16 Input Level fsig kHz, A-weighted Hz.20 Input Level fsig kHz, A-weighted Hz.16 Input Level fsig kHz, A-weighted Hz.16
from Analog Input SCART Output
MONO_IN, SCn_IN_s1) SCn_OUT_s1) SCn_OUT_s1)
from Input SCART Output
from Input Main/AUX-Output Analog Volume Analog Volume Total Harmonic Distortion from Analog Input Output
DACp_s1)
MONO_IN, SCn_IN_s1)
0.03
Input Level with resp. VAICL, fsig kHz, unweighted Hz.16 Input Level dBr, fsig kHz, unweighted Hz.20 Input Level dBr, fsig kHz, unweighted Hz.16 Input Level dBr, fsig kHz, unweighted Hz.16
from Analog Input SCART Output
MONO_IN, SCn_IN_s SCn_OUT_s1) SCn_OUT_s1)
from Input SCART Output
from Input Main Output
DACp_s1)
means "1", "2", "3", "4";
means "R";
means
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Symbol
Parameter
Name Min.
Limit Values Typ. Max.
Unit
Test Conditions
CROSSTALK Specifications XTALK Crosstalk Attenuation Input Level fsig kHz, unused analog inputs connected ground unweighted Hz.20 unweighted Hz.16 (unweighted Hz.20 same signal source left right disturbing channel, effect each observed output channel
between left right channel within SCART Input/Output pair (LR, SCn_IN SCn_OUT1) SC1_IN SC2_IN Output SC3_IN Output Input SCn_OUT1) between left right channel within Main Output pair Input DACp1) between SCART Input/Output pairs disturbing program observed program MONO/SCn_IN SCn_OUT MONO/SCn_IN SCn_OUT1) MONO/SCn_IN SCn_OUT unsel. MONO/SCn_IN Output MONO/SCn_IN SCn_OUT Input SCn_OUT1) MONO/SCn_IN unselected Input SC1_OUT1) Crosstalk between Main Output pairs Input DACp1)
(unweighted Hz.16 kHz) same signal source left right disturbing channel, effect each observed output channel (unweighted Hz.20 kHz) same signal source left right disturbing channel, effect each observed output channel SCART output load resistance SCART output load resistance
XTALK
Crosstalk from Main Output SCART Output vice versa disturbing program observed program MONO/SCn_IN/DSP SCn_OUT Input DACp1) MONO/SCn_IN/DSP SCn_OUT Input DACp1) Input DACp MONO/SCn_IN SCn_OUT1) Input DACM Input SCn_OUT1) means
means "1", "2", "3", "4";
means "R";
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4.6.3.10. Sound Standard Dependent Characteristics
Symbol Parameter Name Min. NICAM Characteristics (MSP Standard Code dVNICAMOUT S/NNICAM Tolerance Output Voltage NICAM Baseband Signal NICAM Baseband Signal DACp_s SCn_OUT_s1 -1.5 +1.5 2.12 kHz, Modulator input level dBref NICAM: kHz, unweighted kHz, NIC_Presc 7Fhex Output level VRMS DACp_s 2.12 kHz, Modulator input level dBref FM+NICAM, norm conditions Modulator input level dBref; Limit Values Typ. Max. Unit Test Conditions
THDNICAM BERNICAM fRNICAM XTALKNICAM SEPNICAM
Total Harmonic Distortion Noise NICAM Baseband Signal NICAM: Error Rate NICAM Frequency Response 20.15000 NICAM Crosstalk Attenuation (Dual) NICAM Channel Separation (Stereo) -1.0
+1.0
10-7
Characteristics (MSP Standard Code dVFMOUT S/NFM THDFM Tolerance Output Voltage Demodulated Signal Demodulated Signal Total Harmonic Distortion Noise Demodulated Signal DACp_s, SCn_OUT_s1 -1.5 +1.5 FM-carrier, kHz, deviation; FM-carrier MHz, kHz, deviation; RMS, unweighted (for S/N); full input range, FM-Prescale 46hex, Output Level VRMS DACp_s FM-carrier MHz, Modulator input level -14.6 dBref; FM-carriers 5.5/5.74 MHz, kHz, deviation; Bandpass FM-carriers 5.5/5.74 MHz, kHz, deviation;
fRFM
Frequency Responses, 20.15000 Crosstalk Attenuation (Dual)
-1.0
+1.0
XTALKFM
SEPFM
Channel Separation (Stereo)
Characteristics (MSP Standard Code S/NAM(1) S/NAM(2) THDAM fRAM
Demodulated Signal measurement condition: RMS/Flat Demodulated Signal measurement condition: QP/CCIR Total Harmonic Distortion Noise Demodulated Signal Frequency Response 50.12000 means "R";
DACp_s, SCn_OUT_s1
-2.5 +1.0
level: 0.1-0.8 AM-carrier FM/AM prescaler output VRMS Loudspeaker out; Standard Code 09hex video/chroma components
means "2";
means
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Symbol
Parameter
Name Min.
Limit Values Typ. Max.
Unit
Test Conditions
BTSC Characteristics (MSP Standard Code 20hex, 21hex) S/NBTSC BTSC Stereo Signal BTSC-SAP Signal DACp_s, SCn_OUT_s1) SAP, 100% modulation, deemphasis, unweighted SAP, 100% EIM2), MNR, unweighted SAP, 1%.66% EIM2),
THDBTSC
THD+N BTSC Stereo Signal THD+N BTSC Signal
fRDBX
Frequency Response BTSC Stereo, Hz.12 Frequency Response BTSCSAP, Hz.9
-1.0 -1.0 -2.0 -2.0
fRMNR
Frequency Response BTSC Stereo, Hz.12 Frequency Response BTSCSAP, Hz.9
5%.66% EIM2), SAP, white noise, Modulation, SAP, 100% modulation, deemphasis, Bandpass 1%.66% EIM2), Modulation, carrier modulated with 15.734 level mVpp indication: STATUS Bit[6] standard BTSC stereo signal, sound carrier only
XTALKBTSC
Stereo Stereo
SEPDBX
Stereo Separation Hz.10 Hz.12 Stereo Separation Pilot deviation threshold Stereo Stereo ANA_IN1+, ANA_IN2+
SEPMNR FMpil
15.563
15.843
fPilot
Pilot Frequency Range
means "2"; means "R"; means refers 75-µs Equivalent Input Modulation. defined audio-signal level which results stated percentage modulation, when encoding process replaced 75-µs preemphasis network.
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Symbol
Parameter
Name Min.
Limit Values Typ. Max.
Unit
Test Conditions
BTSC Characteristics (MSP Standard Code 20hex, 21hex) with minimum input signal level mVpp (measured without video/chroma signal components) S/NBTSC BTSC Stereo Signal BTSC-SAP Signal DACp_s, SCn_OUT_s1 SAP, 100% modulation, deemphasis, unweighted SAP, 100% EIM2), MNR, unweighted SAP, 1%.66% EIM2),
THDBTSC
THD+N BTSC Stereo Signal THD+N BTSC Signal
0.15
fRDBX
Frequency Response BTSC Stereo, Hz.12 Frequency Response BTSCSAP, Hz.9
-1.0 -1.0 -2.0 -2.0
fRMNR
Frequency Response BTSC Stereo, Hz.12 Frequency Response BTSCSAP, Hz.9
5%.66% EIM2), SAP, white noise, Modulation, SAP, 100% modulation, deemphasis, Bandpass 1%.66% EIM2), Modulation,
XTALKBTSC
Stereo Stereo
SEPDBX
Stereo Sep
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