323xD Comb Filter Video Processor Edition July 2001 6251-472-1PD
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323xD Comb Filter Video Processor
Edition July 2001 6251-472-1PD
323xD
Contents Page Section 1.1. 1.2. 1.3. 2.1. 2.1.1. 2.1.2. 2.1.3. 2.1.4. 2.1.5. 2.1.6. 2.2. 2.3. 2.3.1. 2.3.2. 2.3.3. 2.3.4. 2.3.5. 2.3.6. 2.3.7. 2.3.8. 2.3.9. 2.3.10. 2.4. 2.4.1. 2.4.2. 2.4.3. 2.4.4. 2.4.4.1. 2.4.4.2. 2.4.4.3. 2.4.5. 2.4.6. 2.5. 2.5.1. 2.5.2. 2.5.3. 2.5.4. 2.6. 2.7. 2.8. 2.9. 2.9.1. 2.9.2. 2.9.3. Title Introduction System Architecture Video Processor Family Applications Functional Description Analog Video Front-End Input Selector Clamping Automatic Gain Control Analog-to-Digital Converters Digitally Controlled Clock Oscillator Analog Video Output Adaptive Comb Filter Color Decoder IF-Compensation Demodulator Chrominance Filter Frequency Demodulator Burst Detection Saturation Control Color Killer Operation Automatic standard recognition Compensation /1-H Comb Filter Luminance Notch Filter Skew Filtering Component Interface Processor Component Analog Front-End Matrix Component YCrCb Control Softmixer Static Switch Mode Static Mixer Mode Dynamic Mixer Mode 4:4:4 4:2:2 Downsampling Fast Blank Signal Monitoring Horizontal Scaler Horizontal Lowpass-filter Horizontal Prescaler Horizontal Scaling Engine Horizontal Peaking-filter Vertical Scaler Contrast Brightness Blackline Detector Control Data Output Signals Line-Locked Clock Generation Sync Signals DIGIT3000 Output Format
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Contents, continued Page Section 2.9.4. 2.9.5. 2.9.6. 2.9.7. 2.9.8. 2.9.9. 2.10. 2.10.1. 2.11. 2.12. 2.12.1. 2.12.2. 2.12.3. 2.12.4. 2.12.5. 2.12.6. 2.12.7. 2.12.8. 2.12.9. 2.12.10. 2.12.11. 3.1. 3.2. 3.2.1. 3.2.2. 4.1. 4.2. 4.3. 4.4. 4.5. 4.6. 4.6.1. 4.6.2. 4.6.3. 4.6.4. 4.6.4.1. 4.6.4.2. 4.6.4.3. 4.6.4.4. 4.6.4.5. 4.6.4.6. Title Line-Locked 4:2:2 Output Format Line-Locked 4:1:1 Output Format ITU-R Output Format Output Code Levels Output Ports Test Pattern Generator PAL+ Support Output Signals PAL+/Color+ Support Video Sync Processing Picture Picture (PIP) Processing Control Configurations Display Modes Predefined Inset Picture Size Acquisition Display Window Frame Background Color Vertical Shift Main Picture Free Running Display Mode Frame Field Display Mode External Field Memory Field-Buffer-Extension Mode Double-Windows-Extension Mode Serial Interface I2C-Bus Interface Control Status Registers Calculation Vertical East-West Deflection Coefficients Scaler Adjustment Specifications Outline Dimensions Connections Short Descriptions Descriptions (pin numbers PQFP80 package) Configuration Circuits Electrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions Recommended Crystal Characteristics Characteristics Characteristics, Clock Output Characteristics, Clock Input/Output, External Clock Input (XTAL1) Characteristics, Reset Input, Test Input, VGAV Input, YCOEQ Input Characteristics, Power-up Sequence Characteristics, FPDAT Input/Output Characteristics, Interface
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323xD
Contents, continued Page Section 4.6.4.7. 4.6.4.8. 4.6.4.9. 4.6.4.10. 4.6.4.11. 4.6.4.12. 4.6.4.13. 5.1. 5.2. 5.2.1. 5.2.2. 5.2.3. 5.2.3.1. 5.2.3.2. 5.2.3.3. Title Characteristics, Address Select I2CSEL Input Characteristics, Analog Video Component Inputs Characteristics, Analog Front-End ADCs Characteristics, Analog Input Characteristics, Output Specification Characteristics, Input Specification Characteristics, Clock Output Specification Application Circuit Application Note: mode with 323xD Application Note: Mode Programming Procedure Program Mode Registers Programming Control Examples Select Predefined Mode Select Strobe Effect Expert Mode Select Predefined Mode Tuner Scanning Data Sheet History
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323xD
Comb Filter Video Processor
Introduction 323xD high-quality, single-chip video front-end, which targeted 16:9, 50/60-Hz 100/120 sets. combined with other members DIGIT3000 family (such 331x) and/or used with 3rd-party products. main features 323xD high-performance adaptive comb filter separator with adjustable vertical peaking multi-standard color decoder PAL/NTSC/SECAM including substandards four CVBS, S-VHS input, CVBS output RGB/YCrCb component inputs, Fast Blank (FB) input integrated high-quality converters associated clamp circuits multi-standard sync processing linear horizontal scaling (0.25 well non-linear horizontal scaling `Panoramavision' PAL+ preprocessing line-locked clock, data sync, 656-output interface peaking, contrast, brightness, color saturation tint RGB/ YCrCb CVBS/S-VHS high-quality soft mixer controlled Fast Blank
processing four picture sizes normal size) with 8-bit resolution
predefined display configurations expert mode (fully programmable) control interface external field memory I2C-bus interface 20.25-MHz crystal, external components 80-pin PQFP package
1.1. System Architecture Fig.1-1 shows block diagram video processor
VIN1 VIN2 VIN3 VIN4 VOUT
Analog Front-end
Adaptive Comb Filter NTSC
Color Decoder NTSC SECAM Saturation Tint
Mixer
Scaler Panorama Mode Contrast Brightness
Output Formatter ITU-R ITU-R Memory Control
CrCb YCOE FIFO CNTL
Peaking
RGB/ YCrCb RGB/ YCrCb
Processing Analog Component Matrix Front-End Contrast Saturation Brightness Tint
Clock Gen.
Sync Clock Generation
Clock Sync Sync
20.25
Fig. 1-1: Block diagram 323xD
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1.2. Video Processor Family video processor family supports /32-kHz systems available with different comb filter options. Table gives overview video processor family.
Table 1-1: Processor Family Double-Scan Line-Locked Clock Applications Features Type Adaptive Combfilter (PAL/NTSC) Panorama Vision Analog Component Inputs Vertical Scaler (PIP) Digital Output Interface ITU-R 601, ITU-R ITU-R 601, ITU-R ITU-R 601, ITU-R ITU-R 601, ITU-R ITU-R ITU-R ITU-R
3230D 3231D 3232D 3233D 3215C 3210A 3211A
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323xD
external sources, such MPEG-2 set-top boxes transparent (4:2:2) quality. Furthermore, transforms RGB/Fast Blank signals common digital video makes those signals available 100-Hz upconversion double-scan processing. some European countries (Italy), this feature mandatory. 94xx from Micronas) indicates memory based image processing, such scan rate conversion, vertical processing (Zoom), PAL+ reconstruction. supports memory-based applications through line-locked clocks, syncs, data. Additionally, 323xD provides 656-output interface FIFO control signals. Examples:
1.3. Applications Fig. depicts several applications. Since functions video front-end, must complemented with additional functionality form complete set. 331x contains video back-end with video postprocessing (contrast, peaking, CTI,.), H/V-deflection, insertion (SCART, Text, PIP,.) tube control (cutoff, white-drive, beam current limiter). generates beam scan velocity modulation output from digital YCrCb signals. Note, that this signal generated from external analog inputs. component interface 323xD provides high-quality analog interface with character insertion capability. also allows appropriate processing
Europe: kHz/50 kHz/100 interlaced kHz/60 kHz/60 non-interlaced
YCrCb/RGBFB
CVBS
323xD
FIFO
YCrCb/RGBFB CVBS
323xD
331x
Defl. Defl. Defl.
CVBS
323xD
331x
YCrCb/RGBFB
CVBS
323xD
331x
Fig. 1-2: 32xxD applications 15-kHz application Europe double-scan application (US, Japan) with YCrCb inputs 100-Hz application (Europe) with RGBFB inputs
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323xD
Functional Description 2.1. Analog Video Front-End This block provides analog interfaces video inputs mainly carries analog-to-digital conversion following digital video processing. block diagram given Fig. 2-1. Most functional blocks front-end digitally controlled (clamping, AGC, clock-DCO). control loops closed Fast Processor (`FP') embedded decoder.
2.1.3. Automatic Gain Control digitally working automatic gain control adjusts magnitude selected baseband +6/-4.5 logarithmic steps optimal range ADC. gain video input stage including steps/V with
2.1.4. Analog-to-Digital Converters ADCs provided digitize input signals. Each converter runs with 20.25 resolution. integrated bandgap circuit generates required reference voltages converters. ADCs 2-stage subranging type.
2.1.1. Input Selector five analog inputs connected. Four inputs composite video S-VHS luma signal. These inputs clamped sync back porch amplified variable gain amplifier. input connection S-VHS carrier chrominance signal. This input internally biased fixed gain amplifier. second S-VHS chroma signal connected video-input VIN1.
2.1.5. Digitally Controlled Clock Oscillator clock generation also part analog front end. crystal oscillator controlled digitally control processor; clock frequency adjusted within ±150 ppm.
2.1.6. Analog Video Output 2.1.2. Clamping composite video input signals coupled clamping voltage stored coupling capacitors generated digitally controlled current sources. clamping level back porch video signal. S-VHS chroma also coupled. input internally biased center input range. input signal Luma available analog video output pin. signal this must buffered source follower. output voltage thus signal used drive line. magnitude adjusted with steps together with main AGC.
Analog Video Output CVBS/Y CVBS/Y CVBS/Y CVBS/Y/C VIN4 VIN3 VIN2 VIN1 input clamp gain bias
+6/-4.5
digital CVBS Luma
digital Chroma system clocks
reference generation
frequency
DVCO ±150
20.25
Fig. 2-1: Analog front-end
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typically defines comb strength horizontal edges. determines amount remaining cross-luminance sharpness edges respectively. increases, comb strength, cross luminance reduction sharpness, increases. typically determines comb filter behavior vertical edges. increases, comb strength, amount hanging dots, decreases. After selecting combfilter performance horizontal vertical direction, diagonal picture performance further optimized adjusting DDR. increases, crawl diagonal colored edges reduced. enhance vertical resolution picture, provides vertical peaking circuitry. filter gain adjustable between coring filter suppresses small amplitudes reduce noise artifacts. relation comb filter, this vertical peaking widely contributes optimal two-dimensional resolution homogeneity.
2.2. Adaptive Comb Filter adaptive comb filter used high-quality luminance/chrominance separation NTSC composite video signals. comb filter improves luminance resolution (bandwidth) reduces interferences like cross-luminance cross-color. adaptive algorithm eliminates most mentioned errors without introducing artifacts noise. block diagram comb filter shown Fig. 2-2. filter uses four line delays process information three video lines. have fixed phase relationship color subcarrier three channels, system clock (20.25 MHz) fractionally locked color subcarrier. This allows processing color standards substandards using single crystal frequency. CVBS signal three channels filtered subcarrier frequency bandpass/notch filters. output three channels used adaption logic select weighting that used reconstruct luminance/chrominance signal from bandpass/notch filter signals. using soft mixing signals switching artifacts adaption algorithm completely suppressed. comb filter uses middle line reference, therefore, comb filter delay lines. comb filter switched off, delay lines used pass luma/chroma signals from converters luma/chroma outputs. Thus, processing delay always lines. order obtain best-suited picture quality, user possibility influence behavior adaption algorithm going from moderate combing strong combing. Therefore, following three parameters adjusted: (horizontal difference gain) (vertical difference gain) (diagonal reducer)
2.3. Color Decoder this block, standard luma/chroma separation multi-standard color demodulation carried out. color demodulation uses asynchronous clock, thus allowing unified architecture color standards. block diagram color decoder shown Fig. 2-4. luma well chroma processing, shown here. color decoder also provides several special modes, e.g. wide band chroma format which intended S-VHS wide bandwidth chroma. Also, filter settings available processing PAL+ helper signal. adaptive comb filter used luma chroma separation, color decoder uses S-VHS mode processing. output color decoder YCrC 4:2:2 format.
Luma Chroma Mixers Adaption Logic
Bandpass Filter CVBS Input Delay Line Bandpass/ Notch Filter
Luma Output
Chroma Output
Delay Line Chroma Input
Bandpass Filter
Fig. 2-2: Block diagram adaptive comb filter (PAL mode)
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2.3.1. IF-Compensation With off-air mistuned reception, attenuation higher frequencies asymmetry around color subcarrier compensated. Four different settings IF-compensation possible (see Fig. 2-3): flat compensation) dB/octave dB/octave dB/MHz last setting gives very large boost high frequencies. provided SECAM signals that decoded using filter specified originally standard. 2.3.2. Demodulator
entire signal (which might still contain luma) quadrature-mixed baseband. mixing frequency equal subcarrier NTSC, thus achieving chroma demodulation. SECAM, mixing frequency 4.286 giving quadrature baseband components modulated chroma. After mixer, lowpass filter selects chroma components; downsampling stage converts color difference signals multiplexed half rate data stream. subcarrier frequency demodulator generated direct digital synthesis; therefore, substandards such 3.58 NTSC 4.43 also demodulated.
2.3.3. Chrominance Filter demodulation followed lowpass filter color difference signals PAL/NTSC. SECAM requires modified lowpass function with bell filter characteristic. output lowpass filter, luma information eliminated. lowpass filters calculated time multiplex color signals. Three bandwidth settings (narrow, normal, broad) available each standard (see Fig. 2-5). PAL/NTSC, wide band chroma filter selected. This filter intended high bandwidth chroma signals, e.g. nonstandard wide bandwidth S-VHS signal.
Fig. 2-3: Frequency response chroma IF-compensation
Luma CVBS
Notch Filter
Luma
Delay
CrossSwitch
Chroma
Compensation MIXER DC-Reject Lowpass Filter Phase/Freq Demodulator
Chroma
ColorPLL/ColorACC
Fig. 2-4: Color decoder
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color killer operation; they used automatic standard detection well.
2.3.6. Color Killer Operation color killer uses burst-phase /burst-frequency measurement identify PAL/NTSC SECAM color signal. PAL/NTSC, color switched (killed) long color subcarrier locked. SECAM, killer controlled toggle burst frequency. burst amplitude measurement used switch color burst amplitude below programmable threshold. Thus, color will killed very noisy signals. color amplitude killer programmable hysteresis.
PAL/NTSC
2.3.7. Automatic Standard Recognition burst-frequency measurement also used automatic standard recognition (together with status horizontal vertical locking) thus allowing completely independent search line color standard input signal. following standards distinguished: B,G,H,I; NTSC SECAM; NTSC preselection allowed standards, recognition enabled/disabled each standard separately. least standard enabled, 323xD checks regularly horizontal vertical locking input signal state color killer. error exists several adjacent fields standard search started. Depending measured line number burst frequency current standard selected. error handling, recognition algorithm delivers following status information: search active (busy) search terminated, failed found standard disabled vertical standard invalid control range Color saturation adjustable independently color standard. PAL/NTSC used reference ACC. SECAM necessary gains calculated automatically. SECAM decoding, frequency burst measured. Thus, current chroma carrier frequency identified used control SECAM processing. burst measurements also control color found
SECAM
Fig. 2-5: Frequency response chroma filters
2.3.4. Frequency Demodulator frequency demodulator demodulating SECAM signal implemented CORDIC-structure. calculates phase magnitude quadrature components coordinate rotation. phase output CORDIC processor differentiated obtain demodulated frequency. After deemphasis filter, signals scaled standard amplitudes crossover-switch.
2.3.5. Burst Detection Saturation Control PAL/NTSC system burst reference color signal. phase magnitude outputs CORDIC gated with color used controlling phase-locked loop (APC) demodulator automatic color control (ACC) PAL/ NTSC.
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2.3.8. Compensation/1-H Comb Filter color decoder uses fully integrated delay line. Only active video stored. delay line application depends color standard: NTSC: PAL: comb filter color compensation color compensation
CVBS
Notch filter Chroma Process.
Luma
Chroma Process.
chroma
conventional
CVBS
Notch filter
S-VHS
SECAM: crossover switch
Chroma Process. Delay
NTSC compensated mode, Fig. color signal averaged adjacent lines. Thus, cross-color distortion chroma noise reduced. NTSC comb filter mode, Fig. delay line composite signal path, thus allowing reduction cross-color components, well cross-luminance. loss vertical resolution luminance channel compensated adding vertical detail signal with removed color information. adaptive comb filter used, NTSC comb filter deselected.
compensated
CVBS
Delay Notch filter
Chroma Process.
comb filter Fig. 2-6: NTSC color decoding options
CVBS
Notch filter
Chroma Process.
Delay
conventional
Luma
Chroma
Chroma Process.
Delay
S-VHS Fig. 2-7: color decoding options
CVBS
Notch filter
Chroma Process.
Delay
Fig. 2-8: SECAM color decoding
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323xD
2.4. Component Interface Processor This block (see Fig. 2-10) contains necessary circuitry dedicated external analog components (YCrCb_cip) such YCrCb signals from players, other sources with Fast Blank real time insertion main picture (YCrCb_main). 2.4.1. Component Analog Front-End 323xD provides analog RGB/YCrCb input ports, with Fast Blank capability without. Analog component signals contain high-frequency components OSD) and/or high-frequency clock residues. Thus, recommended implement analog anti-alias low-pass filters each input, including MHz). While signals coupled clamping capacitors, Fast Blank input requires coupling.
2.3.9. Luminance Notch Filter composite video signal applied, color information suppressed programmable notch filter. position filter center frequency depends subcarrier frequency PAL/NTSC. SECAM, notch directly controlled chroma carrier frequency. This considerably reduces cross-luminance. frequency responses three systems shown Fig. 2-9.
PAL/NTSC notch filter
selected signal channel further converted into digital form three high-quality ADCs running 20.25 with resolution bit. input digitized with resolution bit. Note: 323xD synchronized always main CVBS/Y input. component mode, sync signal this input accordingly.
2.4.2. Matrix
SECAM notch filter Fig. 2-9: Frequency responses luma notch filter PAL, NTSC, SECAM
signals converted YCrCb format matrix operation: 0.299R 0.587G 0.114B (R-Y)= 0.701R 0.587G 0.114B (B-Y)=-0.299R 0.587G 0.886B case YCrCb input matrix bypassed. 2.4.3. Component YCrCb Control 323xD supports following picture adjustment parameters component signal: contrast 63/32 -128 brightness saturation 63/32 saturation 63/32 tint degrees
2.3.10. Skew Filtering system clock free-running locked line frequency. Therefore, sampling pattern orthogonal. decoded YCrCb signals converted orthogonal sampling raster skew filters, which part scaler block. skew filters controlled skew parameter allow application group delay input signals without introducing waveform frequency response distortion. amount phase shift this filter controlled horizontal PLL1. accuracy filters 1/32 clocks luminance clocks chroma. Thus 4:2:2 YCrCb data orthogonal pixel format even case nonstandard input signals such VCR.
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Table shows settings achieve exact level matching between YCrCb_cip YCrCb_main channel. Table 2-1: Standard picture settings
factor clamped hence selecting YCrCb_main component input YCrCb_cip (see Table 2-2).
2.4.4.2. Static Mixer Mode input format YCrCb contrast brightness satCr satCb signal YCrCb_main component signal YCrCb_cip also statically mixed. this environment, manually controlled registers FBGAIN FBOFFS according following expression: FBGAIN*(31-FBOFFS) necessary limitation rounding operation built-in range: static mixer mode well previously mentioned static switch mode (see Table 2-2), softmixer operates independently analog Fast Blank input.
Note: Vpp, sync) 2.4.4. Softmixer After automatic delay matching, component signals upsampled main video signal gathered onto unique YCrCb channel means versatile 4:4:4 softmixer (see also Fig. 2-10). softmixer circuit consists Fast Blank (FB) processing block supplying mixing factor (0.64) high quality signal mixer achieving output function: YCrCb_mix=( k*YCrCb_main+ (64-k)*YCrCb_cip )/64 softmixer supports several basic modes that selected (see Table 2-2).
2.4.4.3. Dynamic Mixer Mode dynamic mixer mode, mixer controlled Fast Blank signal. 323xD provides linear mixing coefficient k=kl FBGAIN*(FB-FBOFFS) digitized Fast Blank), non-linear mixing coefficient knl=F(kl), which results from further non-linear processing While linear mixing coefficient used insert full-screen video signal, non-linear coefficient well-suited insert Fast Blank related signals like text. non-linear mixing reduces disturbing effects like over/undershoots critical Fast Blank edges.
2.4.4.1. Static Switch Mode simplest most common application softmixer used static switch between YCrCb_main YCrCb_cip. This instance adequate handle component signal.
mixer YCrCb_main VIDEO processing YCrCb_mix
YCrCb_cip RGB/YCrCb Component Processing
Fig. 2-10: Block diagram component mixer
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Table 2-2: softmixer modes
analog fast blank input
mode Force YCrCb main Force RGB/ YCrCb Static Mixer Linear nonLinear
SELLIN
FBCLP
MODE
reading register <27> <27>FBLSTAT <27>FBLRISE <27>FBLFALL
<27>FBLHIGH
Fig. 2-11: Fast Blank Monitor additional monitoring also provided RGB/YCrCb signal; indicates whether ADCs inputs clipped not. case clipping conditions (1Vpp input example) range extended using bit. CLIPD: RGB/YC input clip, reset register read
2.5. Horizontal Scaler 4:2:2 YCrCb signal from mixer output processed horizontal scaler. contains lowpass filter, prescaler, scaling engine peaking filter. scaler block allows linear nonlinear horizontal scaling input signal range 1/32 Nonlinear scaling, also called "panorama vision", provides geometrical distortion input picture. used picture with format 16:9 screen stretching picture geometry borders. Also, inverse effect called water glass produced scaler. summary scaler modes given Table 2-3.
2.4.5. 4:4:4 4:2:2 Downsampling After mixer, 4:4:4 YCrCb_mix data stream downsampled 4:2:2 format. this sake, chroma lowpass filter provided eliminate high-frequency components above which typically present inserted high resolution RGB/ YCrCb sources. case main video processing (loop-through) only, recommended bypass this filter using CIPCFBY.
2.5.1. Horizontal Lowpass-filter 2.4.6. Fast Blank Signal Monitoring analog Fast Blank state monitored means four readable bits. These bits used controller SCART signal ident: FBHIGH: high, reset register read FBSTAT: status register read FBRISE: rising edge, reset register read FBFALL: falling edge, reset register read luma filter block applies anti-aliasing lowpass filters. cutoff frequencies selectable have adapted horizontal scaling ratio.
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Table 2-3: Scaler modes Mode Scale Factor 0.75 linear nonlinear compr 1.33 linear Description source displayed 16:9 tube, with side panels source displayed 16:9 tube, Borders distorted Letterbox source (PAL+) displayed tube, vertical overscan with cropping side panels Letterbox source (PAL+) displayed tube, vertical overscan, borders distorted, cropping sample rate conversion line-locked clock
Compression 16:9 Panorama 16:9
Zoom
Water glass 16:9
nonlinear zoom
20.25 13.5
0.66
Fig. 2-12: YCrCb downsampling lowpass-filter 2.5.2. Horizontal Prescaler achieve horizontal compression ratio between 1/32 double window operation) linear downsampler resamples input signal (=no presampling),
2.5.4. Horizontal Peaking-filter horizontal scaler block offers extra peaking filter sharpness control. center frequency peaking filter automatically adopts horizontal scaling ratio. Three center frequencies selectable (see Fig. 2-13: center sampling rate center sampling rate center sampling rate
2.5.3. Horizontal Scaling Engine scaler contains programmable decimation filter, FIFO memory, programmable interpolation filter. scaler input filter also used pixel skew correction, 2.3.10. decimator/interpolator structure allows optimal FIFO memory. allows linear nonlinear horizontal scaling input video signal range 0.25 controlling scaler done internal Fast Processor. filter gain adjustable between coring filter suppresses small amplitudes reduce noise artifacts.
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amplitude, external controller reads this register, calculates vertical scaling coefficient transfers settings, e.g. vertical sawtooth parameters, horizontal scaling coefficient etc., VPC. Letterbox signals containing logos left right side black areas processed black lines, while subtitles, inserted black areas, processed non-black lines. Therefore subtitles visible screen. suppress subtitles, vertical zoom coefficient calculated selecting larger number black lines only. Dark video scenes with contrast level compared letterbox area indicated BLKPIC bit.
LLC1/MHz
Fig. 2-13: Peaking characteristics
2.9. Control Data Output Signals 323xD supports output modes: DIGIT3000 mode, output interfaces main system clock, line-locked mode, generates asynchronous line-locked clock that used output interfaces. delivers either YCrC 4:2:2 YCrC 4:1:1 data stream, each with separate sync information. case YCrCb 4:2:2 format, 323xD also provides interface with embedded syncs according ITU-R656.
2.6. Vertical Scaler operation, vertical scaler compresses incoming 4:2:2 YCrCb active video signal vertical direction. supports vertical compression ratio compression), case vertical compression filter performs compensation automatically standard delay line should bypassed (see 2.3.8.).
2.9.1. Line-Locked Clock Generation on-chip rate multiplier used synthesize desired output clock frequency 13.5/16/18 MHz. double clock frequency output available support systems. synthesizer controlled embedded RISC controller, which also controls front-end loops (clamp, AGC, PLL1, etc.). This allows generation line-locked output clock regardless system clock (20.25 MHz) which used comb filter operation color decoding. control scaling output clock frequency kept independent allow aspect ratio conversion combined with sample rate conversion. line-locked clock circuity generates control signals, e.g. horizontal/vertical sync, active video output, also interface from internal (20.25 MHz) clock external line-locked clock system. line-locked clock required, i.e. DIGIT3000 mode, system runs 20.25 main clock. horizontal timing reference this mode provided front-sync signal. this case, line-locked clock block interfaces from 20.25 main clock. synchronization signals from line-locked clock block still available, every line internal counters reset with main-sync signal. double clock signal available DIGIT3000 mode.
2.7. Contrast Brightness 323xD provides selectable contrast brightness adjustment luma samples. control ranges are: contrast 63/32 -128 brightness Note: ITU-R luma output code levels 240), contrast brightness
2.8. Blackline Detector case letterbox format input video, e.g. Cinemascope, PAL+ etc., black areas upper lower part picture visible. suitable remove reduce these areas vertical zoom and/or shift operation. 323xD supports this feature letterbox detector. circuitry detects black video lines measuring signal amplitude during active video. every field number black lines upper lower part picture measured, compared previous measurement minima stored register BLKLIN. adjust picture
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2.9.2. Sync Signals front will provide number sync/control signals which output with output clock. sync signals generated line-locked clock block. Href: AVO: Vref: INTLC: horizontal sync active video (programmable) horizontal clamp (programmable) vertical sync interlace Luma Chroma note: C*xY Cb17 Cb16 Cr17 Cr16
2.9.5. Line-Locked 4:1:1 Output Format orthogonal 4:1:1 output format compatible industry standard. YCrCb samples skew-corrected interpolated orthogonal sampling raster (see Table 2-5). Table 2-5: 4:1:1 Orthogonal output format Cb15 Cb14 Cr15 Cr14 Cb13 Cb12 Cr13 Cr12 Cb11 Cb10 Cr11 Cr10
horizontal signals qualified with field information, i.e. signals present lines. horizontal timing shown Fig. 2-16. Details horizontal/vertical timing given Fig. 2-20. Note: ITU-R656 compliant output format, sync information embedded data stream.
pixel number number)
2.9.3. DIGIT3000 Output Format picture format between DIGIT3000 4:2:2 YCrCb with 20.25 samples/s. Only active video transferred, synchronized system main sync signal (MSY) which indicates start valid data each scan line which initializes color multiplex. video data orthogonally sampled YCrCb, output format given Table 2-4. number active samples line 1080 standards (525 625). output switched 4:1:1 mode with output format according Table 2-5. line, serial data transferred which contains information about main picture such current line number, odd/even field etc.). generated deflection circuitry represents orthogonal timebase entire system. Table 2-4: Orthogonal 4:2:2 output format Luma Chroma
2.9.6. ITU-R Output Format This interface uses 4:2:2 data stream line-locked clock 13.5 MHz. Luminance chrominance information multiplexed following order: Cb1, Cr1, Timing reference codes inserted into data stream beginning each video line: `Start active video'-Header (SAV) inserted before first active video sample `End active video'-code (EAV) inserted after last active video sample. incoming videostream limited range 1.254 since data words used identification reference headers. Both headers contain information about field type field blanking. data words occurring during horizontal blanking interval between filled with 0x10 luminance 0x80 chrominance information. Table shows format header. activation this output format, following selections must assured: 13.5 line locked clock double-clock mode enabled
2.9.4. Line-Locked 4:2:2 Output Format line-locked mode, 323xD provides industry standard pixel stream YCrC data. difference DIGIT3000 native mode only number active samples, which course, depends chosen scaling factor. Thus, Table valid both 4:2:2 modes.
ITU-R656-mode enabled binary offset Cr/Cb data Note that following changes extensions ITU-R656 standard have been included support horizontal vertical scaling:
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Table 2-6: Coding SAV/EAV-header
Word
First Second Third Fourth
Both length number active video lines varies with selected window parameters. compliance with ITU-R656 recommendation, size samples line must selected each window. During blanked video lines SAV/EAV headers suppressed pairs. assure vertical sync detection V-flag header last active video line Additionally, during field blanking SAV/EAV headers (with V-flag inserted.
during field during field during active linesV during vertical field blanking SAV,H (video task only)
bits Hamming-coded protection bits.
dependent window size 1728 samples
Digital Video Output
constant during horizontal blanking Y=10hex; CR=CB=80hex
SAV: "start active video" header EAV: "end active video" header
Fig. 2-14: Output video data with embedded reference headers (@27 MHz)
DATA LLC1 LLC2
SAV1
SAV2
SAV3
SAV4
CBn-1
Yn-1
CRn-1
EAV1
EAV2
EAV3
EAV4
Fig. 2-15: Detailed data output (double-clock
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Table 2-7: Output signals corresponding different formats Format YCrCb422 YCrCb422 ITU-R dblclk enable656 HSync PAL/NTSC PAL/NTSC used VSync PAL/NTSC PAL/NTSC used marks active pixels marks active pixels used Y-Data 4:2:2 4:2:2 ITU-R C-Data 4:2:2 tri-stated tri-stated
multiplex luminance chrominance information embedding 656-headers enabled independently. overview resulting output formats corresponding signals given Table 2-7.
conversion (shared with existing ADCs) mixing with subcarrier frequency lowpass filter gain control chroma delay compensation composite video path
2.9.7. Output Code Levels Output Code Levels correspond ITU-R code levels: 16.240 Black Level CrCb 128±112 overview over output code levels given Table 2-8.
output luma output port Helper signals processed like main video luma signals, i.e. they subject scaling, sample rate conversion orthogonalization activated. adaptive comb filter processing switched helper lines. expected that further helper processing (e.g. nonlinear expansion, matched filter) performed outside VPC.
2.9.8. Output Ports data sync pins operate compliant levels tri-stated registers. Additionally, data outputs tri-stated YCOE output enable immediately. This function allows digital insertion digital video source MPEG aso.). ensure optimum performance data clock outputs automatically adopt driver strength depending their specific external load (max. 50pF). Therefore external resistors and/or inductors should connected these pins. Sync Fifo control pins have adjusted manually register.
2.10.1. Output Signals PAL+/Color+ Support PAL+/Color+ signal, line image contains 16/9 core picture lines which standard format. upper lower lines contain PAL+ helper signal, line contains signalling information PAL+ transmission. PAL+ mode, signal core picture, which during lines 60-274 372-586, replaced orthogonal composite video input signal. order signal 8-bit port width, signal amplitudes used. During helper window, which lines 24-59, 275-310, 336-371, 587-622, demodulated helper signal processed horizontal scaler output circuitry. available luma output port. processing helper reference lines different wide screen signaling part black reference helper burst signals. code levels given detail Table 2-8, output signal helper reference line shown Fig.
2.9.9. Test Pattern Generator YCrCb outputs switched test mode where YCrCb data generated digitally 323xD. Test patterns include luma/chroma ramps, flat field pseudo color bar.
2.10. PAL+ Support PAL+, 323xD provides basic helper preprocessing:
Micronas
323xD
Table 2-8: Output signal code levels PAL/PAL+ signal Output Signal Output Format Standard YCrCb (100% Chroma) CVBS, CrCb binary Luma Outputs Y[7:0] Black/Zero Level Amplitude Chroma Outputs C[7:0] Output Format offset binary signed binary (luma) offset binary signed Demodulated Helper Helper Helper black level, Ref. Burst signed binary offset binary ±109 (WSS:106) (128-109) Amplitude 128±112 ±112 128±112 ±112
horizontal pixel counter horizontal sync (HS) horizontal clamp (HC) start stop programmable line length (programmable)
newline (internal signal)
start video output (programmable)
active video (AVO)
start stop programmable
vertical sync (VS), field vertical sync (VS), field line length/2
field
field
Fig. 2-16: Horizontal timing line-locked mode
black level SIgnal Helper Burst (demodulated)
binary format signed format
Fig. 2-17: PAL+ helper reference line output signal
Micronas
323xD
2.11. Video Sync Processing Fig. 2-18 shows block diagram front-end sync processing. extract sync information from video signal, linear phase lowpass filter eliminates noise video contents above MHz. sync separated slicer; sync phase measured. variable window selected improve noise immunity slicer. phase comparator measures falling edge sync, well integrated sync pulse. sync phase error filtered phase-locked loop that computed timing front-end derived from counter that part this PLL, thus counts synchronously video signal. separate hardware block measures signal back porch also allows gathering maximum/minimum video signal. This information processed used gain control clamping.
vertical sync separation, sliced video signal integrated. uses integrator value derive vertical sync field information. information extracted video sync processing multiplexed onto hardware front sync signal (FSY) distributed rest video processing system. format front sync signal given Fig. 2-19. Frequency phase characteristics analog video signal derived from PLL1. results scaler unit data interpolation orthogonalization clock synthesizer line-locked clock generation. Horizontal vertical syncs latched with line-locked clock.
PLL1
lowpass syncslicer video input frontend timing clamp signal meas. clamping, colorkey, FIFO_write clock synthesizer syncs clock syncs horizontal sync separation phase comparator lowpass counter front sync generator front sync skew vblank field
vertical sync separation
Sawtooth Parabola Calculation
FIFO
vertical serial data
vertical sawtooth
Fig. 2-18: Sync separation block diagram
input analog video
skew
skew used
reserved (not scale)
vertical sync Parity field field field
Fig. 2-19: Front sync format
Micronas
323xD
field
CCIR
Front-Sync (FSY)
Vertical Sync (VS) Interlace (INTLC) 1clk
field
CCIR
Vertical Sync (VS)
Interlace (INTLC) Active Video Output (AVO) helper line (internal signal) signal matches output video
following signals identical field1 field2
helper lines 23-59, 275-310, 336-371, 587-623 (internal signal), signal matches output video
Fig. 2-20: Vertical timing 323xD shown reference input video. Video output signals delayed comb filter version (VPC 323xD).
Micronas
323xD
2.12. Picture Picture (PIP) Processing Control 2.12.1. Configurations support and/or scan rate conversion (SRC) applications, 323xD provides several control signals external field memory Fig. 2-21 demonstrates applications with single 323xD. these cases VPCsingle writes main picture several inset picture(s) into field memory. Only these pictures displayed
live. These configurations suitable features such turner scan, still picture, still picture simple scan rate conversion. Fig. 2-22 shows enhanced configuration with 323xD's. this case, live several still pictures inserted into main live video signal. processes inset picture writes original decimated picture into field memory. VPCmain delivers main picture, combines with inset picture(s) from field memory stores combined video signal into second field memory SRC.
YCrCb YCrCb/RGB CVBS
323xD
(single)
FFRSTW FFWE,FFIE LLC1
field memory
FIFORRD FIFORD LLC2 LLC2
331x
Def.
YCrCb YCrCb/RGB CVBS
323xD
(single)
FFRSTW FFWE,FFIE LLC1
field memory
YCrCb FFRE LLC1
LLC1
Fig. 2-21: Typical configurations with single 323xD
YCrCb/RGB
323xD
(pip)
field FFRSTW memory FFWE
FFIE LLC1 FFRSTW* YCrCb (for PIP)
YCrCb
YCrCb FFRSTW FFRE FFOE
CVBS (for PIP)
LLC1
YCrCb FFWE FFIE LLC1
YCrCb/RGB CVBS (for main picture)
323xD
(main)
field FIFORRD memory
(for SRC) FIFORD LLC2 LLC2
331x
Def.
only used field-buffer-extension mode double-windows-extension mode
Fig. 2-22: Enhanced configuration with 323xD
Micronas
323xD
inset pictures displayed with without frame controlled I2C. fixed frame width pixels lines. Table 2-10: Inset picture size (without frame) predefined modes size horizontal [pixel/line] screen 13.5 16:9 screen 13.5 vertical [line/field] line line
summary modes given Table 2-9. Table 2-9: 323xD modes applications Working mode Function decimate video signal inset pictures write inset pictures into field memory write frame background into field memory deliver video signal main picture read inset pictures from field memory insert them into main picture write resulting video signal into field memory scan rate conversion (SRC) decimate video signal main inset picture(s) write inset pictures into field memory write frame background into field memory write main picture part outside inset pictures into field memory read field memory (optional)
main
single
2.12.2. Display Modes minimize programming effort, predefined modes already implemented, including double windows, single multi-PIP (Fig. 2-23 2-24). addition expert mode available advanced applications. this case inset picture size, well window arrangements fully programmable. Examples mode programming given 5.2.
2.12.3. Predefined Inset Picture Size predefined display modes based four fixed inset picture sizes (see Table 2-10). corresponding picture resizing achieved integrated horizontal vertical scaler 323xD, which must programmed accordingly (see Table 2-11 2-13).
Micronas
323xD
Table 2-11: Scaler Settings predefined modes 13.5 size SCINC1 h'43 full h'600 h'600 h'480 h'600 h'480 FFLIM h'42 h'2d0 h'168 h'f0 h'b4 h'78 h'168 SCPIP h'41 h'00 h'11 h'16 h'1a h'1f h'01 SCBRI h'52 h'010 h'110 h'210 h'210 h'310 h'110 SCINC1 h'43 h'800 h'400 h'600 h'400 h'600 h'600 16:9 FFLIM h'42 h'21c h'10e h'b4 h'87 h'5a h'168 SCPIP h'41 h'00 h'1a h'1b h'1b h'1f h'01 SCBRI h'52 h'010 h'210 h'210 h'310 h'310 h'110
double h'600
Note: BR=16 register SC-BRI!: Table 2-12: Scaler Settings predefined modes size SCINC1 h'43 full h'510 h'510 h'798 h'510 h'798 FFLIM h'42 h'354 h'1aa h'11c h'd5 h'8e h'1aa SCPIP h'41 h'00 h'11 h'15 h'1a h'1e h'01 SCBRI h'52 h'010 h'110 h'110 h'210 h'210 h'110 SCINC1 h'43 h'6c0 h'6c0 h'510 h'6c0 h'510 h'510 16:9 FFLIM h'42 h'27f h'140 h'd4 h'a0 h'6a h'1aa SCPIP h'41 h'00 h'11 h'16 h'1a h'1f h'01 SCBRI h'52 h'010 h'110 h'210 h'210 h'310 h'110
double h'510
Note: BR=16 register SC-BRI!: Table 2-13: Settings NEWLIN, AVSTRT AVSTOP size NEWLIN h'22
VPCsingle VPCpip VPCmain
13.5 AVSTRT h'28 AVSTO h'29 NEWLIN h'22
VPCsingle VPCpip
16.0 AVSTRT h'28 AVSTO h'29
VPCmain
full 1/2.1/6
h'86 h'194
h'86 h'86 h'86
h'86 h'86 h'86
h'356 h'356 h'356
h'a8 h'1de h'a8
h'a8 h'a8 h'a8
h'a8 h'a8 h'a8
h'3f0 h'3f0 h'3f0
double h'86
Note: NEWLIN AVSTRT must FIFOTYPE=0
Micronas
323xD
Mode
Mode
Mode
Mode
Mode
Mode
Mode
Mode (4:3)
Fig. 2-23: Predefined Modes
Micronas
323xD
Mode (16:9)
Mode (4:3)
Mode
Mode (16:9)
Mode Mode
Fig. 2-24: Predefined Modes (continued)
Micronas
323xD
2.12.5. Frame Background Color programmable frame colors COLFR1 COLFR2 available high-light particular inset picture. Instead displaying main picture possible fill background with programmable color COLBGD (set SHOWBGD=1 register PIPMODE), multi displays full screen (see mode 10). COLFR1, COLFR2 COLBGD bits wide each. Therefore 65536 colors programmable.
2.12.4. Acquisition Display Window acquisition window defines picture area input active video displayed inset picture screen. display window defines display position inset picture(s) screen. acquisition display windows controlled parameters HSTR, VSTR, NPIX NLIN (see Fig. 2-25 2-26). They indicate coordinate upper-left corner horizontal vertical size active video area. VPCpip VPCsingle mode, these four parameters define acquisition window decimated pixel grid, while VPCmain mode they define display window.
2.12.6. Vertical Shift Main Picture VPCmain mode supports vertical up-shifting main picture letterbox format) enable bottom insets (see mode 11). vertical shift programmable VOFFSET.
HSTR VSTR
2.12.7. Free Running Display Mode NLIN this mode free running sync raster generated guarantee stable display critical cases like tuner scan. Therefore should disabled (see Table 2-14).
Acquisition Window NPIX Active Video
2.12.8. Frame Field Display Mode frame display mode, every field written into field memory. field display mode every second field written into field memory. This configuration suitable multi picture insets freeze mode, since avoids motion artifacts. other hand, frame display mode guarantees maximum vertical temporal resolution animated insets. predefined mode setting frame/field mode done automatically achieve best performance.
Fig. 2-25: Definition acquisition window
HSTR VSTR NLIN Display Window NPIX Active Video Fig. 2-26: Definition display window Micronas
323xD
Table 2-14: Settings Free-Running Mode Control Function VPCsingle write LLC_CLKC (bit[11] h'6d) (bit[15] h'28) VS_LOCK1) (bit[14] h'84) enable/disable enable/disable freerunning sync mode write main pic. VPCpip VPCmain predef. other mode modes
synchronize control input video/ free-running sync signals
VS_LOCK enabled, before enable FLW. case input video" VPCmain, recommended enable free running mode stable display. 2.12.9. External Field Memory requirements external field memory are: FIFO type access with reset write mask function: increasing write address pointer over writing data should controlled separately. output disable function: tri-state table outputs applications, 323xD supports 4:1:1 4:2:2 chrominance format. Table 2-15 shows typical memory size 13.5 system clock application. Table 2-15: Word length minimum size field memory Chrominance format 4:1:1 4:2:2 Word length [bit] Memory size [word] 245376 245376 [bit] 2944512 3926016 RSTWR (reset write/read) resets internal write/ read address pointer zero. (write enable) used enable disable incrementing internal write address pointer. (input enable) used enable writing data from field memory input pins into memory core, disable writing thereby preserving previous content memory (write mask function). (read enable) used enable disable incrementing internal read address pointer. (output enable) used enable disable data output output pins. serial write serial read clock (SWCK SRCK, respectively) field memory line locked clocks LLC1 and/or LLC2 used.
following signals generated 323xD control external field memory:
Micronas
323xD
2.12.10. Field-Buffer-Extension Mode field-buffer-extension mode provides joint lines free display inset picture single modes. this mode, frames (four fields) inset picture stored external field memory. write/read controlling detects timing conflicts causing joint lines artifacts suppresses these conflicts automatically. Table 2-16: Function bits TWOFB FRAMOD FBEXT TWOFB FRAMOD Function field buffer, write only input field frame into field buffer, write both input fields frame into field buffers, write input fields frame alternate into them field buffers, write input fields frame alternate into them, update frame while writing inset picture four field buffers, write input fields frame alternate into them, update frame while writing inset picture Therefore, output FFRSTW VPCpip connected input RSTWPIP (see Fig. 2-22) predefined modes 2.5, field-bufferextension mode enabled FBEXT=1, expert mode FBEXT=1, TWOFB=1 FRAMOD=1. function bits TWOFB FRAMOD shown Table 2-24
2.12.11. Double-Windows-Extension Mode double-windows-extension mode provides joint fields free display second picture Double-Window mode. write/read controlling detects timing conflicts causing joint fields suppresses these conflicts automatically delaying read control signals. output FFRSTW VPCpip should connected input RSTWPIP (see Fig. 2-22)
Micronas
323xD
Serial Interface 3.1. I2C-Bus Interface Communication between external controller done I2C-bus. I2C-bus slave interface uses clock synchronization slow down interface required. I2C-bus interface uses level subaddress: I2C-bus address used address subaddress selects internal registers. multi 323xD applications following three I2C-bus chip addresses selectable I2CSEL pin: I2CSEL VSUP
registers have 16-bit data size; 16-bit registers accessed reading/writing 8-bit data words. Figure shows I2C-bus protocols read write operations interface; read operation requires extra start condition repetition chip address with read command set.
3.2. Control Status Registers Table gives definitions control status registers. number bits indicated each register table number bits implemented hardware, i.e. 9-bit register must always accessed using data bytes will `don't care' write operations read operations. Write registers that read back indicated Table 3-1.
1000
FPWR
send FP-addressbyte high
send FP-addressbyte
write access
1000
FPDAT
send databyte high
send databyte
1000
FPRD
send FP-addressbyte high
send FP-addressbyte
read access
1000
FPDAT
1000
receive databyte high receive databyte
1000
0111 1100
byte Data
write access subaddress read access subaddress
1000
0111 1100
1000
high byte Data byte Data
Start Stop
Fig. 3-1: I2C-bus protocols
Micronas
323xD
register modes given Table w/r: write only register write/read data register read data from register latched with vertical sync
hardware reset initializes control registers automatic chip initialization loads selected registers with default values given Table 3-1.
mnemonics used Micronas demo software given last column.
Micronas
323xD
Table 3-1: Control status registers
Subaddress Number bits Mode Function
Default
Name
Interface h'35 status bit[8:0] bit[11:9] bit[8:0] bit[11:9] bit[11:0] write request read request busy 9-bit read address reserved, zero 9-bit write address reserved, zero data register, reading/writing this register will autoincrement read/ write address. Only data transferred telegram. Black Line Detector h'12 read only register, write this register! After reading, LOWLIN UPLIN reset start measurement. bit[6:0] number lower black lines bit[7] always bit[14:8] number upper black lines bit[15] normal/black picture Circuits h'1F SYNC CONTROL: bit[2:0] reserved (set bit[3] push-pull/tri-state bit[4] push-pull/tri-state other video SYNC Pins bit[5] reserved (set CLOCK/FIFO CONTROL: bit[6] push-pull/tri-state LLC1 bit[7] push-pull/tri-state LLC2 bit[8] push-pull/tri-state CLK20 bit[9] push-pull/tri-state FIFO control pins LUMA/CHROMA DATA (LB[7:0], CB[7:0]) CONTROL: bit[10] tri-state/push-pull Chroma Data pins bit[11] tri-state/push-pull Luma Data pins bit[15:12] reserved (set SYNC GENERATOR CONTROL: bit[1:0] active data same time precedes data clock cycle precedes data clock cycles precedes data three clock cycles bit[2] positive/negative polarity signal bit[3] positive/negative polarity signal bit[4] positive/negative polarity signal bit[5] positive/negative polarity signal bit[6] reserved (set bit[7] positive/negative polarity INTLC signal TRPAD AVODIS SNCDIS BLKLIN FPRD FPWR FPDAT FPSTA
h'36 h'37 h'38
LOWLIN UPLIN BLKPIC
LLC1DIS LLC2DIS CLK20DIS
FFSNCDIS
CDIS YDIS
h'20
SYNCMODE
AVOPRE
HSINV HCINV AVOINV VSINV INTLCINV
Micronas
323xD
Table 3-1: Control status registers
Subaddress Number bits Mode Function Default Name
h'23
OUTPUT STRENGTH: bit[3:0] 0.15 output strength strong, weak) bit[9:4] address output FIFO control pins FFIE, FFOE, FFWR, FFRE FFRSTWR SYNC pins AVO, INTERLACE,VS bit[10] read/write output strength bit[15:11] reserved (set V-SYNC DELAY CONTROL: bit[7:0] delay clock cycles LSB) Interface
OUTSTR PADSTR PADADD
PADWR VSDEL VSDEL
h'30
h'24
OUTPUT INTERFACE disable hor. vert. blanking invalid data mode vertical window VFLAG vsync VFLAG enable suppression 656-headers during invalid video lines enable ITU-656 output format LLC1/LLC2 used reference clock output mode: DIGIT 3000 Sync Generator
OUT656 DBLNK VSMODE HSUP 656enable DBLCLK OMODE
h'21
LINE LENGTH: bit[10:0]
bit[15:11] h'26 START: bit[10:0]
LINE LENGTH register mode, this register defines cycle sync counter which generates SYNC pulses. mode, synccounter counts from LINE LENGTH, this register "number pixels line -1". DIGIT3000 mode, LINE LENGTH 1295 correct adjustment vertical signals. reserved (set START defines beginning signal respect value sync counter. reserved (set select pos./neg. polarity HSYA/VSYA dis-/enable Front-End horizontal vertical sync outputs HSYA/VSYA STOP defines signal respect value sync counter. reserved (set
1295
LINLEN
HCSTRT
bit[13:11] bit[14] bit[15] h'27 bit[10:0] bit[15:11]
HVSYAPOL
HVSYA HCSTOP
Micronas
323xD
Table 3-1: Control status registers
Subaddress Number bits Mode Function
Default
Name
h'28
START: bit[10:0]
bit[11] bit[12] bit[13] bit[14] bit[15] h'29
START defines beginning signal respect value sync counter. reserved (set dis-/enable suppression during invalid video lines vertical standard flywheel (312/262 lines) used disable interlace flywheel enable vertical free mode (flywheel) STOP defines signal respect value sync counter. reserved test picture generation (set normal operation) disable/enable test pattern generator luma output mode: ramp (240 chroma output: 422/411 mode chroma output: pseudo color bar/zero LMODE NEWLINE defines readout start next line respect value sync counter. value this register must greater than correct operation should identical AVOSTART (recommended). case 1H-bypass mode scaler block, NEWLINE function. reserved (set
AVSTRT
AVOGATE FLWSTD DIS_INTL AVSTOP
STOP: bit[10:0]
bit[15:11] bit[11] bit[13:12] bit[14] bit[15] h'22 NEWLINE: bit[10:0]
COLBAREN
LMODE
M411 CMODE
NEWLIN
bit[15:11]
Micronas
323xD
Table 3-1: Control status registers
Subaddress Number bits Mode Function Default Name
Control h'84 MODE: bit[0] bit[1] bit[2] bit[3] bit[4] bit[5]
VPCMODE
dis-/enable field memory control double/single application select VPCpip/VPC main mode 4:3/16:9 screen 13.5/16 output pixel rate vertical window size based 625/525 line video bit[7:6] field memory type reserved PHILIPS 4955TJ reserved other (OKI MSM5412222, bit[11:8] evaluated only, bit[7:6]=11 bit[8] delay video output compared LLC1 clock, DBLCLK=0 LLC2 clock, DBLCLK=1 bit[9] pos/neg polarity signals bit[10] pos/neg polarity signals bit[11] pos/neg polarity RSTWR signal bit[12] reserved (set bit[13] vertical position synchronized input video/vertical sync case video input, FLW=0 disabled. main combined with feature-box without read/write mask only! bit[14] vertical position synchronized input video/free running sync raster bit[15] reserved (set This register updated when PIPOPER register written.
ENA_PIP SINGVPC MAINVPC F16TO9 F16MHZ W525
FIFOTYPE
VIDEODEL
WEREINV IEOEINV
RSTWRINV
AV_LOCK
VS_LOCK
Micronas
323xD
Table 3-1: Control status registers
Subaddress Number bits Mode Function
Default
Name
h'85
MODE: bit[3:0] select predefined mode select expert mode bit[5:4] used expert mode only bit[4] write one/both input field(s) frame into field buffer case TWOFB=0 bit[5] one/two field buffer(s) Note: please 2.12.10 detailed description FRAMOD TWOFB field-buffer-extension mode bit[6] show video/the background color picture bit[13:7] used VPCmain only bit[7] dis-/enable vertical up-shifting main picture bit[13:8] 0.62 number lines vertical up-shift bit[14] dis-/enable field-buffer-extension mode, only used VPCpip VPCmain single Modes bif[15] dis-/enable double-window-extension mode, only used VPCmain predefined mode This register updated when PIPOPER register written.
PIPMODE MODSEL
FRAMOD TWOFB
SHOWBGD
VSHIFT VOFFSET FBEXT
DWEXT
Micronas
323xD
Table 3-1: Control status registers
Subaddress Number bits Mode Function Default Name
h'83
OPERATION: VPCpip VPCsingle: bit[1:0] number inset picture accessed x-direction bit[3:2] number inset picture accessed y-direction bit[6:4] start write inset picture with frame stop writing fill frame with color COLFR1 fill frame with color COLFR2 fill inset picture with frame using color COLBGD fill inset picture frame using color COLBGD start write inset picture frame write main picture (VPCsingleonly)
PIPOPER NSPX NSPY WRPIC WRSTOP
WRFRCOL1 WRFRCOL2
WRBGD
WRBGDNF
WRPICNF WRMAIN
VPCmain: bit[3:0] bit[6:4] other
bit[7]
reserved start display stop display enable still main picture1) disable still main picture1) enable still PIP1) disable still PIP1) reserved processed/new command flag, normally write After setting takes effect, this indicate operation complete.
DISSTART DISSTOP
STMAINON STMAINOFF STPIPON STPIPOFF
NEWCMD
This Mode available only combination with FIFO type field memory (see Section 2.12.9.) scan rate conversion. COLBGD
h'80
BACKGROUND COLOR: binary offset bit[[4:0] chrominance component bit[9:5] chrominance component bit[15:10] luminance component (all other bits YCBCR This register updated when PIPOPER register written.
h'81
FRAME COLOR binary offset Only used VPCpip VPCsingle: bit[[4:0] chrominance component bit[9:5] chrominance component bit[15:10] luminance component (all other bits YCBCR This register updated when PIPOPER register written.
h'3e0
COLFR1
Micronas
323xD
Table 3-1: Control status registers
Subaddress Number bits Mode Function
Default
Name
h'82
FRAME COLOR binary offset only used VPCpip VPCsingle: bit[[4:0] chrominance component bit[9:5] chrominance component bit[15:10] luminance component (all other bits YCBCR This register updated when PIPOPER register written.
h'501f
COLFR2
h'86
LINE OFFSET: Only used VPCpip VPCsingle: bit[8:0] line offset upper-left corner inset picture with NSPX=0 NSPY=0 display window bit[9] internal default/external setting bit[8:0] bit[15:10] reserved (set This register updated when PIPOPER register written.
LINOFFS
h'89
PIXEL OFFSET: Only used VPCpip VPCsingle: bit[7:0] quarter pixel offset upper-left corner inset picture with NSPX=0 NSPY=0 display window bit[8] internal default/external setting bit[7:0] bit[15:9] reserved (set This register updated when PIPOPER register written.
PIXOFFS
Micronas
323xD
Table 3-1: Control status registers
Subaddress Number bits Mode Function Default Name
h'87
VERTICAL START: bit[8:0] VPCpip VPCsingle: vertical start active video segment used inset picture VPCmain vertical start inset picture(s) main picture Exception: bit[8:0] VPCmain predefined mode DWEXT=1: length lines) FIFO read-write conflict interval length length length length PHILIPS 4955TJ, MSM541222,. bit[9] internal default/external setting bit[8:0]
VSTR
Only used predefined mode DWEXT=1: bit[11:10] start position line number) FIFO read-write conflict interval PHILIPS 4955TJ MSM541222,. bit[15:12] defines max. drift LLC1 clocks) between rstwr impulses VPCpip VPCmain, where double-windowextension mode active.
h'8a
VSTR_JF
DIFLIM
HORIZONTAL START: bit[7:0] VPCpip VPCsingle: horizontal start active video segment used inset picture VPCmain: horizontal start inset picture(s) main picture both cases HSTR given number 4-pixel-groups. bit[8] internal default/external setting bit[7:0] bit[15:9] reserved (set NUMBER LINES: Only used expert modes: bit[8:0] VPCpip VPCsingle: number lines active video segment used inset picture VPCmain: number lines inset picture(s) bit[15:9] reserved (set This register updated when PIPOPER register written.
HSTR
h'88
NLIN
Micronas
323xD
Table 3-1: Control status registers
Subaddress Number bits Mode Function
Default
Name
h'8b
NUMBER PIXEL LINE: Only used expert modes: bit[7:0] VPCpip VPCsingle: quarter number pixels line active video segment used inset picture VPCmain: quarter number pixels line inset picture(s) This register updated when PIPOPER register written.
NPIX
h'8c
NUMBER PIXEL LINE FIELD BUFFER(S): bit[7:0] bit[8] quarter number allocated pixels line field buffer(s) internal default/external setting bit[7:0] (must expert mode, optional predefined modes) reserved (set
NPFB
bit[15:9]
This register updated when PIPOPER register written. h'8dh'8f reserved, don't write Control h'90 SATURATION RGB/YCrCb COMPONENT INPUT: bit[5:0] saturation 0.63 bit[11:6] saturation 0.63 bit[15:12] reserved (set TINT CONTROL RGB/YUV COMPONENT INPUT: bit[5:0] tint -20.+20 degrees bit[7:6] reserved (set BRIGHTNESS RGB/YUV COMPONENT INPUT: bit[7:0] brightness -128.+127 CONTRAST RGB/YUV COMPONENT INPUT: bit[13:8] contrast 0.63 bit[15:14] reserved (set SOFTMIXER CONTROL: bit[0] rgb/main video delay (0:normal 1:dynamic) bit[1] linear (0)/nonlinear(1) mixer select bit[7:4] fastblank gain bit[3:2] reserved (set SOFTMIXER CONTROL: bit[5:0] fastblank offset correction (0.63 fb-FBOFFS bit[7:6] fastblank mode: force (equ. fb=0) normal mode active) force main (equ. fb=64) CIPSAT SATCb SATCr
h'91
CIPTNT CIPBRCT CIPBR CIPCT CIPMIX1 RGBDLY SELLIN FBGAIN CIPMIX2 FBOFFS FBMODE
h'92
h'94
h'95
Micronas
323xD
Table 3-1: Control status registers
Subaddress Number bits Mode Function Default Name
h'96
RANGE bit[0] reserved (set bit[1] 0/+3dB extended range INPUT PORT SELECT bit[2] input port select SOFTMIXER CONTROL: bit[5] clamp programable value (0:normal fb=31-FBOFFS bit[6] bypass chroma 444->422 decimation filter RGB/YUV SELECT: bit[7] rgb/yuv input select bit[4:3] reserved (set MONITOR: bit[0] bit[1] bit[2] bit[3] high, reset reg. read falling edge, reset reg. read rising edge, reset reg. read status register read
CIPCNTL RGBSEL FBCLP CIPCFBY CIPMON FBHIGH FBFALL FBRISE FBSTAT
h'97
CLIP DETECTOR: bit[4] rgb/yuv input clip detect, reset read Hardware h'9f Hardware version number bit[7:0] 0/255 hardware 1=A, aso. bit[11:8] product code VPC32x0D VPC32x1D VPC32x2D VPC32x3D bit[15:12] 0/15 product code VPC323xD 100Hz version VPC324xD 50Hz version
CLIPD
read only
Micronas
323xD
Table 3-2: Control Registers Fast Processor
default values initialized reset indicates: register initialized according current standard when register changed.
Subaddress Function Default Name
Standard Selection h'20 Standard select: bit[2:0] standard B,G,H,I NTSC SECAM NTSC44 NTSC COMB 4.433618 3.579545 4.286 4.433618 3.575611 3.582056 4.433618 3.579545 NTSC SECAM NTSC44 PALM PALN PAL60 NTSCC SDTMOD
bit[3]
standard modifier modified simple NTSC modified compensated NTSC SECAM modified monochrome NTSCC modified monochrome PAL+ mode off/on COMB mode S-VHS mode: S-VHS/COMB bits allow following modes: composite input signal comb filter active S-VHS input signal CVBS mode (composite input signal, luma notch)
bit[4] bit[5] bit[6]
PALPLUS COMB SVHS
Option bits allow suppress parts initialization; this used color standard search: bit[7] bit[8] bit[9] bit[10] bit[11] hpll setup vertical setup setup comb filter setup only status bit, normally write After switched standard, this indicate operation complete. Standard automatically initialized when insel register written. SDTOPT
Micronas
323xD
Subaddress
Function
Default
Name
h'148
Enable automatic standard recognition bit[0] B,G,H,I 4.433618 bit[1] NTSC 3.579545 bit[2] SECAM 4.286 bit[3] NTSC44 4.433618 bit[4] 3.575611 bit[5] 3.582056 bit[6] 4.433618 bit[10:7] reserved bit[11] reset status information `switch' register `asr_status' (cleared automatically) disable recognition; enable recognition Note: correct operation don't change reg. 21h, while enabled!
ASR_ENABLE
h'14e
Status bit[0] bit[1] bit[2] bit[3] bit[4] bit[5]
automatic standard recognition error vertical standard (neither detected standard disabled search active search terminated, failed color found standard been switched (since last reset this flag with bit[11] asr_enable)
00000 00001 search started, because vwin error detected
ASR_STATUS VWINERR DISABLED BUSY FAILED NOCOLOR SWITCH
bit[4:0]
input SECAM
00010 search started, because detected vert. standard 0x1x0 01x00 01x10 10100
enabled search started still active search failed (found standard correct) search failed, (detected color standard enabled) color found (monochrome input switch betw. CVBS/SVHS necessary)
Micronas
323xD
Subaddress
Function
Default
Name
h'21
Input select: bit[1:0] bit[2] bit[4:3] bit[6:5] bit[11]
writing this register will also initialize standard luma selector VIN3 VIN2 VIN1 VIN4 chroma selector VIN1/CIN compensation dB/Okt dB/Oct dB/MHz only SECAM chroma bandwidth selector narrow normal broad wide adaptive/fixed SECAM notch filter enable luma lowpass filter hpll speed change terrestrial mixed status bit, write this indicate operation complete.
INSEL
bit[7] bit[8] bit[10:9]
FNTCH LOWP HPLLMD
h'22
picture start position: This register sets start point active video used e.g. panning. setting updated when `sdt' register updated when scaler mode register `scmode' written. luma/chroma delay adjust. bit[5:0] reserved, zero bit[11:6] luma delay clocks, allowed range setting updated when `sdt' register updated. helper delay register (PAL+ mode only) bit[11:0] delay adjust helper lines adjustable from -96.96, step corresponds 1/32 clock component input main video input delay matching bit[5:0] reserved, zero bit[11:6] delay adjust cip/main 0.18 clocks, 9=matched setting updated when `sdt' register updated. mode select, pull-in range limited bit[1:0] 31.5 35.2 37.9 reserved bit[10] disable/enable mode bit[11] status bit, write this indicate operation complete.
SFIF
h'23
LDLY
h'29
HLP_DLY
h'27
CIP_MATCH VGA_C
h'2f
VGAMODE
Micronas
323xD
Subaddress
Function
Default
Name
Comb Filter h'28 comb filter control register bit[1:0] notch filter select flat frequency characteristic min. peaked med. peaked max. peaked bit[3:2] diagonal reduction min. reduction max. reduction bit[4:5] horizontal difference gain min. gain max. gain bit[7:6] vertical difference gain max. gain min. gain bit[11:8] vertical peaking gain vertical peaking. max. vertical peaking comb filter test register bit[1:0] reserved, bit[2] disable/enable vertical peaking rejection filter bit[3] disable/enable vertical peaking coring bit[11:4] reserved, Color Processing h'30 Saturation control bit[11:0] 0.4094 4095 bit[10:0] 0.2047 2070 (2070 corresponds 100% saturation) reserved CR-attenuation PAL+ Helper gain adjust (1591 corresponds 100% helper gain 2047 corresponds 100% gain) select Helper gain (CR-attenuation disabled) select CR-attenuation 1591 CR_ATT ACC_SAT h'e7 COMB_UC NOSEL
CMB_TST
h'55
h'17a
bit[11] h'17d h'39 h'3a h'16c
1280
CR_ATT_ENA ACCH KILVL KILHY HLPDIS
multiplier value PAL+ Helper Signal b[10:0] eeemmmmmmmm bit[10:0] 0.2047 amplitude killer level (0:killer disabled)
amplitude killer hysteresis automatic helper disable nonstandard signals bit[11:0] automatic function disabled bit[1:0] enable bit[11:2] 1.50 number fields switch helper signal NTSC tint angle, ±512
h'dc
TINT
Micronas
323xD
Subaddress
Function
Default
Name
DVCO h'f8 h'f9 crystal oscillator center frequency adjust, -2048 2047 crystal oscillator center frequency adjustment value line-lock mode, true adjust value DVCO ADJUST. factory crystal alignment, using standard video signal: disable autolock mode, DVCO lock mode, read crystal offset from ADJUST register negative value initial center frequency adjustment DVCO. crystal oscillator line-locked mode, lock command/status write: enable lock disable lock read: unlocked >2047 locked crystal oscillator line-locked mode, autolock feature. autolock enabled, crystal oscillator locking started automatically. bit[11:0] threshold, 0:autolock -720 read only DVCO ADJUST
h'f7
XLCK
h'b5
AUTOLCK
Micronas
323xD
Subaddress
Function
Default
Name
Status Register h'12 general purpose control bits bit[2:0] reserved, change bit[3] vertical standard force bit[8:4] reserved, change bit[9] disable flywheel interlace bit[11:10] reserved, change enable vertical free mode vfrc dflw standard recognition status bit[0] vertical lock bit[1] horizontally locked bit[2] signal detected bit[3] color amplitude killer active bit[4] disable amplitude killer bit[5] color ident killer active bit[6] disable ident killer bit[7] interlace detected bit[8] vertical sync detection bit[9] spurious vertical sync detection bit[12:10] reserved input noise level, available only 323xC number lines field, P/S: 312, vertical field counter, incremented field measured sync amplitude value, nominal: (PAL), (NTSC) measured burst amplitude firmware version number bit[7:0] internal revision number bit[11:8] firmware release hardware register h'9f status macrovision detection bit[0] pulse detected bit[1] pseudo sync detected
VFRC DFLW
h'13
h'14 h'cb h'15 h'74 h'36 h'f0
read only read only read only read only read only read only
NOISE NLPF VCNT SAMPL BAMPL
h'170
read only
MCV_STATUS
Micronas
323xD
Subaddress
Function
Default
Name
Scaler Control Register h'40 scaler mode register bit[1:0] scaler mode linear scaling mode nonlinear scaling mode, 'panorama' nonlinear scaling mode, 'waterglass' reserved bit[2] reserved, bit[3] color mode select 4:2:2 mode 4:1:1 mode bit[4] scaler bypass bit[5] reserved, bit[6] luma output format ITU-R luma output format (16-240) CVBS output format bit[7] chroma output format ITU-R (offset binary) signed bit[10:8] reserved, bit[11] scaler update command, when registers updated control register bit[1:0] horizontal downsampling downsampling downsampling downsampling downsampling bit[3:2] vertical compression compression compression compression compression bit[4] vertical filter enable bit[5] interlace offset vertical filter (NTSC mode only) start line field (ITUR spec) start line field (NTSC spec) this register updated when scaler mode register written active video length 1H-FIFO bit[11:0] length pixels D3000 mode (1296/h)1080 mode (864/h)720 this register updated when scaler mode register written scaler1 coefficient: This scaler compresses signal. compression factor value c*1024 required. bit[11:0] allowed values from 1024. 4095 This register updated when scaler mode register written. scaler2 coefficient: This scaler expands signal. expansion factor value 1/c*1024 required. bit[11:0] allowed values from 256.1024 This register updated when scaler mode register written. scaler1/2 nonlinear scaling coefficient This register updated when scaler mode register written. SCMODE PANO
S411
h'41
SCPIP DOWNSAMP
PIPSIZE
PIPE
INTERLACE_OFF
h'42
1080
FFLIM
h'43
1024
SCINC1
h'44
1024
SCINC2
h'45
SCINC
Micronas
323xD
Subaddress
Function
Default
Name
h'47 h'4b h'4c h'50 h'52
scaler1 window controls, table 12-bit registers control nonlinear scaling This register updated when scaler mode register written. scaler2 window controls, table 12-bit registers control nonlinear scaling This register updated when scaler mode register written. brightness register bit[7:0] luma brightness -128.127 ITU-R output format: CVBS output format: bit[9:8] horizontal lowpass filter bypass filter filter filter bit[10] horizontal lowpass filter highresolution chroma bypass/filter enabled bit[11] dis-/enable luma limited this register updated when scaler mode register written contrast register bit[5:0] luma contrast 0.63 ITU-R output format: bit[7:6] horizontal peaking filter narrow broad bit[10:8] peaking gain peaking. max. peaking bit[11] peaking filter coring enable bypass/coring enabled this register updated when scaler mode register written Control Register
SCW1_0
SCW2_0
SCBRI
LPF2
CBW2 YLIM16 SCCT
h'53
PKCOR
h'65
vertical freeze start freeze llc_start line number llc_stop bit[11:0] allowed values from -156.+156 vertical freeze stop freeze llc_start line number llc_stop bit[11:0] allowed values from -156.+156 clock center frequency 12.27 -79437 h'FEC9B2 13.5 174763 h'02AAAB 14.75 194181 h'02F685 -135927 h'FDED08 174763 h'02AAAB
LLC_START
h'66
LLC_STOP
h'69 h'6a
h'02A 2731 h'AAB
LLC_CLOCKH LLC_CLOCKL
Micronas
323xD
Subaddress
Function
Default
Name
h'61
frequency limiter, 12.27 13.5 14.75 clock generator control word bit[5:0] hardware register shadow llc_clkc llc_clkc llc_clkc llc_clkc llc_clkc bit[10:6] reserved bit[11] enable/disable
LLC_DFLIMIT
h'6d
2053
LLC_CLKC
Micronas
323xD
3.2.2. Scaler Adjustment case linear scaling, most scaler registers need set. Only scaler mode, active video length, fixed scaler increments (scinc1/scinc2) must written. adjustment scaler nonlinear scaling modes should parameters given table 3-4. example `panorama vision' mode with 13.5 line-locked clock depicted Fig. 3-2. figure shows scaling input signal variation scaling factor during active video line. scaling factor starts below i.e. borders video data expanded scaler scaling factor becomes compression scaling done scaler When picture center reached, scaling factor held constant. second border scaler increment inverted scaling factor changes back symmetrically. picture indicates function scaler increments scaler window parameters. correct adjustment requires that pixel counts respective windows always number output samples scaler
3.2.1. Calculation Vertical East-West Deflection Coefficients Table formula calculation deflection initialization parameters from polynominal coefficients a,b,c,d,e given vertical East-West deflection. polynomial
0.5) 0.5)2 0.5)3 0.5)4
initialization values accumulators a0.a3 vertical deflection a0.a4 East-West deflection 12-bit values. coefficients that should used calculate initialization values different field frequencies given below, values must scaled 128, i.e. value vertical deflection
1365.3 682.7 682.7)
Table 3-3: Tables Calculation Initialization values Vertical Sawtooth East-West Parabola Vertical Deflection Vertical Deflection -1365.3 1083.5 +682.7 -1090.2 429.9 -682.7 +1645.5 -1305.8 1023.5
125.6 -2046.6 1584.8
East-West Deflection -682.7 +1363.4 -898.4 585.9
-341.3 111.9 1365.3 -899.6 586.8 -85.3 84.8 -111.1 72.1 341.3 -454.5 898.3 -1171.7 756.5
-1365.3 899.6
+682.7 -904.3 296.4
East-West Deflection
-341.3 134.6 1365.3 -1083.5 849.3 -85.3 102.2 -161.2 341.3 -548.4 1305.5
Micronas
323xD
border
center
border
input signal video signal
output signal scinc compression ratio scinc1 scinc2 expansion (scaler2) scaler window cutpoints
compression (scaler1)
compression (scaler1)
expansion (scaler2)
Fig. 3-2: Scaler operation `panorama' mode 13.5
Table 3-4: Set-up values nonlinear scaler modes Mode DIGIT3000 (20.25 MHz) `waterglass' border Register scinc1 scinc2 scinc fflim scw1 scw1 scw1 scw1 scw1 scw2 scw2 scw2 scw2 scw2 center 1643 1024 center 1427 1024 `panorama' border center 1024 center 1024 (13.5 MHz) `waterglass' border center 2464 1024 center 2125 1024 `panorama' border center 1024 center 1024
Micronas
323xD
Specifications 4.1. Outline Dimensions
0.17 0.04 12.0 17.2 0.15 0.37 0.04 23.2 0.15 ±0.2 0.05 18.4
SPGS705000-3(P80)/1E
Fig. 4-1: 80-Pin Plastic Quad Flat Package (PQFP80) Weight approximately 1.61 Dimensions
4.2. Connections Short Descriptions connected used, leave vacant obligatory; connect described circuit diagram SUPPLYA 4.75.5.25 SUPPLYD 3.15.3.45
PQFP 80-pin
Name
Type
Connection used) VREF VREF VREF VREF VREF VREF
Short Description
B1/CB1IN G1/Y1IN R1/CR1IN B2/CB2IN G2/Y2IN R2/CR2IN ASGF FFRSTWIN VSUPCAP VSUPD
Blue1/Cb1 Analog Component Input Green1/Y1 Analog Component Input Red1/Cr1 Analog Component Input Blue2/Cb2 Analog Component Input Green2/Y2 Analog Component Input Red2/Cr2 Analog Component Input Analog Shield GNDF FIFO Reset Write Input Digital Decoupling Circuitry Supply Voltage Supply Voltage, Digital Circuitry Ground, Digital Circuitry Digital Decoupling Circuitry Clock
SUPPLYD SUPPLYD IN/OUT
GNDD
Micronas
323xD
PQFP 80-pin
Name
Type
Connection used) GNDD GNDD GNDD GNDY GNDY GNDY GNDY GNDY GNDY GNDY GNDY GNDC GNDC GNDC GNDC
Short Description
RESQ TEST VGAV YCOEQ FFIE FFWE FFRSTW FFRE FFOE CLK20 GNDPA VSUPPA LLC2 LLC1 VSUPLLC GNDLLC GNDY VSUPY
IN/OUT IN/OUT IN/OUT SUPPLYD SUPPLYD SUPPLYD SUPPLYD
Data Reset Input, Active Test Pin, connect GNDD VGAV Input Output Enable Input, Active FIFO Input Enable FIFO Write Enable FIFO Reset Write/Read FIFO Read Enable FIFO Output Enable Main Clock Output 20.25 Decoupling Circuitry Decoupling Circuitry Supply Voltage Double Clock Output Clock Output Supply Voltage, Circuitry Ground, Circuitry Picture Luma (MSB) Picture Luma Picture Luma Picture Luma Ground, Luma Output Circuitry Supply Voltage, Luma Output Circuitry Picture Luma Picture Luma Picture Luma Picture Luma (LSB) Picture Chroma (MSB) Picture Chroma Picture Chroma Picture Chroma
Micronas
323xD
PQFP 80-pin
Name
Type
Connection used) GNDC GNDC GNDC GNDC
Short Description
VSUPC VSUPSY INTLC FSY/HC/HSYA MSY/HS FPDAT/VSYA VSTBY CLK5 XTAL1 XTAL2 ASGF I2CSEL ISGND VSUPF VOUT VIN1 VIN2 VIN3 VIN4
SUPPLYD SUPPLYD SUPPLYD SUPPLYD IN/OUT IN/OUT SUPPLYA
Supply Voltage, Chroma Output Circuitry Ground, Chroma Output Circuitry Picture Chroma Picture Chroma Picture Chroma Picture Chroma (LSB) Ground, Sync Circuitry Supply Voltage, Sync Circuitry Interlace Output Active Video Output Front Sync/ Horizontal Clamp Pulse/Front-End Horizontal Sync Output Main Sync/Horizontal Sync Pulse Vertical Sync Pulse Front-End /Back-End Data/Front-End Vertical Sync Output Standby Supply Voltage Clock Output Analog Crystal Input Analog Crystal Output Analog Shield GNDF Ground, Analog Front-End Reference Voltage Top, Analog Address Select Signal Ground Analog Input, connect Supply Voltage, Analog Front-End Analog Video Output Chroma Analog Video Input Video Analog Input Video Analog Input Video Analog Input Video Analog Input
SUPPLYA OUTPUT SUPPLYA SUPPLYA
VRT*
Micronas
323xD
PQFP 80-pin
Name
Type
Connection used) VREF GNDD
Short Description
VSUPAI GNDAI VREF FB1IN AISGND
SUPPLYA SUPPLYA OUTPUT SUPPLYA
Supply Voltage, Analog Component Inputs Front-End Ground, Analog Component Inputs Front-End Reference Voltage Top, Analog Component Inputs Front-End Fast Blank Input Signal Ground Analog Component Inputs, connect GNDAI connected
chroma selector must (CIN chroma select) available since 323xD-C5 Data (Fig. 4-13) This connects data line. Reset Input RESQ (Fig. 4-3) level this resets 323xD. Test Input TEST (Fig. 4-3) This enables factory test modes. normal operation, must connected ground. VGAV-Input (Fig. 4-3) This connected vertical sync signal signal. Output Enable Input YCOEQ (Fig. 4-3) level this enables luma chroma outputs. FIFO Input Enable FFIE (Fig. 4-4) This connected external field memory. FIFO Write Enable FFWE (Fig. 4-4) This connected external field memory. FIFO Reset Write/Read FFRSTW (Fig. 4-4) This connected RSTW external field memory. FIFO Read Enable FFRE (Fig. 4-4) This connected external field memory. FIFO Output Enable FFOE (Fig. 4-4) This connected external field memory.
4.3. Descriptions (pin numbers PQFP80 package) Pins Analog Component Inputs RGB1/YCrCb1 (Fig. 4-11) These analog component inputs with fast blank control. YCrCb signal converted using component converter. input signals must AC-coupled. Pins Analog Component Inputs RGB2/YCrCb2 (Fig. 4-11) These analog component inputs without fastblank control. YCrCb signal converted using component converter. input signals must AC-coupled. Ground, Analog Shield Front-End GNDF FIFO Reset Write Input FFRSTWIN (Fig. 4-3) case VPCD application, this connects FFRSTW VPCDpip. Supply Voltage, Decoupling Circuitry VSUPCAP This connected with nF/1.5 nF/390 GNDCAP. Supply Voltage, Digital Circuitry VSUPD Ground, Digital Circuitry GNDD Ground, Decoupling Circuitry GNDCAP Clock (Fig. 4-13) This connects clock line.
Micronas
323xD
nous input signal. timing programmable synchronize external video horizontally, that asynchronous input video stored external memory. timing fixed. DIGIT3000 mode, this supplies front sync information. Main Sync/Horizontal Sync Pulse MSY/HS (Fig. 4-4) This supplies horizontal sync pulse information line-locked mode. DIGIT3000 mode, this main sync input. Vertical Sync Pulse, (Fig. 4-4) This supplies vertical sync signal. Front-End /Back-End Data/Front-End Vertical Sync Output FPDAT/VSYA (Fig. 4-5) DIGIT3000 mode, this interfaces 331x back-end processor. information deflection drives white drive control, beam current limiter, transmitted this pin. mode, this signal used synchronize external video vertically, that asynchronous input video stored external memory. timing fixed. used, this connected with VSUPSY. Standby Supply Voltage VSTDBY standby mode, only clock oscillator active, GNDF should ground reference. Please activate RESQ before powering-up other supplies Clock Output CLK5 (Fig. 4-10) This provides clock frequency microcontroller, e.g. 3000 controller. also used 331x display controller standby clock. Pins 62and XTAL1 Crystal Input XTAL2 Crystal Output (Fig. 4-7) These pins connected 20.25 crystal oscillator which digitally tuned integrated shunt capacitances. CLK20 CLK5 clock signals derived from this oscillator. external clock into XTAL1. this case, clock frequency adjustment must switched off. Ground, Analog Front-End GNDF
Main Clock Output CLK20 (Fig. 4-4) This 20.25 main clock output. Ground, Analog Circuitry GNDPA Supply Voltage, Analog Circuitry VSUPPA This connected with nF/1.5 GNDPA Double Output Clock, LLC2 (Fig. 4-4) Output Clock, LLC1 (Fig. 4-4) This clock reference luma, chroma, status outputs. Supply Voltage, Circuitry VSUPLLC This connected with GNDLLC Ground, Circuitry GNDLLC Pins Luma Outputs (Fig. 4-4) These output pins carry digital luminance data. outputs clocked with LLC1 clock. ITUR656 mode, data multiplexed clocked with LLC2 clock. Ground, Luma Output Circuitry GNDY This connected with GNDY Supply Voltage, Luma Output Circuitry VSUPY Pins Chroma Outputs C7-C0 (Fig. 4-4) These outputs carry digital CrCb chrominance data. outputs clocked with clock. CrCb data sampled half clock rate multiplexed. CrCb multiplex reset each line. ITUR656 mode, chroma outputs tri-stated. Supply Voltage, Chroma Output Circuitry VSUPC This connected with GNDC Ground, Chroma Output Circuitry GNDC Ground, Sync Circuitry GNDSY Supply Voltage, Sync Circuitry VSUPSY This connected with nF/1.5 GNDSY Interlace Output, INTLC (Fig. 4-4) This supplies interlace information, indicates first field, indicates second field. Active Video Output, (Fig. 4-4) This indicates active video output data. signal clocked with LLC1 clock. Front Sync/Horizontal Clamp Pulse/Front-End Horizontal Sync Output, FSY/HC/HSYA (Fig. 4-4) This signal used clamp external video signal, that synchro-
Reference Voltage (Fig. 4-8) this pin, reference voltage converters decoupled. connected with µF/47 Signal Ground Pin. address select I2CSEL (Fig. 4-12) This determines address
Micronas
323xD
Table 4-1: 323xD address select I2CSEL GNDF VSUPF Add. 88/89 8C/8D 8E/8F
Pins 72-75 Video Input (Fig. 4-11) These analog video inputs. CVBS S-VHS luma signal converted using luma (Video converter. VIN1 input also switched chroma (Video ADC. input signal must AC-coupled. Supply Voltage, Analog Component Inputs Front-End VSUPAI This connected with nF/1.5 nF/390 Ground, Analog Component Inputs Front-End Reference Voltage VREF (Fig. 4-8) this pin, reference voltage analog component converters decoupled. connected with µF/47 Analog Component Signal Ground Pin. Fast Blank Input FB1IN (Fig. 4-10) This connected analog fast blank signal. controls insertion RGB1/YCrCb1 signals. input signal must DC-coupled. Signal Analog Component Inputs AISGND (Fig. 4-10) This high quality ground reference component input signals.
Signal Analog Input ISGND (Fig. This high quality ground reference video input signals. Supply Voltage, Analog Front-End VSUPF (Fig. 4-8) This connected with nF/1.5 nF/390 GNDF Analog Video Output, VOUT (Fig. 4-6) analog video signal that selected main (luma, CVBS) output this pin. emitter follower required this pin. Chroma Input (Fig. 4-9) This connected S-VHS chroma signal. resistive divider used bias input signal middle converter input range. only connected chroma (Video converter. signal must AC-coupled.
Micronas
323xD
4.4. Configuration
INTLC FSY/HC/HSYA MSY/HS FPDAT/VSYA VSTBY CLK5 XTAL1 XTAL2 ASGF VSUPSY GNDSY GNDC VSUPC
GNDF I2CSEL ISGND VSUPF VOUT VIN1 VIN2 VIN3 VIN4 VSUPAI GNDAI VREF FB1IN AISGND
VSUPY GNDY GNDLLC VSUPLLC LLC1 LLC2 VSUPPA GNDPA
323xD
B1/CB1IN G1/Y1IN R1/CR1IN B2/CB2IN G2/Y2IN R2/CR2IN ASGF FFRSTWIN VSUPCAP VSUPD GNDD GNDCAP
CLK20 FFOE FFRE FFRSTW FFWE FFIE YCOEQ VGAV TEST RESQ
Fig. 4-2: 80-pin PQFP package
Micronas
323xD
4.5. Circuits VSUPD
0.5M
VSTBY
GNDD Fig. 4-3: Input pins RESQ, TEST, VGAV, YCOEQ, FFRSTWRIN SUPD SUPP Vref
ECLK GNDF
Fig. 4-7: Input/Output Pins XTAL1, XTAL2
SUPF Reference ISGND
Fig. 4-8: Pins VRT, ISGND VREF, AISGND
Fig. 4-4: Output pins C0-C7, Y0-Y7, FSY, MSY, AVO, INTLC, LLC1, LLC2, CLK20, FFWE, FFRE, FFIE, FFRD, RSTWR
VSUPF
VSUPD Fig. 4-9: Chroma input
GNDF
GNDD VSTBY GNDF VSUPF VOUT VREF VSUPF GNDF
Fig. 4-5: Input/Output FPDAT
in's
Fig. 4-10: Output CLK5
Fig. 4-6: Output VOUT GNDF Fig. 4-11: Input pins VIN1-VIN4, RGB/YCrCb1/2, FB1IN
Micronas
323xD
VSUPF
I2CSEL
GNDD Fig. 4-13: Pins SDA,
VGNDF Fig. 4-12: I2CSEL
Micronas
323xD
4.6. Electrical Characteristics 4.6.1. Absolute Maximum Ratings Symbol VSUPA/D Parameter Ambient Operating Temperature Storage Temperature Supply Voltage, Supply Inputs Input Voltage, Inputs Output Voltage, Outputs Min. -0.3 -0.3 -0.3
Max. VSUPA+0.3 VSUPD+0.3
Unit
Stresses beyond those listed "Absolute Maximum Ratings" cause permanent damage device. This stress rating only. Functional operation device these other conditions beyond those indicated "Recommended Operating Conditions/Characteristics" this specification implied. Exposure absolute maximum ratings conditions extended periods affect device reliability.
4.6.2. Recommended Operating Conditions Symbol VSUP VSUPD fXTAL Parameter Ambient Operating Temperature Case Operating Temperature Supply Voltages, analog Supply Pins Supply Voltages, digital Supply Pins Clock Frequency Name XTAL1/2 Min. 4.75 3.15 Typ. 20.25 Max. 5.25 3.45 Unit
Micronas
323xD
4.6.3. Recommended Crystal Characteristics Symbol fP/fP fP/fP Parameter Operating Ambient Temperature Parallel Resonance Frequency with Load Capacitance Accuracy Adjustment Frequency Temperature Drift Series Resistance Shunt Capacitance Motional Capacitance Min. Typ. 20.250000 Max. Unit
Load Capacitance Recommendation Lext External Load Capacitance from pins Ground (pin names: Xtal1 Xtal2)
Characteristics 2,3) ICLoadmin Effective Load Capacitance min. DCO-Position, Code package: 68PLCC Effective Load Capacitance Range, Codes from 0.255
ICLoadrng
12.7
Remarks defining External Load Capacitance:
External capacitors each crystal ground required. They necessary tune effective load capacitance PCBs required load capacitance crystal. higher capacitors, lower clock frequency results. nominal free running frequency should match MHz. different layouts customer PCBs matching capacitor size should determined application. suggested value figure based experience with various layouts. Tuning condition: Code DVCO Register=-720
Remarks Pulling Range DCO:
pulling range function used crystal effective load capacitance (CICLoad +CLoadBoard). resulting frequency with effective load capacitance CLeff CICLoad LoadBoard CLeff)
Remarks codes
hardware register bits, control register uses range -2048.2047
Micronas
323xD
4.6.4. Characteristics
VSUPF 4.75 5.25 VSUPD 3.15 3.45 20.25 min./max. values VSUPF VSUPD 20.25 typical values Symbol PTOT IVSUPA IVSUPD IVSTDBY Parameter Total Power Dissipation Current Consumption Current Consumption Current Consumption Input Output Leakage Current VSUPF VSUPD VSTDBY Pins Name Min. Typ. Max. 1000 Unit
4.6.4.1. Characteristics, Clock Output
Symbol Parameter Output Voltage Output High Voltage Name CLK5 Min. Typ. Max. STDBY Unit Test Conditions -IOL CLOAD
Output Transition Time
4.6.4.2. Characteristics, Clock Input/Output, External Clock Input (XTAL1)
Symbol VDCAV Parameter Average Name CLK20 Min. VSUPD/2 VSUPD/2 XTAL1 Typ. SUPD/2 SUPD/2 Max. VSUPD/2 VSUPD/2 Unit Test Conditions CLOAD CLOAD CLOAD only test purposes capacitive coupling used, XTAL2 open
VOUT Peak Peak Output Transition Time Input Trigger Level Clock Input Voltage
4.6.4.3. Characteristics, Reset Input, Test Input, VGAV Input, YCOEQ Input
Symbol tOEED Parameter Input Voltage Input High Voltage Data Output Enable/Disable Time Name RESQ TEST VGAV YCOEQ YCOEQ Min. Typ. Max. Unit Test Conditions
Micronas
323xD
4.6.4.4. Characteristics, Power-up Sequence
Symbol tVdel tVrmpl Parameter Ramp Difference Supplies Transition Time Supplies Name Min. Typ. Max. Unit Test Conditions
tVrmp VSUPAI VSUPF
time tVdel VSUPD VSTBY
time max.
(maximum guaranteed start-up time)
time RESQ VSUPD min.
time max. 0.05ms SDA/SCL I2C-cycles invalid
time Fig. 4-14: Power-Up sequence
Micronas
323xD
4.6.4.5. Characteristics, FPDAT Input/Output
Symbol tODL Parameter Output Voltage Output Hold Time Output Delay Time Input Voltage Input High Voltage Input Setup Time Input Hold Time Load capacitance Name FPDAT Min. Typ. Max.
Unit
Test Conditions
4.6.4.6. Characteristics, Interface
Symbol fSCL tLOW tHIGH Data Data Parameter Input Voltage Input High Voltage Output Voltage Name SDA, Min. Typ. Max. Unit Test Conditions
Input Capacitance Signal Fall Time Signal Rise Time Clock Frequency Period High Period Data Time high DATA Hold Time
4.6.4.7. Characteristics, Address Select I2CSEL Input
Symbol VMED Parameter Input Voltage Input High Voltage Input Medium Voltage Name I2CSEL Min. GNDF Typ. Max. VSUPF Unit Test Conditions
Micronas
323xD
4.6.4.8. Characteristics, Analog Video Component Inputs
Symbol VVIN Parameter Analog Input Voltage Name VIN1, VIN2 VIN3, VIN4 R1/CR1IN G1/Y1IN B1/CB1IN R2/CR2IN G2/Y2IN B2/CB2IN FBIN VIN1, VIN2 VIN3, VIN4 Min. Typ. Max. Unit Test Conditions
Input Coupling Capacitor Video Inputs Input Coupling Capacitor Chroma Input Input Coupling Capacitor Component Input
R1/CR1IN G1/Y1IN B1/CB1IN R2/CR2IN G2/Y2IN B2/CB2IN
4.6.4.9. Characteristics, Analog Front-End ADCs
Symbol VVRT Luma Path RVIN CVIN VVIN DNLAGC VINCL ICL-LSB DNLICL Input Resistance Input Capacitance Full Scale Input Voltage Full Scale Input Voltage step width Differential Non-Linearity Input Clamping Level, CVBS VIN1 VIN2 VIN3 VIN4 VIN1 VIN2 VIN3 VIN4 VIN1 VIN2 VIN3 VIN4 0.166 ±0.5 min. Gain max. Gain 6-Bit Resolution= Steps fsig=1MHz, max. AGC-Gain Binary Level min. Gain I-DAC, bipolar VVIN =1.5 Code Clamp-DAC=0 Parameter Reference Voltage Name VREF Min. Typ. Max. Unit Test Conditions µF/10 Probe
Clamping Resolution Input Clamping Current step Clamping Differential NonLinearity
±0.5
steps
Micronas
323xD
Symbol Chroma Path RCIN VCIN CINDC
Parameter
Name
Min.
Typ.
Max.
Unit
Test Conditions
Input Resistance SVHS Chroma Full Scale Input Voltage, Chroma Input Bias Level, SVHS Chroma Binary Code Open Chroma Input
VIN1
1.08
1.32
Component Path RVIN CVIN VVIN VVINCL VINCL Input Resistance Input Capacitance Full Scale Input Voltage Full Scale Input Voltage Input Clamping Level RGB, R1/CR1IN G1/Y1IN B1/CB1IN R2/CR2IN G2/Y2IN B2/CB2IN 0.85 1.06 min. Gain (XAR=-0) max. Gain (XAR=-1) Binary Level XAR=-0 Binary Level XAR=-0 Full Scale MHz, XAR=-0 I-DAC, bipolar VVIN =1.5 Code Clamp-DAC=0
Input Clamping Level
Gain Match ICL-LSB DNLICL Clamping Resolution Input Clamping Current step Clamping Differential NonLinearity
0.59
0.85
1.11 ±0.5
steps
Dynamic Characteristics Video-Paths (Luma Chroma) Component-Paths XTALK Bandwidth Crosstalk, Video Inputs Total Harmonic Distortion VIN1 VIN2 VIN3 VIN4 R1/CR1IN G1/Y1IN B1/CB1IN R2/CR2IN G2/Y2IN B2/CB2IN input signal level MHz, signal level MHz, harmonics, signal level MHz, outputs, signal level Code Density, DC-ramp
SINAD
Signal Noise Distortion Ratio Integral Non-Linearity Differential Non-Linearity Differential Gain Differential Phase
±0.8
dBr, signal DC-ramp
Micronas
323xD
Symbol
Parameter
Name
Min.
Typ.
Max.
Unit
Test Conditions
Analog Video Output AGCVOUT DNLAGC OUTDC Output Voltage step width, VOUT Differential Non-Linearity DC-level VOUT Bandwidth Out: VOUT VIN1 VIN2 VIN3 VIN4 1.333 ±0.5 clamped Back porch Input: main range, CL10 Input: main range, CL10 MHz, Harmonics VPP, AGC= Resolution=7 Steps MSBs main
VOUT Total Harmonic Distortion
CLVOUT
ILVOUT
Load Capacitance Output Current
VOUT
±0.1
4.6.4.10.Characteristics, Analog Input
Symbol RFBIN FBIN THFBMO BWFBIN THDFBIN Parameter Input Resistance Full Scale Input Voltage Threshold FB-Monitor Bandwidth Total Harmonic Distortion Name FB1IN Min. 0.85 Typ. 0.65 Max. Unit input signal level MHz, harmonics, signal level MHz, outputs, signal level Code Density, DC-ramp Test Conditions Code Clamp-DAC=0
SINADFBIN INLFBIN DNLFBIN
Signal Noise Distortion Ratio Integral Non-Linearity Differential Non-Linearity
±0.8
Micronas
323xD
4.6.4.11.Characteristics, Output Specification
Output Specification SYNC, CONTROL, DATA Pins: Y[7:0], C[7:0], AVO, INTLC, FSY, FFIE, FFWE, FFOE, FFRD, FFRSTWR
Symbol Parameter Load Capacitance Output Voltage Output High Voltage Output Hold Time Name Min. Typ. Max. Unit Cload =50pF Cload =50pF LLC2=27.0MHz, OMODE=1 DBCLK=0/1 LLC2=27.0MHz, OMODE=1, DBCLK=0/1, NOTE1 LLC2=32.0MHz, OMODE=1, DBCLK=0/1 LLC2=32.0MHz, OMODE=1, DBCLK=0/1, NOTE1 CLK20=20.25MHz, OMODE=0, NOTE1 CLK20=20.25MHz, OMODE=0, NOTE1 Test Conditions
Output Delay Time
Output Hold Time
Output Delay Time
Output Hold Time
Output Delay Time
NOTE
CLOAD depends selected driver strength which I2C-programable.
Table 4-1: Adjustable driver strength AVO, INTLC, FFIE, FFWE, FFOE, FFRD, FFRSTWR: Strength 0000 0001 0010 0011 0100 0101 0110 0111 Load 47,5pF 45,0 42,5 40,0pF 37,5 35,0 32,5 Strength 1000 1001 1010 1011 1100 1101 1110 1111 Load 30,0pF 27,5 25,0 22,5 20,0pF 17,5pF 15,0 12,5
Micronas
323xD
CLK20 20.25
case DIGIT3000 mode
LLC2
case Mode
LLC1
case Mode
Output
Data valid
Data valid
Fig. 4-15: Sync, control, data outputs
write address point disable
disable
N+10 N+11
disable
SWCK
FFWE
FFIE
D0-D11
Fig. 4-16: Field memory write cycle timing
Micronas
323xD
read address point disable
disable
N+10 N+11
disable
SRCK
FFRE
FFOE
D0-D11
Hi-z
Hi-z
Hi-z
Fig. 4-17: Field memory read cycle timing
Micronas
323xD
4.6.4.12.Characteristics, Input Specification Input Specification SYNC, CONTROL, DATA Pin: (DIGIT3000 mode only)
Symbol Parameter Input Voltage Input High Voltage Input Setup Time Input Hold Time Name Min. Typ. Max. Unit Test Conditions
CLK20 20.25
case DIGIT3000 Mode
Input
Data valid
LLC1 13.5
case Mode
Input
Data valid
Fig. 4-18: Sync, control, data inputs
Micronas
323xD
4.6.4.13.Characteristics, Clock Output Specification Line-Locked Clock Pins: LLC1, LLC2
Symbol Parameter Load capacitance Output Voltage Output High Voltage Name LLC1, LLC2 LLC1, LLC2 LLC1, LLC2 Min. Typ. Max.
Unit
Test Conditions
13.5 Line Locked Clock 1/T1 tWL1 tWH1 tR1, 1/T2 tWL2 tWH2 tR2, LLC1 Clock Frequency LLC1 Clock Time LLC1 Clock High Time Clock Rise/Fall Time Clock LLC2 Clock Frequency LLC2 Clock Time LLC2 Clock High Time Clock Rise/Fall TimeClock LLC1 LLC1 LLC1 LLC1 LLC2 LLC2 LLC2 LLC2 12.5 14.5
Line Locked Clock 1/T1 tWL1 tWH1 tR1, 1/T2 tWL2 tWH2 tR2, LLC1 Clock Frequency LLC1 Clock Time LLC1 Clock High Time Clock Rise/Fall TimeClock LLC2 Clock Frequency LLC2 Clock Time LLC2 Clock High Time Clock Rise/Fall TimeClock LLC1 LLC1 LLC1 LLC1 LLC2 LLC2 LLC2 LLC2 14.8 29.6 17.2 34.4
common timings modes tSKS Clock Skew LLC1=13.5MHz, LLC2=27MHz
Micronas
323xD
tWH13 tWL13
LLC1 (13.5 ±7%)
tWH27 tWL27
LLC2 ±7%)
Fig. 4-19: Line-locked clock output pins
Micronas
323xD
Application Circuit
323xD
Micronas
323xD
5.1. Application Note: mode with 323xD 100-Hz applications desirable display VGA-signal this case, VGA-graphic card delivers signals. These signals "directly" back-end signal processing. generates stable line-locked clock 100-Hz system relation sync signals. While V-sync connected VGAV directly, H-sync pulse-shaped amplitude adjusted until connected video input pins VPC. recommended circuitry filter sync given figure below.
analog
47pF 31kHz BC848B 1N4148 1N4148 analog analog
Video Input
Fig. 5-1: Application circuit horizontal VGA-input
Micronas
323xD
5.2. Application Note: Mode Programming 5.2.1. Procedure Program Mode VPCpip VPCsingle: scaler according size used (see Table 2-11). write registers VPCMODE PIPMODE according mode set. expert mode write registers NLIN, NPIX NPFB. write registers COLBGD, COLFR1, COLFR2, HSTR VSTR, different value default used. write registers LINOFFS PIXOFFS, different value default more than inset pictures direction used. write register PIPOPER fill frame background inset picture. This step repeated inset pictures multi application. VPCmain: scaler full size video (see Table 2-11). write registers VPCMODE PIPMODE according mode set. expert mode write registers NLIN, NPIX NPFB. write registers COLBGD, HSTR VSTR, different value default used. write register PIPOPER start displaying PIP. Table 5-1: register programing control register VPCMODE, PIPMODE, PIPOPER COLBGD, COLFR1, COLFR2, HSTR, VSTR LINOFFS, PIXOFFS should written always update
VPCpip VPCsingle: write register PIPOPER start filling inset picture with live video. Only tuner scanning: write register PIPOPER stop filling inset picture with live video changing channel. repeat steps inset pictures multi application. Only VPCsingle: write register PIPOPER start filling main picture part outside inset picture(s) with live video. VPCmain: write registers HSTR VSTR, position should changed. write register PIPOPER, quit mode. application with single VPC, step dropped. Additionally, free running mode should cases shown Table 2-14. 5.2.2. Registers Programming Control program mode, register VPCMODE, PIPMODE PIPOPER should written always, other registers used only expert mode default values modified (see Table 5-1).
should written only, default values have modified only used expert mode, when more than inset pictures direction used. VPCmain used. VPCsingle only used different value default more than inset pictures direction used
NLIN, NPIX, NPFB
should written, only expert mode. predefined modes default values used.)
Micronas
323xD
Table 5-2: Limits register settings programming mode register NPFB NPIX NLIN HSTR VSTR PIXOFFS LINOFFS VPCmain VPCpip VPCsingle
NPFB NPIXmain (X=2 other field memories) NPFB NLINmain total field memory size NPIX NPFB NPIX NPELfp NPFB NLIN total field memory size NLIN NROWfp HSTR< NPELfp NPIXmain VSTR NROWfp NLINmain used used NPIX NPELsp NLIN NROWsp HSTR NPELsp NPIXPIP VSTR NROWsp NLINPIP PIXOFFS NPIXmain (number pixels inset pictures right PIXOFFS) LINOFFS NLINmain (number lines inset pictures below LINOFFS)
Notes:
NPIXmain NLINmain: correspond VPCmain NPIXPIP NLIN PIP: correspond VPCsingle VPCpip NROWfp NPELfp: number lines field number pixels line full picture (e.g. NROWfp=288, NPELfp= 13.5 MHz) NROWsp NPELsp: number lines field number pixels line inset picture
limits register settings given Table 5-2. range check value limitation carried field memory controller. illegal setting these parameters leads error behavior function. display controlled commands written into register PIPOPER. VPCmain, display turned commends DISSTART DISSTOP. VPCsingle, commands available: WRFRCOL1, WRFRCOL2: fill frame inset picture with color COLFR1 COLFR2, WRBGD, WRBGDNF: fill inset picture with background color COLBGD, WRPIC, WRPICNF, WRSTOP: start stop write inset picture with active video, WRMAIN: start write main picture part outside inset picture(s) with active video (only VPCsingle). While WRPIC, WRSTOP, WRFRCOL1, WRFRCOL2 WRBGD control display with frame (see Fig. 5-2), WRPICNF WRBGDNF control display without frame (see Fig. 5-3). number inset picture addressed current commend given bits NSPX NSPY register PIPOPER.
display window, coordinate upper-left corner inset picture with NSPX=0 NSPY=0 defined registers LINOFFS PIXOFFS. maximal inset pictures used, setting these registers needed. default setting LINOFFS=0 PIXOFFS=0 takes effect. more than inset pictures involved application, these inset pictures should grouped, that inset pictures each group addressed bits NSPX NSPY. writing each group, registers LINOFFS PIXOFFS should correctly (see Fig.5-4).
(LINOFFS, PIXOFFS)
NSPY NSPX
display window
Fig. 5-2: inset pictures with frame
Micronas
323xD
5.2.3.2. Select Strobe Effect Expert Mode
(LINOFFS, PIXOFFS)
NSPY NSPX
LINOFFS
display window
Fig. 5-3: inset pictures without frame
Fig. 5-4: Example expert mode
5.2.3. Examples 5.2.3.1. Select Predefined Mode
Scaler settings VPCpip:
SCINC1 h'480 FFLIM h'78 NEWLIN h'194 AVSTRT h'86 AVSTOP h'356 SC_PIP h'1f SC_BRI h'310 SC_CT h'30 SC_MODE h'00 (for S411=0)
Scaler settings VPCpip:
SCINC1 h'600 FFLIM h'168 NEWLIN h'194 AVSTRT h'86 AVSTOP h'356 SC_PIP h'11 SC_BRI h'110 SC_CT h'30 SC_MODE h'00 (for S411=0)
controller settings show strobe effect: VPCpip: VPCMODE h'01 PIPMODE h'0f VSTR h'202 HSTR h'101 NPIX h'1c NLIN h'2c NPFB h'132
PIPOPER h'c0 (write background wait until NEWCMD PIPOPER h'a0 (write frame wait until NEWCMD PIPOPER h'80 (start writing wait until NEWCMD PIPOPER h'c4 (write background wait until NEWCMD PIPOPER h'a4 (write frame wait until NEWCMD PIPOPER h'84 (start writing wait until NEWCMD PIPOPER h'c8 (write background wait until NEWCMD PIPOPER h'a8 (write frame wait until NEWCMD PIPOPER h'88 (start writing
controller settings start display: VPCpip: VPCMODE h'01 PIPMODE h'02 PIPOPER h'c0 (write background) wait until NEWCMD PIPOPER h'a0 (write frame) wait until NEWCMD PIPOPER h'80 (start writing PIP)
After that position changed HSTR VSTR registers. e.g. HSTR h'03
VPCmain: VPCMODE h'05 PIPMODE h'02 PIPOPER h'80 (start display PIP) controller settings stop display: VPCmain: PIPOPER h'90 (stop display PIP)
Micronas
323xD
PIPMODE h'06 PIPOPER h'c0 (write background wait until NEWCMD PIPOPER h'a0 (write frame wait until NEWCMD PIPOPER h'c1 (write background wait until NEWCMD PIPOPER h'a1 (write frame wait until NEWCMD PIPOPER h'c4 (write background wait until NEWCMD PIPOPER h'a4 (write frame wait until NEWCMD PIPOPER h'c5 (write background wait until NEWCMD PIPOPER h'a5 (write frame wait until NEWCMD
wait until NEWCMD PIPOPER h'cc (write background wait until NEWCMD PIPOPER h'ac (write frame wait until NEWCMD PIPOPER h'8c (start writing wait until NEWCMD LINOFFS h'2b8 PIPOPER h'c0 (write background wait until NEWCMD PIPOPER h'a0 (write frame wait until NEWCMD PIPOPER h'80 (start writing wait until NEWCMD PIPOPER h'c4 (write background wait until NEWCMD PIPOPER h'a4 (write frame wait until NEWCMD PIPOPER h'84 (start writing
VPCmain: VPCMODE h'05 PIPMODE h'0f VSTR h'201 HSTR h'193 NPIX h'1e NLIN h'116 NPFB h'132 PIPOPER h'80 (start display PIP) controller settings stop display: VPCmain: PIPOPER h'90 (stop display PIP)
VPCmain: VPCMODE h'05 PIPMODE h'46 PIPOPER h'80 (start display multi PIP) VPCpip: tune channel PIPOPER h'80 (start writing wait until NEWCMD PIPOPER h'90 (stop writing wait until NEWCMD
tune other channel PIPOPER h'81 (start writing wait until NEWCMD PIPOPER h'91 (stop writing wait until NEWCMD tune other channel PIPOPER h'84 (start writing wait until NEWCMD PIPOPER h'94 (stop writing wait until NEWCMD tune other channel PIPOPER h'85 (start writing wait until NEWCMD PIPOPER h'95 (stop writing wait until NEWCMD tuning writing four inset pictures repeated.
5.2.3.3. Select Predefined Mode Tuner Scanning
Scaler settings VPCpip:
SCINC1 h'600 FFLIM h'168 NEWLIN h'194 AVSTRT h'86 AVSTOP h'356 SC_PIP h'11 SC_BRI h'110 SC_CT h'30 SC_MODE h'00 (for S411=0)
controller settings stop tuner scanning: controller settings tuner scanning: VPCpip: VPCMODE h'01 VPCmain: PIPOPER h'90 (stop display PIP)
Micronas
323xD
Data Sheet History Preliminary data sheet: "VPC 323XD Comb Filter Video Processor", July 2001, 6251-472-1PD. First release preliminary data sheet.
Micronas GmbH Hans-Bunte-Strasse D-79108 Freiburg (Germany) P.O. D-79008 Freiburg (Germany) Tel. +49-761-517-0 +49-761-517-2174 E-mail: docservice@micronas.com Internet: www.micronas.com Printed Germany Order 6251-472-1PD
information data contained this data sheet without commitment, considered offer conclusion contract, shall they construed create liability. issue this data sheet invalidates previous issues. Product availability delivery exclusively subject respective order confirmation form; same applies orders based development samples delivered. this publication, Micronas GmbH does assume responsibility patent infringements other rights third parties which result from use. Further, Micronas GmbH reserves right revise this publication make changes content, time, without obligation notify person entity such revisions changes. part this publication reproduced, photocopied, stored retrieval system, transmitted without express written consent Micronas GmbH.
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