SHEET SHEET STATUS SHEETS PMIC SHEET PREPARED Kenneth Rice S
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REVISIONS DESCRIPTION Update drawing current requirements. Editorial changes throughout. DATE (YR-MO-DA) 02-05-10 APPROVED Raymond Monnin
SHEET SHEET STATUS SHEETS PMIC
SHEET PREPARED Kenneth Rice
STANDARD MICROCIRCUIT DRAWING
THIS DRAWING AVAILABLE DEPARTMENTS AGENCIES DEPARTMENT DEFENSE
CHECKED Jeff Bowling APPROVED Raymond Monnin
DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216 http://www.dscc.dla.mil
DRAWING APPROVAL DATE 97-07-31
MICROCIRCUIT, MEMORY, DIGITAL, CMOS, PROGRAMMABLE LOGIC ARRAY, MONOLITHIC SILICON
AMSC
REVISION LEVEL
SIZE SHEET
CAGE CODE
67268
5962-97523
DSCC FORM 2233 DISTRIBUTION STATEMENT Approved public release; distribution unlimited.
5962-E388-02
SCOPE Scope. This drawing documents product assurance class levels consisting high reliability (device classes space application (device class choice case outlines lead finishes available reflected Part Identifying Number (PIN). When available, choice Radiation Hardness Assurance (RHA) levels reflected PIN. PIN. shown following example: 5962 97523
Federal stock class designator
designator (see 1.2.1)
Device type (see 1.2.2)
Device class designator (see 1.2.3)
Case outline (see 1.2.4)
Lead finish (see 1.2.5)
Drawing number 1.2.1 designator. Device classes marked devices meet MIL-PRF-38535 specified levels marked with appropriate designator. Device class marked devices meet MIL-PRF-38535, appendix specified levels marked with appropriate designator. dash indicates non-RHA device. 1.2.2 Device type(s). device type(s) identify circuit function follows: Device type Generic number 4010E-4 Circuit function 10000 gate programmable array Access time
1.2.3 Device class designator. device class designator single letter identifying product assurance level follows: Device class Device requirements documentation Vendor self-certification requirements MIL-STD-883 compliant, nonJAN class level microcircuits accordance with MIL-PRF-38535, appendix Certification qualification MIL-PRF-38535
1.2.4 Case outline(s). case outline(s) designated MIL-STD-1835 follows: Outline letter Descriptive designator CMGA8-P191 figure figure Terminals Package style grid array package Quad flat package Quad flat package
1.2.5 Lead finish. lead finish specified MIL-PRF-38535 device classes MIL-PRF-38535, appendix device class
actual number pins used, maximum listed MIL-STD-1835.
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Absolute maximum ratings. Supply voltage range ground potential (VCC) input voltage range Voltage applied three-state output (VIS) Maximum power Thermal resistance, junction-to-case (JC): Case outline Case outlines Junction temperature (TJ) Lead temperature (soldering, seconds) Storage temperature range Recommended operating conditions. Case operating temperature range (TC) -55°C +125°C Supply voltage relative ground (VCC) +4.5 minimum +5.5 maximum Ground voltage (GND) APPLICABLE DOCUMENTS Government specification, standards, handbooks. following specification, standards, handbooks form part this drawing extent specified herein. Unless otherwise specified, issues these documents those listed issue Department Defense Index Specifications Standards (DoDISS) supplement thereto, cited solicitation. SPECIFICATION DEPARTMENT DEFENSE MIL-PRF-38535 Integrated Circuits, Manufacturing, General Specification for. STANDARDS DEPARTMENT DEFENSE MIL-STD-883 MIL-STD-1835 HANDBOOKS DEPARTMENT DEFENSE MIL-HDBK-103 MIL-HDBK-780 List Standard Microcircuit Drawings. Standard Microcircuit Drawings. Test Method Standard Microcircuits. Interface Standard Electronic Component Case Outlines. -0.5 +7.0 -0.5 +0.5 -0.5 +0.5 MIL-STD-1835 20°C/W +150°C +260°C -65°C +150°C
(Unless otherwise indicated, copies specification, standards, handbooks available from Standardization Document Order Desk, Robbins Avenue, Building Philadelphia, 19111-5094.)
Stresses above absolute maximum rating cause permanent damage device. Extended operation maximum levels degrade performance affect reliability. When thermal resistance this case specified MIL-STD-1835 that value shall supersede value indicated herein. Maximum junction temperature shall exceeded except allowable short duration burn-in screening conditions accordance with method 5004 MIL-STD-883. voltage values this drawing with respect VSS.
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Non-Government publications. following documents form part this document extent specified herein. Unless otherwise specified, issues documents which adopted those listed issue DoDISS cited solicitation. Unless otherwise specified, issues documents listed DoDISS issues documents cited solicitation. ELECTRONIC INDUSTRIES ALLIANCE (EIA) JESD Latch-Up Test. (Application copies should addressed Electronic Industries Alliance, 2500 Wilson Boulevard, Arlington, 22201-3834.) Order precedence. event conflict between text this drawing references cited herein, text this drawing takes precedence. Nothing this document, however, supersedes applicable laws regulations unless specific exemption been obtained. REQUIREMENTS Item requirements. individual item requirements device classes shall accordance with MIL-PRF-38535 specified herein modified device manufacturer's Quality Management (QM) plan. modification plan shall affect form, fit, function described herein. individual item requirements device class shall accordance with MIL-PRF-38535, appendix non-JAN class level devices specified herein. Design, construction, physical dimensions. design, construction, physical dimensions shall specified MIL-PRF-38535 herein device classes MIL-PRF-38535, appendix herein device class 3.2.1 Case outlines. case outlines shall accordance with 1.2.4 herein figure 3.2.2 Terminal connections. terminal connections shall specified figure 3.2.3 Logic block diagram. logic block diagram shall specified figure Electrical performance characteristics postirradiation parameter limits. Unless otherwise specified herein, electrical performance characteristics postirradiation parameter limits specified table shall apply over full case operating temperature range. Electrical test requirements. electrical test requirements shall subgroups specified table IIA. electrical tests each subgroup defined table Marking. part shall marked with listed herein. addition, manufacturer's also marked listed MIL-HDBK-103. packages where marking entire number feasible space limitations, manufacturer option marking "5962-" device. product using this option, designator shall still marked. Marking device classes shall accordance with MIL-PRF-38535. Marking device class shall accordance with MIL-PRF-38535, appendix 3.5.1 Certification/compliance mark. certification mark device classes shall "QML" required MIL-PRF-38535. compliance mark device class shall required MIL-PRF-38535, appendix Certificate compliance. device classes certificate compliance shall required from QML-38535 listed manufacturer order supply requirements this drawing (see 6.6.1 herein). device class certificate compliance shall required from manufacturer order listed approved source supply MIL-HDBK-103 (see 6.6.2 herein). certificate compliance submitted DSCC-VA prior listing approved source supply this drawing shall affirm that manufacturer's product meets, device classes requirements MIL-PRF-38535 herein device class requirements MIL-PRF-38535, appendix herein. Certificate conformance. certificate conformance required device classes MIL-PRF-38535 device class MIL-PRF-38535, appendix shall provided with each microcircuits delivered this drawing.
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Notification change device class device class notification DSCC-VA change product (see herein) involving devices acquired this drawing required change defined MIL-PRF-38535, appendix Verification review device class device class DSCC, DSCC's agent, acquiring activity retain option review manufacturer's facility applicable required documentation. Offshore documentation shall made available onshore option reviewer. 3.10 Microcircuit group assignment device class Device class devices covered this drawing shall microcircuit group number (see MIL-PRF-38535, appendix QUALITY ASSURANCE PROVISIONS Sampling inspection. device classes sampling inspection procedures shall accordance with MIL-PRF-38535 modified device manufacturer's Quality Management (QM) plan. modification plan shall affect form, fit, function described herein. device class sampling inspection procedures shall accordance with MIL-PRF-38535, appendix Screening. device classes screening shall accordance with MIL-PRF-38535, shall conducted devices prior qualification technology conformance inspection. device class screening shall accordance with method 5004 MIL-STD-883, shall conducted devices prior quality conformance inspection. 4.2.1 Additional criteria device class Delete sequence specified initial (preburn-in) electrical parameters through interim (postburn-in) electrical parameters method 5004 substitute lines through table herein. test circuit shall maintained manufacturer under document revision level control shall made available preparing acquiring activity upon request. test circuit shall specify inputs, outputs, biases, power dissipation, applicable, accordance with intent specified test method 1015. Interim final electrical parameters shall specified table herein.
4.2.2 Additional criteria device classes burn-in test duration, test condition test temperature, approved alternatives shall specified device manufacturer's plan accordance with MIL-PRF-38535. burn-in test circuit shall maintained under document revision level control device manufacturer's Technology Review Board (TRB) accordance with MILPRF-38535 shall made available acquiring preparing activity upon request. test circuit shall specify inputs, outputs, biases, power dissipation, applicable, accordance with intent specified test method 1015. Interim final electrical test parameters shall specified table herein. Additional screening device class beyond requirements device class shall specified MIL-PRF38535, appendix
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TABLE Electrical performance characteristics. Test Symbol Conditions -55°C +125°C unless otherwise specified -4.0 Group subgroups Device type Limits Unit
High level output voltage
level output voltage
Quiescent supply current Input leakage current pull-up current (when selected) Horizontal long line pull-up current (when selected) Input capacitance Output capacitance Functional test Tpid 20*Tilo Int. Tops Tpid 20*Thho Int. Tops Tpid 20*Tiho Int. Tops Tpid 20*Trio Int. Tops Tcko Int. Tick Tcko Int. Thhck Tcko Int. Tdick Tcko Int. Tihck Tcko Int. Tecck
ICCO IRIN IRLL COUT
logic Mhz, 4.4.1e Mhz, VOUT 4.4.1e 4.4.1c
-0.02
-0.25
99.1 119.1 139.1 173.1 10.1 11.1 12.2 10.1
footnotes table.
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TABLE Electrical performance characteristics continued.
Test
Symbol
Conditions -55°C +125°C unless otherwise specified
Group subgroups
Device type
Limits
Unit
Interconnect tpid tops topcy tsum tBYP Interconnect tpid tops tascy tsum tBYP Interconnect tpid tops tincy tsum Interconnect tpid tops tincy tsum tBYP
tB10 tB11 tB12 tB13
197.7
107.4
43.5
WIDE DECODER SWITCHING CHARACTERISTICS Full length, both pull-ups inputs from I-pins Full length, both pull-ups inputs from internal logic Half length, pull-up inputs from I-pins Half length, pull-up inputs from internal logic TWAF TWAFL TWAO TWAOL figures applicable.
SWITCHING CHARACTERISTICS Combinatorial delay inputs outputs Combinatorial delay inputs outputs Combinatorial delay inputs outputs fast carry logic operand inputs (F1,F2,G1, COUT fast carry logic add/ subtract input (F3) COUT footnotes table. TILO TIHO figures applicable.
THHO
TOPCY
TASCY
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TABLE Electrical performance characteristics. continued. Test Symbol Conditions -55°C +125°C unless otherwise specified Group subgroups Device type Limits Unit
SWITCHING CHARACTERISTICS Continued. fast carry logic initialization inputs (F1,F3) COUT fast carry logic through function generators outputs fast carry logic COUT, bypass function generators Sequential delays clock outputs Set-up time before clock inputs Set-up time before clock inputs Set-up time before clock inputs Set-up time before clock inputs Set-up time before clock inputs Set-up time before clock inputs S/R, going (inactive) Hold time after clock inputs Hold time after clock inputs Hold time after clock inputs Hold time after clock inputs Hold time after clock inputs Hold time after clock inputs S/R, going (inactive) footnotes table. TINCY figures applicable
TSUM
TBYP
TCKO TICK TIHCK THHCK TDICK TECCK TRCK
TCKI TCKIH TCKHH TCKDI TCKEC TCKR
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TABLE Electrical performance characteristics continued. Test Symbol Conditions -55°C +125°C unless otherwise specified Group subgroups Device type Limits Unit
SWITCHING CHARACTERISTICS Continued. Clock high time Clock time Set/Reset direct width (high) Set/Reset direct delay, from Master set/reset width (high low) Master set/reset delay from global set/reset TRPW TRIO TMRW TMRQ figures applicable
SWITCHING CHARACTERISTICS (RAM OPTION) Read operation, address read cycle time Read operation, address read cycle time Read operation data valid after address change write enable) Read operation data valid after address change write enable) Read during write, clocking data into flip flop address setup time before clock Read during write, clocking data into flip flop address setup time before clock Read during write, data valid after going active Read during write, (DIN stable before footnotes table. TRCT TILO figures applicable
TIHO
TICK
TIHCK
TWOT
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TABLE Electrical Performance Characteristics continued. Test Symbol Conditions -55°C +125°C unless otherwise specified Group subgroups Device type Limits Unit
SWITCHING CHARACTERISTICS (RAM OPTION) Continued. Read during write, data valid after Read during write, (DIN change during Read during write, clocking data into flip flop, setup time before clock Read during write, clocking data into flip flop, setup time before clock Read during write, clocking data into flip flop, data setup time before clock Read during write, clocking data into flip flop, data setup time before clock Write operation, address write cycle time Write operation, address write cycle time Write operation, write enable pulse width (high) Write operation, write enable pulse width (high) Write operation, address setup time before beginning Write operation, address setup time before beginning Write operation, address hold time after Write operation, address hold time after footnotes table. TDOT TWCK figures applicable
TWCKT
TDCK
TDCKT
TWCT TWPT
TAST
TAHT
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TABLE Electrical Performance Characteristics continued. Test Symbol Conditions -55°C +125°C unless otherwise specified Group subgroups Device type Limits Unit
SWITCHING CHARACTERISTICS (RAM OPTION) Continued. Write operation, setup time before Write operation, setup time before Write operation, hold time after figure applicable
TDST
TDHT
SWITCHING CHARACTERISTICS Input propagation delay, Input propagation delay, transparent latch (fast) Input propagation delay, transparent latch (with delay) Input propagation delay, clock (IK) (flip-flop) Input propagation delay, clock (IK) (latch enable) Setup time, clock (IK), fast Setup time, clock (IK), with delay Hold time, clock (IK), fast Hold time, clock (IK), with delay Output propagation delay clock (OK) pad, (fast) Output propagation delay clock (OK) pad, (slew rate limited) Output propagation delay output (fast) footnotes table. TPID TPLI figures applicable
TPDLI
12.2
TIKRI TIKLI TPICK TPICKD TIKPI TIKPID TOKPOF TOKPOS figures applicable figures applicable
11.3
11.5
TOPF
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TABLE Electrical Performance Characteristics continued. Test Symbol Conditions -55°C +125°C unless otherwise specified Group subgroups Device type Limits Unit
SWITCHING CHARACTERISTICS continued Output propagation delay output (slew rate limited) Output propagation delay 3state begin hi-Z (fast) Output propagation delay 3state active valid (fast) Output propagation delay 3state active valid (slew rate limited) Setup time, output clock (OK) Hold time, output clock (OK) Clock high time Global set/reset delay from through Global set/reset delay from Global set/reset width TOPS figures applicable
TTSHZF TTSONF
TTSONS
13.7
TOOK TOKO TCH/ TRRI TRPO TMRW
20.3
GUARANTEED INPUT OUTPUT PARAMETERS (Pin Pin, inputs) Global Clock Output (fast) using Global Clock Output (slewlimited) using Input setup time, using delay) Input hold time, using delay) Input setup time, using (with delay) Input hold time, using (with delay) footnotes table. TICKOF TICKO TPSUF TPHF TPSU Output Flip-Flop; Input Flip-Flop Latch
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TABLE Electrical Performance Characteristics continued. Test Symbol Conditions -55°C +125°C unless otherwise specified Group subgroups Device type Limits Unit
EDGE TRIGGERED (Synchronous) SWITCHING CHARACTERISTICS GUIDELINES Address write cycle time (clock period) Clock pulse width (active edge) TWCS TWCTS TWPS 16x2 32X1 16X2 TWPTS figure Address setup time before clock Address hold time after clock setup time before clock hold time after clock setup time before clock hold time after clock TASS TASTS TAHS TAHTS TDSS TDSTS TDHS TDHTS TWSS TWSTS TWHS TWHTS Data valid after clock TWOS TWOTS footnotes table. Size 32X1 16X2 32X1 16X2 32X1 16X2 32X1 16X2 32X1 16X2 32X1 16X2 32X1 16X2 32X1 10.3 11.6
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TABLE Electrical Performance Characteristics continued. Test Symbol Conditions -55°C +125°C unless otherwise specified Group subgroups Device type Limits Unit
EDGE TRIGGERED (Synchronous) DUAL-PORT SWITCHING CHARACTERISTICS GUIDELINES Address write cycle time (clock period) Clock pulse width (active edge) Address setup time before clock Address hold time after clock setup time before clock hold time after clock setup time before clock hold time after clock Data valid after clock TWCDS TWPDS Size 16X1 16X1 16X1 16X1 16X1 16X1 16X1 16X1 16X1
TASDS TAHDS TDSDS TDHDS TWSDS TWHDS TWODS
figure
With percent outputs simultaneously sinking maximum pins. With output current loads, active input long line pull-resistors, package pins GND, configured with MakeBits "tie" option. These delays specified from decoder input decoder output. pad-to-pad delays, input delay (TPID) output delay (TOPF TOPS). Parameter tested guaranteed characterization data which taken initial device introduction, prior introduction significant changes. Parameter directly tested. Devices first percent functionally tested. Benchmark patterns (tB1 tB13) then used determine compliance this parameter. Characterization data taken initial device introduction, after design process changes, which affect this parameter. Benchmark patterns (tB1 tB13) used determine compliance this parameter. Timing option identical timing. Values indicated guaranteed characterization data application note, provided manufacturer, followed. application note followed, indicated values typical only. Timing measured threshold, with external capacitive loads including test fixture. Slew rate limited output rise/fall times approximately times longer than fast output rise/fall times. maximum total external capacitive load simultaneous fast mode switching same direction power/ground pair. slew-rate limited outputs this total times larger. Exceeding this maximum capacitive load result ground bounce greater than amplitude, less than duration, which might cause problems when drives clocks other asynchronous signals. Voltage levels unused (bonded unbonded) pads must valid logic levels. Each configured with internal pull-up pull-down resistor alternatively configured driven output driven from external source. Input setup times hold times specified with respect internal clock (IK). calculate system setup time, subtract clock delay (clock from specified input setup time value, subtract below zero. "Negative" hold time means that delay input data adequate external system hold time zero, provided input clock uses global signal distribution from Timing option identical timing. Applicable read timing specifications identical level sensitive read timing.
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Case
NOTE: Package marking non-lid side, therefore, goes clockwise when device mounted with down position. package just like this package except marking traditional side when mounted with goes counter clockwise. FIGURE Case outline.
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Case
Inches .001 .002 .005 .006 .008 .009 .014 .0175 .020 .021 .035 .040 .043 .090 .115 .910 1.350 1.510 1.720 2.300 2.500
0.02 0.05 0.13 0.15 0.20 0.23 0.36 0.44 0.51 0.53 0.89 1.02 1.09 2.29 2.92 23.11 34.29 38.35 43.69 58.42 63.50
NOTE: government preferred system measurement metric system. However, this item originally designed using inch-pound units measurement. event conflict between metric inch-pound units, inch-pound units shall take precedence.
FIGURE Case outline.
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Case outline
Device type Terminal number
Terminal symbol (TD1) SGCK1 (A15, I/O) (TCK) (TMS) SGCK2 (I/O) PGCK2 (I/O)
Device type Terminal number
Terminal symbol (A14) PGCK1 (A16, I/O) (A17) (A13) (HDC) (LDC) (A12)
Device type Terminal number
Terminal symbol (A10) (A11) (A9) (A8) INIT (A6) (A7)
CONNECT
FIGURE Terminal connections.
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Case outline Continued.
Device type Terminal number
Terminal symbol (A5) (A4) (A3)
Device type Terminal number
Terminal symbol (CS1, (A0, SGCK4 (I/O)-DOUT (D3) (D7) SGCK3 (I/O) PGCK4 (I/O, (D0, DIN)
Device type Terminal number (D4) (D5) PGCK3 (I/O) DONE CCLK
Terminal symbol
RCLK BUSY /RDY) (D1) (D2) (D6) PROG
CONNECT
FIGURE Terminal connections Continued.
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Case outline
Device type Terminal number
Terminal symbol PGCK1 (A16, I/O) (A17) (TDI) (TCK) (TMS)
Device type Terminal number
Terminal symbol SGCK2 (I/O) PGCK2 (I/O) (HDC) (LDC)
Device type Terminal number
Terminal symbol INIT SGCK3 (I/O) DONE PROG (D7) PGCK3 (I/O) (D6)
CONNECT
FIGURE Terminal connections Continued.
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Case outline Continued.
Device type Terminal number
Terminal symbol (D5) (D4) (D3) (D2)
Device type Terminal number (D1)
Terminal symbol
Device type Terminal number
Terminal symbol (A7) (A8) (A9) (A10) (A11) (A12) (A13) (A14) SGCK1 (A15, I/O)
RCLK BUSY /RDY) (D0, DIN) SGCK4 (I/O)-DOUT CCLK (A0, PGCK4 (I/O, (CS1, (A3) (A4) (A5) (A6)
CONNECT
FIGURE Terminal connections Continued.
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BLOCK
FIGURE Logic block diagrams.
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Simplified block diagram
(RAM Carry logic functions shown)
FIGURE Logic block diagrams Continued.
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CONFIGURABLE LOGIC BLOCK (CLB)
FIGURE Logic block diagrams Continued.
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Detail dedicated carry logic
FIGURE Logic block diagrams Continued.
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edge-triggered single port
edge-triggered single-port addresses identical) FIGURE Logic block diagrams Continued.
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edge-triggered dual-port
FIGURE Logic block diagrams Continued.
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FIGURE Logic block diagrams Continued.
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BOUNDARY SCAN LOGIC
FIGURE Logic block diagrams Continued.
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CONFIGURABLE LOGIC BLOCK (CLB) SWITCHING CHARACTERISTICS
FIGURE Timing diagrams switching characteristics
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FIGURE Timing diagrams switching characteristics Continued.
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SYNCHRONOUS
SYNCHRONOUS DUAL PORT
FIGURE Timing diagrams switching characteristics Continued.
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FIGURE Load circuit.
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Qualification inspection device classes Qualification inspection device classes shall accordance with MIL-PRF-38535. Inspections performed shall those specified MIL-PRF-38535 herein groups inspections (see 4.4.1 through 4.4.4). Conformance inspection. Technology conformance inspection classes shall accordance with MIL-PRF-38535 including groups inspections specified herein. Quality conformance inspection device class shall accordance with MIL-PRF-38535, appendix specified herein. Inspections performed device class shall those specified method 5005 MIL-STD-883 herein groups inspections (see 4.4.1 through 4.4.4). 4.4.1 Group inspection. Tests shall specified table herein. Subgroups table method 5005 MIL-STD-883 shall omitted. device class subgroups tests shall include verifying functionality device. device classes subgroups shall include verifying functionality device. (latch-up) tests shall measured only initial qualification after design process changes which affect performance device. device class procedures circuits shall maintained under document revision level control manufacturer shall made available preparing activity acquiring activity upon request. device classes procedures circuits shall under control device manufacturer's accordance with MIL-PRF-38535 shall made available preparing activity acquiring activity upon request. Testing shall pins, five devices with zero failures. Latch-up test shall considered destructive. Information contained JESD used reference. Subgroup (CIN COUT measurements) shall measured only initial qualification after process design changes which affect input capacitance. Capacitance shall measured between designated terminal frequency MHz. Sample size devices with failures, input terminals tested.
4.4.2 Group inspection. group inspection end-point electrical parameters shall specified table herein. 4.4.2.1 Additional criteria device class Steady-state life test conditions, method 1005 MIL-STD-883: Test condition test circuit shall maintained manufacturer under document revision level control shall made available preparing acquiring activity upon request. test circuit shall specify inputs, outputs, biases, power dissipation, applicable, accordance with intent specified test method 1005 MIL-STD-883. +125°C, minimum. Test duration: 1,000 hours, except permitted method 1005 MIL-STD-883.
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TABLE IIA. Electrical test requirements. Line Test requirements Subgroups accordance with MIL-STD-883, 5005, table Device class Interim electrical parameters (see 4.2) Static burn-in (method 1015) Same line Dynamic burn-in (method 1015) Final electrical parameters (see 4.2) Group test requirements (see 4.4) Group end-point electrical parameters (see 4.4) Group end-point electrical parameters (see 4.4) Group end-point electrical parameters (see 4.4) Required 3,7*, 8A,8B,9,10,11 4**, Required 4**, Required Subgroups accordance with MIL-PRF-38535, table III)
Device class
Device class
Required
Required Required 4**,
Blank spaces indicate tests applicable. subgroups combined when using high-speed testers. Subgroups functional tests shall verify functionality device. indicates applies subgroup 4.4.1e. indicates delta limit (see table IIB) shall required where specified, delta values shall computed with reference previous interim electrical parameters (see line 4.4.1d.
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TABLE IIB. Delta limits +25°C. Parameter Device types ICCO standby specified limit table specified limit table
above parameter shall recorded before after required burn-in life tests determine delta. 4.4.2.2 Additional criteria device classes steady-state life test duration, test condition test temperature, approved alternatives shall specified device manufacturer's plan accordance with MIL-PRF-38535. test circuit shall maintained under document revision level control device manufacturer's accordance with MIL-PRF-38535 shall made available acquiring preparing activity upon request. test circuit shall specify inputs, outputs, biases, power dissipation, applicable, accordance with intent specified test method 1005 MIL-STD-883. 4.4.3 Group inspection. group inspection end-point electrical parameters shall specified table herein. 4.4.4 Group inspection. Group inspection required only parts intended marked radiation hardness assured (see herein). End-point electrical parameters shall specified table herein. device classes devices test vehicle shall subjected radiation hardness assured tests specified MIL-PRF-38535 level being tested. device class devices shall subjected radiation hardness assured tests specified MIL-PRF-38535, appendix level being tested. device classes must meet postirradiation end-point electrical parameter limits defined table +25°C ±5°C, after exposure, subgroups specified table herein. When specified purchase order contract, copy delta limits shall supplied.
Delta measurements device classes Delta measurements, specified table IIA, shall made recorded before after required burn-in screens steady-state life tests determine delta compliance. electrical parameters measured, with associated delta limits listed table IIB. device manufacturer may, option, either perform delta measurements within hours after burn-in perform final electrical parameter tests, subgroups Programming procedures. programming procedures shall specified device manufacturer shall made available upon request. PACKAGING Packaging requirements. requirements packaging shall accordance with MIL-PRF-38535 device classes MIL-PRF-38535, appendix device class
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NOTES Intended use. Microcircuits conforming this drawing intended Government microcircuit applications (original equipment), design applications, logistics purposes. 6.1.1 Replaceability. Microcircuits covered this drawing will replace same generic device covered contractor prepared specification drawing. 6.1.2 Substitutability. Device class devices will replace device class devices. Configuration control SMD's. proposed changes existing SMD's will coordinated with users record individual documents. This coordination will accomplished using Form 1692, Engineering Change Proposal. Record users. Military industrial users should inform Defense Supply Center Columbus when system application requires configuration control which SMD's applicable that system. DSCC will maintain record users this list will used coordination distribution changes drawings. Users drawings covering microelectronic devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0544. Comments. Comments this drawing should directed DSCC-VA Columbus, Ohio 43216-5000, telephone (614) 692-0547. Abbreviations, symbols, definitions. abbreviations, symbols, definitions used herein defined MIL-PRF-38535 MIL-HDBK-1331. CCLK DONE PROGRAM RCLK INIT PGCK1-PGCK4 RDY/BUSY A0-A17 D0-D7 DOUT +5.0 SUPPLY VOLTAGE GROUND CONFIGURATION CLOCK DONE PROGRAM READ CLOCK MODE MODE MODE TEST DATA OUTPUT TEST DATA TEST CLOCK TEST MODE SELECT HIGH DURING CONFIGURATION DURING CONFIGURATION INIT PRIMARY GLOBAL INPUTS During peripheral parallel mode configuration, this indicates when chip ready another byte data written into After configuration complete, this becomes user programmed pin. CHIP SELECT, WRITE CHIP SELECT, WRITE WRITE STROBE READ STROBE ADDRESS DATA DATA INPUT DATA OUTPUT INPUT/OUTPUT
6.5.1 Timing limits. table timing values shows either minimum maximum limit each parameter. Input requirements specified from external system point view. Thus, address setup time shown minimum since system must supply least that much time (even though most devices require it). other hand, responses from memory specified from device point view. Thus, access time shown maximum since device never provides data later than that time.
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6.5.2 Waveforms. Waveform symbol Input MUST VALID CHANGE FROM CHANGE FROM DON'T CARE CHANGE PERMITTED Output WILL VALID WILL CHANGE FROM WILL CHANGE FROM CHANGING STATE UNKNOWN HIGH IMPEDANCE Sources supply. 6.6.1 Sources supply device classes Sources supply device classes listed QML-38535. vendors listed QML-38535 have submitted certificate compliance (see herein) DSCC-VA have agreed this drawing. 6.6.2 Approved sources supply device class Approved sources supply class listed MIL-HDBK-103. vendors listed MIL-HDBK-103 have agreed this drawing certificate compliance (see herein) been submitted accepted DSCC-VA. BUFFER SWITCHING CHARACTERISTICS Test Symbol Conditions -55°C +125°C unless otherwise specified note. Group subgroups Device type Limits
Unit
TBUF driving horizontal Longline (L.L.) L.L. while low(buffer active) TBUF driving horizontal Longline (L.L.) goinglow L.L. going from resistive pull high active low, (TBUF configured open drain going L.L. active valid L.L. inactive going high L.L. (inactive) with single pull-up resistor going high L.L. (inactive) with pair pull-up resistor
TIO1
TIO2
10.5
TOFF TPUS TPUF
13.5
NOTE: These values typical. They tested, characterized, guaranteed derived from benchmark timing patterns.
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STANDARD MICROCIRCUIT DRAWING BULLETIN DATE: 02-05-10 Approved sources supply 5962-97523 listed below immediate acquisition information only shall added MIL-HDBK-103 QML-38535 during next revision. MIL-HDBK-103 QML-38535 will revised include addition deletion sources. vendors listed below have agreed this drawing certificate compliance been submitted accepted DSCC-VA. This bulletin superseded next dated revision MIL-HDBK-103 QML-38535.
Standard microcircuit drawing 5962-9752301QXC 5962-9752301QYC 5962-9752301QZC
Vendor CAGE number 68994 68994 68994
Vendor similar XC4010E-4PG191B XC4010E-4CB196B XC4010E-4CB196B
lead finish shown each representing hermetic package most readily available from manufacturer listed that part. desired lead finish listed contact vendor determine availability. Caution. this number item acquisition. Items acquired this number satisfy performance requirements this drawing.
Vendor CAGE number 68994
Vendor name address Xilinx, Incorporated 2100 Logic Drive Jose, 95124
information contained herein disseminated convenience only Government assumes liability whatsoever inaccuracies information bulletin.
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