393,216-Word 32-Bit 4-Bank FIFO-SGRAM FEDS82V48540-01 Issue

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393,216-Word 32-Bit 4-Bank FIFO-SGRAM FEDS82V48540-01 Issue

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Semiconductor MS82V48540
393,216-Word 32-Bit 4-Bank FIFO-SGRAM
FEDS82V48540-01
Issue Date:Nov. 2002
GENERAL DESCRIPTION
MS82V48540 48-Mbit system clock synchronous dynamic random access memory. addition conventional random read/write access function, MS82V48540 provides automatic address increment function automatic bank switching function. Therefore, once column addresses set, continuous serial accesses possible while banks automatically switched till input Precharge command. MS82V48540 ideal digital camera buffer memory applications.
FEATURES
393,216 words bits banks memory (1,536 rows columns bits banks) Single ±0.3 power supply LVTTL compatible inputs outputs Programmable burst length full page) Programmable latency Automatic address increment function automatic bank switching function Power Down operation Clock Suspend operation 3,072 refresh cycles/64 Auto refresh self refresh capability Package: 86-pin plastic TSOP (II) (TSOPII86-P-400-0.50-K) (Product MS82V48540-xTA) indicates speed rank.
PRODUCT FAMILY
Family MS82V48540-7 MS82V48540-8 Max. Operating Frequency Access Time Package 86-pin Plastic TSOP (II) (400 mil)
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MS82V48540
CONFIGURATION (TOP VIEW)
VCCQ VSSQ VCCQ VSSQ DQM0 A10/AP DQM2 DQ16 VSSQ DQ17 DQ18 VCCQ DQ19 DQ20 VSSQ DQ21 DQ22 VCCQ DQ23
DQ15 VSSQ DQ14 DQ13 VCCQ DQ12 DQ11 VSSQ DQ10 VCCQ DQM1 DQM3 DQ31 VCCQ DQ30 DQ29 VSSQ DQ28 DQ27 VCCQ DQ26 DQ25 VSSQ DQ24
86-Pin Plastic TSOP (II) (Type
Name BA0, Function Address Inputs Column Address Inputs Bank Address System Clock Input Clock Enable Chip Select Address Strobe Column Address Strobe Name DQM0 DQM3 DQ31 VCCQ VSSQ Function Write Enable Mask Enable Data Inputs/outputs Supply Voltage Ground Supply Voltage Ground Connection
Note: same power supply voltage must provided every VCCQ pin. same voltage level must provided every VSSQ pin.
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MS82V48540
BLOCK DIAGRAM
DQM0 DQM3
Timing Register
Controller
Bank Controller
BA0,
Internal Column Address Counter
BA0,
Column
Address Buffers
Internal Address Counter
Column Decoders Sense Amplifiers
Decoders
Input Data Register
Input Buffers
Word Drivers
12Mb Memory Cells Bank Bank Bank Bank
Read Data Register
Address Buffers
Output Buffers
DQ31
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DESCRIPTION
Fetches inputs edge. Disables enables device operation asserting deactivating inputs except CLK, CKE, DQM0, DQM1, DQM2 DQM3. Masks system clock deactivate subsequent operation. deactivated, system clock will masked that subsequent operation deactivated. should asserted least cycle prior command. column multiplexed. address: RA10 Column address: Selects bank activated during address latch time selects bank precharge read/write during column address latch time. "L", "L": Bank "H", "L": Bank "L", "H": Bank "H", "H": Bank Functionality depends combination. details, function truth table. Masks read data clocks later when DQM0 DQM3 edge clock signal. Masks write data same clock when DQM0 DQM3 edge clock signal. DQM0 controls DQ7, DQM1 controls DQ15, DQM2 controls DQ16 DQ23, DQM3 controls DQ24 DQ31. Data inputs/outputs multiplexed same pin.
Address
BA0,
DQM0 DQM3
DQ31
*Notes: When "High" clock transition from "Low" "High", inputs except CLK, CKE, DQM0, DQM1, DQM2, DQM3 invalid. When issuing active, read write command, bank selected BA1.
Active, read write Bank Bank Bank Bank
auto precharge function enabled disabled A10/AP input when read write command issued.
A10/AP Operation After burst, bank holds active status. After burst, bank precharged automatically. After burst, bank holds active status. After burst, bank precharged automatically. After burst, bank holds active status. After burst, bank precharged automatically. After burst, bank holds active status. After burst, bank precharged automatically.
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When issuing precharge command, bank precharged selected A10/AP, inputs.
A10/AP Operation Bank precharged. Bank precharged. Bank precharged. Bank precharged. banks precharged.
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COMMAND OPERATION
Mode Register Command (CS, RAS, CAS, "Low") MS82V48540 mode register that defines operation mode "CAS Latency, Burst Length, Burst Sequence". Mode Register command should executed just after MS82V48540 powered Before entering this command, banks must precharged. Next command issued after tRSC. Auto Refresh Command (CS, RAS, "Low", "High") Auto Refresh command performs refresh automatically address counter. refresh operation must performed 3,072 times within next command issued after from last Auto Refresh command. Before entering this command, banks must precharged. Self Refresh Entry/Exit Command (CS, RAS, CAS, "Low", "High") self refresh operation continues after Self Refresh Entry command entered, with level left "low". This operation terminates making level "high". self refresh operation performed automatically internal address counter MS82V48540 chip. self refresh mode, external refresh control required. Before entering self refresh mode, banks must precharged. Next command issued after tRC. Single Bank Precharge Command (CS, RAS, A10/AP "Low", "High") Single Bank Precharge command triggers bank precharge operation. Precharge bank selected BA1. Banks Precharge Command (CS, RAS, "Low", CAS, A10/AP "High") Bank Precharge command triggers precharge banks. this command executed during special bank active mode, special bank active mode terminated. Bank Active Command (CS, "Low", CAS, "High") Bank Active command activates bank selected BA1. Bank Active command corresponds conventional DRAM's falling operation. addresses A10, BA1" strobed. Write Command (CS, CAS, A10/AP "Low", "High") Write command required begin burst write operation. Then burst access initial column address strobed. Write with Auto Precharge Command (CS, CAS, "Low", RAS, A10/AP "High") Write with Auto Precharge command required begin burst write operation with automatic precharge after burst write. command that interrupts this operation cannot issued. Read Command (CS, CAS, A10/AP "Low", RAS, "High") Read command required begin burst read operation. Then burst access initial column address strobed.
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Read with Auto Prechaege Command (CS, "Low", RAS, A10/AP "High") Read with Auto Precharge command required begin burst read operation with auto precharge after burst read. command that interrupts this operation cannot issued. Operation Command "Low", RAS, CAS, "High") Operation command does trigger operation. Device Deselect Command "High") Device Deselect command disables RAS, CAS, Address input. This command does trigger operation. Data Write/Output Enable Command (DQMi "Low") Data Write/Output Enable command enables DQ31 read write. each DQM0, corresponds DQ7, DQ15, DQ16 DQ23 DQ24 DQ31 respectively. Data Mask/Output Disable Command (DQMi "High") Data Mask/Output Disable command disables DQ31 read write. read cycle output buffers disabled after clocks write cycle input buffers disabled same clock. each DQM0, corresponds DQ7, DQ15, DQ16 DQ23 DQ24 DQ31 respectively. Burst Stop Command (CS, "Low", RAS, "High") Burst Stop command stops burst access. After Burst Stop command entered, output buffer goes into high impedance state.
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SPECIAL READ/WRITE OPERATION
special read write operation activated executing Read Write command after selecting special page mode with Mode Register command. automatic bank switching automatic address increment operations activated executing Bank Active command during Special Page mode, serial access starts from address fetched with Read Write command. burst operation starts from start address toward column. When last column address reached, bank automatically switched address also automatically incremented serial access continues from start column address. automatic bank switching automatic address increment operations continue until Bank Precharge command executed each time last column address reached. Since bank switching address increment automatically made during special read write operation, address proceeds shown following figure.
1535
Bank "H",
1535
Bank "H",
Operation ended input Bank Precharge command.
3073 3075 3077 3079 6143 3174 3076 3078 3080 6144
1535
Bank "L",
1535
Bank "L",
Start address Column
3071
3072
Note) circled numbers indicate orders address increment.
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TRUTH TABLE
Command Truth Table
Function Device Deselect Operation Mode Register Auto Refresh Bank Activate Read Read with Auto Precharge Write Write with Auto Precharge Precharge Select Bank Precharge Banks Burst Stop Address BA0, A10/AP CODE
Truth Table
Function Data Write/Output Enable Data Mask/Output Disable DQMi
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Function Truth Table (1/3)
Note Current State Idle Active (ACT) Active (Special Page Mode) (SACT) Read (RD) Write (WT) Address A10: A10: ILLEGAL ILLEGAL Active Auto Refresh/Self refresh Read Write ILLEGAL Precharge ILLEGAL Serial Read Serial Write ILLEGAL ILLEGAL Precharge ILLEGAL (Continue Active after Burst ends) (Continue Active after Burst ends) Burst Stop Active Term Burst, Read Term Burst, start Write ILLEGAL Term Burst, execute Precharge ILLEGAL (Continue Active after Burst ends) (Continue Active after Burst ends) Burst Stop Active Term Burst, start Read Term Burst, Write ILLEGAL Term Burst, execute Precharge ILLEGAL Action Note
Op-Code Mode Register Write
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Function Truth Table (2/3)
Note Current State Read with Auto Precharge (RAP) Write with Auto Precharge (WAP) Read (Special Page Mode) (SRD) Write (Special Page Mode) (SWT) Precharging (PRE) Address A10: A10: A10: A10: Action (Continue Burst enter Precharge) (Continue Burst enter Precharge) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL (Continue Burst enter Precharge) (Continue Burst enter Precharge) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL (Continue serial read) (Continue serial read) ILLEGAL ILLEGAL ILLEGAL ILLEGAL Precharging ILLEGAL (Continue serial write) (Continue serial write) ILLEGAL ILLEGAL ILLEGAL ILLEGAL Precharging ILLEGAL Idle after Idle after ILLEGAL ILLEGAL ILLEGAL ILLEGAL Note
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Function Truth Table (3/3)
Note Current State Refreshing (REF) Address Action Idle after Idle after ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Note
ABBREVIATIONS Bank Address Operation command
Address
Column Address
Notes: inputs enabled when high least cycle prior inputs. Illegal bank specified state, legal some cases depending state bank selection. avoid contention, satisfy tCCD tDPL. bank precharging idle state. Precharges activated bank A10/AP. Illegal bank idle.
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Function Truth Table
Current State Self Refresh (SREF) CKEn-1 CKEn Power Down (PD) Banks Idle (ABI) State Other than Listed Above Address INVALID Exit Self Refresh Exit Self Refresh ILLEGAL ILLEGAL ILLEGAL (Maintain Self Refresh) INVALID Exit Self Refresh Exit Self Refresh ILLEGAL ILLEGAL ILLEGAL (Continue power down mode) Refer Truth Table Enter Power Down Enter Power Down ILLEGAL ILLEGAL ILLEGAL Enter Self Refresh ILLEGAL Refer Truth Table Begin Clock Suspend Next Cycle Enable Clock Next Cycle Continue Clock Suspension Action Note
Note:
Power-down self refresh entered only when banks idle state.
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Mode Address Keys
Operation Code Mode Setting Vender Only
*Note
Latency Reserved Reserved Reserved Reserved Reserved Reserved
Burst Type Sequential Interleave
Burst Length Reserved Reserved Special page Full Page Reserved Reserved Reserved Reserved Reserved Reserved
Write Burst Length Length Burst
Single
*Note select Special Page mode, "L". write burst length during Special Page mode only Burst. POWER SEQUENCE With "H", other inputs state, turn power supply start system clock. After voltage reached specified level, pause more with input kept state. Issue precharge bank command. Apply Auto-refresh more times. Enter mode register command.
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Burst Length Sequence
Starting Address (column address binary) Sequential Type Interleave Type supported supported
Starting Address (column address binary) Sequential Type Interleave Type
Starting Address (column address binary) Sequential Type Interleave Type
Special, Full Sequential only
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READ/WRITE COMMAND INTERVAL
Read Read Command Interval
RD-A RD-B Hi-Z
1cycle
Write Write Command Interval
WT-A WT-B Hi-Z
1cycle
Write Read Command Interval
WT-A RD-B Hi-Z
WT-A RD-B Hi-Z
1cycle
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Read Write Command Interval
RD-A WT-B
Hi-Z
1cycle
RD-A WT-B
Hi-Z
RD-A
Hi-Z necessary WT-B
Hi-Z
Hi-Z necessary
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BURST TERMINATION
Burst Read Termination Precharging READ Cycle
Full Hi-Z Hi-Z
Burst Read Termination Precharging WRITE Cycle
Full Hi-Z Hi-Z
Note: data will written
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Read Burst Stop Command
Full Hi-Z
Hi-Z
Write Burst Stop Command
Full Hi-Z
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AUTO PRECHARGE
Read with Auto Precharge
Auto precharge starts Hi-Z
Auto precharge starts Hi-Z
(tRAS satisfied)
Write with Auto Precharge
Auto precharge starts Hi-Z
Auto precharge starts
Hi-Z
(tRAS satisfied)
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ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter Voltage Power Supply Relative Voltage Input Relative Short Circuit Output Current Power Dissipation Operating Temperature Storage Temperature Symbol VIN, VOUT Topr Tstg Rating -0.5 -0.5 Unit
Recommended Operating Conditions
70°C) Parameter Power Supply Voltage Input High Voltage Input Voltage Symbol Min. -0.3 Typ. Max. Unit
Capacitance
(VCC ±0.3 25°C, MHz) Parameter Input Capacitance A10, BA0, BA1) Input Capacitance (CLK, CKE, RAS, CAS, DQM3) Output Capacitance (DQ0 DQ31) Symbol CIN1 CIN2 COUT Min. Max. Unit
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Characteristics
Parameter Output High Voltage Output Voltage Input Leakage Current Output Leakage Current Operating Current Bank) Precharge Standby Current Power Down Mode Symbol ICC1 ICC2P ICC2PS ICC2N Test Condition Other IOH= -2.0 IOL= MS82V48540-7 MS82V48540-8 Min. Max. Min. Max. Unit Note
min. min. Burst min. min. min.
Precharge Standby Current Power Down Mode
ICC2NS ICC3P ICC3PS ICC3N
Active Standby Current Power Down Mode
min.
Active Standby Current Power Down Mode Operating Current (Burst Mode) Refresh Current Self Refresh Current
ICC3NS ICC4 ICC5 ICC6
min. min. 0.2V
Notes maximum value power supply current obtained with output open. Address data changed only time during cycle.
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Characteristics Test conditions measurements assume Reference level measuring timing input signals Transition times measured between VIL. longer than reference level measuring timing input signals (MIN.) (MAX). access time measured Input levels testing V/0.4
tSetup tHold Input Output
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Synchronous Characteristics
Parameter Clock Cycle Time Access Time from High Level Width Level Width Data-out Hold Time Data-out Low-impedance Time Data-out High-impedance Time Data-in Setup Time Data-in Hold Time Address Setup Time Address Hold Time Setup Time Hold Time Command (CS, RAS, CAS, DQM) Setup Time Command (CS, RAS, CAS, DQM) Hold Time Latency Latency Latency Latency Symbol tCK3 tCK2 tAC3 tAC2 tCKS tCKH tCMS tCMH MS82V48540-7 Min. Max. MS82V48540-8 Min. Max. Unit Note
Note Output load.
Output
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Asynchronous Characteristics
Parameter REF/ACT/SACT Command Period Command Period SACT Command Period Command Period PRE-ALL (Special Page) SACT Command Period Delay Time ACT/SACT READ/WRITE Command Command Period READ/WRITE READ/WRITE Command Period Data-in Command Period Data Output WRITE Command Input Time Mode Register Cycle Time Transition Time Refresh Time Symbol tRAS tRASS tRPS tRCD tRRD tCCD tDPL tOWD tRSC tREF MS82V48540-7 Min. Max. 120k MS82V48540-8 Min. Max. 120k Unit Note
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TIMING WAVEFORM
READ/WRITE CYCLE
tCKH
tCKS
tCMS tCMH
Hi-Z
tRCD
tCMS
tCMH
DAb1 DAb2
QAa1 QAa2
tOWD tRAS
tDPL
ACT-A RD-A WT-A PRE-A ACT-D
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Special READ CYCLE Special Page,
Hi-Z
QAa1 QAa2 QAa3 QAa4
Qn-1
tRCD
Qn+1 Qn+2
tRASS SRD-A Special Read Start PRE-ALL
tRPS SACT-D
SACT-A
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Special WRITE CYCLE Special Page,
Hi-Z
DAa1 DAa2 DAa3 DAa4 DAa5
Dn-2 Dn-1
tRCD
tRASS SWT-A Special Write Start
tDPL
tRPS SACT-B
SACT-A
PRE-ALL
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Mode Register
Hi-Z
PRE-ALL
tRSC
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Auto Reflesh
Hi-Z
PRE-ALL
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Self Reflesh (Entry Exit)
Hi-Z
PRE-ALL
SELF Entry
SELF Exit
SELF Entry
SELF Exit
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Burst Termination Precharging
Hi-Z
DAa1 DAa2
QAb1 QAb2 QAb3 QAb4
ACT-A
WT-A
PRE-A
ACT-A
RD-A
PRE-A Command Termination
Command Termination
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Auto Precharging
Hi-Z
QAa1 QAa2 QAa3 QAa4 DBa1 DBa2 DBa3 DBa4
ACT-A
RAP-A
ACT-B AP-A
WAP-B AP-B
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Power Down Mode Clock Suspension
tCKS Hi-Z
QAa1 QAa2
QAa3
QAa4
ACT-A Entry
RD-A Exit
PRE-A Clock Mask Start Clock Mask Entry Exit
ACTIVE STANDBY
PRECHARGE STANDBY
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CLOCK Suspend Exit Power Down Exit
Clock Suspend Active Power Down) Exit Power Down Precharge Power Down) Exit
Internal Command
Note
tCKS
Note
Internal Command
tCKS
Note
Notes: Active power down: both bank active state. Precharge power down: both bank precharge state. should issued. command issued after Clock.
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Byte Read/Write Operation DQM)
DQM0 DQM1 DQM2 DQM3
QBa1 QBa1 QBa2 QBa3 DBb2 DBb3 DBb4
QBa2 QBa3 QBa4
DBb1
DBb3 DBb4
QBa3 QBa4
DBb1 DBb2
DBb4
QBa1 QBa2
QBa4
DBb1 DBb2 DBb3
ACT-B
RD-B
WT-B Byte Byte Byte Byte DQ8-15 DQ24-31 DQ0-7 DQ16-23 Read Read Write Write Byte Byte Byte Byte DQ16-23 DQ0-7 DQ8-15 DQ24-31 Read Read Write Write
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Burst Read Single Write
Hi-Z
QAa1 QAa2 QAa3 QAa4
ACT-B
RD-B
Single WT-B
Single WT-B
PRE-B
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Random Column Read (Continuous Read Same Bank)
QAa1 QAa2 QAa3 QAa4 QAb1 QAb2 QAc1 QAc2 QAc3 QAc4
ACT-A
RD-A
RD-A
RD-A
PRE-A
ACT-A
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Random Column Write (Continuous Write Same Bank)
DBa1 DBa2 DBa3 DBa4 DBb1 DBb2 DBc1 DBc2 DBc3 DBc4
ACT-B
WT-B
WT-B
WT-B
PRE-B
ACT-B
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Interleaved Column Read
QAa1 QAa2 QAa3 QAa4 QBa1 QBa2 QBb1 QBc2 QAb1 QAb2 QAb3 QAb4
ACT-A
RD-A ACT-B tRCD tRRD
RD-B
RD-B
RD-A
PRE-B
PRE-A
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Interleaved Column Write
DCa1 DCa2 DCa3 DCa4 DDa1 DDa2 DDb1 DDb2 DCb1 DCb2 DCb3 DCb4
ACT-C
WT-C ACT-D tRCD tRRD
WT-D
WT-D
WT-C
PRE-D
PRE-C
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PACKAGE DIMENSIONS
(Unit:
TSOP(2)86-P-400-0.50-K
Mirror finish
Notes Mounting Surface Mount Type Package
Package material Lead frame material treatment Package weight Rev. No./Last Revised
Epoxy resin alloy Solder plating (5µm) 0.53 TYP. 1/Jul. 1998
surface mount type packages very susceptible heat reflow mounting humidity absorbed storage. Therefore, before perform reflow mounting, contact Oki's responsible sales person product name, package name, number, package code desired mounting conditions (reflow method, temperature times).
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REVISION HISTORY
Document Date Page Previous Current Edition Edition
First edition Changed speed rank indication "Package" FEATURES Section from "x". Changed device names Family column table PRODUCT FAMILY Section. FEDS82V48540-01 Nov. 2002 Changed names family devices table Characteristics Section. Changed names family devices table Synchronous Characteristics Section. Changed names family devices table Asynchronous Characteristics Section.
Description
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NOTICE information contained herein change without notice owing product and/or technical improvements. Before using product, please make sure that information being referred up-to-date. outline action examples application circuits described herein have been chosen explanation standard action performance product. When planning product, please ensure that external conditions reflected actual circuit, assembly, program designs. When designing your product, please product below specified maximum ratings within specified operating ranges including, limited operating voltage, power dissipation, operating temperature. assumes responsibility liability whatsoever failure unusual unexpected operation resulting from misuse, neglect, improper installation, repair, alteration accident, improper handling, unusual physical electrical stress including, limited exposure parameters beyond specified maximum ratings operation outside specified operating range. Neither indemnity against license third party's industrial intellectual property right, etc. granted connection with product and/or information drawings contained herein. responsibility assumed infringement third party's right which result from thereof. products listed this document intended general electronics equipment commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products authorized system application that requires special enhanced quality reliability characteristics system application where failure such system application result loss damage property, death injury humans. Such applications include, limited traffic automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, life-support systems. Certain products this document need government approval before they exported particular countries. purchaser assumes responsibility determining legality export these products will take appropriate necessary steps their expense these. part contents contained herein reprinted reproduced without prior permission. Copyright 2002 Electric Industry Co., Ltd.
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393,216-Word 32-Bit 4-Bank FIFO-SGRAM FEDS82V48540-01 Issue

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