4-Bank 1,048,576-Word 16-Bit SYNCHRONOUS DYNAMIC FEDD56V62160E-01
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Semiconductor MD56V62160E
4-Bank 1,048,576-Word 16-Bit SYNCHRONOUS DYNAMIC
FEDD56V62160E-01
Issue Date: Feb. 2002
DESCRIPTION MD56V62160E 4-Bank 1,048,576-word 16-bit Synchronous dynamic fabricated Oki's silicon-gate CMOS technology. device operates inputs outputs LVTTL compatible. FEATURES
Silicon gate, quadruple polysilicon CMOS, 1-transistor memory cell 4-Bank 1,048,576-word 16-bit configuration Single power supply, ±0.3 tolerance Input LVTTL compatible Output LVTTL compatible Refresh 4096 cycles/64 Programmable data transfer mode
Latency Burst Length Full Page) Data scramble (sequential, interleave) auto-refresh, Self-refresh capability
Packages:
54-pin plastic TSOP (TypeII) MD56V62160E-xxTA) indicates speed rank. PRODUCT FAMILY
Family
Max. Frequency
Access Time (Max.) tAC2 tAC3
MD56V62160E-7 MD56V62160E-10
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FEDD56V62160E-01
Semiconductor
MD56V62160E
CONFIGURATION (TOP VIEW)
VCCQ VSSQ VCCQ VSSQ LDQM DQ16 VSSQ DQ15 DQ14 VCCQ DQ13 DQ12 VSSQ DQ11 DQ10 VCCQ UDQM
54-Pin Plastic TSOP(II) Type) Name A0-A10 Function System Clock Chip Select Clock Enable Address Bank Select Address Address Strobe Column Address Strobe Write Enable Name UDQM, LDQM VCCQ VSSQ Function Data Input/ Output Mask Data Input/ Output Power Supply (3.3 Ground Data Output Power Supply (3.3 Data Output Ground Connection
Note same power supply voltage must provided every VCCQ pin. same voltage level must provided every VSSQ pin.
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Semiconductor
MD56V62160E
DESCRIPTION
Fetches inputs edge. Disables enables device operation asserting deactivating inputs except CLK, CKE, UDQM LDQM. Masks system clock deactivate subsequent operation. deactivated, system clock will masked that subsequent operation deactivated. should asserted least cycle prior command. column multiplexed. address RA11 Column Address Slects bank activated during address latch time selects bank precharge read/write during column address latch time.
Address
A13, (BA0, BA1) UDQM, LDQM
Functionality depends combination. details, function truth table.
Masks read data clocks later when UDQM LDQM edge clock signal. Masks write data same clock when UDQM LDQM edge clock signal. UDQM controls upper byte LDQM controls lower byte. Data inputs/outputs multiplexed same pin.
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Semiconductor
MD56V62160E
BLOCK DIAGRAM
UDQM LDQM
Progra-m Register Latency Burst Controller Controller
Timing Register
Bank Controller
A13,
Internal Col. Address Counter
Input Data Register Column Address Buffers Column Decoders
Input Buffers
Sense Amplifiers Internal Address Counter
Read Data Register
Output Buffers
DQ16
Decoders Decoders
Word Drivers Word Drivers
16Mb Memory Cells 16Mb Memory Cells
Address Buffers
Sense Amplifiers
Column Decoders
Column Decoders
Sense Amplifiers
Decoders Decoders
Word Drivers Word Drivers
16Mb Memory Cells 16Mb Memory Cells
Sense Amplifiers
Column Decoders
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FEDD56V62160E-01
Semiconductor
MD56V62160E
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter Voltage Relative Supply Voltage Storage Temperature Power Dissipation Short Circuit Output Current Operating Temperature
Symbol VIN, VOUT VCCQ Tstg Topr
Value -0.5 VCC+ -0.5 1000
Unit
25°C
Recommended Operating Conditions
(Voltages referenced Parameter Power Supply Voltage Input High Voltage Input Voltage Symbol VCC, VCCQ Min. -0.3 Typ. Max. Unit
Capacitance
(Vbias 25°C, MHz) Parameter Input Capacitance (CLK) Input Capacitance (RAS, CAS, CKE, UDQM, LDQM, A13) Input/Output Capacitance (DQ1 DQ16) COUT Symbol CCLK Min. Max. Unit
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MD56V62160E
Characteristics
MD56V62160 Condition Parameter
Symbol
E-10 Max. Min. Max.
Unit
Note
Bank
Output High Voltage Output Voltage Input Leakage Current Output Leakage Current
Others
-2.0mA 2.0mA
Min.
ICC1 Average Power Supply Current (Operating)
Min. Bank Min. Active Burst Min. Min. tRRD Min. Burst
Both ICC1D Banks Active
Power Supply Current (Standby) Average Power Supply Current (Clock Suspension) Average Power Supply Current (Active Standby) Power Supply Current (Burst) Power Supply Current (Auto-Refresh) Average Power Supply Current (Self-Refresh) Average Power Supply Current (Power Down)
Both ICC2 Banks Min. Precharge Both ICC3S Banks Active
Min.
ICC3
Bank Min. Active
Both ICC4 Banks Active ICC5
Min.
Bank Min. Active Min.
Both ICC6 Banks Precharge
Min.
Both ICC7 Banks Min. Precharge
Notes: Measured with outputs open. address data changed once left unchanged during cycle. address data changed once left unchanged during cycles.
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MD56V62160E
Mode Address Keys
Single Write Latency Burst Type Burst Length
BRSW Normal Single Write
Reserved Reserved Reserved Reserved Reserved
Sequential
Interleave
Reserved Reserved Reserved Reserved Reserved Reserved Full Page Reserved
Notes: A10, A11, should stay during mode cycle. MD56V62160E supports methods Power Sequence. POWER SEQUENCE With inputs state, turn power supply start system clock. After voltage reached specified level, pause more with input kept state. Issue precharge bank command. Apply auto-refresh eight more times. Enter mode register setting command. POWER SEQUENCE With inputs state, turn power supply start system clock. After voltage reached specified level, pause more with input kept state. Issue precharge bank command. Enter mode register setting command. Apply auto-refresh eight more times.
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MD56V62160E
Characteristics (1/2)
Note1, MD56V62160 Parameter Symbol Min. Max. 100,000 Min. +1CLK E-10 Max. 100,000 Unit Note
Clock Cycle Time Access Time from Clock Clock High Pulse Time Clock Pulse Time Input Setup Time Input Hold Time Output Impedance Time from Clock Output High Impedance Time from Clock Output Hold from Clock
Random Read Write Cycle Time Precharge Time Pulse Width Delay Time Write Recovery Time Bank Active Delay Time Refresh Time Power-down Exit setup Time Delay Time (Min.) Clock Disable Time from Data Output High Impedance Time from UDQM, LDQM Dada Input Mask Time from UDQM, LDQM
tCC3 tCC2 tCC1 tAC3 tAC2 tCC1 tOLZ tOHZ tRAS tRCD tRRD tREF tRDE lCCD lCKE lDOZ lDOD
+1CLK
Cycle Cycle Cycle Cycle
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MD56V62160E
Characteristics (2/2)
Note1, MD56V62160 Parameter Symbol Min. Data Input Mask Time from Write Command Data Output High Impedance Time from Precharge Command Active Command Input Time from Mode Register Command Input (Min.) Write Command Input Time from Output lDWD lROH Max. Min. E-10 Max. Cycle Cycle Unit Note
lMRD
Cycle
lOWD
Cycle
Notes: measurements assume that reference level timing input signals input signal conditions below. Output load.
Output (External Load)
access time defined longer than then reference level timing input signals VIL.
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Semiconductor
MD56V62160E
TIMING CHART
Read Write Cycle (Same Bank) @CAS Latency Burst Length
tRCD
ADDR
A12,
UDQM, LDQM
Active Read Command Active Write Command
Precharge Command
Precharge Command
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MD56V62160E
Single Read-Write-Read Cycle (Same Page) @CAS Latency Burst Length
High
ADDR A12. ICCD
tOHZ tOLZ lOWD
UDQM, LDQM
Active Read Command Write Command Precharge Command
Read Command
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MD56V62160E
*Notes: When "High" clock transition from "Low" "High", inputs except CLK, CKE, UDQM LDQM invalid. When issuing active, read write command, bank selected A13.
Active, read write Bank Bank Bank Bank
auto precharge function enabled disabled input when read write command issued.
Operation After burst, bank holds idle status. After burst, bank precharged automatically. After burst, bank holds idle status. After burst, bank precharged automatically. After burst, bank holds idle status. After burst, bank precharged automatically. After burst, bank holds idle status. After burst, bank precharged automatically.
When issuing precharge command, bank precharged selected inputs.
Operation Bank precharged. Bank precharged. Bank precharged. Bank precharged. banks precharged.
input data write command latched same clock (Write latency output forced high impedance (1CLK+ tOHZ after UDQM, LDQM entry.
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Semiconductor
MD56V62160E
Page Read Write Cycle (Same Bank) @CAS Latency Burst Length
High
Bank Active
ICCD ADDR
A12,
lOWD
Note
Note
UDQM, LDQM
Read Command Read Command Write Command Precharge Command Write Command
*Notes: write data before burst read ends, UDQM LDQM should asserted three cycles prior write command avoid contention. assert precharge before burst write ends, wait after last write data input. Input data during precharge input cycle will masked internally.
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Semiconductor
MD56V62160E
Burst Read Single Write Cycle (Same Bank) @CAS Latency Burst Length
tRCD
ADDR
A12,
Note
UDQM, LDQM
Active Read Command Write Command Read Command
Precharge Command
*Note: high during mode register cycle, write burst length
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Semiconductor
MD56V62160E
Read Write Cycle with Auto Precharge Burst Length
High
tRRD
ADDR
A12,
Latency=1
A-Bank Precharge Start
UDQM, LDQM Latency=2
A-Bank Precharge Start
UDQM, LDQM Latency=3
A-Bank Precharge Start
UDQM, LDQM
Active (A-Bank) Active (B-Bank)
Bank Read with Auto Precharge
Bank Write with Auto Precharge
Bank Precharge Start Point
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Semiconductor
MD56V62160E
Bank Interleave Random Read Cycle @CAS Latency Burst Length
High
tRRD
ADDR
A12,
QAa0 QAa1 QAa2 QAa3
QBb1 QBb2 QBb3 QBb4
QAc0 QAc1 QAc2 QAc3
UDQM, LDQM
Active Read Command Read Command Active (A-Bank) (B-Bank) (A-Bank) (B-Bank) Read Command Active Precharge Command (A-Bank) (A-Bank) Precharge Command (A-Bank) (B-Bank)
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MD56V62160E
Bank Interleave Random Write Cycle @CAS Latency Burst Length
High
ADDR
A12,
DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3
DAc0 DAc1
UDQM, LDQM
Active (A-Bank) Active (B-Bank) Write Command (A-Bank) Write Command (B-Bank) Precharge Command (A-Bank) Write Command (A-Bank) Precharge Command (A-Bank)
Precharge Command (B-Bank) Active (A-Bank)
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Semiconductor
MD56V62160E
Bank Interleave Page Read Cycle @CAS Latency Burst Length
Note
High
ADDR
A12,
QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1 IROH
UDQM, LDQM
Active (A-Bank) Active (B-Bank) Read Command (B-Bank) Read Command (B-Bank) Read Command (A-Bank) Precharge Command (A-Bank)
Read Command (A-Bank)
Read Command (A-Bank)
*Note: ignored when RAS, high same cycle.
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Semiconductor
MD56V62160E
Bank Interleave Page Write Cycle @CAS Latency Burst Length
High
ADDR
A12,
DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 DBd0
UDQM, LDQM
Active (A-Bank) Active (B-Bank) Write Command (B-Bank) Write Command (B-Bank) Precharge Command (Both Bank) Write Command (A-Bank)
Write Command (A-Bank)
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Semiconductor
MD56V62160E
Bank Interleave Random Read/Write Cycle @CAS Latency Burst Length
High
ADDR
A12,
QAa0 QAa1 QAa2 QAa3
QBb0 QBb1 QBb2 QBb3
QAc0 QAc1 QAc2 QAc3
UDQM, LDQM
Active (A-Bank) Read Command (A-Bank) Active (B-Bank) Write Command (B-Bank) Read Command (A-Bank)
Precharge Command (A-Bank)
Active (A-Bank)
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Semiconductor
MD56V62160E
Bank Interleave Page Read/Write Cycle @CAS Latency Burst Length
High
ADDR
CAa0
CBb0
CAc0
A12,
QAa0 QAa1 QAa2 QAa3
DBb0 DBb1 DBb2 DBb3
QAc0 QAc1 QAc2 QAc3
UDQM, LDQM
Read Command (A-Bank) Write Command (B-Bank) Read Command (A-Bank)
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FEDD56V62160E-01
Semiconductor
MD56V62160E
Clock Suspension Operation Cycle @CAS Latency Burst Length
Note Note
ADDR
A12,
Note
tOHZ
tOHZ
Note
UDQM, LDQM
Active Read Command Read CLOCK Suspension Read Command Read Write Write Command Write CLOCK Suspension
*Note:
When Clock Suspension asserted, next clock cycle ignored. When UDQM LDQM asserted, read data after clock cycles masked. When UDQM LDQM asserted, write data same clock cycle masked. When LDQM High, input/output data masked. When UDQM High, input/output data DQ16 masked.
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FEDD56V62160E-01
Semiconductor
MD56V62160E
Read Write Cycle (Same Bank) @CAS Latency Burst Length
Note tRCD
ADDR
A12,
UDQM, LDQM
Active Read Command Write Command Precharge Command
*Note: Case latency READ interrupted WRITE. minimum command interval [burst length cycles. UDQM, LDQM must high least clocks prior write command.
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Semiconductor
MD56V62160E
Read Interruption Precharge Command @Burst Length
High
ADDR
A12,
Latency=1 Note lROH UDQM, LDQM Latency=2 Note lROH UDQM, LDQM Latency=3 Note lROH UDQM, LDQM
Active Read Command Precharge Command
*Note: precharge asserted before burst read ends, then read data will output after lROH equals latency.
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FEDD56V62160E-01
Semiconductor
MD56V62160E
Burst Stop Command @Burst Length
High
ADDR
A12,
Latency
UDQM, LDQM Latency
UDQM, LDQM Latency
UDQM, LDQM
Read Command Burst Stop Command Write Command Burst Stop Command
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Semiconductor
MD56V62160E
Power Down Mode @CAS Latency Burst Length
tREF (min.) Note tPDE Note
ADDR
A12,
UDQM, LDQM
Power-down Entry Active Clock Power-down Exit Suspension Entry Read Command Clock Suspension Exit Precharge Command
*Note: When both banks precharge state, low, then MD56V62160E enters power-down mode maintains mode while low. release circuit from power-down mode, high longer than tPDE (tSI 1CLK).
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MD56V62160E
Self Refresh Cycle
ADDR
A12,
Hi-Z
UDQM, LDQM
Self Refresh Entry Self Refresh Exit Active
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Semiconductor
MD56V62160E
Mode Register Cycle
Auto Refresh Cycle
High
High
lMRD
ADDR
UDQM, LDQM
Command Auto Refresh Auto Refresh
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MD56V62160E
FUNCTION TRUTH TABLE (Table (1/2)
Current State Idle
ADDR
Code ILLEGAL ILLEGAL Active
Action
Auto-Refresh Self-Refresh Mode Register Write Read Write ILLEGAL Precharge ILLEGAL (Continue Active after Burst ends) (Continue Active after Burst ends) Term Burst Active Term Burst, start Burst Read Term Burst, start Burst Write ILLEGAL Term Burst, execute Precharge ILLEGAL (Continue Active after Burst ends) (Continue Active after Burst ends) Term Burst Active Term Burst, start Burst Read Term Burst, start Burst Write ILLEGAL Term Burst, execute Precharge ILLEGAL (Continue Burst enter Precharge) (Continue Burst enter Precharge) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL (Continue Burst enter Precharge) (Continue Burst enter Precharge) ILLEGAL ILLEGAL
Active
Read
Write
Read with Auto Precharge
Write with Auto Precharge
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MD56V62160E
FUNCTION TRUTH TABLE (Table (2/2)
Current State1
Write with Auto Precharge Precharge
ADDR
ILLEGAL ILLEGAL ILLEGAL Idle after Idle after ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL
Action
Write Recovery
Active
ILLEGAL Active after tRCD Active after tRCD ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Idle after Idle after ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL
Refresh
Mode Register Access
ABBREVIATIONS Address Bank Address Column Address Auto Precharge
OPeration command
Notes inputs enabled when high least cycle prior inputs. Illegal bank specified state, legal some cases depending state bank selection. Satisfy timing lCCD prevent contention. bank precharging idle state. Precharges activated bank A10. Illegal bank idle.
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MD56V62160E
FUNCTION TRUTH TABLE (Table
Current State CKEn-1 Self Refresh Power Down
CKEn
ADDR
Action INVALID Exit Self Refresh Exit Self Refresh ILLEGAL ILLEGAL ILLEGAL (Maintain Self Refresh) INVALID Exit Power Down Exit Power Down ILLEGAL ILLEGAL ILLEGAL (Continue power down mode) Refer Table Enter Power Down Enter Power Down ILLEGAL ILLEGAL ILLEGAL Enter Self Refresh ILLEGAL Refer Operations Table Begin Clock Suspend Next Cycle Enable Clock Next Cycle Continue Clock Suspension
Banks Idle (ABI)
State Other than Listed Above
*Notes minimum set-up time tPDE satisfied when transition from "H", operates asynchronously that command input same internal clock cycle. Power-down self-refresh entered only when banks idle state.
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MD56V62160E
PACKAGE DIMENSIONS
(Unit:
TSOP(2)54-P-400-0.80-K
Mirror finish
Notes Mounting Surface Mount Type Package
Package material Lead frame material treatment Package weight Rev. No./Last Revised
Epoxy resin alloy Solder plating (5µm) 0.55 TYP. 1/Aug. 1997
surface mount type package, which very susceptible heat reflow mounting humidity absorbed storage. Therefore, before perform reflow mounting, contact Oki's responsible sales person product name, package name, number, package code desired mounting conditions (reflow method, temperature times).
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FEDD56V62160E-01
Semiconductor
MD56V62160E
REVISION HISTORY
Document
FEDD56V62160E-01
Date
Feb. 2002
Page Previous Current Edition Edition
First edition
Description
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Semiconductor
MD56V62160E
NOTICE information contained herein change without notice owing product and/or technical improvements. Before using product, please make sure that information being referred up-to-date. outline action examples application circuits described herein have been chosen explanation standard action performance product. When planning product, please ensure that external conditions reflected actual circuit, assembly, program designs. When designing your product, please product below specified maximum ratings within specified operating ranges including, limited operating voltage, power dissipation, operating temperature. assumes responsibility liability whatsoever failure unusual unexpected operation resulting from misuse, neglect, improper installation, repair, alteration accident, improper handling, unusual physical electrical stress including, limited exposure parameters beyond specified maximum ratings operation outside specified operating range. Neither indemnity against license third party's industrial intellectual property right, etc. granted connection with product and/or information drawings contained herein. responsibility assumed infringement third party's right which result from thereof. products listed this document intended general electronics equipment commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products authorized system application that requires special enhanced quality reliability characteristics system application where failure such system application result loss damage property, death injury humans. Such applications include, limited traffic automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, life-support systems. Certain products this document need government approval before they exported particular countries. purchaser assumes responsibility determining legality export these products will take appropriate necessary steps their expense these. part contents contained herein reprinted reproduced without prior permission. Copyright 2001 Electric Industry Co., Ltd.
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