Semiconductor MSM56V16160F 2-Bank 524,288-Word 16-Bit SYNCHRONOUS
|
|
|
Top Searches for this datasheet
FEDD56V16160F-02
Semiconductor MSM56V16160F
2-Bank 524,288-Word 16-Bit SYNCHRONOUS DYNAMIC
This version: March. 2001 Previous version January. 2001
DESCRIPTION MSM56V16160F 2-Bank 524,288-word 16-bit Synchronous dynamic fabricated Oki's silicon-gate CMOS technology. device operates 3.3V. inputs outputs LVTTL compatible. FEATURES
Silicon gate, quadruple polysilicon CMOS, 1-transistor memory cell 2-Bank 524,288-word 16-bit configuration Single 3.3V power supply, ±0.3V tolerance Input LVTTL compatible Output LVTTL compatible Refresh 4096 cycles/64ms Programmable data transfer mode
Latency (1,2,3) Burst Length (1,2,4,8,Full Page) Data scramble (sequential, interleave) auto-refresh, Self-refresh capability
Packages:
50-pin 400mil plastic TSOP (Type (TSOPII50-P-400-0.80-1K) (Product MSM56V16160F-xxTS-K) indicates speed rank. PRODUCT FAMILY
Family
Max. Frequency 125MHz 100MHz
Access Time (Max.) tAC2 tAC3
MSM56V16160F-8 MSM56V16160F-10
1/31
FEDD56V16160F-02
Semiconductor
MSM56V16160F
CONFIGURATION (TOP VIEW)
VSSQ DQ16 DQ15 VSSQ DQ14 DQ13 VCCQ DQ12 DQ11 VSSQ DQ10 VCCQ UDQM
VCCQ VSSQ VCCQ LDQM
50-Pin Plastic TSOP (II) Type)
Name A0-A10
Function System Clock Chip Select Clock Enable Address Bank Select Address Address Strobe Column Address Strobe Write Enable
Name UDQM, LDQM VCCQ VSSQ
Function Data Input Output Mask Data Input Output Power Supply (3.3V) Ground (0V) Data Output Power Supply (3.3V) Data Output Ground (0V) Connection
Note same power supply voltage must provided every VCCQ pin. same voltage level must provided every VSSQ pin.
2/31
FEDD56V16160F-02
Semiconductor
MSM56V16160F
DESCRIPTION
Fetches inputs edge. Disables enables device operation asserting deactivating inputs except CLK, CKE, UDQM LDQM. Masks system clock deactivate subsequent operation. deactivated, system clock will masked that subsequent operation deactivated. should asserted least cycle prior command. column multiplexed. address RA10 Column Address Slects bank activated during address latch time selects bank precharge read/write during column address latch time. A11="L" Bank A11="H" Bank
Address
UDQM, LDQM
Functionality depends combination. details, function truth table.
Masks read data clocks later when UDQM LDQM edge clock signal. Masks write data same clock when UDQM LDQM edge clock signal. UDQM controls upper byte LDQM controls lower byte. Data inputs/outputs multiplexed same pin.
3/31
FEDD56V16160F-02
Semiconductor
MSM56V16160F
BLOCK DIAGRAM
UDQM LDQM
Latency Burst Controller Controller
Timing Register
Programing Register
Bank Controlle
Internal Col. Address Counter
A0-A11
Input Data Registe Column Address Buffers Column Decoders
Input Buffers
Sense Amplifiers Internal Address Counter
Read Data Registe
Output Buffers
-DQ16
Decoder
Word Drivers
Memory Cells
Address Buffers
Decoder
Word Drivers
Memory Cells
Sense Amplifiers
Column Decoders
4/31
FEDD56V16160F-02
Semiconductor
MSM56V16160F
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage Relative Supply Voltage Storage Temperature Power Dissipation Short Circuit Output Current Operating Temperature Symbol VIN, VOUT VCCQ Tstg Topr Value -0.5 VCC+ -0.5 Unit
25°C
RECOMMENDED OPERATIING CONDITIONS
(Voltages referenced Parameter Power Supply Voltage Input High Voltage Input Voltage Symbol VCC, VCCQ Min. -0.3 Typ. Max. Unit
CAPACITANCE
(VBIAS 1.4V, 25°C, MHz) Parameter Input Capacitance (CLK) Input Capacitance (CKE, A11, RAS, CAS, UDQM, LDQM Input/Output Capacitance (DQ1 DQ16) Symbol CCLK COUT Min. Max. Unit
5/31
FEDD56V16160F-02
Semiconductor
MSM56V16160F
CHARACTERISTICS
MSM56V16160 Condition Parameter
Symbol
F-10 Max. Min. Max.
Unit
Note
Bank
Output High Voltage Output Voltage Input Leakage Current Output Leakage Current
Others
IOH=-2.0mA IOL=2.0mA Min. Min. Burst Min. Min. tRRD Min. Burst Min.
Min.
ICC1 Average Power Supply Current (Operating)
Bank CKEVIH Active
Both ICC1D Banks Active
CKEVIH
Power Supply Current (Standby) Average Power Supply Current (Clock Suspension) Average Power Supply Current (Active Standby) Power Supply Current (Burst) Power Supply Current (Auto-Refresh) Average Power Supply Current (Self-Refresh) Average Power Supply Current (Power Down)
Both ICC2 Banks CKEVIH Precharge Both ICC3S Banks Active
CKEVIL
Min.
ICC3
Bank CKEVIH Active
Min.
Both ICC4 Banks Active ICC5
CKEVIH
Min.
Bank CKEVIH Active
Min. Min.
Both CKEVIL ICC6 Banks Precharge Both CKEVIL ICC7 Banks Precharge
Min.
Min.
Notes: Measured with outputs open. address data changed once left unchanged during cycle. address data changed once left unchanged during cycles.
6/31
FEDD56V16160F-02
Semiconductor
MSM56V16160F
Mode Address Keys
Latency Burst Type Burst Length
Reserved Reserved Reserved Reserved Reserved
Sequential Interleave
Reserved Reserved Reserved Full Page
Reserved Reserved Reserved Reserved
Notes: should stay during mode cycle. MSM56V16160F support methods Power Sequence. POWER SEQUENCE With inputs state, turn power supply start system clock. After voltage reached specified level, pause 200µs more with input kept state. Issue precharge bank command. Apply auto-refresh eight more times. Enter mode register setting command. POWER SEQUENCE With inputs state, turn power supply start system clock. After voltage reached specified level, pause 200µs more with input kept state. Issue precharge bank command. Enter mode register setting command. Apply auto-refresh eight more times.
7/31
FEDD56V16160F-02
Semiconductor
MSM56V16160F
CHARACTERISTICS (1/2)
Note MSM56V16160 Parameter Symbol Min. Max. 100,000 Min. +1CLK F-10 Max. 100,000 Unit Note
Clock Cycle Time Access Time from Clock Clock High Pulse Time Clock Pulse Time Input Setup Time Input Hold Time Output Impedance Time from Clock Output High Impedance Time from Clock Output Hold from Clock
Random Read Write Cycle Time Precharge Time Pulse Width Delay Time Write Recovery Time Bank Active Delay Time Refresh Time Power-down Exit setup Time Input Level Transition Time Delay Time (Min.) Clock Disable Time from Data Output High Impedance Time from UDQM, LDQM Dada Input Mask Time from UDQM, LDQM
tCC3 tCC2 tCC1 tAC3 tAC2 tAC1 tOLZ tOHZ tRAS tRCD tRRD tREF tRDE lCCD lCKE lDOZ lDOD
+1CLK
Cycle Cycle Cycle Cycle
8/31
FEDD56V16160F-02
Semiconductor
MSM56V16160F
CHARACTERISTICS (2/2)
Note MSM56V16160 Parameter Symbol Min. Data Input Mask Time from Write Command Data Output High Impedance Time from Precharge Command Active Command Input Time from Mode Register Command Input (Min.) Write Command Input Time from Output lDWD lROH Max. Min. F-10 Max. Cycle Cycle Unit Note
lMRD
Cycle
lOWD
Cycle
Notes: measurements assume that 1ns. reference level timing input signals 1.4V. Output load.
Z=50 Output 50pF (External Load)
access time defined 1.4V. longer than 1ns, then reference level timing input signals VIL.
9/31
FEDD56V16160F-02
Semiconductor
MSM56V16160F
TIMING CHART
Read Write Cycle (Same Bank) @CAS Latency=2, Burst Length=4
tRCD
ADDR
tOHZ
UDQM, LDQM
Active Read Command Active Write Command
Precharge Command
Precharge Command
10/31
FEDD56V16160F-02
Semiconductor
MSM56V16160F
Single Read-Write-Read Cycle (Same Page) @CAS Latency=2, Burst Length=4
High
ADDR ICCD
tOHZ tOLZ lOWD
UDQM, LDQM
Active Read Command Write Command Precharge Command
Read Command
11/31
FEDD56V16160F-02
Semiconductor
MSM56V16160F
*Note: When "High" clock transition from "Low" "High", inputs except CKE, UDQM LDQM invalid. When issuing active, read write command, bank selected A11.
Active, read write Bank Bank
auto precharge function enabled disabled input when read write command issued.
Operation After burst, bank holds idle status. After burst, bank precharged automatically. After burst, bank holds idle status. After burst, bank precharged automatically.
When issuing precharge command, bank precharged selected inputs.
Operation Bank precharged. Bank precharged. Both banks precharged.
input data write command latched same clock (Write latency=0). output forced high impedance (1CLK+ tOHZ after UDQM, LDQM entry.
12/31
FEDD56V16160F-02
Semiconductor
MSM56V16160F
Page Read Write Cycle (Same Bank) @CAS Latency=2, Burst Length=4
High
Bank Active
ICCD ADDR
lOWD
Note
Note
UDQM, LDQM
Read Command Read Command Write Command Precharge Command Write Command
*Note: write data before burst read ends, UDQM LDQM should asserted three cycles prior write command avoid contention. assert precharge before burst write ends, wait after last write data input. Input data during precharge input cycle will masked internally.
13/31
FEDD56V16160F-02
Semiconductor
MSM56V16160F
Read Write Cycle with Auto Precharge Burst Length=4
High
tRRD
ADDR
Latency=1
A-Bank Precharge Start
UDQM, LDQM Latency=2
A-Bank Precharge Start
UDQM, LDQM Latency=3
A-Bank Precharge Start
UDQM, LDQM
Active (A-Bank) Active (B-Bank)
Bank Read with Auto Precharge
Bank Write with Auto Precharge
Bank Precharge Start Point
14/31
FEDD56V16160F-02
Semiconductor
MSM56V16160F
Bank Interleave Random Read Cycle @CAS Latency=2, Burst Length=4
High
tRRD
ADDR
QAa0 QAa1 QAa2 QAa3
QBb1 QBb2 QBb3 QBb4
QAc0 QAc1 QAc2 QAc3
UDQM, LDQM
Active Read Command Read Command Active (A-Bank) (A-Bank) (B-Bank) (B-Bank) Active Read Command Precharge Command (A-Bank) Precharge Command (A-Bank) (A-Bank) (B-Bank)
15/31
FEDD56V16160F-02
Semiconductor
MSM56V16160F
Bank Interleave Random Write Cycle @CAS Latency=2, Burst Length=4
High
ADDR
DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3
DAc0 DAc1
UDQM, LDQM
Active (A-Bank) Active (B-Bank) Write Command (A-Bank) Write Command (B-Bank) Precharge Command (A-Bank) Write Command (A-Bank) Precharge Command (A-Bank)
Precharge Command (B-Bank) Active (A-Bank)
16/31
FEDD56V16160F-02
Semiconductor
MSM56V16160F
Bank Interleave Page Read Cycle @CAS Latency=2, Burst Length=4
Note
High
ADDR
QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1 IROH
UDQM, LDQM
Active (A-Bank) Active (B-Bank) Read Command (B-Bank) Read Command (B-Bank) Read Command (A-Bank) Precharge Command (A-Bank)
Read Command (A-Bank)
Read Command (A-Bank)
*Note: ignored when RAS, high same cycle.
17/31
FEDD56V16160F-02
Semiconductor
MSM56V16160F
Bank Interleave Page Write Cycle @CAS Latency=2, Burst Length=4
High
ADDR
DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 DBd0
UDQM, LDQM
Active (A-Bank) Active (B-Bank) Write Command (B-Bank) Write Command (B-Bank) Precharge Command (Both Bank) Write Command (A-Bank)
Write Command (A-Bank)
18/31
FEDD56V16160F-02
Semiconductor
MSM56V16160F
Bank Interleave Random Read/Write Cycle @CAS Latency=2, Burst Length=4
High
ADDR
QAa0 QAa1 QAa2 QAa3
QBb0 QBb1 QBb2 QBb3
QAc0 QAc1 QAc2 QAc3
UDQM, LDQM
Active (A-Bank) Read Command (A-Bank) Active (B-Bank) Write Command (B-Bank) Read Command (A-Bank)
Precharge Command (A-Bank)
Active (A-Bank)
19/31
FEDD56V16160F-02
Semiconductor
MSM56V16160F
Bank Interleave Page Read/Write Cycle @CAS Latency=2, Burst Length=4
High
ADDR
CAa0
CBb0
CAc0
QAa0 QAa1 QAa2 QAa3
DBb0 DBb1 DBb2 DBb3
QAc0 QAc1 QAc2 QAc3
UDQM, LDQM
Read Command (A-Bank) Write Command (B-Bank) Read Command (A-Bank)
20/31
FEDD56V16160F-02
Semiconductor
MSM56V16160F
Clock Suspension Operation Cycle @CAS Latency=2, Burst Length=4
Note Note
ADDR
Note
tOHZ
tOHZ
Note
UDQM, LDQM
Active Read Command Read CLOCK Suspension Read Command Read Write Write Command Write CLOCK Suspension
*Note:
When Clock Suspension asserted, next clock cycle ignored. When UDQM LDQM asserted, read data after clock cycles masked. When UDQM LDQM asserted, write data same clock cycle masked. When LDQM High, input/output data masked. When UDQM High, input/output data DQ16 masked.
21/31
FEDD56V16160F-02
Semiconductor
MSM56V16160F
Read Write Cycle (Same Bank) @CAS Latency=2, Burst Length=4
Note tRCD
ADDR
UDQM, LDQM
Active Read Command Write Command Precharge Command
*Note: Case latency READ interrupted WRITE. minimum command interval [burst length cycles. UDQM, LDQM must high least clocks prior write command.
22/31
FEDD56V16160F-02
Semiconductor
MSM56V16160F
Read Interruption Precharge Command @Burst Length=8
High
ADDR
Latency=1 Note lROH UDQM, LDQM Latency=2 Note lROH UDQM, LDQM Latency=3 Note lROH UDQM, LDQM
Active Read Command Precharge Command
*Note: precharge asserted before burst read ends, then read data will output after lROH equals latency.
23/31
FEDD56V16160F-02
Semiconductor
MSM56V16160F
Burst Stop Command @Burst Length=8
High
ADDR
Latency=1
UDQM, LDQM Latency=2
UDQM, LDQM Latency=3
UDQM, LDQM
Read Command Burst Stop Command Write Command Burst Stop Command
24/31
FEDD56V16160F-02
Semiconductor
MSM56V16160F
Power Down Mode @CAS Latency=2, Burst Length=4
tREF (min.) Note tPDE Note
ADDR
UDQM, LDQM
Power-down Entry Active Clock Power-down Suspension Exit Entry Read Command Clock Suspension Exit Precharge Command
*Note: When both banks precharge state, low, then MSM56V16160F enters power-down mode maintains mode while low. release circuit from power-down mode, high longer than tPDE (tSI 1CLK).
25/31
FEDD56V16160F-02
Semiconductor
MSM56V16160F
Self Refresh Cycle
ADDR
Hi-Z
UDQM, LDQM
Self Refresh Entry Self Refresh Exit Active
26/31
FEDD56V16160F-02
Semiconductor
MSM56V16160F
Mode Register Cycle
Auto Refresh Cycle
High
High
lMRD
ADDR
UDQM, LDQM
Command Auto Refresh Auto Refresh
27/31
FEDD56V16160F-02
Semiconductor
MSM56V16160F
FUNCTION TRUTH TABLE (Table (1/2)
Current State1 Idle
ADDR
Code ILLEGAL ILLEGAL Active
Action
Auto-Refresh Self-Refresh Mode Register Write Read Write ILLEGAL Precharge ILLEGAL (Continue Active after Burst ends) (Continue Active after Burst ends) Term Burst Active Term Burst, start Burst Read Term Burst, start Burst Write ILLEGAL Term Burst, execute Precharge ILLEGAL (Continue Active after Burst ends) (Continue Active after Burst ends) Term Burst Active Term Burst, start Burst Read Term Burst, start Burst Write ILLEGAL Term Burst, execute Precharge ILLEGAL (Continue Burst enter Precharge) (Continue Burst enter Precharge) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL (Continue Burst enter Precharge) (Continue Burst enter Precharge) ILLEGAL ILLEGAL
Active
Read
Write
Read with Auto Precharge
Write with Auto Precharge
28/31
FEDD56V16160F-02
Semiconductor
MSM56V16160F
FUNCTION TRUTH TABLE (Table (2/2)
Current State1
Write with Auto Precharge Precharge
ADDR
ILLEGAL ILLEGAL ILLEGAL Idle after Idle after ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL
Action
Write Recovery
Active
ILLEGAL Active after tRCD Active after tRCD ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Idle after Idle after ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL
Refresh
Mode Register Access
ABBREVIATIONS Address Bank Address OPeration command Column Address Auto Precharge Notes inputs enabled when high least cycle prior inputs. Illegal bank specified state, legal some cases depending state bank selection. Satisfy timing lCCD prevent contention. bank precharging idle state. Precharges activated bank A10. Illegal bank idle.
29/31
FEDD56V16160F-02
Semiconductor
MSM56V16160F
FUNCTION TRUTH TABLE (Table
Current State CKEn-1 Self Refresh
CKEn
ADDR
Action INVALID Exit Self Refresh Exit Self Refresh ILLEGAL ILLEGAL ILLEGAL (Maintain Self Refresh) INVALID Exit Power Down Exit Power Down ILLEGAL ILLEGAL ILLEGAL (Continue power down mode) Refer Table Enter Power Down Enter Power Down ILLEGAL ILLEGAL ILLEGAL Enter Self Refresh ILLEGAL Refer Operations Table Begin Clock Suspend Next Cycle Enable Clock Next Cycle Continue Clock Suspension
Power Down
Banks Idle (ABI)
State Other than Listed Above
*Notes minimum set-up time tPDE satisfied when transition from "H", operates asynchronously that command input same internal clock cycle. Power-down self-refresh entered only when banks idle state.
30/31
FEDD56V16160F-02
Semiconductor
MSM56V16160F
NOTICE information contained herein change without notice owing product and/or technical improvements. Before using product, please make sure that information being referred up-to-date. outline action examples application circuits described herein have been chosen explanation standard action performance product. When planning product, please ensure that external conditions reflected actual circuit, assembly, program designs. When designing your product, please product below specified maximum ratings within specified operating ranges including, limited operating voltage, power dissipation, operating temperature. assumes responsibility liability whatsoever failure unusual unexpected operation resulting from misuse, neglect, improper installation, repair, alteration accident, improper handling, unusual physical electrical stress including, limited exposure parameters beyond specified maximum ratings operation outside specified operating range. Neither indemnity against license third party's industrial intellectual property right, etc. granted connection with product and/or information drawings contained herein. responsibility assumed infringement third party's right which result from thereof. products listed this document intended general electronics equipment commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products authorized system application that requires special enhanced quality reliability characteristics system application where failure such system application result loss damage property, death injury humans. Such applications include, limited traffic automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, life-support systems. Certain products this document need government approval before they exported particular countries. purchaser assumes responsibility determining legality export these products will take appropriate necessary steps their expense these. part contents contained herein reprinted reproduced without prior permission. Copyright 2001 Electric Industry Co., Ltd.
31/31
Other recent searches
XZDMG14A2 - XZDMG14A2 XZDMG14A2 Datasheet
SD05C - SD05C SD05C Datasheet
SD24C - SD24C SD24C Datasheet
PJ-055C - PJ-055C PJ-055C Datasheet
MC100EL57 - MC100EL57 MC100EL57 Datasheet
CM300DY-24H - CM300DY-24H CM300DY-24H Datasheet
2SC4628 - 2SC4628 2SC4628 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
