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Hitachi Single-Chip Microcomputer H8/3297 Series H8/3297 HD6473297, HD6433297 H8/3296 HD6433296 H8/3294 HD6473294, HD6433294 H8/3292 HD6433292 Hardware Manual
Edition
When using this document, keep following mind: This document may, wholly partially, subject change without notice. rights reserved: permitted reproduce duplicate, form, whole part this document without Hitachi's permission. Hitachi will held responsible damage user that result from accidents other reasons during operation user's unit accoording this document. Circuitry other examples described herein meant merely indicate characteristics performance Hitachi's semiconductor products. Hitachi assumes responsibility intellectual property claims other problems that result from applications based examples described herein. license granted implication otherwise under patents other rights third party Hitachi, Ltd. MEDICAL APPLICATIONS: Hitachi's products authorized MEDICAL APPLICATIONS without written consent appropriate officer Hitachi's sales company. Such includes, limited life support system. Buyers Hitachi's products requested notify relevant hitachi sales offices when planning products MEDICAL APPLICATIONS.
Preface
H8/3297 Series series high-performance microcontrollers with fast H8/300 core on-chip supporting functions optimized embedded control. These include ROM, RAM, three types timers, serial communication interface, converter, ports, other functions needed control system configurations, that compact, high-performance systems implemented easily. series includes H8/3297 with 60-kbyte 2-kbyte RAM, H8/3296 with 48-kbyte 2-kbyte RAM, H8/3294 with 32-kbyte 1-kbyte RAM, H8/3292 with 16-kbyte 512-byte RAM. entire H8/3297 Series available mask-ROM versions. H8/3297 H8/3294 also available ZTATTM* (zero turn-around time) versions, providing quick flexible response conditions from ramp-up through full-scale volume production, even applications with frequently-changing specifications. This manual describes hardware H8/3297 Series. Refer H8/300 Series Programming Manual detailed description instruction set. Note: ZTATis registered trademark Hitachi, Ltd.
Contents
Section
Overview. Overview Block Diagram. Assignments Functions. 1.3.1 Arrangement. 1.3.2 Functions
Section
Overview 2.1.1 Features. 2.1.2 Address Space. 2.1.3 Register Configuration. Register Descriptions. 2.2.1 General Registers. 2.2.2 Control Registers 2.2.3 Initial Register Values Data Formats. 2.3.1 Data Formats General Registers 2.3.2 Memory Data Formats. Addressing Modes 2.4.1 Addressing Mode. 2.4.2 Calculation Effective Address. Instruction Set. 2.5.1 Data Transfer Instructions 2.5.2 Arithmetic Operations 2.5.3 Logic Operations 2.5.4 Shift Operations 2.5.5 Manipulations 2.5.6 Branching Instructions. 2.5.7 System Control Instructions 2.5.8 Block Data Transfer Instruction States 2.6.1 Overview. 2.6.2 Program Execution State 2.6.3 Exception-Handling State. 2.6.4 Power-Down State Access Timing Cycle. 2.7.1 Access On-Chip Memory (RAM ROM) 2.7.2 Access On-Chip Register Field External Devices
Section
Operating Modes Address Space Overview 3.1.1 Mode Selection 3.1.2 Mode System Control Registers System Control Register (SYSCR). Mode Control Register (MDCR) Address Space Each Operating Mode. Exception Handling Overview Reset 4.2.1 Overview. 4.2.2 Reset Sequence 4.2.3 Disabling Interrupts after Reset. Interrupts 4.3.1 Overview. 4.3.2 Interrupt-Related Registers. 4.3.3 External Interrupts 4.3.4 Internal Interrupts 4.3.5 Interrupt Handling 4.3.6 Interrupt Response Time. 4.3.7 Precaution Note Stack Handling. Wait-State Controller Overview 5.1.1 Features. 5.1.2 Block Diagram. 5.1.3 Input/Output Pins. 5.1.4 Register Configuration. Register Description 5.2.1 Wait-State Control Register (WSCR). Wait Modes.
Overview 6.1.1 Block Diagram. 6.1.2 Wait-State Control Register (WSCR). Oscillator Circuit Duty Adjustment Circuit. Prescaler
Section
Section
Section
Clock Pulse Generator
Section
Ports Overview Port 7.2.1 Overview. 7.2.2 Register Configuration Descriptions. 7.2.3 Functions Each Mode. 7.2.4 Input Pull-Up Transistors Port 7.3.1 Overview. 7.3.2 Register Configuration Descriptions. 7.3.3 Functions Each Mode. 7.3.4 Input Pull-Up Transistors Port 7.4.1 Overview. 7.4.2 Register Configuration Descriptions. 7.4.3 Functions Each Mode. 7.4.4 Input Pull-Up Transistors Port 7.5.1 Overview. 7.5.2 Register Configuration Descriptions. 7.5.3 Functions Port 7.6.1 Overview. 7.6.2 Register Configuration Descriptions. 7.6.3 Functions Port 7.7.1 Overview. 7.7.2 Register Configuration Descriptions. 7.7.3 Functions Port 7.8.1 Overview. 7.8.2 Register Configuration Descriptions. 16-Bit Free-Running Timer Overview 8.1.1 Features. 8.1.2 Block Diagram. 8.1.3 Input Output Pins 8.1.4 Register Configuration. Register Descriptions. 8.2.1 Free-Running Counter (FRC) 8.2.2 Output Compare Registers (OCRA OCRB). 8.2.3 Input Capture Registers (ICRA ICRD).
Section
8.2.4 Timer Interrupt Enable Register (TIER). 8.2.5 Timer Control/Status Register (TCSR) 8.2.6 Timer Control Register (TCR). 8.2.7 Timer Output Compare Control Register (TOCR). Interface Operation 8.4.1 Incrementation Timing. 8.4.2 Output Compare Timing. 8.4.3 Clear Timing 8.4.4 Input Capture Timing 8.4.5 Timing Input Capture Flag (ICF) Setting. 8.4.6 Setting Output Compare Flags (OCFA OCFB) 8.4.7 Setting Overflow Flag (OVF) Interrupts Sample Application Usage Notes
Section
8-Bit Timers Overview 9.1.1 Features. 9.1.2 Block Diagram. 9.1.3 Input Output Pins 9.1.4 Register Configuration. Register Descriptions. 9.2.1 Timer Counter (TCNT). 9.2.2 Time Constant Registers (TCORA TCORB) 9.2.3 Timer Control Register (TCR). 9.2.4 Timer Control/Status Register (TCSR) 9.2.5 Serial/Timer Control Register (STCR). Operation 9.3.1 TCNT Incrementation Timing. 9.3.2 Compare Match Timing. 9.3.3 External Reset TCNT 9.3.4 Setting TCSR Overflow Flag (OVF). Interrupts Sample Application Usage Notes 9.6.1 Contention between TCNT Write Clear 9.6.2 Contention between TCNT Write Increment 9.6.3 Contention between TCOR Write Compare-Match 9.6.4 Contention between Compare-Match Compare-Match 9.6.5 Incrementation Caused Changing Internal Clock Source
Section
10.1
10.2
10.3
10.4
Watchdog Timer Overview 10.1.1 Features. 10.1.2 Block Diagram. 10.1.3 Register Configuration. Register Descriptions. 10.2.1 Timer Counter (TCNT). 10.2.2 Timer Control/Status Register (TCSR) 10.2.3 Register Access. Operation 10.3.1 Watchdog Timer Mode. 10.3.2 Interval Timer Mode. 10.3.3 Setting Overflow Flag. Usage Notes 10.4.1 Contention between TCNT Write Increment. 10.4.2 Changing Clock Select Bits (CKS2 CKS0). 10.4.3 Recovery from Software Standby Mode Serial Communication Interface
Overview 11.1.1 Features. 11.1.2 Block Diagram. 11.1.3 Input Output Pins 11.1.4 Register Configuration. Register Descriptions. 11.2.1 Receive Shift Register (RSR) 11.2.2 Receive Data Register (RDR). 11.2.3 Transmit Shift Register (TSR). 11.2.4 Transmit Data Register (TDR) 11.2.5 Serial Mode Register (SMR) 11.2.6 Serial Control Register (SCR) 11.2.7 Serial Status Register (SSR) 11.2.8 Rate Register (BRR) 11.2.9 Serial/Timer Control Register (STCR). Operation 11.3.1 Overview. 11.3.2 Asynchronous Mode. 11.3.3 Synchronous Mode Interrupts Usage Notes
Section
11.1
11.2
11.3
11.4 11.5
Section
12.1
Converter Overview
12.2
12.3 12.4
12.5 12.6
12.1.1 Features. 12.1.2 Block Diagram. 12.1.3 Input Pins 12.1.4 Register Configuration. Register Descriptions. 12.2.1 Data Registers (ADDRA ADDRD). 12.2.2 Control/Status Register (ADCSR) 12.2.3 Control Register (ADCR) Interface Operation 12.4.1 Single Mode (SCAN 12.4.2 Scan Mode (SCAN 12.4.3 Input Sampling Conversion Time 12.4.4 External Trigger Input Timing. Interrupts Usage Notes
Section
13.1
13.2
Overview 13.1.1 Block Diagram. 13.1.2 Enable (RAME) System Control Register (SYSCR) Operation 13.2.1 Expanded Modes (Modes 13.2.2 Single-Chip Mode (Mode ROM. Overview 14.1.1 Block Diagram. PROM Mode. 14.2.1 PROM Mode Setup. 14.2.2 Socket Adapter Assignments Memory Map. PROM Programming 14.3.1 Programming Verifying 14.3.2 Notes Programming 14.3.3 Reliability Programmed Data. 14.3.4 Erasing Data Handling Windowed Packages. Power-Down State Overview 15.1.1 System Control Register (SYSCR). Sleep Mode 15.2.1 Transition Sleep Mode.
Section
14.1 14.2
14.3
14.4
Section
15.1 15.2
15.3
15.4
15.2.2 Exit from Sleep Mode. Software Standby Mode 15.3.1 Transition Software Standby Mode. 15.3.2 Exit from Software Standby Mode 15.3.3 Clock Settling Time Exit from Software Standby Mode. 15.3.4 Sample Application Software Standby Mode 15.3.5 Usage Note. Hardware Standby Mode 15.4.1 Transition Hardware Standby Mode. 15.4.2 Recovery from Hardware Standby Mode 15.4.3 Timing Relationships.
Section
16.1 16.2
16.3
Electrical Specifications. Absolute Maximum Ratings Electrical Characteristics 16.2.1 Characteristics 16.2.2 Characteristics 16.2.3 Converter Characteristics. Operational Timing. 16.3.1 Timing 16.3.2 Control Signal Timing 16.3.3 16-Bit Free-Running Timer Timing 16.3.4 8-Bit Timer Timing. 16.3.5 Serial Communication Interface Timing 16.3.6 Port Timing. 16.3.7 External Clock Output Timing
Instruction List. Operation Code Map. Number States Required Execution.
Appendix Instruction Set.
Appendix Register Field
Register Addresses Names. Register Descriptions.
Appendix Port Block Diagrams
Port Block Diagram Port Block Diagram Port Block Diagram Port Block Diagrams. Port Block Diagrams. Port Block Diagrams. Port Block Diagrams.
Appendix States
Port States Each Mode.
Appendix Appendix
Timing Transition Recovery from Hardware Standby Mode. Product Code Lineup
Appendix Package Dimensions
Section Overview
Overview
H8/3297 Series single-chip microcomputers features H8/300 core complement on-chip supporting modules implementing variety system functions. H8/300 high-speed processor with architecture featuring powerful bit-manipulation instructions, ideally suited realtime control applications. on-chip supporting modules implement peripheral functions needed system configurations. These include ROM, RAM, three types timers 16-bit free-running timer, 8-bit timers, watchdog timer), serial communication interface (SCI), converter, ports. H8/3297 Series operate single-chip mode expanded modes, depending requirements application. entire H8/3297 Series available with mask ROM. H8/3297 H8/3294 also available ZTATversions* that programmed user site. Note: ZTAT(zero turn-around time) trademark Hitachi, Ltd. Table lists features H8/3297 Series.
Table Features
Item Specification Two-way general register configuration Eight 16-bit registers, Sixteen 8-bit registers High-speed operation Maximum clock rate clock): 16-bit register-register add/subtract: MHz), MHz), MHz) 8-bit multiply: MHz), 1167 MHz), 1400 MHz) 8-bit divide: MHz), 1167 MHz), 1400 MHz) Streamlined, concise instruction Instruction length: bytes Register-register arithmetic logic operations instruction data transfer between registers memory Instruction features Multiply instruction bits bits) Divide instruction bits bits) Bit-accumulator instructions Register-indirect specification positions Memory H8/3297: 60k-byte ROM; 2k-byte H8/3296: 48k-byte ROM; 2k-byte H8/3294: 32k-byte ROM; 1k-byte H8/3292: 16k-byte ROM; 512-byte
16-bit freerunning timer channel) 8-bit timer channels) Watchdog timer (WDT) channel) Serial communication interface (SCI) channel) converter
16-bit free-running counter (can also count external events) output-compare lines Four input capture lines (can buffered) Each channel 8-bit up-counter (can also count external events) time constant registers Overflow generate reset interrupt Also usable interval timer Asynchronous synchronous mode (selectable) Full duplex: transmit receive simultaneously On-chip baud rate generator 10-bit resolution Eight channels: single scan mode (selectable) Start conversion externally triggered Sample-and-hold function
ports
input/output lines which drive LEDs) input-only lines
Table Features (cont)
Item Interrupts Wait control Operating modes Power-down modes Other features Specification Four external interrupt lines: NMI, IRQ0 IRQ2 on-chip interrupt sources Three selectable wait modes Expanded mode with on-chip disabled (mode Expanded mode with on-chip enabled (mode Single-chip mode (mode Sleep mode Software standby mode Hardware standby mode On-chip oscillator
Table Features (cont)
Item Series lineup Specification
Part Number Version MHz) Version MHz) HD6473297C16 Version MHz) Package HD6473297C16 64-pin windowed shrink (DC-64S) 64-pin shrink (DP-64S) 64-pin (FP-64A) 80-pin TQFP (TFP-80C) 64-pin shrink (DP-64S) 64-pin (FP-64A) Mask PROM
Product Name H8/3297 ZTAT
HD6473297P16 HD6473297F16 HD6473297TF16 H8/3297 HD6433297P16 HD6433297P12 HD6433297F16 HD6433297F12 HD6433297TF16 HD6433297TF12 H8/3296 HD6433296P16 HD6433296P12 HD6433296F16 HD6433296F12 HD6433296TF16 HD6433296TF12 H8/3294 ZTAT HD6473294P16 HD6473294F16 HD6473294TF16 H8/3294 HD6433294P16 HD6433294P12 HD6433294F16 HD6433294F12 HD6433294TF16 HD6433294TF12 H8/3292 HD6433292P16 HD6433292P12 HD6433292F16 HD6433292F12 HD6433292TF16 HD6433292TF12
HD6473297P16 HD6473297F16 HD6473297TF16 HD6433297VP10 HD6433297VF10
HD6433297VTF10 80-pin TQFP (TFP-80C) HD6433296VP10 HD6433296VF10 64-pin shrink (DP-64S) 64-pin (FP-64A) Mask
HD6433296VTF10 80-pin TQFP (TFP-80C) HD6473294P16 HD6473294F16 HD6473294TF16 HD6433294VP10 HD6433294VF10 64-pin shrink (DP-64S) 64-pin (FP-64A) 80-pin TQFP (TFP-80C) 64-pin shrink (DP-64S) 64-pin (FP-64A) Mask PROM
HD6433294VTF10 80-pin TQFP (TFP-80C) HD6433292VP10 HD6433292VF10 64-pin shrink (DP-64S) 64-pin (FP-64A) Mask
HD6433292VTF10 80-pin TQFP (TFP-80C)
Block Diagram
Figure shows block diagram H8/3297 Series.
XTAL EXTAL
Clock pulse generator
STBY H8/300
Address
Data (Low) P10/A0 P11/A1 P12/A2 P13/A3 P14/A4 P15/A5 P16/A6 P17/A7
Data (High)
Port
Watchdog timer Serial communication interface
/IRQ 2/ADTRG /IRQ /IRQ /WAIT
16-bit freerunning timer Port
Port
8-bit timer channels)
10-bit converter channels)
P30/D0 P31/D1 P32/D2 P33/D3 P34/D4 P35/D5 P36/D6 P37/D7
Port
Port
Port
/FTCI/TMCI /FTOA /FTIA /FTIB/TMRI /FTIC/TMO /FTID/TMCI /FTOB/TMRI /TMO
AVCC AVSS
/TxD
/RxD
Figure Block Diagram
/SCK
Port
Assignments Functions
1.3.1 Arrangement Figure shows arrangement DC-64S DP-64S packages. Figure shows arrangement FP-64A package. Figure shows arrangement TFP-80C package.
P40/ADTRG/IRQ2 P41/IRQ1 P42/IRQ0 P43/RD P44/WR P45/AS P47/WAIT P50/TxD P51/RxD P52/SCK STBY XTAL EXTAL P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6 P77/AN7 P60/FTCI/TMCI0 P61/FTOA
P37/D7 P36/D6 P35/D5 P34/D4 P33/D3 P32/D2 P31/D1 P30/D0 P10/A0 P11/A1 P12/A2 P13/A3 P14/A4 P15/A5 P16/A6 P17/A7 P20/A8 P21/A9 P22/A10 P23/A11 P24/A12 P25/A13 P26/A14 P27/A15 P67/TMO1 P66/FTOB/TMRI1 P65/FTID/TMCI1 P64/FTIC/TMO0 P63/FTIB/TMRI0 P62/FTIA
Figure Arrangement (DC-64S DP-64S, view)
P22/A10
P24/A12
P25/A13
P30/D0 P31/D1 P32/D2 P33/D3 P34/D4 P35/D5 P36/D6 P37/D7 P40/ADTRG/IRQ2 P41/IRQ1 P42/IRQ0 P43/RD P44/WR P45/AS P47/WAIT
P26/A14
P23/A11
P10/A0
P11/A1
P12/A2
P13/A3
P14/A4
P15/A5
P16/A6
P17/A7
P20/A8
P21/A9
P27/A15 P67/TMO1 P66/FTOB/TMRI1 P65/FTID/TMCI1 P64/FTIC/TMO0 P63/FTIB/TMRI0 P62/FTIA P61/FTOA P60/FTCI/TMCI0 AVCC P77/AN7 P76/AN6 P75/AN5 P74/AN4 P73/AN3
P50/TxD
P51/RxD
XTAL
P52/SCK
EXTAL
STBY
P70/AN0
P71/AN1
Figure Arrangement (FP-64A, view)
P72/AN2
P22/A10
P23/A11
P24/A12
P25/A13
P30/D0 P31/D1 P32/D2 P33/D3 P34/D4 P35/D5 P36/D6 P37/D7 P40/ADTRG/IRQ2 P41/IRQ1 P42/IRQ0 P43/RD P44/WR P45/AS P47/WAIT
P26/A14
P10/A0
P11/A1
P12/A2
P13/A3
P14/A4
P15/A5
P16/A6
P17/A7
P20/A8
P21/A9
P27/A15 P67/TMO1 P66/FTOB/TMRI1 P65/FTID/TMCI1 P64/FTIC/TMO0 P63/FTIB/TMRI0 P62/FTIA P61/FTOA P60/FTCI/TMCI0 AVCC P77/AN7 P76/AN6 P75/AN5 P74/AN4 P73/AN3
P50/TxD
P51/RxD
P52/SCK
EXTAL
XTAL
STBY
P70/AN0
P71/AN1
Figure Arrangement (TFP-80C, view)
P72/AN2
AVSS
1.3.2 Functions Assignments Each Operating Mode: Table lists assignments pins DC-64S, DP-64S, FP-64A, TFP-80C packages each operating mode. Table Assignments Each Operating Mode
DC-64S DP-64S FP-64A TFP-80C Mode Expanded modes Mode Single-chip mode PROM Mode mode
P40/IRQ2/ADTRG P40/IRQ2/ADTRG P40/IRQ2/ADTRG EA16 P41/IRQ1 P42/IRQ0 P47/WAIT P50/TxD P51/RxD P52/SCK STBY XTAL EXTAL P41/IRQ1 P42/IRQ0 P47/WAIT P50/TxD P51/RxD P52/SCK STBY XTAL EXTAL P41/IRQ1 P42/IRQ0 P50/TxD P51/RxD P52/SCK STBY XTAL EXTAL EA15
Note: Pins marked should left unconnected. details PROM mode, refer 14.2, PROM Mode.
Table Assignments Each Operating Mode (cont)
DC-64S DP-64S FP-64A TFP-80C Mode AVSS P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6 P77/AN7 AVCC P60/FTCI/TMCI0 P61/FTOA P62/FTIA P63/FTIB/TMRI0 P64/FTIC/TMO0 P65/FTID/TMCI1 P66/FTOB/TMRI1 P67/TMO1 Expanded modes Mode AVSS P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6 P77/AN7 AVCC P60/FTCI/TMCI0 P61/FTOA P62/FTIA P63/FTIB/TMRI0 P64/FTIC/TMO0 P65/FTID/TMCI1 P66/FTOB/TMRI1 P67/TMO1 A27/A15 P26/A14 P25/A13 Single-chip mode PROM Mode AVSS P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6 P77/AN7 AVCC P60/FTCI/TMCI0 P61/FTOA P62/FTIA P63/FTIB/TMRI0 P64/FTIC/TMO0 P65/FTID/TMCI1 P66/FTOB/TMRI1 P67/TMO1 mode EA14 EA13
Note: Pins marked should left unconnected. details PROM mode, refer 14.2, PROM Mode.
Table Assignments Each Operating Mode (cont)
DC-64S DP-64S FP-64A TFP-80C Mode Expanded modes Mode P24/A12 P23/A11 P22/A10 P21/A9 P20/A8 P17/A7 P16/A6 P15/A5 P14/A4 P13/A3 P12/A2 P11/A1 P10/A0 Single-chip mode PROM Mode mode EA12 EA11 EA10
Note: Pins marked should left unconnected. details PROM mode, refer 14.2, PROM Mode.
Functions: Table gives concise description function each pin. Table Functions
Type Power Symbol DC-64S DP-64S FP-64A TFP-80C Name function Power: Connected power supply Connect both pins system power supply Ground: Connected ground Connect pins system ground
Clock
XTAL
Crystal: Connected crystal oscillator. crystal frequency should same desired system clock frequency. external clock input EXTAL pin, reverse-phase clock should input XTAL pin. External crystal: Connected crystal oscillator external clock. frequency external clock should same desired system clock frequency. section 6.2, Oscillator Circuit examples connections crystal external clock. System clock: Supplies system clock peripheral devices. Reset: input causes chip reset. Standby: transition hardware standby mode power-down state) occurs when input received STBY pin. Address bus: Address output pins.
EXTAL
System control STBY
Address
Table Functions (cont)
Type Data control Symbol WAIT DC-64S DP-64S FP-64A TFP-80C Name function Data bus: 8-Bit bidirectional data bus. Wait: Requests insert wait states into cycle when external address accessed. Read: Goes indicate that reading external address. Write: Goes indicate that writing external address. Address strobe: Goes indicate that there valid address address bus. Nonmaskable interrupt: Highestpriority interrupt request. NMIEG system control register (SYSCR) determines whether interrupt recognized rising falling edge input. Interrupt request Maskable interrupt request pins. Mode: Input pins setting operating mode according table below. Mode Description
Interrupt signals
IRQ0 IRQ2 Operating mode control MD1,
Mode Expanded mode with on-chip disabled Mode Expanded mode with on-chip enabled Mode Single-chip mode
Table Functions (cont)
Type Symbol DC-64S DP-64S FP-64A TFP-80C Name function output compare Output pins controlled comparators free-running timer. counter clock input: Input external clock signal free-running timer. input capture Input capture pins free-running timer. 8-bit timer output (channels Compare-match output pins 8-bit timers. 8-bit timer counter clock input (channels External clock input pins 8-bit timer counters. 8-bit timer counter reset input (channels High input these pins resets 8-bit timer counters. Transmit data: Data output serial communication interface. Receive data: Data input serial communication interface.
16-bit free- FTOA, running FTOB timer (FRT) FTCI
FTIA FTID 8-bit timer TMO0, TMO1 TMCI0, TMCI1 TMRI0, TMRI1
Serial communication interface (SCI)
Serial clock: Input/output serial clock. Analog input: Analog signal input pins converter. trigger: External trigger input starting converter. Programmable Wait Mode: number wait states (TW) selected bits inserted accesses external addresses, regardless WAIT state. Analog ground: Ground converter. Connect system ground.
converter
ADTRG AVCC
AVSS
Table Functions (cont)
Type Generalpurpose Symbol DC-64S DP-64S FP-64A TFP-80C Name function Port 8-bit input/output port with programmable input pull-ups driving capability. direction each selected port data direction register (P1DDR). Port 8-bit input/output port with programmable input pull-ups driving capability. direction each selected port data direction register (P2DDR). Port 8-bit input/output port with programmable input pull-ups. direction each selected port data direction register (P3DDR).
Port 8-bit input/output port. direction each selected port data direction register (P4DDR). Port 3-bit input/output port. direction each selected port data direction register (P5DDR).
Port 8-bit input/output port. direction each selected port data direction register (P6DDR). Port 8-bit input port.
Section
Overview
H8/300 fast central processing unit with eight 16-bit general registers (also configurable eight-bit registers) concise instruction designed high-speed operation. 2.1.1 Features main features H8/300 listed below. Two-way register configuration Sixteen 8-bit general registers, Eight 16-bit general registers Instruction with basic instructions, including: Multiply divide instructions Powerful bit-manipulation instructions Eight addressing modes Register direct (Rn) Register indirect (@Rn) Register indirect with displacement (@(d:16, Rn)) Register indirect with post-increment pre-decrement (@Rn+ @-Rn) Absolute address (@aa:8 @aa:16) Immediate (#xx:8 #xx:16) PC-relative (@(d:8, PC)) Memory indirect (@@aa:8)
Maximum 64-kbyte address space High-speed operation frequently-used instructions executed four states
Maximum clock rate clock): 16-bit register-register subtract: MHz), MHz), MHz) 8-bit multiply: MHz), 1167 MHz), 1400 MHz) 8-bit divide: MHz), 1167 MHz), 1400 MHz)
Power-down mode SLEEP instruction
2.1.2 Address Space H8/300 supports address space with maximum size kbytes program code data combined. memory differs depending mode (mode details, section 3.4, Address Space Each Operating Mode. 2.1.3 Register Configuration Figure shows internal register structure H8/300 CPU. There groups registers: general registers control registers.
General registers (Rn) (SP) Stack pointer
Control registers UHUNZ Program counter CCR: Condition code register Carry flag Overflow flag Zero flag Negative flag Half-carry flag Interrupt mask User User
Figure Registers
Register Descriptions
2.2.1 General Registers general registers used both data registers address registers. When used address registers, general registers accessed 16-bit registers R7). When used data registers, they accessed 16-bit registers, high bytes accessed separately 8-bit registers (R0H R7L). also functions stack pointer, used implicitly hardware processing interrupts subroutine calls. assembly-language coding, also denoted letters indicated figure 2-2, (SP) points stack.
Unused area (R7) Stack area
Figure Stack Pointer 2.2.2 Control Registers control registers include 16-bit program counter (PC) 8-bit condition code register (CCR). Program Counter (PC): This 16-bit register indicates address next instruction will execute. Each instruction accessed bits word), least significant ignored (always regarded Condition Code Register (CCR): This 8-bit register contains internal status information, including carry (C), overflow (V), zero (Z), negative (N), half-carry flags interrupt mask (I). 7-Interrupt Mask (I): When this interrupts except masked. This automatically reset start interrupt handling.
6-User (U): This written read software (using LDC, STC, ANDC, ORC, XORC instructions). 5-Half-Carry Flag (H): This flag when ADD.B, ADDX.B, SUB.B, SUBX.B, NEG.B, CMP.B instruction causes carry borrow cleared otherwise. Similarly, when ADD.W, SUB.W, CMP.W instruction causes carry borrow cleared otherwise. used implicitly instructions. 4-User (U): This written read software (using LDC, STC, ANDC, ORC, XORC instructions). 3-Negative Flag (N): This flag indicates most significant (sign bit) result instruction. 2-Zero Flag (Z): This flag indicate zero result cleared indicate nonzero result. 1-Overflow Flag (V): This flag when arithmetic overflow occurs, cleared other times. 0-Carry Flag (C): This flag used subtract instructions, indicate carry borrow most significant result Shift rotate instructions, store value shifted most significant least significant manipulation load instructions, accumulator
LDC, STC, ANDC, ORC, XORC instructions enable load store CCR, clear selected bits logic operations. flags used conditional branching instructions (BCC). action each instruction flag bits, H8/300 Series Programming Manual. 2.2.3 Initial Register Values When reset, program counter (PC) loaded from vector table interrupt mask other bits general registers initialized. particular, stack pointer (R7) initialized. stack pointer should initialized software, first instruction executed after reset.
Data Formats
H8/300 process 1-bit data, 4-bit (BCD) data, 8-bit (byte) data, 16-bit (word) data. manipulation instructions operate 1-bit data specified byte operand. arithmetic logic instructions except ADDS SUBS operate byte data. instruction perform decimal arithmetic adjustments byte data packed form. Each nibble byte treated decimal digit. MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU bits bits), DIVXU bits bits) instructions operate word data.
2.3.1 Data Formats General Registers Data sizes above stored general registers shown figure 2-3.
Data Type
Register
Data Format
1-bit data
Don't care
1-bit data
Don't care
Byte data
Don't care
Byte data
Don't care
Word data
Upper digit
Lower digit
4-bit data
Don't care
Upper digit
Lower digit
4-bit data
Don't care
Legend RnH: Upper digit general register RnL: Lower digit general register MSB: Most significant LSB: Least significant
Figure Register Data Formats
2.3.2 Memory Data Formats Figure indicates data formats memory. Word data stored memory must always begin even address. word access least significant address regarded address specified, address error occurs access performed preceding even address. This rule affects MOV.W instructions branching instructions, implies that only even addresses should stored vector table.
Data Type
Address
Data Format
1-bit data Byte data
Address Address Even address address Even address address Even address address
Word data
Upper bits Lower bits
Byte data (CCR) stack
CCR*
Word data stack
Note: Ignored return Legend CCR: Condition code register
Figure Memory Data Formats When stack addressed register must always accessed word time. When pushed stack, identical copies pushed make complete word. When they restored, lower byte ignored.
Addressing Modes
2.4.1 Addressing Mode H8/300 supports eight addressing modes. Each instruction uses subset these addressing modes. Table Addressing Modes
Addressing Mode Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Absolute address Immediate Program-counter-relative Memory indirect Symbol @(d:16, @Rn+ @-Rn @aa:8 @aa:16 #xx:8 #xx:16 @(d:8, @@aa:8
Register Direct-Rn: register field instruction specifies 16-bit general register containing operand. most cases general register accessed 8-bit register. Only MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU bits bits), DIVXU bits bits) instructions have 16-bit operands. Register Indirect-@Rn: register field instruction specifies 16-bit general register containing address operand. Register Indirect with Displacement-@(d:16, Rn): This mode, which used only instructions, similar register indirect instruction second word (bytes which added contents specified general register obtain operand address. MOV.W instruction, resulting address must even. Register Indirect with Post-Increment Pre-Decrement-@Rn+ @-Rn: Register indirect with Post-Increment-@Rn+ @Rn+ mode used with instructions that load registers from memory. similar register indirect mode, 16-bit general register specified register field instruction incremented after operand accessed. size increment depending size operand: MOV.B; MOV.W. MOV.W, original contents 16-bit general register must even.
Register Indirect with Pre-Decrement-@-Rn @-Rn mode used with instructions that store register contents memory. similar register indirect mode, 16-bit general register specified register field instruction decremented before operand accessed. size decrement depending size operand: MOV.B; MOV.W. MOV.W, original contents 16-bit general register must even.
Absolute Address-@aa:8 @aa:16: instruction specifies absolute address operand memory. MOV.B instruction uses 8-bit absolute address form H'FFxx. upper bits assumed possible address range H'FF00 H'FFFF (65280 65535). MOV.B, MOV.W, JMP, instructions 16-bit absolute addresses. Immediate-#xx:8 #xx:16: instruction contains 8-bit operand second byte, 16-bit operand third fourth bytes. Only MOV.W instructions contain 16-bit immediate values. ADDS SUBS instructions implicitly contain value immediate data. Some manipulation instructions contain 3-bit immediate data (#xx:3) second fourth byte instruction, specifying number. Program-Counter-Relative-@(d:8, PC): This mode used generate branch addresses instructions. 8-bit value byte instruction code added signextended value program counter contents. result must even number. possible branching range -126 +128 bytes (-63 words) from current address. Memory Indirect-@@aa:8: This mode used instructions. second byte instruction code specifies 8-bit absolute address from H'0000 H'00FF 255). word located this address contains branch address. upper bits absolute address (H'00), thus branch address limited values from (H'0000 H'00FF). Note that some addresses this range also used vector table. Refer section 3.4, Address Space Each Operating Mode. address specified branch destination operand address MOV.W instruction, least significant regarded causing word access performed address preceding specified address. section 2.3.2, Memory Data Formats, further information.
2.4.2 Calculation Effective Address Table shows H8/300 calculates effective addresses each addressing mode. Arithmetic, logic, shift instructions register direct addressing (1). ADD.B, ADDX.B, SUBX.B, CMP.B, AND.B, OR.B, XOR.B instructions also immediate addressing (6). instruction uses addressing modes except program-counter relative memory indirect (8). manipulation instructions register direct (1), register indirect (2), 8-bit absolute addressing identify byte operand, 3-bit immediate addressing identify within byte. BSET, BCLR, BNOT, BTST instructions also register direct addressing identify bit.
Table Effective Address Calculation
Effective Address Calculation
regm
Addressing Mode Instruction Format Effective Address regn
Register direct,
regm
regn
Operands contained registers regm regn 16-bit register contents
Register indirect,
16-bit register contents disp
Register indirect with displacement, @(d:16,
disp
Register indirect with post-increment, @Rn+
16-bit register contents
Register indirect with pre-decrement, @-Rn
16-bit register contents
Note: byte operand, word operand
Table Effective Address Calculation (cont)
Effective Address Calculation
H'FF
Addressing Mode Instruction Format Effective address
Absolute address @aa:8
@aa:16
Immediate #xx:8
Operand 2-byte immediate data
#xx:16
PC-relative @(d:8,
contents
Sign extension
disp
disp
Table Effective Address Calculation (cont)
Effective Address Calculation Effective Address
Addressing Mode Instruction Format
Memory indirect, @@aa:8
H'00
Memory contents bits)
Legend reg: General register Operation code disp: Displacement IMM: Immediate data abs: Absolute address
Instruction
H8/300 types instructions, which classified function table 2-3. Table Instruction Classification
Function Data transfer Arithmetic operations Logic operations Shift manipulation Branch System control Block data transfer Instructions MOV, MOVTPE*3, MOVFPE*3, PUSH*1, POP*1 ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA, DAS, MULXU, DIVXU, CMP, AND, XOR, SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR, BLD, BILD, BST, BIST Bcc*2, JMP, BSR, JSR, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, EEPMOV Types Total Notes: PUSH equivalent MOV.W @-SP. equivalent MOV.W @SP+, conditional branch instruction which represents condition code. supported H8/3297 Series.
following sections give concise summary instructions each category, indicate patterns their object code. notation used defined next. Operation Notation
(EAd) (EAs) #imm General register (destination) General register (source) General register Destination operand Source operand Stack pointer Program counter Condition code register (negative) flag (zero) flag (overflow) flag (carry) flag Immediate data #xx:3 #xx:8 #xx:16 disp 3-Bit immediate data 8-Bit immediate data 16-Bit immediate data Displacement Addition Subtraction Multiplication Division logical logical Exclusive logical Move
2.5.1 Data Transfer Instructions Table describes data transfer instructions. Figure shows their object code formats. Table Data Transfer Instructions
Instruction Size* Function (EAs) (EAd) Moves data between general registers between general register memory, moves immediate data general register. @Rn, @(d:16, Rn), @aa:16, #xx:8 #xx:16, @-Rn, @Rn+ addressing modes available byte word data. @aa:8 addressing mode available byte data only. @-R7 @R7+ modes require word operands. specify byte size these modes. supported H8/3437 Series. supported H8/3437 Series. @-SP Pushes 16-bit general register onto stack. Equivalent MOV.W @-SP. @SP+ Pops 16-bit general register from stack. Equivalent MOV.W @SP+,
MOVTPE MOVFPE PUSH
Note: Size: Operand size Byte Word
RmRn
@RmRn
disp
@(d:16, Rm)Rn
@Rm+Rn, Rn@-Rm
@aa:8Rn
@aa:16Rn
#xx:8Rn
#xx:16Rn
MOVFPE, MOVTPE
Legend Operation field Register field disp: Displacement Absolute address abs: IMM: Immediate data
POP, PUSH
Figure Data Transfer Instruction Codes
2.5.2 Arithmetic Operations Table describes arithmetic instructions. figure section 2.5.4, Shift Operations, their object codes. Table Arithmetic Instructions
Instruction Size* Function #imm Performs addition subtraction data general registers, addition immediate data data general register. Immediate data cannot subtracted from data general register. Word data added subtracted only when both words general registers. #imm Performs addition subtraction with carry borrow byte data general registers, addition subtraction immediate data data general register. Increments decrements general register. #imm Adds subtracts immediate data from data general register. immediate data must decimal adjust Decimal-adjusts (adjusts packed BCD) addition subtraction result general register referring CCR. Performs 8-bit 8-bit unsigned multiplication data general registers, providing 16-bit result. Performs 16-bit 8-bit unsigned division data general registers, providing 8-bit quotient 8-bit remainder. #imm Compares data general register with data another general register with immediate data. Word data compared only between general registers. Obtains two's complement (arithmetic complement) data general register.
ADDX SUBX
ADDS SUBS MULXU
DIVXU
Note: Size: Operand size Byte Word
2.5.3 Logic Operations Table describes four instructions that perform logic operations. figure section 2.5.4, Shift Operations, their object codes. Table Logic Operation Instructions
Instruction Size* Function #imm Performs logical operation general register another general register immediate data. #imm Performs logical operation general register another general register immediate data. #imm Performs logical exclusive operation general register another general register immediate data. (Rd) (Rd) Obtains one's complement (logical complement) general register contents.
Note: Size: Operand size Byte
2.5.4 Shift Operations Table describes eight shift instructions. Figure shows object code formats arithmetic, logic, shift instructions. Table Shift Instructions
Instruction SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR Size* Function shift Performs arithmetic shift operation general register contents. shift Performs logical shift operation general register contents. rotate Rotates general register contents. rotate through carry Rotates general register contents through (carry) bit.
Note: Size: Operand size Byte
ADD, SUB, CMP, ADDX, SUBX (Rm) ADDS, SUBS, INC, DEC, DAA, DAS, NEG,
MULXU, DIVXU
ADD, ADDX, SUBX, (#xx:8)
AND, (Rm)
AND, (#xx:8)
Legend Operation field Register field IMM: Immediate data
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR
Figure Arithmetic, Logic, Shift Instruction Codes
2.5.5 Manipulations Table describes bit-manipulation instructions. Figure shows their object code formats. Table Bit-Manipulation Instructions
Instruction BSET Size* Function (<bit no.> <EAd>) Sets specified general register memory specified number, given 3-bit immediate data lower three bits general register. (<bit no.> <EAd>) Clears specified general register memory specified number, given 3-bit immediate data lower three bits general register. (<bit no.> <EAd>) (<bit no.> <EAd>) Inverts specified general register memory. specified number, given 3-bit immediate data lower three bits general register (<bit no.> <EAd>) Tests specified general register memory sets clears flag accordingly. specified number, given 3-bit immediate data lower three bits general register. (<bit no.> <EAd>) ANDs flag with specified general register memory. (<bit no.> <EAd>)] ANDs flag with inverse specified general register memory. number specified 3-bit immediate data. (<bit no.> <EAd>) flag with specified general register memory. (<bit no.> <EAd>)] flag with inverse specified general register memory. number specified 3-bit immediate data. (<bit no.> <EAd>) XORs flag with specified general register memory.
BCLR
BNOT
BTST
BAND BIAND
BIOR
BXOR
Note: Size: Operand size Byte
Table Bit-Manipulation Instructions (cont)
Instruction BIXOR Size* Function [(<bit no.> <EAd>)] XORs flag with inverse specified general register memory. number specified 3-bit immediate data. (<bit no.> <EAd>) Copies specified general register memory flag. (<bit no.> <EAd>) Copies inverse specified general register memory flag. number specified 3-bit immediate data. (<bit no.> <EAd>) Copies flag specified general register memory. (<bit no.> <EAd>) Copies inverse flag specified general register memory. number specified 3-bit immediate data.
BILD
BIST
Note: Size: Operand size Byte
Notes Manipulation Instructions: BSET, BCLR, BNOT, BST, BIST read-modifywrite instructions. They read byte data, modify byte, then write byte back. Care required when these instructions applied registers with write-only bits port registers.
Step Read Modify Write Description Read data byte specified address Modify data byte Write modified data byte back specified address
Example BCLR executed clear port data direction register (P1DDR) under following conditions. P17: Input pin, P16: Input pin, high P10: Output pins, intended purpose this BCLR instruction switch from output input.
Before Execution BCLR Instruction
Input/output state Input Input High Output Output Output Output Output Output
Execution BCLR Instruction BCLR @P1DDR ;clear data direction register
After Execution BCLR Instruction
Input/output state Output Output High Output Output Output Output Output Input High
Explanation: execute BCLR instruction, begins reading P1DDR. Since P1DDR write-only register, read H'FF, even though true value H'3F. Next clears read data, changing value H'FE. Finally, writes this value (H'FE) back P1DDR complete BCLR instruction. result, P10DDR cleared making input pin. addition, P17DDR P16DDR making output pins.
BSET, BCLR, BNOT, BTST
Operand: register direct (Rn) no.: immediate (#xx:3) Operand: register direct (Rn) no.: register direct (Rm)
Operand: register indirect (@Rn) no.:
immediate (#xx:3)
Operand: register indirect (@Rn) no.:
register direct (Rm)
Operand: absolute (@aa:8) no.:
immediate (#xx:3)
Operand: absolute (@aa:8) no.: register direct (Rm)
BAND, BOR, BXOR, BLD,
Operand: register direct (Rn) no.: immediate (#xx:3)
Operand: register indirect (@Rn) no.:
immediate (#xx:3)
Operand: absolute (@aa:8) no.: immediate (#xx:3)
Legend Operation field Register field abs: Absolute address IMM: Immediate data
Figure Manipulation Instruction Codes
2.5.6 Branching Instructions Table describes branching instructions. Figure shows their object code formats. Table Branching Instructions
Instruction Size Function Branches condition true. Mnemonic (BT) (BF) (BHS) (BLO) field 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description Always (true) Never (false) High same Carry clear (High same) Carry (low) equal Equal Overflow clear Overflow Plus Minus Greater equal Less than Greater than Less equal Condition Always Never CZ=0 CZ=1 NV=0 NV=1
Branches unconditionally specified address. Branches subroutine specified address. Branches subroutine specified displacement from current address. Returns from subroutine.
disp
(@Rm)
(@aa:16)
(@@aa:8)
disp
(@Rm)
(@aa:16)
(@@aa:8)
Legend Operation field Condition field Register field disp: Displacement abs: Absolute address
Figure Branching Instruction Codes
2.5.7 System Control Instructions Table 2-10 describes system control instructions. Figure shows their object code formats. Table 2-10 System Control Instructions
Inst5ruction SLEEP Size Function Returns from exception-handling routine. Causes transition power-down state. CCR, #imm Moves immediate data general register contents condition code register. Copies condition code register specified general register. #imm Logically ANDs condition code register with immediate data. #imm Logically condition code register with immediate data. #imm Logically exclusive-ORs condition code register with immediate data. Only increments program counter.
ANDC XORC
Note: Size: Operand size Byte
RTE, SLEEP,
LDC, (Rn)
ANDC, ORC, XORC, (#xx:8)
Legend Operation field Register field IMM: Immediate data
Figure System Control Instruction Codes
2.5.8 Block Data Transfer Instruction Table 2-11 describes EEPMOV instruction. Figure 2-10 shows object code format. Table 2-11 Block Data Transfer Instruction/EEPROM Write Operation Instruction
EEPMOV
Size
Function then repeat until else next; Moves data block according parameters general registers R4L, R4L: size block (bytes) starting source address starting destination address Execution next instruction starts soon block transfer completed. @R5+ @R6+
Legend Operation field
Figure 2-10 Block Data Transfer Instruction/EEPROM Write Operation Code
Notes EEPMOV Instruction EEPMOV instruction block data transfer instruction. moves number bytes specified from address specified address specified
When setting make sure that final destination address R4L) does exceed H'FFFF. value must change from H'FFFF H'0000 during execution instruction.
H'FFFF allowed
States
2.6.1 Overview three states: program execution state, exception-handling state, power-down state. power-down state further divided into three modes: sleep mode, software standby mode, hardware standby mode. Figure 2-11 summarizes these states, figure 2-12 shows state transitions.
State
Program execution state executes successive program instructions. Exception-handling state transient state triggered reset interrupt. executes hardware sequence that includes loading program counter from vector table. Power-down state state which some chip functions stopped conserve power. Sleep mode Software standby mode Hardware standby mode
Figure 2-11 Operating States
Exception handling request Exceptionhandling state
Program execution state Exception handing Interrupt request
SLEEP instruction with SSBY SLEEP instruction
Sleep mode
IRQ0 IRQ2
Software standby mode
Reset state
STBY
Hardware standby mode Power-down state
Notes: transition reset state occurs when goes low, except when chip hardware standby mode. transition from state hardware standby mode occurs when STBY goes low.
Figure 2-12 State Transitions 2.6.2 Program Execution State this state executes program instructions. 2.6.3 Exception-Handling State exception-handling state transient state that occurs when reset interrupted changes normal processing flow. interrupt exception handling, references stack pointer (R7) saves program counter condition code register stack. further details section Exception Handling. 2.6.4 Power-Down State power-down state includes three modes: sleep mode, software standby mode, hardware standby mode. Sleep Mode: entered when SLEEP instruction executed. halts, register contents remain unchanged on-chip supporting modules continue function.
Software Standby Mode: entered SLEEP instruction executed while SSBY (Software Standby) system control register (SYSCR) set. on-chip supporting modules halt. on-chip supporting modules initialized, contents onchip registers remain unchanged long specified voltage supplied. port outputs also remain unchanged. Hardware Standby Mode: entered when input STBY goes low. chip functions halt, including port output. on-chip supporting modules initialized, onchip contents held. section Power-Down State, further information.
Access Timing Cycle
driven system clock period from rising edge system clock next referred "state." Memory access performed two- three-state cycle. On-chip memory, on-chip supporting modules, external devices accessed different cycles described below. 2.7.1 Access On-Chip Memory (RAM ROM) On-chip accessed cycle states designated Either byte word data accessed, 16-bit data bus. Figure 2-13 shows on-chip memory access cycle. Figure 2-14 shows associated states.
cycle
state
state
Internal address
Address
Internal read signal
Internal data (read)
Read data
Internal write signal
Internal data (write)
Write data
Figure 2-13 On-Chip Memory Access Cycle
cycle
state
state
Address
Address
High High High Data bus: high impedance state
Figure 2-14 States during On-Chip Memory Access Cycle
2.7.2 Access On-Chip Register Field External Devices on-chip supporting module registers external devices accessed cycle consisting three states: Only byte data accessed cycle, 8-bit data bus. Access word data instruction codes requires consecutive cycles (six states). Figure 2-15 shows access cycle on-chip register field. Figure 2-16 shows associated states. Figures 2-17 show read write access timing external devices.
cycle
state Internal address Internal read signal Internal data (read) Internal write signal Internal data (write)
state
state
Address
Read data
Write data
Figure 2-15 On-Chip Register Field Access Cycle
cycle
state
state
state
Address
Address
High High High Data bus: high impedance state
Figure 2-16 States during On-Chip Register Field Access Cycle
Read cycle
state
state
state
Address
Address
High Data
Read data
Figure 2-17 External Device Access Timing (Read)
Write cycle
state
state
state
Address
Address
High
Data
Write data
Figure 2-17 External Device Access Timing (Write)
Section Operating Modes Address Space
Overview
3.1.1 Mode Selection H8/3297 Series operates three modes numbered mode selected inputs mode pins (MD1 MD0). table 3-1. Table Operating Modes
Mode Mode Mode Mode Mode High High High High Address space Expanded Expanded Single-chip On-chip Disabled Enabled Enabled On-chip Enabled* Enabled* Enabled
Note: RAME system control register (SYSCR) cleared off-chip memory accessed instead.
Modes expanded modes that permit access off-chip memory peripheral devices. maximum address space supported these externally expanded modes kbytes. mode (single-chip mode), only on-chip on-chip register field used. ports available general-purpose input output. Mode inoperative H8/3297 Series. Avoid setting mode pins mode
3.1.2 Mode System Control Registers Table lists registers related chip's operating mode: system control register (SYSCR) mode control register (MDCR). mode control register indicates inputs mode pins MD0. Table Mode System Control Registers Name
System control register Mode control register
Abbreviation
SYSCR MDCR
Read/Write
Address
H'FFC4 H'FFC5
System Control Register (SYSCR)
Initial value Read/Write SSBY STS2 STS1 STS0 XRST NMIEG RAME
system control register (SYSCR) 8-bit register that controls operation chip. 7-Software Standby (SSBY): Enables transition software standby mode. details, section Power-Down State. recovery from software standby mode external interrupt, SSBY remains cleared writing
SSBY Description SLEEP instruction causes transition sleep mode. SLEEP instruction causes transition software standby mode. (Initial value)
Bits 4-Standby Timer Select (STS2 STS0): These bits select clock settling time when chip recovers from software standby mode external interrupt. During selected time on-chip supporting modules continue stand These bits should according clock frequency that settling time least specific settings, section 15.3.3, Clock Settling Time Exit from Software Standby Mode.
STS2 STS1 STS0
Description Settling time 8,192 states Settling time 16,384 states Settling time 32,768 states Settling time 65,536 states Settling time 131,072 states Disabled (Initial value)
3-External Reset (XRST): Indicates source reset. reset generated input external reset signal, watchdog timer overflow when watchdog timer used. XRST read-only bit. external reset, cleared watchdog timer overflow.
XRST Description Reset caused watchdog timer overflow. Reset caused external input. (Initial value)
2-NMI Edge (NMIEG): Selects valid edge input.
NMIEG Description interrupt requested falling edge input. interrupt requested rising edge input. (Initial value)
1-Reserved: This cannot modified always read 0-RAM Enable (RAME): Enables disables on-chip RAM. RAME initialized reset, initialized software standby mode.
RAME Description on-chip disabled. on-chip enabled. (Initial value)
Mode Control Register (MDCR)
Initial value Read/Write MDS1 MDS0
Note: Initialized according inputs.
mode control register (MDCR) 8-bit register that indicates operating mode chip. Bits 5-Reserved: These bits cannot modified always read Bits 3-Reserved: These bits cannot modified always read 2-Reserved: This cannot modified always read Bits 0-Mode Select (MDS1 MDS0): These bits indicate values mode pins (MD1 MD0), thereby indicating current operating mode chip. MDS1 corresponds MDS0 MD0. These bits read written. When mode control register read, levels mode pins (MD1 MD0) latched these bits.
Address Space Each Operating Mode
Figures show memory maps H8/3297, H8/3296, H8/3294, H8/3292 modes
Mode Expanded Mode without On-Chip H'0000 Vector table H'0049 H'004A H'0049 H'004A H'0000
Mode Expanded Mode with On-Chip H'0000 Vector table H'0049 H'004A
Mode Single-Chip Mode
Vector table
On-chip ROM, PROM 61,312 bytes On-chip ROM, PROM 63,360 bytes
External address space
H'EF7F H'EF80 External address apace H'F77F H'F780 On-chip RAM*, 2,048 bytes H'FF7F H'FF80 External address space H'FF87 H'FF88 On-chip register field H'FFFF H'F77F H'F780 On-chip RAM*, 2,048 bytes H'FF7F H'FF80 External address space H'FF87 H'FF88 On-chip register field H'FFFF H'FF7F H'FF88 H'FFFF H'FF7F H'F780 On-chip RAM, 2,048 bytes
On-chip register field
Note: External memory accessed these addresses when RAME system control register (SYSCR) cleared
Figure H8/3297 Address Space
Mode Expanded Mode without On-Chip H'0000 Vector table H'0049 H'004A H'0049 H'004A H'0000
Mode Expanded Mode with On-Chip H'0000 Vector table H'0049 H'004A
Mode Single-Chip Mode
Vector table
On-chip 49,152 bytes
On-chip 49,152 bytes
External address space
H'BFFF H'C000
H'BFFF
Reserved*1 H'EF7F H'EF80 External address space H'F77F H'F780 On-chip 2,048 bytes H'FF7F H'FF80 External address space H'FF87 H'FF88 On-chip register field H'FFFF H'F77F H'F780 On-chip 2,048 bytes H'FF7F H'FF80 External address space H'FF87 H'FF88 On-chip register field H'FFFF H'FF7F H'FF88 On-chip register field H'FFFF H'F77F H'F780 On-chip 2,048 bytes Reserved*1
Notes: access reserved areas. External memory accessed these addresses when RAME system control register (SYSCR) cleared
Figure H8/3296 Address Space
Mode Expanded Mode without On-Chip H'0000 Vector table H'0049 H'004A H'0049 H'004A H'0000
Mode Expanded Mode with On-Chip H'0000 Vector table H'0049 H'004A
Mode Single-Chip Mode
Vector table
On-chip ROM, PROM 32,768 bytes
On-chip ROM, PROM 32,768 bytes
External address space
H'7FFF H'8000
H'7FFF
External address space
H'FB7F H'FB80
H'FF7F H'FF80 External address space H'FF87 H'FF88 On-chip register field H'FFFF
On-chip 1,024 bytes
H'FB7F H'FB80
H'FF7F H'FF80 External address space H'FF87 H'FF88 On-chip register field H'FFFF
On-chip 1,024 bytes
H'FB80 H'FF7F H'FF88
On-chip 1,024 bytes
On-chip register field H'FFFF
Notes: External memory accessed these addresses when RAME system control register (SYSCR) cleared
Figure H8/3294 Address Space
Mode Expanded Mode without On-Chip H'0000 Vector table H'0049 H'004A H'0049 H'004A H'0000
Mode Expanded Mode with On-Chip H'0000 Vector table H'0049 H'004A
Mode Single-Chip Mode
Vector table
On-chip ROM, PROM 16,384 bytes
On-chip ROM, PROM 16,384 bytes
External address space
H'3FFF H'4000 Reserved*1 H'7FFF H'8000 External address apace H'FB7F H'FB80 H'FD7F H'FD80 H'FB7F H'FB80 H'FD7F H'FD80
H'3FFF H'4000 Reserved*1 H'7FFF
Reserved*1,*2 On-chip RAM*2, bytes
Reserved*1,*2 On-chip RAM*2, bytes
H'FB80 H'FD7F H'FD80 H'FF7F H'FF88 H'FFFF
Reserved*1 On-chip RAM, bytes
H'FF7F H'FF80 External address space H'FF87 H'FF88 On-chip register field H'FFFF
H'FF7F H'FF80 External address space H'FF87 H'FF88 On-chip register field H'FFFF
On-chip register field
Note: access reserved areas. External memory accessed these addresses when RAME system control register (SYSCR) cleared
Figure H8/3292 Address Space
Section Exception Handling
Overview
H8/3297 Series recognizes kinds exceptions: interrupts reset. Table indicates their priority timing their hardware exception-handling sequence. Table Hardware Exception-Handling Sequences Priority
Priority High Type Exception Reset Interrupt Detection Timing Synchronized with clock instruction execution* Timing Exception-Handling Sequence hardware exception-handling sequence begins soon changes from high. When interrupt requested, hardware exception-handling sequence begins current instruction, current hardware exception-handling sequence.
Note: detected after ANDC, ORC, XORC, instructions.
Reset
4.2.1 Overview reset highest exception-handling priority. When goes low, when there watchdog timer reset (when reset option selected watchdog timer overflow), current processing stops chip enters reset state. internal state registers on-chip supporting modules initialized. reset exception-handling sequence starts when returns from high, watchdog reset pulse. 4.2.2 Reset Sequence reset state begins when goes watchdog reset generated. ensure correct resetting, power-on should held least reset during operation, should held least system clock cycles. watchdog reset pulse width always system clocks. states during reset, appendix States. following sequence carried when reset exception handling begins. internal state registers on-chip supporting modules initialized, condition code register (CCR) loads program counter with first word vector table (stored addresses H'0000 H'0001) starts program execution. should held when power switched off, well when power switched
Figure indicates timing reset sequence modes Figure indicates timing mode
Vector fetch RES/watchdog timer reset (internal) Internal address Internal read signal Internal write signal Internal data bits) Reset vector address (H'0000) Starting address program First instruction program
Internal Instruction processing prefetch
Figure Reset Sequence (Mode Program Stored On-Chip ROM)
Vector fetch RES/watchdog timer reset (internal)
Internal processing
Instruction prefetch
bits)
(1), (2), (5), (6),
Reset vector address: H'0000, H'0001 Starting address program (contents reset vector): upper byte, lower byte Starting address program: (4), First instruction program: first byte, second byte
Figure Reset Sequence (Mode
4.2.3 Disabling Interrupts after Reset After reset, interrupt were accepted before initialization stack pointer (SP: R7), program counter condition code register might saved correctly, leading program crash. prevent this, interrupts, including NMI, disabled immediately after reset. first program instruction therefore always executed. This instruction should initialize stack pointer (example: MOV.W #xx:16, SP). After reset exception handling, order initialize contents CCR, manipulation instruction executed before instruction initialize stack pointer. Immediately after execution manipulation instruction, interrupts including disabled. next instruction initialize stack pointer.
Interrupts
4.3.1 Overview interrupt sources include four external sources (NMI, IRQ0 IRQ2), internal sources on-chip supporting modules. Table lists interrupt sources priority order gives their vector addresses. When more interrupts requested, interrupt with highest priority served first. features these interrupts are: highest priority always accepted. internal external interrupts except masked CCR. When interrupts other than accepted. IRQ0 IRQ2 sensed falling edge input signal, level-sensed. type sensing selected each interrupt individually. edge-sensed, either rising falling edge selected. interrupts individually vectored. software interrupt-handling routine does have determine what type interrupt occurred. watchdog timer generate either overflow interrupt, depending needs application. details, section Watchdog Timer.
Table Interrupts
Interrupt source IRQ0 IRQ1 IRQ2 Reserved ICIA (Input capture ICIB (Input capture ICIC (Input capture ICID (Input capture OCIA (Output compare OCIB (Output compare FOVI (Overflow) CMI0A (Compare-match CMI0B (Compare-match OVI0 (Overflow) CMI1A (Compare-match CMI1B (Compare-match OVI1 (Overflow) (Receive error) (Receive end) (TDR empty) (TSR empty) (Conversion end) WOVF (WDT overflow) Vector Table Address Priority H'0006 H'0007 H'0008 H'0009 H'000A H'000B H'000C H'000D H'000E H'000F H'0010 H'0011 H'0012 H'0013 H'0014 H'0015 H'0016 H'0017 H'0018 H'0019 H'001A H'001B H'001C H'001D H'001E H'001F H'0020 H'0021 H'0022 H'0023 H'0024 H'0025 H'0026 H'0027 H'0028 H'0029 H'002A H'002B H'002C H'002D H'002E H'002F H'0030 H'0031 H'0032 H'0033 H'0034 H'0035 H'0036 H'0037 H'0038 H'0039 H'003A H'003B H'003C H'003D H'003E H'003F H'0040 H'0041 H'0042 H'0043 H'0044 H'0045 H'0046 H'0047 H'0048 H'0049 High
16-bit freerunning timer
8-bit timer
8-bit timer
Reserved Serial communication interface Reserved
converter Watchdog timer
Notes: H'0000 H'0001 contain reset vector. H'0002 H'0005 reserved H8/3297 Series available user.
4.3.2 Interrupt-Related Registers interrupt-related registers system control register (SYSCR), sense control register (ISCR), enable register (IER). Table Registers Read Interrupt Controller
Name System control register sense control register enable register Abbreviation SYSCR ISCR Read/write Address H'FFC4 H'FFC6 H'FFC7
System Control Register (SYSCR)
Initial value Read/Write SSBY STS2 STS1 STS0 XRST NMIEG RAME
valid edge line controlled (NMIEG) system control register. 2-NMI Edge (NMIEG): Determines whether nonmaskable interrupt generated falling rising edge input signal.
NMIEG Description interrupt generated falling edge NMI. interrupt generated rising edge NMI. (Initial state)
section 3.2, System Control Register, information other SYSCR bits. Sense Control Register (ISCR)-H'FFC6
Initial value Read/Write
IRQ2SC IRQ1SC IRQ0SC
Bits 3-Reserved: These bits cannot modified always read
Bits 0-IRQ2 IRQ0 Sense Control (IRQ2SC IRQ0SC): These bits determine whether IRQ2 IRQ0 level-sensed sensed falling edge.
Bits IRQ2SC IRQ0SC Description interrupt generated when IRQ2 IRQ0 inputs low. (Initial state)
interrupt generated falling edge IRQ2 IRQ0 inputs.
Enable Register (IER)
Initial value Read/Write IRQ2E IRQ1E IRQ0E
Bits 3-Reserved: These bits cannot modified always read Bits 0-IRQ2 IRQ0 Enable (IRQ2E IRQ0E): These bits enable disable IRQ2 IRQ0 interrupts individually.
Bits IRQ2E IRQ0E IRQ2 IRQ0 interrupt requests disabled. IRQ2 IRQ0 interrupt requests enabled. Description (Initial state)
When edge sensing selected setting bits IRQ2SC IRQ0SC possible interrupt-handling routine executed even though corresponding enable (IRQ2E IRQ0E) cleared interrupt disabled. interrupt requested while enable (IRQ2E IRQ0E) request will held pending until served. enable cleared while request still pending, request will remain pending, although requests will recognized. interrupt mask cleared interrupthandling routine executed even though enable execution interrupt-handling routines under these conditions desired, avoided using following procedure disable clear interrupt requests. CCR, masking interrupts. Note that automatically when execution jumps interrupt vector. Clear desired bits from IRQ2E IRQ0E disable interrupt requests. Clear corresponding IRQ2SC IRQ0SC bits then them again. Pending IRQn interrupt requests cleared when CCR, IRQnSC IRQnE
4.3.3 External Interrupts four external interrupts IRQ2 IRQ0. These four interrupts used recover from software standby mode. NMI: nonmaskable interrupt generated rising falling edge input signal regardless whether (interrupt mask) CCR. valid edge selected NMIEG system control register. vector number hardware exception-handling sequence IRQ2 IRQ0: These interrupt signals level-sensed sensed falling edge input, selected ISCR bits IRQ2SC IRQ0SC. These interrupts masked collectively CCR, enabled disabled individually setting clearing bits IRQ2E IRQ0E enable register. When these interrupts accepted, IRQ2 IRQ0 have interrupt vector numbers They prioritized order from IRQ2 (low) IRQ0 (high). details, table 4-2. Interrupts IRQ2 IRQ0 depend whether pins IRQ2 IRQ0 input output pins. When using external interrupts IRQ2 IRQ0, clear corresponding bits these pins input state, these pins input output pins timers, serial communication interface, converter. 4.3.4 Internal Interrupts Nineteen internal interrupts requested on-chip supporting modules. Each interrupt source vector number, interrupt-handling routine does have determine which interrupt occurred. internal interrupts masked when When these interrupts accepted, mask further interrupts (except NMI). vector numbers priority order, table 4-2.
4.3.5 Interrupt Handling Interrupts controlled interrupt controller that arbitrates between simultaneous interrupt requests, commands start hardware interrupt exception-handling sequence, furnishes necessary vector number. Figure shows block diagram interrupt controller.
interrupt IRQ0 flag IRQ0E IRQ0 interrupt Priority decision
Interrupt controller
Interrupt request
Vector number
WOVF interrupt
(CCR)
Note: edge-sensed interrupts, these gates change circuit shown below. IRQ0 edge IRQ0E IRQ0 flag
IRQ0 interrupt
Figure Block Diagram Interrupt Controller interrupts interrupts from on-chip supporting modules (except reset selected watchdog timer overflow) have corresponding enable bits. When enable cleared interrupt signal sent interrupt controller, interrupt ignored. These interrupts also masked setting CPU's interrupt mask Accordingly, these interrupts accepted only when their enable cleared nonmaskable interrupt (NMI) always accepted, except reset state hardware standby mode.
When another enabled interrupt requested, interrupt controller transfers interrupt request indicates corresponding vector number. (When more interrupts requested, interrupt controller selects vector number interrupt with highest priority.) When notified interrupt request, current instruction current hardware exception-handling sequence, starts hardware exception-handling sequence interrupt latches vector number. Figure flowchart interrupt (and reset) operations. Figure shows interrupt timing sequence case which software interrupt-handling routine on-chip stack on-chip RAM. interrupt request sent interrupt controller when interrupt occurs, when interrupt occurs input line on-chip supporting module provided enable that interrupt interrupt controller checks accepts interrupt request cleared only requests accepted; other interrupt requests remain pending. Among accepted interrupt requests, interrupt controller selects request with highest priority passes CPU. Other interrupt requests remain pending. When receives interrupt request, waits until completion current instruction hardware exception-handling sequence, then starts hardware exception-handling sequence interrupt latches interrupt vector number. hardware exception-handling sequence, first pushes onto stack. figure 4-5. stacked indicates address first instruction that will executed return from software interrupt-handling routine. Next masking further interrupts except NMI. vector address corresponding vector number generated, vector table entry this vector address loaded into program counter, execution branches software interrupt-handling routine address indicated that entry.
Program execution
Interrupt requested? NMI?
IRQ0? IRQ1? WOVF? Pending
Latch vector
Save
Reset
Save
Read vector address
Branch software interrupt-handling routine
Figure Hardware Interrupt-Handling Sequence
(R7) Stack area
SP(R7)
CCR* (upper byte) (lower byte) Even address
Before interrupt accepted
Pushed onto stack
After interrupt accepted
Program counter CCR: Condition code register Stack pointer Notes: contains address first instruction executed after return. Registers must saved restored word access even address. Ignored return.
Figure Usage Stack Interrupt Handling comprised byte, when saved stack, treated word data. During interrupt processing, identical bytes data saved stack create word data. When instruction executed restore value from stack, byte located even address loaded into CCR, byte located address ignored.
Interrupt accepted Interrupt priority decision. Wait Instruction Internal instruction. prefetch processing Interrupt request signal Vector fetch
Stack
Instruction prefetch (first instruction Internal interrupt-handling process- routine)
Internal address
Internal read signal Internal write signal
Internal 16-bit data
(10)
Instruction prefetch address (Pushed stack. Instruction executed return from interrupt-handling routine.) Instruction code (Not executed) Instruction prefetch address (Not executed) SP-2 SP-4 Address vector table entry Vector table entry (address first instruction interrupt-handling routine) (10) First instruction interrupt-handling routine
Figure Timing Interrupt Sequence
4.3.6 Interrupt Response Time Table indicates number states that elapse from interrupt request signal until first instruction software interrupt-handling routine executed. Since on-chip memory accessed bits time, very fast interrupt service obtained placing interrupt-handling routines on-chip stack on-chip RAM. Table Number States before Interrupt Service
Number States Reason Wait Interrupt priority decision Wait completion current instruction*1 Save Fetch vector Fetch instruction Internal processing Total On-Chip Memory External Memory 17*2 12*2 12*2
Notes: These values apply current instruction EEPMOV. wait states inserted external memory access, number wait states. internal interrupts.
4.3.7 Precaution Note that following type contention occur interrupt handling. When software clears enable interrupt disable interrupt, interrupt becomes disabled after execution clearing instruction. enable cleared BCLR instruction, example, interrupt requested during execution that instruction, instant when instruction ends interrupt still enabled, after execution instruction, hardware exception-handling sequence executed interrupt. higherpriority interrupt requested same time, however, hardware exception-handling sequence executed higher-priority interrupt interrupt that disabled ignored. Similar considerations apply when interrupt request flag cleared Figure shows example which OCIAE cleared
write cycle TIER Internal address TIER address
OCIA interrupt handling
Internal write signal OCIAE OCFA OCIA interrupt signal
Figure Contention between Interrupt Disabling Instruction above contention does occur enable flag cleared while interrupt mask
Note Stack Handling
word access, least significant address always assumed stack always accessed word access. Care should taken keep even value stack pointer (general register R7). PUSH MOV.W @-SP MOV.W @SP+, instructions push registers stack. Setting stack pointer value cause programs crash. Figure shows example damage caused when stack pointer contains address.
H'FECC H'FECD
H'FECF
instruction
MOV.B R1L, @-R7
H'FECF
improperly stored beyond stack
lost
PCH: PCL: R1L:
Upper byte program counter Lower byte program counter General register Stack pointer
Figure Example Damage Caused Setting Address
Section Wait-State Controller
Overview
H8/3297 Series on-chip wait-state controller that enables insertion wait states into cycles interfacing low-speed external devices. 5.1.1 Features Features wait-state controller listed below. Three selectable wait modes: programmable wait mode, auto-wait mode, wait mode Automatic insertion zero three wait states
5.1.2 Block Diagram Figure shows block diagram wait-state controller.
Internal data
WAIT
Wait-state controller (WSC) WSCR
Wait request signal
Legend WSCR: Wait-state control register
Figure Block Diagram Wait-State Controller
5.1.3 Input/Output Pins Table summarizes wait-state controller's input pin. Table Wait-State Controller Pins
Name Wait Abbreviation WAIT Input Function Wait request signal access external addresses
5.1.4 Register Configuration Table summarizes wait-state controller's register. Table Register Configuration
Address H'FFC2 Name Wait-state control register Abbreviation WSCR Initial Value H'08
Register Description
5.2.1 Wait-State Control Register (WSCR) WSCR 8-bit readable/writable register that selects wait mode wait-state controller (WSC) specifies number wait states. also controls frequency division clock signals supplied supporting modules.
Initial value Read/Write CKDBL WMS1 WMS0
WSCR initialized H'08 reset hardware standby mode. initialized software standby mode.
Bits 6-Reserved 5-Clock Double (CKDBL): Controls frequency division clock signals supplied supporting modules. details, section Clock Pulse Generator. 4-Reserved: This reserved, written read. initial value Bits 2-Wait Mode Select (WMS1/0): These bits select wait mode.
WMS1 WMS0 Description Programmable wait mode wait states inserted wait-state controller wait mode auto-wait mode (Initial value)
Bits 0-Wait Count (WC1/0): These bits select number wait states inserted access external address areas.
Description wait states inserted wait-state controller state inserted states inserted states inserted (Initial value)
Wait Modes
Analog power supply: Analog power supply converter. converter used, connect AVCC system power supply (VCC). Figure shows timing when wait count
Address
External address
Read access Data Read data
Write access Data Write data
Figure Programmable Wait Mode
Wait Mode: accesses external addresses, number wait states (TW) selected bits inserted. WAIT fall system clock last these wait states, additional wait state inserted. WAIT remains low, wait states continue inserted until WAIT signal goes high. wait mode useful inserting four more wait states, inserting different numbers wait states different external devices. Figure shows timing when wait count (WC1 additional wait state inserted WAIT input.
Inserted wait count
Inserted WAIT signal
WAIT Address External address
Read access
Read data Data
Write access Data Write data
Note: Arrows indicate time sampling WAIT pin.
Figure Wait Mode
Auto-Wait Mode: WAIT low, number wait states (TW) selected bits inserted. auto-wait mode, WAIT fall system clock state, number wait states (TW) selected bits inserted. additional wait states inserted even WAIT remains low. auto-wait mode used easy interface low-speed memory, simply routing chip select signal WAIT pin. Figure shows timing when wait count
WAIT
Address
External address
External address
Read access Data Read data Read data
Write access Data Write data Write data
Note: Arrows indicate time sampling WAIT pin.
Figure Auto-Wait Mode
Section Clock Pulse Generator
Overview
H8/3297 Series built-in clock pulse generator (CPG) consisting oscillator circuit, duty adjustment circuit, divider prescaler that generates clock signals on-chip supporting modules. 6.1.1 Block Diagram Figure shows block diagram clock pulse generator.
XTAL EXTAL
Oscillator circuit
Duty adjustment circuit
(system clock)
(for supporting modules) Prescaler
Frequency divider (1/2) CKDBL
Figure Block Diagram Clock Pulse Generator Input external clock signal EXTAL pin, connect crystal resonator XTAL EXTAL pins. system clock frequency will same input frequency. This same system clock frequency supplied timers other supporting modules, divided two. selection made software, controlling CKDBL bit.
6.1.2 Wait-State Control Register (WSCR) WSCR 8-bit readable/writable register that controls frequency division clock signals supplied supporting modules. also controls wait-state insertion. WSCR initialized H'08 reset hardware standby mode. initialized software standby mode.
Initial value Read/Write CKDBL WMS1 WMS0
Bits 6-Reserved 5-Clock Double (CKDBL): Controls frequency division clock signals supplied supporting modules.
CKDBL Description undivided system clock supplied clock supporting modules. (Initial value) system clock divided supplied clock supporting modules.
4-Reserved: This reserved, written read. initial value Bits 2-Wait Mode Select (WMS1/0) Bits 0-Wait Count (WC1/0) These bits control wait-state insertion. details, section Wait-State Controller.
Oscillator Circuit
external crystal connected across EXTAL XTAL pins, on-chip oscillator circuit generates system clock signal. Alternatively, external clock signal applied EXTAL pin. Connecting External Crystal Circuit Configuration: external crystal connected example figure 6-2. Table indicates appropriate damping resistance AT-cut parallel resonance crystal should used.
EXTAL
XTAL
Figure Connection Crystal Oscillator (Example) Table Damping Resistance
Frequency (MHz)
Crystal Oscillator: Figure shows equivalent circuit crystal resonator. crystal resonator should have characteristics listed table 6-2.
XTAL EXTAL
AT-cut parallel resonating crystal
Figure Equivalent Circuit External Crystal Table External Crystal Parameters
Frequency (MHz) (pF)
crystal with same frequency desired system clock frequency
Note Board Design: When external crystal connected, other signal lines should kept away from crystal circuit prevent induction from interfering with correct oscillation. figure 6-4. crystal load capacitors should placed close possible XTAL EXTAL pins.
allowed
Signal
Signal
XTAL
EXTAL
Figure Notes Board Design around External Crystal
Input External Clock Signal Circuit Configuration: external clock signal input shown examples figure 6-5. example figure 6-5, external clock signal should kept high during standby. XTAL left open, make sure stray capacitance does exceed
EXTAL
External clock input
XTAL
Open
Connections with XTAL left open
EXTAL 74HC04 XTAL
External clock input
Connections with inverted clock input XTAL
Figure External Clock Input (Example)
External Clock Input external clock signal should have same frequency desired system clock Clock timing parameters given table figure 6-6. Table Clock Timing
Item Symbol pulse tEXL width external clock input High pulse tEXH width external clock input External clock rise time External clock fall time Clock pulse width Clock pulse width high tEXr tEXf ±10% Unit Test Conditions Figure
tcyc tcyc tcyc tcyc Figure 16-4
tEXH
tEXL
EXTAL
tEXr
tEXt
Figure External Clock Input Timing
Table shows external clock output settling delay time, figure shows external clock output settling delay timing. oscillator duty adjustment circuit have function adjusting waveform external clock input EXTAL pin. When specified clock signal input EXTAL pin, internal clock signal output settles after elapse external clock output settling delay time (tDEXT). clock signal output remains unsettled during tDEXT period, reset signal should driven retain reset state. Table External Clock Output Settling Delay Time Conditions: AVCC AVSS
Item External clock output settling delay time Symbol tDEXT* Unit Note Figure
Note: tDEXT includes pulse width (tRESW) tcyc.
2.7V
STBY
EXTAL (Internal extenal)
tDEXT*
Note: tDEXT includes pulse width (tRESW) tcyc.
Figure External Clock Output Settling Delay Time
Duty Adjustment Circuit
When clock frequency above, duty adjustment circuit adjusts duty cycle signal from oscillator circuit generate system clock
Prescaler
clock on-chip supporting modules either same frequency system clock this frequency divided two, depending CKDBL bit. prescaler divides frequency generate internal clock signals with frequencies from
Section Ports
Overview
H8/3297 Series five 8-bit input/output ports, 8-bit input port, 3-bit input/output port. Table lists functions each port each operating mode. table indicates, port pins multiplexed, functions differ depending operating mode. Each port data direction register (DDR) that selects input output, data register (DR) that stores output data. manipulation instructions will executed port data direction registers, "Notes Manipulation Instructions" section 2.5.5, Manipulation Instructions. Ports drive load 90-pF capacitive load. Port drive load 30-pF capacitive load. Ports drive LEDs (with 10-mA current sink). Ports drive darlington pair. Ports have built-in pull-up transistors. block diagrams ports, appendix Port Block Diagrams.
Table Port Functions
Expanded Modes Port Port Description 8-bit port drive LEDs Built-in input pull-ups 8-bit port drive LEDs Built-in input pull-ups 8-bit port Built-in input pull-ups Pins P10/A7 Mode Lower address output Mode Lower address output general input Upper address output (A15 general input Single-Chip Mode Mode General input/output
Port
P20/A15
Upper address output (A15
General input/output
Port
P30/
Data
General input/output
Port
8-bit port
P47/WAIT
Expanded data control input (WAIT)/ General General input/output input/output
P45/AS P44/WR P43/RD P42/IRQ0 P41/IRQ1 P40/IRQ2/ADTRG Port 3-bit port P52/SCK P51/RxD P50/TxD P67/TMO1 P66/FTOB/TMRI1 P65/FTID/TMCI1 P64/FTIC/TMO0 P63/FTIB/TMRI0 P62/FTIA P61/FTOA P60/FTCI/TMCI0
System clock output Expanded data control output (RD,
output general input General input/output
Trigger input converter (ADTRG), external interrupt input (IRQ2 IRQ0), general input/output Serial communication interface input/output (TxD,RxD, SCK) general input/output 16-bit free-running timer input/output (FTCI, FTOA, FTIA, FTIB, FTIC, FTID, FTOB), 8-bit timer input/output (TMCI0, TMO0, TMRI0, TMCI1, TMO1, TMRI1) general input/output
Port
8-bit port
Port
8-bit input port
Analog input converter (AN7 AN0) general input
Port
7.2.1 Overview Port 8-bit input/output port with configuration shown figure 7-1. functions differ depending operating mode. Port built-in, software-controllable input pull-up transistors that used modes Pins port drive load 90-pF capacitive load. They also drive LEDs darlington transistors.
Port pins P17/A7 P16/A6 P15/A5 Port P14/A4 P13/A3 P12/A2 P11/A1 P10/A0
configuration mode (expanded mode with on-chip disabled) (output) (output) (output) (output) (output) (output) (output) (output)
configuration mode (expanded mode with on-chip enabled) (output)/P17 (input) (output)/P16 (input) (output)/P15 (input) (output)/P14 (input)) (output)/P13 (input) (output)/P12 (input) (output)/P11 (input) (output)/P10 (input)
configuration mode (single-chip mode) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output)
Figure Port Configuration
7.2.2 Register Configuration Descriptions Table summarizes port registers. Table Port Registers
Name Port data direction register Port data register Port input pull-up control register Abbreviation P1DDR P1DR P1PCR Read/Write Initial Value H'FF (mode H'00 (modes H'00 H'00 Address H'FFB0 H'FFB2 H'FFAC
Port Data Direction Register (P1DDR)
Mode Initial value Read/Write Modes Initial value Read/Write
P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR
P1DDR controls input/output direction each port Mode P1DDR values fixed Port consists lower address output pins. P1DDR values cannot modified always read hardware standby mode, address high-impedance state. Mode port used address output corresponding P1DDR general input this cleared Mode port used general output corresponding P1DDR general input this cleared modes P1DDR write-only register. Read data invalid. read, bits always read P1DDR initialized H'00 reset hardware standby mode. software standby mode retains existing values, transition software standby mode occurs while P1DDR corresponding remains output state.
Port Data Register (P1DR)
Initial value Read/Write
P1DR 8-bit register that stores data pins P10. When P1DDR port read, value P1DR obtained directly, regardless actual state. When P1DDR cleared port read state obtained. P1DR initialized H'00 reset hardware standby mode. software standby mode retains existing values. Port Input Pull-Up Control Register (P1PCR)
Initial value Read/Write
P17PCR P16PCR P15PCR P14PCR P13PCR P12PCR P11PCR P10PCR
P1PCR 8-bit readable/writable register that controls input pull-up transistors port P1DDR cleared (designating input) corresponding P1PCR input pull-up transistor turned P1PCR initialized H'00 reset hardware standby mode. software standby mode retains existing values.
7.2.3 Functions Each Mode Port different functions different modes. separate description each mode given below. Functions Mode mode (expanded mode with on-chip disabled), port automatically used lower address output A0). Figure shows functions mode
(output) (output) (output) Port (output) (output) (output) (output) (output)
Figure Functions Mode (Port
Mode mode (expanded mode with on-chip enabled), port provide lower address output pins general input pins. Each becomes lower address output P1DDR general input this cleared Following reset, pins input pins. used address output, their P1DDR bits must Figure shows functions mode
When P1DDR (output) (output) (output) Port (output) (output) (output) (output) (output)
When P1DDR (input) (input) (input) (input) (input) (input) (input) (input)
Figure Functions Mode (Port
Mode mode (single-chip mode), input output direction each selected individually. becomes general input when P1DDR cleared general output when this Figure shows functions mode
(input/output) (input/output) (input/output) Port (input/output) (input/output) (input/output) (input/output) (input/output)
Figure Functions Mode (Port 7.2.4 Input Pull-Up Transistors Port built-in programmable input pull-up transistors that available modes pull-up each turned individually. turn input pull-up mode corresponding P1PCR clear corresponding P1DDR P1PCR cleared H'00 reset hardware standby mode, turning input pull-ups off. software standby mode, previous state maintained. Table indicates states input pull-up transistors each operating mode. Table States Input Pull-Up Transistors (Port
Mode Reset Hardware Standby Software Standby On/off On/off Other Operating Modes On/off On/off
Notes: Off: input pull-up transistor always off. On/off: input pull-up transistor P1PCR P1DDR otherwise.
Port
7.3.1 Overview Port 8-bit input/output port with configuration shown figure 7-5. functions differ depending operating mode. Port built-in, software-controllable input pull-up transistors that used modes Pins port drive load 90-pF capacitive load. They also drive LEDs darlington transistors.
configuration mode (expanded mode with on-chip disabled) (output) (output) (output) (output) (output) (output) (output) (output) configuration mode (expanded mode with on-chip enabled) (output)/P27 (input) (output)/P26 (input) (output)/P25 (input) (output)/P24 (input) (output)/P23 (input) (output)/P22 (input) (output)/P21 (input) (output)/P20 (input)
Port pins P27/A15 P26/A14 P25/A13 Port P24/A12 P23/A11 P22/A10 P21/A9 P20/A8
configuration mode (single-chip mode) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output)
Figure Port Configuration
7.3.2 Register Configuration Descriptions Table summarizes port registers. Table Port Registers
Name Port data direction register Port data register Port input pull-up control register Abbreviation P2DDR P2DR P2PCR Read/Write Initial Value H'FF (mode H'00 (modes H'00 H'00 Address H'FFB1 H'FFB3 H'FFAD
Port Data Direction Register (P2DDR)
Mode Initial value Read/Write Modes Initial value Read/Write
P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR
P2DDR controls input/output direction each port Mode P2DDR values fixed Port consists upper address output pins. P2DDR values cannot modified always read hardware standby mode, address high-impedance state. Mode port used address output corresponding P2DDR general input this cleared Mode port used general output corresponding P2DDR general input this cleared modes P2DDR write-only register. Read data invalid. read, bits always read P2DDR initialized H'00 reset hardware standby mode. software standby mode retains existing values, transition software standby mode occurs while P2DDR corresponding remains output state.
Port Data Register (P2DR)
Initial value Read/Write
P2DR 8-bit register that stores data pins P20. When P2DDR port read, value P2DR obtained directly, regardless actual state. When P2DDR cleared port read state obtained. P2DR initialized H'00 reset hardware standby mode. software standby mode retains existing values. Port Input Pull-Up Control Register (P2PCR)
Initial value Read/Write
P27PCR P26PCR P25PCR P24PCR P23PCR P22PCR P21PCR P20PCR
P2PCR 8-bit readable/writable register that controls input pull-up transistors port P2DDR cleared (designating input) corresponding P2PCR input pull-up transistor turned P2PCR initialized H'00 reset hardware standby mode. software standby mode retains existing values.
7.3.3 Functions Each Mode Port different functions different modes. separate description each mode given below. Functions Mode mode (expanded mode with on-chip disabled), port automatically used upper address output (A15 A8). Figure shows functions mode
(output) (output) (output) Port (output) (output) (output) (output) (output)
Figure Functions Mode (Port
Mode mode (expanded mode with on-chip enabled), port provide upper address output pins general input pins. Each becomes upper address output P2DDR general input this cleared Following reset, pins input pins. used address output, their P2DDR bits must Figure shows functions mode
When P2DDR (output) (output) (output) Port (output) (output) (output) (output) (output)
When P2DDR (input) (input) (input) (input) (input) (input) (input) (input)
Figure Functions Mode (Port
Mode mode (single-chip mode), input output direction each selected individually. becomes general input when P2DDR cleared general output when this Figure shows functions mode
(input/output) (input/output) (input/output) Port (input/output) (input/output) (input/output) (input/output) (input/output)
Figure Functions Mode (Port
7.3.4 Input Pull-Up Transistors Port built-in programmable input pull-up transistors that available modes pull-up each turned individually. turn input pull-up mode corresponding P2PCR clear corresponding P2DDR P2PCR cleared H'00 reset hardware standby mode, turning input pull-ups off. software standby mode, previous state maintained. Table indicates states input pull-up transistors each operating mode. Table States Input Pull-Up Transistors (Port
Mode Reset Hardware Standby Software Standby On/off On/off Other Operating Modes On/off On/off
Notes: Off: input pull-up transistor always off. On/off: input pull-up transistor P2PCR P2DDR otherwise.
Port
7.4.1 Overview Port 8-bit input/output port with configuration shown Figure 7-9. functions differ depending operating mode. Port built-in, software-controllable input pull-up transistors that used mode Pins port drive load 90-pF capacitive load. They also drive darlington pair.
Port pins P37/D7 P36/D6 P35/D5 Port P34/D4 P33/D3 P32/D2 P31/D1 P30/D0
configuration mode (expanded mode with on-chip disabled) mode (expanded mode with on-chip enabled) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) configuration mode (single-chip mode) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output)
Figure Port Configuration
7.4.2 Register Configuration Descriptions Table summarizes port registers. Table Port Registers
Name Port data direction register Port data register Port input pull-up control register Abbreviation P3DDR P3DR P3PCR Read/Write Initial Value H'00 H'00 H'00 Address H'FFB4 H'FFB6 H'FFAE
Port Data Direction Register (P3DDR)
Initial value Read/Write
P3DDR 8-bit readable/writable register that controls input/output direction each port P3DDR write-only register. Read data invalid. read, bits always read Modes mode (expanded mode with on-chip disabled) mode (expanded mode with on-chip enabled), input/output directions designated P3DDR ignored. Port automatically consists input/output pins 8-bit data D0). data high-impedance state during reset, during hardware software standby. Mode port used general output corresponding P3DDR general input this cleared P3DDR initialized H'00 reset hardware standby mode. software standby mode retains existing values, transition software standby mode occurs while P3DDR corresponding remains output state.
Port Data Register (P3DR)
Initial value Read/Write
P3DR 8-bit register that stores data pins P30. When P3DDR port read, value P3DR obtained directly, regardless actual state. When P3DDR cleared port read state obtained. P3DR initialized H'00 reset hardware standby mode. software standby mode retains existing values. Port Input Pull-Up Control Register (P3PCR)
Initial value Read/Write
P37PCR P36PCR P35PCR P34PCR P33PCR P32PCR P31PCR P30PCR
P3PCR 8-bit readable/writable register that controls input pull-up transistors port P3DDR cleared (designating input) corresponding P3PCR input pull-up transistor turned P3PCR initialized H'00 reset hardware standby mode. software standby mode retains existing values. input pull-ups cannot used slave mode (when host interface enabled).
7.4.3 Functions Each Mode Port different functions different modes. separate description each mode given below. Functions Modes mode (expanded mode with on-chip disabled) mode (expanded mode with on-chip enabled), port automatically used input/output pins data D0). Figure 7-10 shows functions modes
Modes (input/output) (input/output) (input/output) Port (input/output) (input/output) (input/output) (input/output) (input/output)
Figure 7-10 Functions Modes (Port
Mode mode (single-chip mode), input output direction each selected individually. becomes general input when P3DDR cleared general output when this Figure 7-11 shows functions mode
(input/output) (input/output) (input/output) Port (input/output) (input/output) (input/output) (input/output) (input/output)
Figure 7-11 Functions Mode (Port 7.4.4 Input Pull-Up Transistors Port built-in programmable input pull-up transistors that available mode pull-up each turned individually. turn input pull-up mode corresponding P3PCR clear corresponding P3DDR P3PCR cleared H'00 reset hardware standby mode, turning input pull-ups off. software standby mode, previous state maintained. Table indicates states input pull-up transistors each operating mode. Table States Input Pull-Up Transistors (Port
Mode Reset Hardware Standby Software Standby On/off Other Operating Modes On/off
Notes: Off: input pull-up transistor always off. On/off: input pull-up transistor P3PCR P3DDR otherwise.
Port
7.5.1 Overview Port 8-bit input/output port that multiplexed with interrupt input pins (IRQ0 IRQ2), input/output pins control signals (RD, WAIT), input (ADTRG) converter, output system clock. Figure 7-12 shows configuration port Pins port drive load 90-pF capacitive load.
Port pins P47/WAIT P45/AS Port P44/WR P43/RD P42/IRQ0 P41/IRQ1
configuration mode (expanded mode with on-chip disabled) mode (expanded mode with on-chip enabled) P47/WAIT (input) (output) (output) (output) (output) (input/output)/IRQ0 (input) (input/output)/IRQ1 (input)
P40/IRQ2/ADTRG (input) (input/output)/IRQ2 (input)/ADTRG (input) configuration mode (single-chip mode) (input/output) (output) (input/output) (input/output) (input/output) (input/output)/IRQ0 (input) (input/output)/IRQ1 (input) (input/output)/IRQ2 /ADTRG (input)
Figure 7-12 Port Configuration
7.5.2 Register Configuration Descriptions Table summarizes port registers. Table Port Registers
Name Port data direction register Port data register Abbreviation P4DDR P4DR Read/Write R/W*1 Initial Value H'40 (modes H'00 (mode Undetermined*2 Address H'FFB5 H'FFB7
Notes: read-only. undetermined. Other bits initially
Port Data Direction Register (P4DDR)
Modes Initial value Read/Write Mode Initial value Read/Write
P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR P41DDR P40DDR
P4DDR 8-bit readable/writable register that controls input/output direction each port functions output corresponding P4DDR input this cleared modes P46DDR fixed cannot modified. P4DDR write-only register. Read data invalid. read, bits always read P4DDR initialized reset hardware standby mode. initial value H'40 modes H'00 mode software standby mode P4DDR retains existing values, transition software standby mode occurs while P4DDR corresponding remains output state.
Port Data Register (P4DR)
Initial value Read/Write
Note: Determined level P46.
P4DR 8-bit register that stores data pins P40. When P4DDR port read, value P4DR obtained directly, regardless actual state, except P46. When P4DDR cleared port read state obtained. This also applies pins used on-chip supporting modules control signals. always returns state. P4DR initialized H'00 reset hardware standby mode. software standby mode retains existing values. 7.5.3 Functions Port functions modes different functions mode pins multiplexed with IRQ0 IRQ2 input, control signal input/output, converter input, system clock output. Table indicates functions port Table Port Functions
P47/WAIT Functions Selection Method P47DDR, operating mode, wait mode determined WSCR select function follws Operating mode Wait mode P47DDR function WAIT used WAIT input Modes WAIT used (WMS1=0, WMS0=1) input output input Mode output
P46DDR operating mode select function follows Operating mode P46DDR function Modes Always output input Mode
output
Table 7-19 Port Functions (cont)
Functions Selection Method P45DDR operating mode select function follows Operating mode P45DDR function P44/WR Modes output input Mode output
P45/AS
P44DDR operating mode select function follows Operating mode P44DDR function Modes output input Mode output
P43/RD
P43DDR operating mode select function follows Operating mode P43DDR function Modes output input Mode output
P42/IRQ0 P42DDR function input IRQ0 input IRQ0 input used when IRQ0E P41/IRQ1 P41DDR function input IRQ1 input IRQ1 input used when IRQ1E P40/IRQ2/ ADTRG P40DDR function input IRQ2 input ADTRG input IRQ2 input used when IRQ2E ADTRG input used when TRGE ADCR output output output
Port
7.6.1 Overview Port 3-bit input/output port that multiplexed with input/output pins (TxD, RxD, SCK) serial communication interface. port functions same operating modes. Figure 7-13 shows configuration port Pins port drive load 30-pF capacitive load. They also drive darlington pair.
Port pins (input/output)/SCK (input/output) Port (input/output)/RxD (input) (input/output)/TxD (output)
Figure 7-13 Port Configuration 7.6.2 Register Configuration Descriptions Table 7-10 summarizes port registers. Table 7-10 Port Registers
Name Port data direction register Port data register Abbreviation P5DDR P5DR Read/Write Initial Value H'F8 H'F8 Address H'FFB8 H'FFBA
Port Data Direction Register (P5DDR)
Initial value Read/Write
P5DDR 8-bit register that controls input/output direction each port functions output corresponding P5DDR input this cleared P5DDR write-only register. Read data invalid. read, bits always read P5DDR initialized H'F8 reset hardware standby mode. software standby mode retains existing values, transition software standby mode occurs while P5DDR corresponding remains output state. transition software standby mode occurs while port being used SCI, will initialized, will revert general-purpose input/output, controlled P5DDR P5DR. Port Data Register (P5DR)
Initial value Read/Write
P5DR 8-bit register that stores data pins P50. Bits reserved. They cannot modified, always read When P5DDR port read, value P5DR obtained directly, regardless actual state. When P5DDR cleared port read state obtained. This also applies pins used pins. P5DR initialized H'F8 reset hardware standby mode. software standby mode retains existing values.
7.6.3 Functions Port same functions each operating mode. pins also used input/output pins. Table 7-11 indicates functions port Table 7-11 Port Functions
P52/SCK Functions Selection Method SCI, bits CKE0 CKE1 SCI, P52DDR select function follows CKE1 CKE0 P52DDR function input output output output input
P51/RxD
P51DDR select function follows P51DDR function input output input
P50/TxD
P50DDR select function follows P50DDR function input output output
Port
7.7.1 Overview Port 8-bit input/output port that multiplexed with input/output pins (FTOA, FTOB, FTIA FTID, FTCI) 16-bit free-running timer (FRT) with input/output pins (TMRI0, TMRI1, TMCI0, TMCI1, TMO0, TMO1) 8-bit timers port functions same operating modes. Figure 7-14 shows configuration port Pins port drive load 90-pF capacitive load. They also drive darlington pair.
Port pins (input/output)/TMO1 (output) (input/output)/FTOB (output)/TMRI1 (input) (input/output)/FTID (input)/TMCI1 (input) Port (input/output)/FTIC (input)/TMO0 (output) (input/output)/FTIB (input)/TMRI0 (input) (input/output)/FTIA (input) (input/output)/FTOA (output) (input/output)/FTCI (input)/TMCI0 (input)
Figure 7-14 Port Configuration
7.7.2 Register Configuration Descriptions Table 7-12 summarizes port registers. Table 7-12 Port Registers
Name Port data direction register Port data register Abbreviation P6DDR P6DR Read/Write Initial Value H'00 H'00 Address H'FFB9 H'FFBB
Port Data Direction Register (P6DDR)
Initial value Read/Write
P67DDR P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR
P6DDR 8-bit readable/writable register that controls input/output direction each port functions output corresponding P6DDR input this cleared P6DDR write-only register. Read data invalid. read, bits always read P6DDR initialized H'00 reset hardware standby mode. software standby mode retains existing values, transition software standby mode occurs while P6DDR corresponding remains output state. transition software standby mode occurs while port being used on-chip supporting module (for example, 8-bit timer output), on-chip supporting module will initialized, will revert general-purpose input/output, controlled P6DDR P6DR.
Port Data Register (P6DR)
Initial value Read/Write
P6DR 8-bit register that stores data pins P60. When P6DDR port read, value P6DR obtained directly, regardless actual state. When P6DDR cleared port read state obtained. This also applies pins used on-chip supporting modules. P6DR initialized H'00 reset hardware standby mode. software standby mode retains existing values.
7.7.3 Functions Port same functions operating modes. pins multiplexed with input/output, 8-bit timer input/output. Table 7-13 indicates functions port Table 7-13 Port Functions
P67/TMO1 Functions Selection Method Bits TCSR 8-bit timer P67DDR, select function follows P67DDR function P66/FTOB/ TMRI1 input output TMO1 output
TOCR P66DDR select function follows P66DDR function input output TMRI1 input TMRI1 input usable when bits CCLR1 CCLR0 both 8-bit timer FTOB output
P65/FTID/ TMCI1
P65DDR function
input
output
FTID input TMCI1 input TMCI1 input usable when bits CKS2 CKS0 8-bit timer select external clock source P64/FTIC/ TMO0 Bits TCSR 8-bit timer P64DDR select function follows P64DDR function input output FTIC input TMO0 output
Table 7-13 Port Functions (cont)
P63/FTIB/ TMRI0 Functions Selection Method P63DDR function input output
FTIB input TMRI0 input TMRI0 input usable when bits CCLR1 CCLR0 both 8bit timer P62/FTIA P62DDR function input FTIA input P61/FTOA TOCR P61DDR select function follows P61DDR function P60/FTCI/ TMCI0 input output FTOA output output
P60DDR function
input
output
FTCI input TMCI0 input FTCI input usable when bits CKS1 CKS0 select external clock source TMCI0 input usable when bits CKS2 CKS0 8-bit timer select external clock source
Port
7.8.1 Overview Port 8-bit input port that also provides analog input pins converter. functions same modes. Figure 7-15 shows configuration port
Port pins (input)/AN7 (input) (input)/AN6 (input) (input)/AN5 (input) Port (input)/AN4 (input) (input)/AN3 (input) (input)/AN2 (input) (input)/AN1 (input) (input)/AN0 (input)
Figure 7-15 Port Configuration
7.8.2 Register Configuration Descriptions Table 7-14 summarizes port registers. Port input port, there data direction register. Table 7-14 Port Register
Name Port input register Abbreviation P7PIN Read/Write Initial Value Undetermined Address H'FFBE
Port Input Register (P7PIN)
Initial value Read/Write
Note: Depends levels pins P70.
When P7PIN read, states always read. P7PIN read-only register cannot written
Section 16-Bit Free-Running Timer
Overview
H8/3297 Series on-chip 16-bit free-running timer (FRT) module that uses 16-bit freerunning counter time base. Applications module include rectangular-wave output independent waveforms), input pulse width measurement, measurement external clock periods. 8.1.1 Features features free-running timer module listed below. Selection four clock sources free-running counter driven internal clock source external clock input (enabling external event counter). independent comparators Each comparator generate independent waveform. Four input capture channels current count captured rising falling edge (selectable) input signal. four input capture registers used separately, buffer mode. Counter cleared under program control free-running counters cleared compare-match Seven independent interrupts Compare-match input capture overflow interrupts requested independently.
8.1.2 Block Diagram Figure shows block diagram free-running timer.
External clock source FTCI Clock select
Internal clock sources Clock Comparematch OCRA (H/L)
Comparator
FTOA0 FTOB0
Overflow Clear Comparator
interface
(H/L)
Internal data
Comparematch
OCRB (H/L) Control logic FTIA FTIB FTIC FTID TCSR TIER TOCR ICIA ICIB ICIC ICID OCIA OCIB FOVI
Capture
ICRA (H/L) ICRB (H/L) ICRC (H/L) ICRD (H/L)
Interrupt signals
Legend FRC: Free-running counter bits) Output compare register bits) OCRA, ICRA, Input capture register bits) TCSR: Timer control/status register bits)
TIER: Timer interrupt enable register bits) TCR: Timer control register bits) TOCR: Timer output compare control register bits)
Figure Block Diagram 16-Bit Free-Running Timer
Module data
8.1.3 Input Output Pins Table lists input output pins free-running timer module. Table Input Output Pins Free-Running Timer Module
Name Counter clock input Output compare Output compare Input capture Input capture Input capture Input capture Abbreviation FTCI FTOA FTOB FTIA FTIB FTIC FTID Input Output Output Input Input Input Input Function Input external free-running counter clock signal Output controlled comparator Output controlled comparator Trigger capturing current count into input capture register Trigger capturing current count into input capture register Trigger capturing current count into input capture register Trigger capturing current count into input capture register
8.1.4 Register Configuration Table lists registers free-running timer module. Table Register Configuration
Name Timer interrupt enable register Timer control/status register Free-running counter (high) Free-running counter (low) Output compare register (high)*2 Output co
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