PM8316 TEMUX PROPRIETARY CONFIDENTIAL RELEASED ISSUE JANUARY 2003
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RELEASED DATA SHEET PMC-1991437 ISSUE
PM8316 TEMUX
PROPRIETARY CONFIDENTIAL RELEASED ISSUE JANUARY 2003
PMC-Sierra, Inc.
DATA SHEET
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER MULTIPLEXER
8555 Baxter Place Burnaby, Canada .415.6000
TEMUX
PM8316
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
RELEASED DATA SHEET PMC-1991437 ISSUE
PM8316 TEMUX
PMC-1991437 (R8), PMC-1991191 (P9)
Disclaimer
Trademarks
PMC-Sierra, Inc.
technology discussed protected more following Patents: U.S. Patent 5,640,398 Canadian patent 2,161,921 Relevant patent applications other patents also exist.
Patents
TEMUX, SBI, PMC-Sierra trademarks PMC-Sierra, Inc.
event will PMC-Sierra, Inc. liable direct, indirect, special, incidental consequential damages, including, limited lost profits, lost business lost data resulting from reliance upon information, whether PMC-Sierra, Inc. been advised possibility such damage.
None information contained this document constitutes express implied warranty PMC-Sierra, Inc. sufficiency, fitness suitability particular purpose such information fitness, suitability particular purpose, merchantability, performance, compatibility with other parts systems, products PMC-Sierra, Inc., portion thereof, referred this document. PMC-Sierra, Inc. expressly disclaims representations warranties kind regarding contents information, including, limited express implied warranties accuracy, completeness, merchantability, fitness particular use, non-infringement.
8555 Baxter Place Burnaby, Canada .415.6000
information proprietary confidential PMC-Sierra, Inc., customers' internal use. event, cannot reproduce part this document, form, without express written consent PMC-Sierra, Inc.
2003 PMC-Sierra, Inc.
Copyright
Legal Information
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
RELEASED DATA SHEET PMC-1991437 ISSUE
PM8316 TEMUX
1999 2000 2000 2001 2001
Original Document. Advance version. Upgrade document from Preview Advance
Preliminary version released conjunction with Rev. tapeout Datasheet updated reflect Issue PMC-1991191.
marked corrections text.
Change Section HDLC interface with bytes buffering terminating facility data link.
New: Figure TEMUX Block Diagram
either ingress egress signals routed framers monitoring HDLC termination.
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
Ingress Flexible Bandwidth Enables (IFBWEN[3:1]). IFBWEN[3:1] inputs constrained such that maximum data rate each IFBWDAT[3:1] less than 48.96 Mbit/s.
System Reference Clock (SREFCLK). This clock must phase locked LREFCLK external connected LREFCLK. When passing transparent virtual tributaries between telecom bus, SREFCLK must same frequency LREFCLK (i.e. L77). Change second note table: outputs TCLK[3:1], TPOS/TDAT[3:1], TNEG/TMFP[3:1], RGAPCLK/RSCLK[3:1], RDATO[3:1], RFPO/RMFPO[3:1], ROVRHD[3:1], TFPO/TMFPO/TGAPCLK[3:1], SBIACT, LAOE/LATPL, RECVCLK1, RECVCLK2, RECVCLK3, CASID[21:1], CCSID, TS0ID, INTB have drive capability. bidirectional signal SDC1FP drive capability. MVID[21:1] have drive capability. Changes section New: Section Change Section 9.3: ESF, out-of-frame declaration based strictly Frame Alignment Signal (F1-F6) errors; frame search never initiated upon
Framer Recovered Clock (RSCLK[3:1]). When demapped from SONET/SDH (i.e. LINEOPT_SPEx 01), RSCLK gapped version CLK52M.
Changes table:
performance monitoring purposes, which include error event accumulation, alarm
Change Section this configuration transmit framers disabled
New: Figure Fractional Application
buses.
Change Section Seamlessly interfaces with 77.76 Drop 77.76
Datasheet updated reflect Issue PMC-1991191. sections noted below
Issue
Issue Date
Details Change
REVISION HISTORY
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
RELEASED DATA SHEET PMC-1991437 ISSUE
PM8316 TEMUX
Change Section 9.6: Received data placed into 127-byte FIFO buffer.
Changes Section 9.21: New: Table Path Signal Label Mismatch State New: Section 19.37.1
Change Section 9.43: (48.96 Mbit/s).
New: Section 9.43.1 Burst Lengths Ingress Flexible Bandwidth Port
0x0157 0x01E9 0x01EA 0x0F20 0x40*N
SIGX Configuration INSBI Thresholds Register
Change Section 12.2.2: When TVTs supported additional constraint exists
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
New: Table Constraints 77.76MHz Change Section 12.2.3: TVTs supported this configuration. Change Section 12.3.2: framer will determine frame alignment within 13ms Change Step 12.8: PBS[2:0] 1XX, discard data byte read step decrement PACKET COUNT, check PBS[1:0] bits errors before deciding whether keep packet. Changes Section 12.14 Change text just before Table signaling contained within robbed positions DS0s will also have arbitrary alignment relative P1P0 bits. Change text just after Table When carrying framed only ITU-T Rec. G.751 format supported. Unframed carried clear channel. Changes Table Frame Stuffing Format Just before Figure LAC1J1V1 signal high when LAPL signal high mark every byte each three STS-1 SPEs. LAV5 signal pulses high mark bytes each tributary. LATPL, multiplexed with LAOE shown separately
0,1,2.) SREFCLK cycles before LAC1 pulse.
between SAC1FP LAC1. Table gives permissible combinations.
Change bullet Section 12.2.1: SAC1FP pulse must (where
RTTB TUG2 TUG2 Interrupt
INSBI Thresholds Register
Changes Table Register Memory Map:
Change Section 9.44: TEMUX identification code 183160CD hexadecimal.
CMV8MCLK, CMVFPB CMVFPC active.
with other pins. CCSID[1:3] outputs always available provided
Change Section 9.40 H-MVIP interface, CCSID[1:3], multiplexed
Changes Section 9.14
excessive CRC-6 errors.
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
RELEASED DATA SHEET PMC-1991437 ISSUE
PM8316 TEMUX
registers. pointer decimal illustrated [x-ref]. Changes Table Changes Table Changes Table Changes Table Changes Table Change bars relative Issue
[Errata Item] Alarms description describes necessary conditions setting
[Errata Item] Functional Timing section there description LADDOE register settings. Also, 77.76MHz tPtel parameter been changed.
description LAPL clearly indicates that will driven only bytes. description 77MHz telecom makes clear that LATOHEN signal.
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
More information about whether TEMUX supports interfaces simultaneously with SPEs over telecom interface. Text added Functional Description section explaining what can/ cannot done dependent config bits.
[Errata Item] order TEMUX work along with TBS/TSE Spectra devices TEMUX must place constant value H1/H2 fields that equals valid pointer corresponding chosen, fixed offset. Added text VTPP portion functional description. references receive alarms affecting removed. This behaviour appropriate according G.707-2000. [Errata Item] mapper/demapper TEMUX operates mode only. Note added that T1/E1s mapped into SPEs with Mapper/Demapper SPEs allowed. "Egress H-MVIP System Interface" section includes text about avoiding controlled frame slips. [Errata Item] each reference linkrate, comment been added explaining that ClkRate[1:0] information valid when been demapped from SONET/SDH D3MD function. LAOE/LATPL same other Combus outputs, drive. Functional timing diagrams Ingress Egress Flexible Bandwidth ports
Some A.C. parameters were added TICLK RCLK.
must devices that combined telecom will have valid LAPL
payload bytes configured TTMP, optionally overhead
have alignment determined SONET/SDH Transmit Pointer Configuration
location LATPL indicates positive pointer justification. three STS-1 SPEs
indicates negative pointer justification when high during byte after
ref], indicates valid tributary payload when high. During location LATPL
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
RELEASED DATA SHEET PMC-1991437 ISSUE
PM8316 TEMUX
Oriented Code Generation" section, more explanation about what happens code overwritten before transmission finished.
"H-MVIP Data Format" section, some text been added describing what
description MFSDC1FP been changed.
=4*(MVED index 7*(SPE-1)
There section outlining PRGD blocks, mentioning program LENGTH registers generate specific PRBS patterns Repetitive patterns.
April 2002
Updated table Operation section (Table Constraints 77.76MHz)
Section Characteristics, VOL, minor corrections: CASID[7:0] changed CASID[21:1] MVID[7:0] changed MVID[21:1]
January 2003
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
Documented Line Side operation throughout document including block diagram
Added more block diagrams showing Transmux mode, Mapper/Mux mode placement T1/E1 framer transmitter High Density Framer mode.
Updated RCLK description limit tolerance input clock maintain demultiplexed clock within standard's requirements.
Updated RGAPCLK/RSCLK description note that external jitter attenuator required when connected output clock PM73122 AAL1gator32 device.
Updated TFPI/TMFPI description correct location TDATIFALL bit. Updated LAOE/LATPL description changing output type tristate output.
Updated CLK52M description stating that when demapping from SONET frequency must 44.928 MHz.
capabilities.
Some minor changes "Notes Desciptions" Item Output drive
Changed tSsbiadd 77MHz 2.7ns from 3ns.
inputs.
Noted that S77_MVED_3 (S77 MVED[3] D10) Schmitt trigger
Changed from 0.8V 0.6V Schmitt trigger pads.
=4*(MVED index 7*(SPE-1)
Changes formula calculating index value:
[Errata Item] comments "Clock Frame Synchronization Constraints".
Flexible bandwidth spec'd load 50pf outputs.
happens applications where F-bit value overwritten transmitter.
included.
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
RELEASED DATA SHEET PMC-1991437 ISSUE
PM8316 TEMUX
Updated SREFCLK description adding that tolerate +/-50
H-MVIP buses both being used.
Updated MVID[21:1] output pins' current drive strength Updated section Transmultiplexing state that section 12.2.3 datasheet sequence TEMUX Programmer's Guide transmux mode must
Updated section 9.11, Transmitter, with details operation inserting
Updated 9.21.3 Desynchronizer note that demapped clock must pass
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
Delay Status (TelecomBus) 0x073F Control Status (TelecomBus).
Updated Version Number Device Identification values Table Identification Register section 11.1 JTAG Test Port.
Updated OEB_RECVCLK_1 Table Boundary Scan Register 11.1 JTAG Test Port. Updated section 12.2.2 Telecom Buses Both 19.44 with constraints when IVTPP EVTPP bypassed. Updated section 12.2.3 Telecom Buses Both 77.76 stating that constraints must followed transmux mode. Updated section 12.3 SLC96, removing references using H-MVIP bus. Updated section 12.10 Using Internal T1/E1 Data Link Transmitter noting that minimum packet size THDL bytes. Updated section 12.14 Loopback Modes removing sentence that states transmitted when digital diagnostic loopback enabled. Added section 12.20 Configuring Line Side SBI. Updated Lead Temperature Maximum rating 225°C from 230°C Table
Control Status (SBI Bus), 0x073C Configuration (TelecomBus), 0x073E
Configuration (SBI Bus), 0x01C6 Delay Status (SBI Bus), 0x01C7
Added following registers Table Register Memory Map: 0x01C4
AAL1gator32 device. Also removed 51.84 option CLK52M.
through external jitter attenuator before connecting PM73122
Demapper section 9.25 Transmit Tributary Byte Synchronous Mapper.
Updated register setting section 9.20 Receive Tributary Byte Synchronous
Updated input multiplexer Figure DS3/E3 Configuration Options.
National Use, bits.
followed operate correctly.
must followed when operating transmux mode. Also that initialization
Updated SDC1FP description noting that input must held when
accurate clock source when operating serial mode.
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
RELEASED DATA SHEET PMC-1991437 ISSUE
PM8316 TEMUX
Corrected maximum RCLK[3:1] frequency mode Table DS3/E3 Receive Interface Timing.
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
Absolute Maximum Ratings.
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
RELEASED DATA SHEET PMC-1991437 ISSUE
PM8316 TEMUX
APPLICATION EXAMPLES
FUNCTIONAL DESCRIPTION.81
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
TRANSPARENT VIRTUAL TRIBUTARIES.81 TRANSMULTIPLEXING FRAMING FRAMING T1/E1 PERFORMANCE MONITORING.93 T1/E1 HDLC RECEIVER
DESCRIPTION
DIAGRAM
DESCRIPTION
T1/E1 EXTRACTION/INSERTION ALARM/ERROR RESPONSE
DS3/E3 FRAMER ONLY BLOCK DIAGRAM
VT/TU MAPPER ONLY MODE BLOCK DIAGRAM.28
MULTIPLEXER MODE BLOCK DIAGRAM
LEVEL BLOCK DIAGRAM
BLOCK DIAGRAM
REFERENCES
APPLICATIONS
FEATURES.1
LEGAL INFORMATION
CONTENTS
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
RELEASED DATA SHEET PMC-1991437 ISSUE
PM8316 TEMUX
9.10 9.11 9.12 9.13 9.14 9.15 9.16 9.17 9.18 9.19 9.20 9.21
T1/E1 RECEIVE PER-CHANNEL CONTROL.95
9.22
9.23 9.24 9.25 9.26
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
RECEIVE TRIBUTARY BYTE SYNCHRONOUS DEMAPPER .131 MAPPER DROP SIDE (D3MD) .132 TRANSMIT TRIBUTARY PATH OVERHEAD PROCESSOR (TTOP)135
TRANSMIT REMOTE ALARM PROCESSOR (TRAP).136 TRANSMIT TRIBUTARY ASYNCHRONOUS MAPPER (TTMP)137 TRANSMIT TRIBUTARY BYTE SYNCHRONOUS MAPPER .138 MAPPER SIDE (D3MA) .139
RECEIVE TRIBUTARY ASYNCHRONOUS DEMAPPER (RTDM) .129
RECEIVE TRIBUTARY TRACE BUFFER (RTTB).128
RECEIVE TRIBUTARY PATH OVERHEAD PROCESSOR (RTOP) .125
TRIBUTARY PAYLOAD PROCESSOR (VTPP) .123
DS3/E3 FRAMING, PERFORMANCE MONITORING MULTIPLEXING .106
T1/E1 PSEUDO RANDOM BINARY SEQUENCE GENERATION DETECTION (PRBS).105
T1/E1 RECEIVE TRANSMIT DIGITAL JITTER ATTENUATORS
T1/E1 HDLC TRANSMITTERS
TRANSMITTER
TRANSMITTER
T1/E1 SIGNALING EXTRACTION
T1/E1 ELASTIC STORE (ELST)
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
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PM8316 TEMUX
9.29 9.30 9.31 9.32 9.33
INSERT SCALEABLE BANDWIDTH INTERCONNECT (INSBI)145
JTAG TEST ACCESS PORT.147 MICROPROCESSOR INTERFACE .148
12.2 12.3 12.4 12.5 12.6
CLOCK FRAME SYNCHRONIZATION CONSTRAINTS .188 SLC96 .191
12.7 12.8 12.9
12.10 USING INTERNAL T1/E1 DATA LINK TRANSMITTER.210 12.11 USING TIME-SLICED T1/E1 TRANSCEIVERS.212
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
SERVICING INTERRUPTS.195 USING PERFORMANCE MONITORING FEATURES .196 USING INTERNAL HDLC TRANSMITTER .200 USING INTERNAL DATA LINK RECEIVER .204 USING INTERNAL T1/E1 DATA LINK RECEIVER.208
FRAME FORMAT.193
12.1
TRIBUTARY INDEXING.186
OPERATION .186
11.1
JTAG TEST PORT .179
TEST FEATURES DESCRIPTION .176
NORMAL MODE REGISTER DESCRIPTION .175
FLEXIBLE BANDWIDTH PORTS .146
EXTRACT SCALEABLE BANDWIDTH INTERCONNECT (EXSBI) .144
9.28
INGRESS SYSTEM H-MVIP INTERFACE.142
9.27
EGRESS H-MVIP SYSTEM INTERFACE .141
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
RELEASED DATA SHEET PMC-1991437 ISSUE
PM8316 TEMUX
12.14 LOOPBACK MODES.217
13.3 13.4 13.5 13.6 13.7
TELECOM DROP INTERFACE TIMING.272 TELECOM INTERFACE TIMING.276
DROP INTERFACE TIMING .281 INTERFACE TIMING .282 EGRESS H-MVIP LINK TIMING .284 INGRESS H-MVIP LINK TIMING .284
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
13.8 13.9
13.10 EGRESS FLEXIBLE BANDWIDTH TIMING .285 13.11 INGRESS FLEXIBLE BANDWIDTH TIMING .286 ABSOLUTE MAXIMUM RATINGS.288 D.C. CHARACTERISTICS.289
SONET/SDH SERIAL ALARM PORT TIMING .280
13.2
SYSTEM SIDE INTERFACE TIMING.268
13.1
LINE SIDE INTERFACE TIMING .264
FUNCTIONAL TIMING.264
12.20 CONFIGURING LINE SIDE .260
12.19 JTAG SUPPORT .252
12.18 FULL FEATURED T1/E1 PATTERN GENERATION DETECTION .248
12.17 H-MVIP DATA FORMAT .243
12.16 DATA FORMATS .221
12.15 TELECOM MAPPER/DEMAPPER LOOPBACK MODES.220
12.13 T1/E1 FRAMER LOOPBACK MODES.215
12.12 AUTOMATIC PERFORMANCE REPORT FORMAT .213
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
RELEASED DATA SHEET PMC-1991437 ISSUE
PM8316 TEMUX
ORDERING THERMAL INFORMATION .320
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
MECHANICAL INFORMATION.321
TEMUX TIMING CHARACTERISTICS .296
MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS.292
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
RELEASED DATA SHEET PMC-1991437 ISSUE
PM8316 TEMUX
FIGURE FIGURE FIGURE FIGURE FIGURE
MULTIPLEXER BLOCK DIAGRAM.27
FIGURE MULTIFRAME ALIGNMENT ALGORITHM FIGURE JITTER TOLERANCE MODES.101
FIGURE JITTER TRANSFER MODES .104
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
FIGURE INGRESS CLOCK SLAVE H-MVIP .143 FIGURE INSERT .146 FIGURE FRAME STRUCTURE .193
FIGURE EGRESS CLOCK SLAVE H-MVIP.141
FIGURE DS/E3 CONFIGURATION OPTIONS.107
FIGURE JITTER TRANSFER MODES .103
FIGURE JITTER TOLERANCE MODES.102
FIGURE
DIAGRAM.38
FIGURE TRANSMUX MODE T1/E1 BLOCK DIAGRAM
MAPPER/MULTIPLEXER MODE T1/E1 BLOCK DIAGRAM
HIGH DENSITY FRAMER MODE T1/E1 BLOCK DIAGRAM
DS3/E3 FRAMER ONLY MODE BLOCK DIAGRAM.29
VT/TU MAPPER BLOCK DIAGRAM.28
FIGURE
TEMUX BLOCK DIAGRAM.26
FIGURE
FRACTIONAL APPLICATION
FIGURE
HIGH DENSITY FRAME RELAY APPLICATION
FIGURE
ANY-SERVICE-ANY-PORT APPLICATION.22
LIST FIGURES
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
RELEASED DATA SHEET PMC-1991437 ISSUE
PM8316 TEMUX
FIGURE COUNT MODE).198
FIGURE DS3/E3 DIAGNOSTIC LOOPBACK DIAGRAM .218
FIGURE OUTPUT CELL (OUT_CELL).258 FIGURE BIDIRECTIONAL CELL (IO_CELL).259 FIGURE LAYOUT OUTPUT ENABLE BIDIRECTIONAL CELLS
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
FIGURE -PIN CONNECTION DIAGRAM LINE SIDE SBI.261 FIGURE RECEIVE BIPOLAR STREAM.264
xiii
FIGURE INPUT OBSERVATION CELL (IN_CELL) .257
FIGURE CONTROLLER FINITE STATE MACHINE .254
FIGURE BOUNDARY SCAN ARCHITECTURE .252
FIGURE PRGD PATTERN GENERATOR .248
FIGURE TELECOM LINE LOOPBACK DIAGRAM .221
FIGURE TELECOM DIAGNOSTIC LOOPBACK DIAGRAM .220
FIGURE LOOPBACK DIAGRAM.219
FIGURE LINE LOOPBACK DIAGRAM .219
FIGURE T1/E1 DIAGNOSTIC DIGITAL LOOPBACK .217
FIGURE T1/E1 LINE LOOPBACK.216
FIGURE EXAMPLE MULTI-PACKET OPERATIONAL SEQUENCE .207
FIGURE TYPICAL DATA FRAME.207
FIGURE CRCE COUNT MODE) .200
FIGURE CRCE COUNT MODE).199
FIGURE CRCE COUNT MODE) .198
FIGURE COUNT MODE) .197
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
RELEASED DATA SHEET PMC-1991437 ISSUE
PM8316 TEMUX
FIGURE RECEIVE UNIPOLAR STREAM.265
FIGURE FRAMER MODE G.751 TRANSMIT INPUT STREAM WITH TGAPCLK
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
FIGURE FRAMER MODE G.832 RECEIVE OUTPUT STREAM .272 FIGURE FRAMER MODE G.832 RECEIVE OUTPUT STREAM WITH RGAPCLK
FIGURE FRAMER MODE G.832 TRANSMIT INPUT STREAM WITH TGAPCLK
FIGURE FRAMER MODE G.832 TRANSMIT INPUT STREAM.271
FIGURE FRAMER MODE G.751 RECEIVE OUTPUT STREAM WITH RGAPCLK
FIGURE FRAMER MODE G.751 RECEIVE OUTPUT STREAM .270
FIGURE FRAMER MODE G.751 TRANSMIT INPUT STREAM.269
FIGURE FRAMER MODE RECEIVE OUTPUT STREAM WITH RGAPCLK
FIGURE FRAMER MODE RECEIVE OUTPUT STREAM .269
FIGURE FRAMER MODE TRANSMIT INPUT STREAM WITH TGAPCLK
FIGURE FRAMER MODE TRANSMIT INPUT STREAM .268
FIGURE TRANSMIT UNIPOLAR STREAM .267
FIGURE TRANSMIT BIPOLAR STREAM .267
FIGURE TRANSMIT UNIPOLAR STREAM.266
FIGURE TRANSMIT BIPOLAR STREAM .266
FIGURE RECEIVE BIPOLAR STREAM .265
FIGURE RECEIVE UNIPOLAR STREAM .264
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
RELEASED DATA SHEET PMC-1991437 ISSUE
PM8316 TEMUX
FIGURE 19.44 TELECOM DROP TIMING LOCKED STS-1 SPES VCS.274
FIGURE REMOTE SERIAL ALARM PORT TIMING.281 FIGURE DROP T1/E1 FUNCTIONAL TIMING .281
FIGURE EGRESS 8.192 MBIT/S H-MVIP LINK TIMING .284
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
FIGURE MICROPROCESSOR INTERFACE READ TIMING.293 FIGURE MICROPROCESSOR INTERFACE WRITE TIMING .295 FIGURE RSTB TIMING.296
FIGURE INGRESS FLEXIBLE BANDWIDTH PORT FUNCTIONAL TIMING287
FIGURE EGRESS FLEXIBLE BANDWIDTH PORT FUNCTIONAL TIMING MASTER.286
FIGURE EGRESS FLEXIBLE BANDWIDTH PORT FUNCTIONAL TIMING SLAVE
FIGURE INGRESS 8.192 MBIT/S H-MVIP LINK TIMING .285
FIGURE JUSTIFICATION REQUEST FUNCTIONAL TIMING
FIGURE DROP DS3/E3 FUNCTIONAL TIMING .282
FIGURE 77.76 TELECOM TIMING.279
FIGURE 19.44 TELECOM TIMING LOCKED CASE
FIGURE 19.44 TELECOM TIMING LOCKED STS-1 SPES VCS.277
FIGURE 77.76 TELECOM DROP TIMING .276
FIGURE 19.44 TELECOM DROP TIMING .275
FIGURE 19.44 TELECOM DROP TIMING STS-1 SPES
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
RELEASED DATA SHEET PMC-1991437 ISSUE
PM8316 TEMUX
FIGURE TELECOM LINE SIDE OUTPUT TIMING.306
FIGURE H-MVIP INGRESS DATA TIMING .315 FIGURE XCLK INPUT TIMING .315
FIGURE JTAG PORT INTERFACE TIMING.319
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
FIGURE PBGA 23X23MM BODY.321
FIGURE REMOTE SERIAL ALARM PORT TIMING.317
FIGURE TRANSMIT LINE INTERFACE TIMING .316
FIGURE H-MVIP EGRESS DATA FRAME PULSE TIMING.314
FIGURE INGRESS FLEXIBLE BANDWIDTH PORT TIMING .312
FIGURE EGRESS FLEXIBLE BANDWIDTH PORT TIMING
FIGURE SYSTEM SIDE DROP COLLISION AVOIDANCE TIMING
FIGURE SYSTEM SIDE DROP TIMING .310
FIGURE SYSTEM SIDE TIMING .308
FIGURE TELECOM LINE SIDE TRISTATE OUTPUT TIMING
FIGURE LINE SIDE TELECOM LINE SIDE INPUT TIMING
FIGURE DS3/E3 RECEIVE INTERFACE TIMING .301
FIGURE DS3/E3 TRANSMIT INTERFACE TIMING .298
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
RELEASED DATA SHEET PMC-1991437 ISSUE
PM8316 TEMUX
TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE
ASYNCHRONOUS MAPPING STS-1 (STM-0/AU3) .132
BOUNDARY SCAN REGISTER .180 INDEXING 1.544 MBIT/S TRIBUTARIES.187
TABLE OPTIONS TABLE OPTIONS TABLE TABLE
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
77.76 TELECOM ALIGNMENT OPTIONS.189 CONSTRAINTS 77.76MHZ .190
19.44 77.76 TELECOM ALIGNMENT 77.76 19.44 TELECOM ALIGNMENT PMON COUNTER SATURATION LIMITS MODE) .196 PMON COUNTER SATURATION LIMITS MODE) .196
INDEXING 2.048 MBIT/S TRIBUTARIES.188
IDENTIFICATION REGISTER .179
INSTRUCTION REGISTER .179
REGISTER MEMORY MAP.148
SYNCHRONIZER STUFFING ALGORITHM. .140
DESYNCHRONIZER CLOCK GAPPING ALGORITHM.135
FORMAT.133
TABLE
ASYNCHRONOUS TRIBUTARY MAPPING.130
TABLE
ASYNCHRONOUS TRIBUTARY MAPPING .129
TABLE
PATH SIGNAL LABEL MISMATCH STATE .127
TABLE
FRAMER FRAMING STATES.90
xvii
LIST TABLES
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
RELEASED DATA SHEET PMC-1991437 ISSUE
PM8316 TEMUX
TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE
STRUCTURE CARRYING MULTIPLEXED LINKS.223
E1/TVT2 TRIBUTARY COLUMN NUMBERING.224 T1/E1 LINK RATE INFORMATION.227
FRAMING FORMAT .232 CHANNEL ASSOCIATED SIGNALING BITS.234
BLOCK FORMAT .235 MULTI-FRAME STUFFING FORMAT .236 FRAMING FORMAT .237 FRAME STUFFING FORMAT .238 TRANSPARENT VT1.5/TU11 FORMAT.239 TRANSPARENT VT2/TU12 FORMAT.242 DATA H-MVIP FORMAT .244 DATA H-MVIP FORMAT.245
xviii
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
TABLE TABLE TABLE TABLE
TABLE
TABLE
FRAMING FORMAT.235
CHANNEL ASSOCIATED SIGNALING BITS.231
FRAMING FORMAT .229
CLOCK RATE ENCODING .228
LINK RATE INFORMATION .228
T1/E1 CLOCK RATE ENCODING.227
T1/TVT1.5 TRIBUTARY COLUMN NUMBERING .223
TABLE
PERFORMANCE REPORT MESSAGE CONTENTS .215
TABLE
PERFORMANCE REPORT MESSAGE STRUCTURE NOTES214
TABLE PERFORMANCE REPORT MESSAGE STRUCTURE CONTENTS
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
RELEASED DATA SHEET PMC-1991437 ISSUE
PM8316 TEMUX
TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE
REPETITIVE PATTERN GENERATION 1).251
DS3/E3 RECEIVE INTERFACE TIMING .300
TABLE TELECOM OUTPUT TIMING 77.76 (FIGURE FIGURE .305
TABLE TABLE
TABLE SYSTEM SIDE DROP TIMING 77.76 (FIGURE FIGURE .309 EGRESS FLEXIBLE BANDWIDTH PORT TIMING (FIGURE INGRESS FLEXIBLE BANDWIDTH PORT TIMING (FIGURE
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
TABLE SYSTEM SIDE DROP TIMING 19.44 (FIGURE FIGURE .308
TABLE
SYSTEM SIDE TIMING 77.76 (FIGURE 88)307
TABLE
SYSTEM SIDE TIMING 19.44 (FIGURE 88)306
TABLE TELECOM LINE SIDE OUTPUT TIMING 19.44 (FIGURE FIGURE .305
TABLE LINE SIDE TELECOM LINE SIDE INPUT TIMING 19.44 (FIGURE .303
DS3/E3 TRANSMIT INTERFACE TIMING .296
RSTB TIMING.296
MICROPROCESSOR INTERFACE WRITE ACCESS .294
MICROPROCESSOR INTERFACE READ ACCESS.292
D.C. CHARACTERISTICS .289
ABSOLUTE MAXIMUM RATINGS .288
TABLE
PSEUDO RANDOM PATTERN GENERATION 0).250
TABLE
H-MVIP FORMAT .246
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
RELEASED DATA SHEET PMC-1991437 ISSUE
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TABLE TABLE TABLE TABLE TABLE
XCLK INPUT (FIGURE .315
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
ORDERING INFORMATION.320
JTAG PORT INTERFACE .318
REMOTE SERIAL ALARM PORT TIMING.317
TRANSMIT LINE INTERFACE TIMING (FIGURE .316
TABLE
H-MVIP INGRESS TIMING (FIGURE .314
TABLE
H-MVIP EGRESS TIMING (FIGURE .312
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
RELEASED DATA SHEET PMC-1991437 ISSUE
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
Each SPE/DS3 independently programmable allow following modes operation:
streams multiplexed into three serial streams. streams multiplexed into three DS3s, DS3s asynchronously mapped into three STS-1/STM-0 SPEs. Multiplexer with ingress egress link monitoring. multiplexed streams mapped asynchronous VT1.5 virtual tributaries TU-11 tributary units, providing transmultiplexing ("transmux") function between SONET/SDH. streams mapped asynchronous TU-12 tributary units into three STM-1/VC3 TUG3 from STM-1/VC4.
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
Four modes operation:
Three STS-1, TUG3 Asynchronous VT1.5 TU-11 Mappers with ingress egress tributary link monitoring.
streams mapped byte synchronous VT1.5 virtual tributaries into three STS-1 SPEs TU-11 tributary units into three STM-1/VC3 TUG3 from STM-1/VC4.
streams mapped asynchronous VT1.5 virtual tributaries into three STS-1 SPEs TU-11 tributary units into three STM-1/VC3 TUG3 from STM-1/VC4.
Eight modes operation:
Integrates T1/E1 framers, three SONET/SDH VT1.5/VT2/TU11/TU12 asynchronous byte synchronous mappers, three full featured multiplexers with framers, three framers, three SONET/SDH mappers single monolithic device terminating multiplexed streams, SONET/SDH mapped streams SONET/SDH mapped streams.
FEATURES
RELEASED DATA SHEET PMC-1991437 ISSUE
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
unchannelized modes operation:
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
Supports insertion extraction arbitrary rate (eg. fractional DS3) data streams from interface. Provides jitter attenuation receive transmit directions.
Supports byte serial Scaleable Bandwidth Interconnect (SBI) interface high density system side device interconnection streams, streams, streams streams. This interface also supports transparent virtual tributaries when used with SONET/SDH mapper.
Supports Mbit/s H-MVIP system interface links, separate Mbit/s H-MVIP system interface channels separate Mbit/s H-MVIP system interface V5.1/V5.2 channels.
VT1.5/TU11 VT2/TU12 tributaries passed between line SONET/SDH system transparent virtual tributaries with pointer processing.
Standalone unchannelized framer mode (ITU-T Rec. G.751) access entire payload.
three streams mapped asynchronously into VC-3s. VC-3s aligned within AU-3s.
Standalone unchannelized framer mode access entire payload.
streams multiplexed into three DS3s following ITU-T G.747 recommendation.
Three STS-1, TUG3 Asynchronous TU-12 Mappers with ingress egress tributary link monitoring.
streams mapped byte synchronous virtual tributaries into three STS-1 TU-12 tributary units into STM-1/VC3 TUG3 from STM-1/VC4.
streams mapped asynchronous virtual tributaries into three STS-1 TU-12 tributary units into STM-1/VC3 TUG3 from STM-1/VC4.
RELEASED DATA SHEET PMC-1991437 ISSUE
PM8316 TEMUX
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
power 1.8V/3.3V CMOS technology. pins tolerant.
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
Each receiver sections: Frames DS-1 signals SLC96 formats. Frames JT-G.704 multiframe formatted signals. Supports alternate CRC-6 calculation Japanese applications.
324-pin fine pitch PBGA package (23mm 23mm). Supports industrial temperature range (-40oC 85oC) operation.
Provides standard signal P1149.1 JTAG test port boundary scan board test purposes.
Provides generic 8-bit microprocessor interface configuration, control status monitoring.
Provides SONET/SDH Add/Drop interface with integrated VT1.5, TU11, TU-12 mapper T1and streams. Also provides mapper.
Transmit clock source selected from either external oscillator from receive side clock (loop-timed).
When configured operate Framer, gapped transmit receive clocks optionally generated interface link layer devices which only need access payload data bits.
Supports C-bit parity formats.
Also provides PRBS generators detectors each tributary error testing DS1, NxDS0 rates recommended ITU-T O.151 O.152.
Provides on-board programmable binary sequence generator detector error testing rates. Includes support patterns recommended ITU-T O.151.
Provides link diagnostic line loopbacks.
Provides three independent de-jittered recovered clocks system timing redundancy.
RELEASED DATA SHEET PMC-1991437 ISSUE
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
Provides Inband Loopback Code generation detection.
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
Line side interface either from interface multiplex from SONET/SDH Drop VT1.5, TU-11, TU-12 demapper. Line side interface also configured bus. System side interface either H-MVIP bus. Frames presence detects "Japanese Yellow" alarm. Supports alternate CRC-6 calculation Japanese applications.
pseudo-random sequence user selectable from detected stream either ingress egress directions. detector counts pattern errors using 16-bit non-saturating PRBS error counter. pseudo-random sequence entire combination DS0s within framed
Provides DS-1 robbed signaling extraction insertion, with optional data inversion, programmable idle code substitution, digital milliwatt code substitution, fixing, superframes signaling debounce perchannel basis.
Provides optional elastic store which used time ingress streams common clock frame alignment support H-MVIP interface.
Provides performance monitoring counters sufficiently large allow performance monitor counter polling minimum rate once second. Optionally, updates performance monitoring counters interrupts microprocessor once second, timed receive line.
Provides HDLC interface with bytes buffering terminating facility data link.
Indicates signaling state change, superframes signaling debounce per-DS0 basis.
Provides bit-oriented code detection HDLC/LAPD interface terminating facility data link.
Supports RAI-CI AIS-CI alarm detection generation.
Provides Red, Yellow, alarm integration.
RELEASED DATA SHEET PMC-1991437 ISSUE
PM8316 TEMUX
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
V5.2 link indication signal detection.
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
Line side interface from SONET/SDH Drop TU-12 demapper. Line side interface also configured bus. System side interface either H-MVIP bus.
pseudo-random sequence user selectable from detected stream either ingress egress directions. detector counts pattern errors using 16-bit non-saturating PRBS error counter. pseudo-random sequence entire combination timeslots within framed
Provides trunk conditioning which forces programmable trouble code substitution signaling conditioning channels selected channels.
programmed generate interrupt change signaling state.
Frames signaling multiframe alignment when enabled extracts channel associated signaling. Alternatively, common channel signaling data link extracted from timeslot
Provides two-frame elastic store buffer backplane rate adaptation that performs controlled slips indicates slip occurrence direction.
Provides performance monitoring counters sufficiently large allow performance monitor counter polling minimum rate once second. Optionally, updates performance monitoring counters interrupts microprocessor once second, timed receive line.
Extracts 4-bit codewords from national bits specified 233.
Provides HDLC interface with bytes buffering terminating national data link.
Frames ITU-T G.704 basic CRC-4 multiframe formatted signals. framing procedures consistent ITU-T G.706 specifications.
Each receiver sections:
Provides external access three de-jittered recovered clocks.
RELEASED DATA SHEET PMC-1991437 ISSUE
PM8316 TEMUX
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
Supports alternate CRC-6 calculation Japanese applications. pseudo-random sequence user selectable from inserted into stream either ingress egress directions. pseudo-random sequence inserted into entire combination DS0s within framed Line side interface through either Interface multiplex SONET/SDH VT1.5, TU-11, TU-12 mapper. Line side interface also configured bus.
Each transmitter sections: Provides FIFO buffer jitter attenuation rate conversion transmit path.
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
System side interface either H-MVIP bus.
Provides FIFO buffer jitter attenuation rate conversion transmitter.
Provides digital phase locked loop generation jitter transmit clock.
Autonomously transmits Performance Report Message each second.
Provides transparency F-bit support SLC96 data link insertion.
Supports transmission alarm indication signal (AIS) Yellow alarm signal SLC96 formats.
Provides byte buffer allow insertion facility data link using host interface.
Provides minimum ones density through Bell (bit "jammed zero code suppression per-DS0 basis.
timed associated receive clock (loop timing) derive timing from data rate received system interface common transmit clock; transmit line clock synthesized from reference.
Each transmitter sections:
Provides external access three de-jittered recovered clocks.
RELEASED DATA SHEET PMC-1991437 ISSUE
PM8316 TEMUX
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
full featured T1/E1 Pattern Generators Detectors:
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
sub-set DS0s within tributary selected.
Provides programmable pseudo-random test sequence generation 2321 length sequences conforming ITU-T O.151 standards) repeating pattern bits. Diagnostic abilities include single error insertion error insertion error rates ranging from 10-1 10-7.
Each generator detector pair associated with E1s.
System side interface either H-MVIP bus.
Line side interface through SONET/SDH TU-12 mapper. Line side interface also configured bus.
Supports transmission alarm indication signal (AIS) remote alarm indication (RAI) signal.
Supports 4-bit codeword insertion national bits specified
Optionally inserts datalink national bits.
pseudo-random sequence user selectable from inserted into stream either ingress egress directions. pseudo-random sequence inserted into entire combination timeslots within framed
Provides digital phase locked loop generation jitter transmit clock.
Provides trunk conditioning which forces programmable trouble code substitution signaling conditioning channels selected channels.
Provides signaling insertion, programmable idle code substitution, digital milliwatt code substitution, data inversion channel basis.
Supports unframed mode framing bit, CRC, data link by-pass.
Transmits G.704 basic CRC-4 multiframe formatted
RELEASED DATA SHEET PMC-1991437 ISSUE
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
Provides individual tributary path signal label register that hold expected label detects tributary path signal label mismatch alarms (PSLM) return matched state each tributary optionally generates interrupts. Detects tributary path signal label unstable alarms (PSLU) return stable state each tributary optionally generates interrupts. Detects assertion removal tributary extended remote defect indications (RDI) each tributary optionally generates interrupts. Calculates compares tributary path BIP-2 error detection code each tributary configurable accumulate BIP-2 errors block basis internal registers. Allows insertion all-zeros all-ones tributary idle code with unequipped indication valid pointer into tributary under software control. Allows software force insertion tributary basis.
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
Detects tributary elastic store underflow overflow optionally generates interrupts.
Detects tributary path alarm indication signal (AIS) return normal state each tributary optionally generates interrupts
Detects loss pointer (LOP) re-acquisition each tributary optionally generates interrupts.
Optionally frames byte path overhead determine tributary multi-frame boundaries generates change loss-of-frame status interrupts.
Compensates pleisiochronous relationships between incoming outgoing higher level (STS-1, AU4, AU3) synchronous payload envelope frame rates through processing lower level tributary pointers.
Seamlessly interfaces with 77.76 Drop 77.76 buses.
Interfaces with byte wide Telecom Add/Drop bus, interfacing directly with PM5362 TUPP-PLUS PM5342 SPECTRA-155 19.44 MHz.
Each three SONET/SDH Tributary Path Processing Sections:
RELEASED DATA SHEET PMC-1991437 ISSUE
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
asynchronous mapping assigns stuff control bits streams independently using digital control loop. Stuff control bits dithered produce fractional mapping jitter receiving desynchronizer. Sets fixed stuff bits asynchronous mappings zeros ones microprocessor control Extracts asynchronous mapped VT1.5 virtual tributaries from STS-1 into streams optional elastic store.
Processes tributary trace message (J2) tributaries carried each STS-1/TUG-3 synchronous payload envelope.
Inserts asynchronous mapped TU-12 tributary units into STM1/VC4 TUG3 STM-1/VC3 from streams.
Inserts asynchronous mapped virtual tributaries into STS1 from streams.
Inserts byte synchronous mapped VT1.5 virtual tributaries into STS-1 TU-11 tributary units into STM-1/VC3 TUG3 from STM1/VC4.
Inserts asynchronous mapped TU-11 tributary units into STM1/VC4 TUG3 STM-1/VC3 from streams.
Inserts asynchronous mapped VT1.5 virtual tributaries into STS-1 from streams.
Each three SONET/SDH VT/TU Mapper Sections:
Calculates inserts tributary path BIP-2 error detection code each tributary.
Support in-band error reporting updating FEBE, bits byte with status incoming stream remote alarm pins.
Inserts valid pointers all-zeros transport overhead bytes outgoing Telecom bus, with valid control signals.
Inserts valid byte all-zeros fixed stuff bytes. Remaining path overhead bytes (J1, all-zeros.
RELEASED DATA SHEET PMC-1991437 ISSUE
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
Performs majority vote C-bit decoding detect stuff requests.
Each three Receiver Sections: Frames signal with maximum average reframe time less than required TR-TSY-000009 Section 4.1.2 TR-TSY-000191 Section 5.2). Decodes B3ZS-encoded signal indicates line code violations. definition line code violation software selectable. Provides indication M-frame boundaries from which M-subframe boundaries overhead positions stream determined external processing.
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
Complies with STS-1 asynchronous mapping standards.
Performs majority vote C-bit decoding detect stuff requests.
Demapper ignores transport overhead bytes, path overhead bytes stuff bits.
Extracts stream from STS-1 (AU3).
Sets fixed stuff bits zeros ones microprocessor control.
Maps stream into STS-1 (AU3).
Each three SONET/SDH Mapper Sections:
Demapper ignores transport overhead bytes, path overhead bytes stuff bits.
Extracts asynchronous mapped TU-12 tributary units from STM-1/VC4 TUG3 STM-1/VC3 into streams optional elastic store.
Extracts asynchronous mapped virtual tributaries from STS-1 into streams optional elastic store.
Extracts asynchronous mapped TU-11 tributary units from STM-1/VC4 TUG3 STM-1/VC3 into streams optional elastic store.
RELEASED DATA SHEET PMC-1991437 ISSUE
PM8316 TEMUX
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
Provides overhead insertion stream. Provides serial clock data interface, allows M-frame boundary and/or overhead positions located external interface.
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
Inserts receive failure (FERF), alarm indication signal (AIS) idle signal when enabled internal register bits. Provides optional automatic insertion receive failure (FERF) detection loss signal (LOS), frame (OOF), alarm indication signal (AIS) alarm condition.
Generates B3ZS encoded 100. repeating pattern pulse mask testing.
Provides B3ZS encoding.
Each three Transmit Sections:
Programmable pseudo-random test-sequence detection-(up length patterns conforming ITU-T O.151 standards) analysis features.
Terminates C-bit parity path maintenance data link with integral HDLC receiver having 128-byte deep FIFO buffer with programmable interrupt threshold. Supports polled interrupt-driven operation. Selectable none, address match detection first byte received packet.
Detects validates bit-oriented codes C-bit parity alarm control channel.
Accumulates 65,535 line code violation (LCV) events second, 65,535 P-bit parity error events second, 1023 F-bit M-bit (framing bit) events second, 65,535 excessive zero (EXZ) events second, when enabled C-bit parity mode operation, 16,383 C-bit parity error events second, 16,383 block error (FEBE) events second.
Extracts valid X-bits indicates receive failure (FERF).
Detects alarm indication signal (AIS) idle signal. Detection algorithms operate correctly presence 10-3 error rate.
RELEASED DATA SHEET PMC-1991437 ISSUE
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
Multiplexer Section:
Multiplexes streams into single format stream. Performs required stuffing/destuffing including generation interpretation C-bits. Includes required FIFO buffers rate adaptation multiplex path. Allows insertion detection payload loopback requests encoded C-bits activated under microprocessor control.
Allows alarm indication signal (AIS) activated cleared demultiplex direction automatically upon loss frame alignment signal. Supports C-bit parity format.
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
Allows alarm indication signal (AIS) activated cleared either direction under microprocessor control.
Internally generates clock integrated C-bit parity multiplex applications. Alternatively accepts external clock reference.
Provides programmable pseudo-random test sequence generation 232-1 length sequences conforming ITU-T O.151 standards) repeating pattern bits. test pattern framed unframed. Diagnostic abilities include single error insertion error insertion error rates ranging from 10-1 10-7.
Optionally inserts C-bit parity path maintenance data link with integral HDLC transmitter. Supports polled interrupt-driven operation.
Supports insertion bit-oriented codes C-bit parity alarm control channel.
Provides diagnostic features allow generation line code violation error events, parity error events, framing error events, when enabled C-bit parity application, C-bit parity error events, block error (FEBE) events.
RELEASED DATA SHEET PMC-1991437 ISSUE
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
Accumulates M-bit F-bit error events second.
Performs required stuffing including generation interpretation C-bits.
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
Performs required inversion second fourth multiplexed streams required ANSI T1.107 Section 7.2. Allows insertion detection payload loopback requests encoded C-bits activated under microprocessor control. Allows tributary alarm indication signal (AIS) activated cleared either direction under microprocessor control.
Includes required FIFO buffers rate adaptation multiplex path.
Multiplexes four three 2048 kbit/s (according ITU-T Rec. G.747) streams into single format stream.
Multiplexer Section:
Provides optional automatic insertion receive failure (FERF) detection frame (OOF), alarm indication signal (AIS) alarm condition.
Provides transmission receive failure (FERF) alarm indication signal (AIS) under microprocessor control.
Generates required bits into transmitted stream. Allows inversion inserted bits diagnostic purposes.
Transmitter Section:
Extracts X-bit remote alarm indication (RAI) indicates receive failure (FERF).
Detects alarm indication signal (AIS) presence 10-3 error rate.
Frames (ANSI T1.107 section signal with maximum average reframe time less than required TR-TSY-000009 Section 4.1.2 TR-TSY-000191 Section 5.2).
Framer Section:
RELEASED DATA SHEET PMC-1991437 ISSUE
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
Frames G.751 G.832 unchannelized data streams.
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
Provides three Mbit/s H-MVIP interfaces common channel signaling (CCS) channels well V5.1 V5.2 channels. mode available through this interface. mode timeslots available through this interface. Optionally, timeslot presented instead timeslot links accessed H-MVIP interface will synchronously timed common H-MVIP clock frame alignment signals, CMV8MCLK, CMVFP, CMVFPC. H-MVIP access Channel Associated Signaling available with Scaleable Bandwidth Interconnect optional replacement
Provides twenty Mbit/s H-MVIP interfaces synchronous access channel associated signaling (CAS) bits DS0s timeslots. bits occupy nibble every byte H-MVIP interfaces repeated over entire multi-frame.
Provides twenty Mbit/s H-MVIP data interfaces synchronous access DS0s links timeslots E1s. DS0s bundled from four links sequential order, 1-4, 5-8, 9-12, 81-84. timeslots bundled from links sequential order, 1-4, 5-8, 9-12, 57-60 61-63.
Synchronous System Interfaces:
G.832, Trail Trace inserted, integral HDLC transmitter provided insert either Network Requirement General Purpose data link.
Provides frame insertion G.751 G.832 applications, alarm insertion, diagnostic features.
Each three Transmit Sections:
G.832, terminates Trail Trace either Network Requirement General Purpose data link.
Each three Framer Sections:
Allows automatic tributary activated upon frame.
RELEASED DATA SHEET PMC-1991437 ISSUE
PM8316 TEMUX
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
Compatible with H-MVIP backplanes supporting 8.192 Mbit/s.
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
Transparent VT/TU access selected only when tributaries mapped into SONET/SDH. Transparent VT1.5s TU-11s selected tributary basis combination with framed unframed T1s. Transparent VT2s TU-12s selected tributary basis combination with framed unframed E1s.
Synchronous access channels timeslots supported locked format mode. Selectable tributary basis.
three arbitrary rate data streams inserted into extracted from serial ports.
Framed unframed access selected basis. Framed unframed access selected basis.
External devices access unframed DS3, framed unchannelized DS3, unframed framed unchannelized unframed (clear channel) T1s, framed T1s, unframed (clear channel) E1s, framed E1s, arbitrary rate clear channel data stream (eg. fractional DS3), transparent virtual tributaries transparent tributary units over this interface.
System side operates either 19.44 77.76 MHz. Line side operates 19.44MHz communicate with PM4318 OCTLIU PM4319 OCTLIU
Provides high density byte serial interconnect framed unframed TEMUX links. Utilizes Add/Drop configuration asynchronously mutliplex T1s, DS3s, with multiple payload link layer processors. Line side system side interfaces configured bus.
Scaleable Bandwidth Interconnect (SBI) Bus:
Alarm status, F-bit inband signaling control available using otherwise unused positions.
access over well with H-MVIP data interface. Common Channel Signaling H-MVIP access available with bus, serial H-MVIP data interfaces.
RELEASED DATA SHEET PMC-1991437 ISSUE
PM8316 TEMUX
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
Transmit timing mastered either TEMUX layer device connecting bus. Timing mastership selectable tributary basis, where tributary either individual DS3.
Channel associated signaling bits channelized explicitly identified across bus.
RELEASED DATA SHEET PMC-1991437 ISSUE
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
SONET/SDH Drop Multiplexers
Optical Access Equipment
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
Digital Access Cross-Connect Systems
Channelized Unchannelized Frame Relay Interfaces
C-Bit Parity Based Multiplexer
Based Multiplexer
SONET/SDH Terminal Multiplexers
Frame Relay switches access devices (FRADS)
High density interfaces multiplexers, multi-service switches, routers digital modems.
High density interfaces multiplexers, multi-service switches, routers digital modems.
APPLICATIONS
RELEASED DATA SHEET PMC-1991437 ISSUE
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
Bell Communications Research Wideband Broadband Digital CrossConnect Systems Generic Criteria, TR-NWT-000233, Issue November 1993
Bell Communications Research Alarm Indication Signal Requirements Objectives, TR-TSY-000191 Issue 1986
Bell Communications Research DS-1 Rate Digital Service Monitoring Unit Functional Specification, TA-TSY-000147, Issue October, 1987
Bell Communications Research, TR-TSY-000009 Asynchronous Digital Multiplexes Requirements Objectives, Issue 1986
American National Standard Telecommunications Integrated Services Digital Network (ISDN) Primary Rate- Customer Installation Metallic Interfaces Layer Specification, ANSI T1.408-1990
American National Standard Telecommunications Customer Installation-toNetwork Metallic Interface Specification, ANSI T1.404-1994
American National Standard Telecommunications Carrier Customer Installation DS-1 Metallic Interface Specification, ANSI T1.403-1999
American National Standard Telecommunications Digital Hierarchy Layer In-Service Digital Transmission Performance Monitoring, ANSI T1.231-1997
American National Standard Telecommunications Digital Hierarchy Formats Specification, ANSI T1.107-1995
American National Standard Telecommunications ANSI T1.105.02 "Synchronous Optical Network (SONET) Payload Mappings," October 1995.
American National Standard Telecommunications ANSI T1.105 "Synchronous Optical Network (SONET) Basic Description Including Multiplex Structure, Rates, Formats," October 1995.
American National Standard Telecommunications Digital Hierarchy Synchronous Format Specifications, ANSI T1.103-1993
REFERENCES
RELEASED DATA SHEET PMC-1991437 ISSUE
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
ETSI 417-1-1 "Transmission Multiplexing (TM); Generic Functional Requirements Synchronous Digital Hierarchy (SDH) equipment; Part 1-1: Generic processes performance," January, 1996.
ETSI 347-1 Signaling Protocols Switching (SPS); Interfaces Digital Local Exchange (LE) V5.2 Interface Support Access Network (AN) Part V5.2 Interface Specification, September 1994.
ETSI 324-1 Signaling Protocols Switching (SPS); interfaces Digital Local Exchange (LE) V5.1 Interface Support Access Network (AN) Part V5.1 Interface Specification, February, 1994.
ETSI Access Digital Section ISDN Primary Rates, 1994
ETSI ISDN Primary Rate User-Network Interface Specification Test Principles, 1992.
Study Group XVIII Report 105, Geneva, 9-19 June 1992
AT&T Accunet T1.5 Service Description Interface Specification, 62411, December, 1990
AT&T Requirements Interfacing Digital Terminal Equipment Services Employing Extended Superframe Format, 54016, September, 1989.
Bell Communications Research OTGR: Network Maintenance Transport Surveillance Generic Digital Transmission Surveillance, TR-TSY-000820, Section 5.1, Issue June 1990
Bell Communications Research Transport Systems Generic Requirements (TSGR): Common Requirement, TR-TSY-000499, Issue December, 1993
Bell Communications Research Integrated Digital Loop Carrier Generic Requirements, Objectives, Interface, TR-NWT-000303, Issue December, 1992
Bellcore GR-253-CORE "SONET Transport Systems: Common Criteria," Issue Revision December 1997.
Bell Communications Research Digital Interface Between SLC96 Digital Loop Carrier System Local Digital Switch, TR-TSY-000008, Issue August 1987
RELEASED DATA SHEET PMC-1991437 ISSUE
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
ITU-T Recommendation O.151 Error Performance Measuring Equipment Operating Primary Rate Above, October 1992 ITU-T Recommendation O.152 Error Performance Measuring Equipment Rates kbit/s kbit/s, October 1992
ITU-T Recommendation I.431 Primary Rate User-Network Interface Layer Specification, 1993.
ITU-T Recommendation G.965, V-Interfaces Digital Local Ex-hange (LE) V5.2 Interface (Based 2048 kbit/s) Support Access Network (AN), March 1995.
ITU-T Recommendation G.964, V-Interfaces Digital Local Ex-hange (LE) V5.1 Interface (Based 2048 kbit/s) Support Access Network (AN), June 1994.
ITU-T Recommendation G.823, Control Jitter Wander within Digital Networks which Based 2048 kbit/s Hierarchy, 03/94
ITU-T Recommendation G.783 Characteristics Synchronous Digital Hierarchy (SDH) Equipment Functional Blocks, April, 1997.
ITU-T Recommendation G.775, Loss Signal (LOS) Alarm Indication Signal (AIS) Defect Detection Clearance Criteria, 11/94
ITU-T Recommendation G.747 Second Order Digital Multiplex Equipment Operating 6312 kbit/s Multiplexing Three Tributaries 2048 kbit/s, 1988
ITU-T Recommendation G.707 Network Node Interface Synchronous Digital Hierarchy, 1996
ITU-T Recommendation G.732 Characteristics Primary Multiplex Equipment Operating 2048 kbit/s, 1993.
ITU-T Recommendation G.706 Frame Alignment Procedures Relating G.704 Frame Structures, 1991.
ITU-T Recommendation G.704 Synchronous Frame Structures Used Primary Hierarchical Levels, July 1995.
ETSI, Generic Functional Requirements Synchronous Digital Hierarchy (SDH) Equipment, 1996
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HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
GO-MVIP, H-MVIP Standard, Release1.1a, 1997
GO-MVIP, Multi-Vendor Integration Protocol, MVIP-90, Release 1.1, 1994
Nippon Telegraph Telephone Corporation Technical Reference HighSpeed Digital Leased Circuit Services, Third Edition, 1990.
Standard JT-I431 ISDN Primary Rate User-Network Interface Layer Specification, 1995.
Standard JT-G706 Frame Synchronization Procedure
Standard JT-G704 Frame Structures Primary Secondary Hierarchical Digital Interfaces, 1995.
International Organization Standardization, 3309:1984 High-Level Data Link Control procedures Frame Structure
ITU-T Recommendation Q.921 ISDN User-Network Interface Data Link Layer Specification, March 1993
ITU-T Recommendation O.153 Basic Parameters Measurement Error Performance Rates below Primary Rate, October 1992.
RELEASED DATA SHEET PMC-1991437 ISSUE
PM8316 TEMUX
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
FREEDM 84A672
APPI
Utopia
Utopia APPI
Figure
Any-Service-Any-Port Application
Spectra
TEMUX
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
Figure illustrates frame relay (FREEDM84A672), circuit emulation (AAL1gator32) Ainverse multiplexing (IMA84) supported same port with common enabling technology.
AAL1gator32
Telecom
Packet/Cell Interworking Function
APPLICATION EXAMPLES
RELEASED DATA SHEET PMC-1991437 ISSUE
PM8316 TEMUX
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
TEMUX TEMUX
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
Spectra
TEMUX
FREEDM
Interworking Function
Utopia
Packet/Cell
APPI
TEMUX
APPI
Utopia
Telecom
Figure
High Density Frame Relay Application
RELEASED DATA SHEET PMC-1991437 ISSUE
PM8316 TEMUX
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
FPGA
IFBWCLK
IFBWEN
RMFPO RDATO RSCLK
TMFPO
TEMUX-84
EFBWDREQ EFBWDAT EFBWCLK
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
support evolving fractional applications, flow-controlled ports provide access bandwidth. Several non-standard schemes have been devised portion payload. Given that these protocols subject change, they best supported external programmable logic. Figure illustrates implementation. Other implementations applications possible. ingress direction, framed presented FPGA, whose responsibility identify utilitized bits payload. Valid bits indicated Ingress Flexible Bandwidth Port enable signal, IFBWEN.
44.736
FPGA
EFBWEN
TMFPI
TICLK
TDATI
IFBWDAT
Figure
Fractional Application
RELEASED DATA SHEET PMC-1991437 ISSUE
PM8316 TEMUX
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
egress direction, FPGA formats payload DS3, while TEMUX inserts frame overhead. FPGA contains data buffer. Based frame alignment dictated TMFPO signal, FPGA inserts bits from data buffer into payload according protocol supported. ensure data buffer replenished, FPGA asserts EFBWDREQ signal initiate transfer bit. Egress Flexible Bandwidth Port responds asserting EFWBEN coincident with EFWBDAT presenting valid data. participates modulating SAJUST_REQ output match data rate that required keep internal FIFOs centered.
bits collected into bytes TEMUX inserted into payload Drop bus.
RELEASED DATA SHEET PMC-1991437 ISSUE
PM8316 TEMUX
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
Figure block diagram Transmux Mode.
LIUs
DS3/E3 System
Figure
TEMUX Block Diagram
System side access available Synchronous H-MVIP interfaces bus. line side access clock data interface line interface units (LIUs) mapped into SONET/SDH telecom bus. Unchannelized system side access available through bus.
D3MA Telecom EVTPP
DS3/E3 TRAN
PISO
Figure shows complete TEMUX links multiplexed into DS3s mapped into telecom SONET VT1.5 virtual tributaries TU-11 TU-12 tributary units. links mapped into telecom SONET virtual tributaries TU-12 tributary units. Line side interface also configured bus.
Egress Flexible Port Egress H-MVIP T1/E1 JAT84 T1/E1 JAT84 T1/E1 TRAN84 T1/E1 FRMR84 T1/E1 ELST84
H-MVIP EXSBI System Side T1/E1 ELST84 INSBI T1/E1 SIGX84 Ingress H-MVIP H-MVIP Ingress Flexible Port
Level Block Diagram
TTOP
TRAP
INSBI (byte)
TTMP (bit)
Line Side
IVTPP Telecom D3MD
RTOP/ RTTB
RTDM (bit) EXSBI (byte)
DS3/E3 FRMR
PISO
LIUs
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
DS3/E3 System
BLOCK DIAGRAM
RELEASED DATA SHEET PMC-1991437 ISSUE
PM8316 TEMUX
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
Figure
LIUs
TRAN
Multiplexer Block Diagram
Figure shows TEMUX configured multiplexer, connected synchronous H-MVIP system side bus. this example TEMUX provides synchronous access fully channelized (access DS0s) multiplexed into DS3. There also synchronous H-MVIP access channel associated signaling channels (CAS). Additional H-MVIP interfaces used provide synchronous access common channel signaling channels (CCS), although this same information available within data H-MVIP signals.
T1/E1 TRAN84 T1/E1 T1/E1 ELST84 T1/E1 ELST84 Egress
Multiplexer Mode Block Diagram
T1/E1 SIGX84 Ingress
PISO
T1/E1 JAT84 T1/E1 JAT84
LIUs
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
SIPO
RELEASED DATA SHEET PMC-1991437 ISSUE
PM8316 TEMUX
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
VTPP
TTOP
TRAP
INSBI
Telecom
VTPP RTOP/ RTTB
TTMP (bit)
Figure
VT/TU Mapper Block Diagram
Figure shows TEMUX configured mapper. this mode TEMUX bypasses framers provides access independent unframed 1.544 Mbit/s streams independent unframed 2.048 Mbit/s streams. 1.544 Mbit/s 2.048 Mbit/s streams accessed system side bus. framers used monitor passing traffic either ingress egress direction. Multiplexer mode operates much same mapper shown Figure
T1/E1 JAT84 T1/E1 JAT84
EXSBI T1/E1 FRMR84 INSBI
VT/TU Mapper Only Mode Block Diagram
RTDM (bit) EXSBI
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
RELEASED DATA SHEET PMC-1991437 ISSUE
PM8316 TEMUX
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
Figure
DS3/E3 Framer Only Mode Block Diagram
TCLK TPOS/TDAT TNEG/FP
B3ZS/ HDB3 Encode
TRAN DS3/E3 Tran Fram DS3/E3 eceive Fram
TDPR HDLC
Figure shows TEMUX configured framer. this mode TEMUX provides access three full DS3/E3 unchannelized payloads. payload access (right side diagram) clock data interfacing modes, utilizing gapped clock mask DS3/E3 overhead bits second utilizing ungapped clock with overhead indications separate overhead signal. also used provide access unchannelized DS3/E3.
RCLK/VCLK RPOS/RDAT RNEG/RLCV
B3ZS/ HDB3 Decod
RDLC HDLC
Perf. onitor
T1/E1 Extraction/Insertion Alarm/Error Response Figure below shows positioning interaction TXFRMR RXFRMR when TEMUX configured High Density Framer mode. TXFRMR insert HDLC messages software with THDL. also insert messages automatically based upon information gathered RXFRMR. RXFRMR collects T1/E1 receieved PMON data optionally sends this information TXFRMR. RXFRMR also sends received HDLC stream RDHL processing. Figure also shows RXFRMR sending reponse indications TXFRMR informing when
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
TFPO/FPO/TGAPC RGAPCLK/RSCLK RDATO RFPO/RMFPO ROVRHD
DS3/E3 Framer Only Block Diagram
RELEASED DATA SHEET PMC-1991437 ISSUE
PM8316 TEMUX
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
HDLC Receiver (PRM Processing) RHDL
Figure
High Density Framer Mode T1/E1 Block Diagram
RJAT
From SONET/SDH Demappers Demux from Line Side
T1/E1 Receive Framer RXFRMR
SIGX/RXELST/RPCC System side
insert Yellow alarm, FEBEs bits) Alarm bit) towards line side.
APRM Data
HDLC Transmitter (PRM Insertion) THDL
SONET/SDH Mappers Line Side
Yellow Alarm Response Indication
TJAT
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
Figure shows T1/E1 PMON extraction block diagram when TEMUX configured Mapper/Multiplexer mode. this mode T1/E1 data carried clear channel bi-directionally between line side system side. There ability collect T1/E1 PMON, RXFRMR extract FDL, RHDL either direction, only direction time. TXPMON RJAT Indirect Channel Data Register selects chooses direction PMON extraction. TXFRMR available this mode, thus HDLC insertion possible, insertion Yellow, FEBEs RAI.
T1/E1 Transmit Framer TXFRMR
From TXELST/TPCC System side
RELEASED DATA SHEET PMC-1991437 ISSUE
PM8316 TEMUX
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
From SONET/SDH Demappers Demux from Line Side
RJAT TXPMON
RPCC System side
TJAT
T1/E1 Receive Framer RXFRMR
HDLC Receiver (PRM Processing) RHDL
Figure
Mapper/Multiplexer Mode T1/E1 Block Diagram
SONET/SDH Mappers Line Side
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
more information Transmux, section 9.2.
TXFRMR available this mode, thus HDLC insertion possible, insertion Yellow, FEBEs RAI.
Figure below shows T1/E1 PMON extraction block diagram when TEMUX configured Transmux mode. this mode T1/E1 data carried clear channel bi-directionally between Mulitplexers T1/E1 Mappers. There ability collect T1/E1 PMON, RXFRMR extract FDL, RHDL either direction, only direction time. TXPMON RJAT Indirect Channel Data Register selects chooses direction PMON extraction.
From TPCC System side
RELEASED DATA SHEET PMC-1991437 ISSUE
PM8316 TEMUX
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
From SONET/SDH Demappers
TXPMON
TJAT
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
RJAT
SONET/SDH Mappers
T1/E1 Receive Framer RXFRMR
HDLC Receiver (PRM Processing) RHDL
Figure
Transmux Mode T1/E1 Block Diagram
Muliplexer
From Demultiplexer
RELEASED DATA SHEET PMC-1991437 ISSUE
PM8316 TEMUX
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
ingress direction, each links either demultiplexed from channelized extracted from SONET VT1.5, TU-11 TU-12 mapped bus. Each framer configured frame common signal formats (SF, SLC96, Japanese variants) bypassed (unframed mode). Each framer detects presence Yellow patterns also integrates Yellow, Red, alarms. performance monitoring with accumulation CRC-6 errors, framing errors, out-of-frame events, changes frame alignment provided. TEMUX
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
Each framers transmitters independently software configurable, allowing timing master feature selection without changes external wiring. tributaries mixed VC-3/TUG-3/DS3 granularity.
TEMUX used SONET/SDH VT/TU mapper multiplexer with performance monitoring either ingress egress direction E1s. this configuration transmit framers disabled either ingress egress signals routed framers performance monitoring purposes, which include error event accumulation, alarm monitoring HDLC termination.
This device also configured framer, providing external access full payload, VT/TU mapper, providing access unframed 1.544 Mbit/s 2.048 Mbit/s links.
TEMUX supports asynchronous multiplexing demultiplexing DS1s into three signals specified ANSI T1.107, Bell Communications Research TR-TSY-000009 ITU-T Rec. G.747. supports asynchronous byte synchronous mapping demapping into SONET/SDH specified ANSI T1.105, Bell Communications Research GR-253-CORE ITU-T Recommendation G.707. TEMUX also supports mapping into TU-12s. Transparent VT1.5s TU-11s Transparent VT2s TU-12s transferred between SONET/SDH interface interface.
PM8316 High Density T1/E1 Framer with Integrated VT/TU Mappers Multiplexers (TEMUX feature-rich device applications requiring high density link termination over (G.747) channelized channelized SONET/SDH facilities.
DESCRIPTION
RELEASED DATA SHEET PMC-1991437 ISSUE
PM8316 TEMUX
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
egress direction, framing generated into either multiplex according ITU-T Rec. G.747 SONET/SDH mapped bus. Each transmitter generates framing basic G.704 signal. signaling multiframe alignment structure multiframe structure optionally inserted. Framing optionally disabled. Transmission
performance monitoring with accumulation CRC-4 errors, block errors framing errors provided. TEMUX provides receive HDLC controller detection termination messages national bits. Detection 4-bit Sa-bit codewords defined ITU-T G.704 ETSI 300-233 supported. V5.2 link signal detection also supported. interrupt generated change state codewords. elastic store slip buffering rate adaptation backplane timing provided, signaling extractor that supports signaling debounce, signaling freezing, idle code substitution, digital milliwatt tone substitution, data inversion, signaling fixing per-channel basis. Receive side data signaling trunk conditioning also provided.
framers support detection various alarm conditions such loss frame, loss signaling multiframe loss multiframe. framers also support reception remote alarm signal, remote multiframe alarm signal, alarm indication signal, time slot alarm indication signal.
ingress direction, each links either demultiplexed from according ITU-T Rec. G.747 extracted from SONET/SDH TU-12 mapped bus. Each framer detects indicates presence remote alarm patterns also integrates alarms.
egress direction, framing generated into either multiplex SONET/SDH mapped bus. Each transmitter frames formats, framing optionally disabled. TEMUX supports signaling insertion, idle code substitution, data insertion, line loopback, data inversion zero-code suppression per-DS0 basis. PRBS generation detection supported framed unframed basis.
also detects presence oriented codes, detects terminates HDLC messages data link. HDLC messages terminated byte FIFO. elastic store that optionally supports slip buffering adaptation backplane timing provided, signaling extractor that supports signaling debounce, signaling freezing interrupt signaling state change per-DS0 basis. TEMUX also supports inband loopback code generation detection, idle code substitution, digital milliwatt code insertion, data link extraction, trunk conditioning, data sign magnitude inversion, pattern generation detection per-DS0 basis.
RELEASED DATA SHEET PMC-1991437 ISSUE
PM8316 TEMUX
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
Scaleable Bandwidth Interconnect (SBI) high density byte serial system interface provides higher levels integration dense interconnect. interconnects both synchronously asynchronously. allows transmit timing mastered either TEMUX link layer device connected bus. addition framed TEMUX transport unframed links framed unframed links over bus. When configured multiplexer/demultiplexer framer, TEMUX accepts outputs either digital B3ZS-encoded bipolar unipolar signals compatible with C-bit parity applications. receive direction, TEMUX frames signals with maximum average reframe time presence 10-3 error rate detects line code violations, loss signal, framing errors, parity errors, Cbit parity errors, block errors, AIS, receive failure idle code. framer off-line framer, indicating both frame (OOF) change frame alignment (COFA) events. error events (C-BIT, FEBE, etc.) still indicated while framer OOF, based previous frame alignment. When C-bit parity mode, Path Maintenance Data Link Alarm Control (FEAC) channels extracted. HDLC receivers provided Path Maintenance Data Link support. addition, valid bit-oriented codes FEAC channels detected available through microprocessor port. Error event accumulation also provided TEMUX Framing errors, line code violations, excessive zeros occurrences, parity errors, C-bit parity errors, block errors accumulated. Error accumulation continues even while off-line framers indicating OOF. counters intended
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
synchronous backplane systems, Mbit/s H-MVIP interfaces provided access 2016 channels, channel associated signaling (CAS) 2016 channels common channel signaling (CCS) combination thereof). signaling H-MVIP interface independent channel H-MVIP access. H-MVIP interfaces requires that common clocks frame pulse used along with slip buffers.
TEMUX generate jitter transmit clock from variety clock references, also provides jitter attenuation receive path. Three jitter attenuated recovered T1/E1 clocks routed outside TEMUX network timing applications.
4-bit codewords defined ITU-T G.704 ETSI 300-233 supported. PRBS generation detection supported framed unframed basis.
RELEASED DATA SHEET PMC-1991437 ISSUE
PM8316 TEMUX
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
Framing demultiplexed 6312 kbit/s data streams supports (ANSI TI.107) frame formats. maximum average reframe time DS2. receive failure detected M-bit F-bit errors accumulated. framer off-line framer, indicating both COFA events. Error
When configured multiplexer mode, seven 6312 kbit/s data streams demultiplexed multiplexed into each signal. stuffing rate adaptation performed. C-bits appropriately, with option inserting loopback requests. Interrupts generated upon detection loopback requests received DS3. inserted 6312 kbit/s tributaries both multiplex demultiplex directions. C-bit parity supported sourcing 6.3062723 clock, which corresponds stuffing ratio 100%.
TEMUX used framer transport framed unchannelized data streams complying ITU-T Recommendations G.751 G.832. line interface configured either unipolar HDB3encoded.
TEMUX also supports diagnostic options which allow insert, when appropriate transmit framing format, parity path parity errors, F-bit framing errors, M-bit framing errors, invalid P-bits, line code violations, all-zeros, AIS, Remote Alarm Indications, Remote Alarms. Pseudo Random Binary Sequence (PRBS) inserted into payload checked receive payload errors. fixed 100100. pattern available insertion directly into B3ZS encoder proper pulse mask shape verification.
transmit direction, TEMUX inserts framing, bits. When enabled C-bit parity operation, bit-oriented code transmitters HDLC transmitters provided insertion FEAC channels Path Maintenance Data Links into appropriate overhead bits. Alarm Indication Signals, Receive Failure idle signal inserted using either internal registers configured automatic insertion upon received errors. When operation selected, C-bit Parity (the first C-bit first sub-frame) forced toggle that downstream equipment will confuse M23-formatted stream with stuck-at-1 C-bits C-bit Parity application. Transmit timing from external reference from receive direction clock.
polled once second, sized saturate 10-3 error rate. Transfer count values holding registers initiated through microprocessor interface.
RELEASED DATA SHEET PMC-1991437 ISSUE
PM8316 TEMUX
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
SONET/SDH mapper maps demaps T1s, three DS3s into three STS-1 SPEs, TUG3s VC3s through three elastic stores. fixed stuff bits zeros ones under microprocessor control. asynchronous demapper performs majority vote C-bit decoding detect stuff requests asynchronous mappings. VT1.5/VT2/TU11/TU-12 mapper uses elastic store jitter attenuator capability minimize jitter introduced stuffing. TEMUX configured, controlled monitored generic 8-bit microprocessor through which internal registers accessed. sources interrupts masked acknowledged through microprocessor interface.
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
SONET/SDH line side interface provides STS-1 synchronous payload envelope processing generation, TUG3 tributary unit group processing generation within virtual container virtual container processing generation. payload processor aligns monitors performance SONET virtual tributaries (VTs) tributary units (TUs). Maintenance functions tributary include detection loss pointer, alarm, tributary path signal label mismatch tributary path signal label unstable alarms. Optionally interrupts generated assertion removal above alarms. Counts accumulated tributary path BIP-2 errors block basis FEBE indications. synchronous payload envelope generator generates tributary pointers calculates inserts tributary path BIP-2. generator also inserts FEBE, byte. Software force insertion tributary basis.
When configured framer unchannelized payload links available external device.
Each seven 6312 kbit/s multiplexers independently configured multiplex demultiplex four 1544 kbit/s DS1s three 2048 kbit/s according ITU-T Rec. G.747 into formatted signal. Tributary frequency deviations accommodated using internal FIFOs stuffing. C-bits appropriately, with option inserting loopback requests. Interrupts generated upon detection loopback requests received DS2. inserted speed tributaries both multiplex demultiplex directions.
events (FERF, MERR, FERR, PERR, RAI, framing word errors) still indicated while framer indicating OOF, based previous alignment.
RELEASED DATA SHEET PMC-1991437 ISSUE
PM8316 TEMUX
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
Figure
Diagram
TEMUX packaged 324-pin PBGA package having body size 23mm 23mm ball pitch center balls used signal I/Os thermal balls. names locations defined Description Table section Mechanical information this package section
DIAGRAM
PBGA
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
Bottom View
RELEASED DATA SHEET PMC-1991437 ISSUE
PM8316 TEMUX
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
Line Side Interface RCLK[3] RCLK[2] RCLK[1] Input
RNEG/RLCV[3] RNEG/RLCV[2] RNEG/RLCV[1]
Input
RPOS[3:1] RDAT[3:1] sampled rising edge associated RCLK default enabled sampled falling edge associated RCLK setting RFALL DS3/E3 Master Receive Line Options register. Negative Input Pulse (RNEG[3:1]). RNEG[3:1] represent negative pulses received B3ZSencoded DS3s HDB3-encoded when dual rail input format selected. Line code violation (RLCV[3:1]). RLCV[3:1] represent receive line code violations when single rail input format selected. RNEG[3:1] RLCV[3:1] sampled rising edge associated RCLK default enabled sampled falling edge RCLK setting RFALL DS3/E3 Master Receive Line Options register.
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
Receive Data Input (RDAT[3:1]). RDAT[3:1] represent (unipolar) input data streams when single rail input format selected.
RPOS/RDAT[3] RPOS/RDAT[2] RPOS/RDAT[1]
Input
Positive Input Pulse (RPOS[3:1]). RPOS[3:1] represent positive pulses received B3ZSencoded DS3s HDB3-encoded when dual rail input format selected.
Receive Input Clocks (RCLK[3:1]). RCLK[3:1] provide receive direction timing three DS3s E3s. RCLK[3:1] nominally 44.736 34.368 MHz, duty cycle clock inputs. RCLK input frequency must always remain within +/-20 such that generated demultiplexed frequency remains within channelized applications.
Name
Type
Function
DESCRIPTION
RELEASED DATA SHEET PMC-1991437 ISSUE
PM8316 TEMUX
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
TPOS[3:1] TDAT[3:1] updated falling edge associated TCLK default enabled updated rising edge associated TCLK setting TRISE DS3/E3 Master Transmit Line Options register. TPOS[3:1] TDAT[3:1] updated TICLK[3:1] rather than TCLK[3:1] when TICLK DS3/E3 Master Transmit Line Options register set.
Transmit Data Output (TDAT[3:1]). TDAT[3:1] represent (unipolar) output data streams when single rail output format selected.
TPOS/TDAT[3] TPOS/TDAT[2] TPOS/TDAT[1]
Output Transmit Positive Pulse (TPOS[3:1]). TPOS[3:1] represent positive pulses transmitted B3ZSAA1 encoded HDB3-encoded lines when dualrail output format selected.
TCLK[3] TCLK[2] TCLK[1]
Output
Transmit Clock (TCLK[3:1]). TCLK[3:1] provide timing circuitry downstream transmitters TEMUX TCLK[3:1] nominally 44.736 34.368 MHz, duty cycle clocks.
Name
Type
Function
RELEASED DATA SHEET PMC-1991437 ISSUE
PM8316 TEMUX
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
TICLK[3] TICLK[2] TICLK[1]
Input
Transmit input clock (TICLK[3:1]). TICLK[3:1] provides transmit direction timing three DS3s E3s. TICLK[3:1] nominally 44.736 34.368 MHz, duty cycle clocks.
TNEG[3:1] TMFP[3:1] updated falling edge associated TCLK default enabled updated rising edge associated TCLK setting TRISE DS3/E3 Master Transmit Line Options register. TNEG[3:1] TMFP[3:1] updated TICLK[3:1] rather than TCLK[3:1] when TICLK DS3/E3 Master Transmit Line Options register set.
Transmit Multiframe Pulse (TMFP[3:1]). These signals mark transmit frame alignment when configured single rail operation. TMFP[3:1] indicate position overhead bits transmit transmission system stream, TDAT[3:1]. TMFP[3:1] high during first (X1) multiframe frame.
TNEG/TMFP[3] TNEG/TMFP[2] TNEG/TMFP[1]
Output Transmit Negative Pulse (TNEG[3:1]). TNEG[3:1] represent negative pulses transmitted B3ZS-encoded HDB3-encoded lines when dual-rail output format selected.
Name
Type
Function
RELEASED DATA SHEET PMC-1991437 ISSUE
PM8316 TEMUX
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
Framer Recovered Clock (RSCLK[3:1]). RSCLK[3:1] valid when TEMUX configured framers setting OPMODE_SPEx[2:0] bits Configuration registers. When demapped from SONET/SDH (i.e. LINEOPT_SPEx 01), RSCLK gapped version CLK52M.
RDATO[3] RDATO[2] RDATO[1]
Output
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
demapped RSCLK must externally dejittered when connecting PM73122 AAL1gator32 device. RSCLK[3:1] recovered clocks timing references RDATO[3:1], RFPO/RMFPO[3:1], ROVRHD[3:1]. Framer Receive Data (RDATO[3:1]). RDATO[3:1] valid when TEMUX configured framers setting OPMODE_SPEx[2:0] bits Configuration registers. RDATO[3:1] received data aligned RFPO/RMFPO[3:1] ROVRHD[3:1]. RDATO[3:1] updated either falling rising edge associated RGAPCLK RSCLK, depending value RSCLKR Master Unchannelized Interface Options register. default, RDATO[3:1] will updated falling edge associated RGAPCLK[3:1] RSCLK[3:1].
RGAPCLK[x] recovered clock timing reference RDATO[x]. RGAPCLK[3:1] held either high during positions which correspond overhead.
RGAPCLK/RSCLK Output RGAPCLK/RSCLK RGAPCLK/RSCLK
Framer Recovered Gapped Clock (RGAPCLK[3:1]). RGAPCLK[3:1] valid when TEMUX configured framers setting OPMODE_SPEx[2:0] bits Configuration registers RXGAPEN Master Unchannelized Interface Options register.
System Side Interface
Name
Type
Function
RELEASED DATA SHEET PMC-1991437 ISSUE
PM8316 TEMUX
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
RFPO/RMFPO[3:1] updated either falling rising edge associated RSCLK depending setting RSCLKR Master Unchannelized Interface Options register. ROVRHD[3] ROVRHD[2] ROVRHD[1] Output Framer Receive Overhead (ROVRHD[3:1]). ROVRHD[3:1] valid when TEMUX configured framers setting OPMODE_SPEx[2:0] bits Configuration registers.
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
ROVRHD[3:1] will high whenever data RDATO[3:1] corresponds overhead position. ROVRHD[3:1] updated either falling rising edge associated RSCLK depending setting RSCLKR Master Unchannelized Interface Options register.
RMFPO[3:1] aligned RDATO[3:1] indicate position first each M-frame first each G.751 G.832 frame. This selected setting RXMFPO Master Unchannelized Interface Options Registers.
RFPO[3:1] aligned RDATO[3:1] indicate position first each M-subframe first each G.751 G.832 frame.
RFPO/RMFPO[3] RFPO/RMFPO[2] RFPO/RMFPO[1]
Output
Framer Receive Frame Pulse/Multi-frame Pulse (RFPO/RMFPO[3:1]). RFPO/RMFPO[3:1] valid when TEMUX configured framer only mode setting OPMODE_SPEx[2:0] bits Configuration registers.
Name
Type
Function
RELEASED DATA SHEET PMC-1991437 ISSUE
PM8316 TEMUX
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
TFPO/TMFPO[3:1] will updated falling edge TICLK when associated TDATIFALL register logic rising edge when TDATIFALL logic Framer Gapped Transmit Clock (TGAPCLK[3:1]). TGAPCLK[3:1] valid when TEMUX configured framers setting OPMODE_SPEx[2:0] bits Configuration registers setting TXGAPEN Master Unchannelized Interface Options register. TGAPCLK[3:1] derived from transmit reference clocks TICLK[3:1] from receive clock looptimed. overhead (gapped) positions generated internal device. TGAPCLK[3:1] held high during overhead positions. This clock useful interfacing devices which source payload data only.
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
mode, TMFPO[3:1] pulse high every 4760 clock cycles, giving reference M-frame indication. TMFPO[3:1] behaves same TFPO[3:1] applications. This selected setting TXMFPO Master Unchannelized Interface Options Registers.
mode, TFPO[3:1] pulse high every clock cycles, giving reference M-subframe indication. mode, TFPO[3:1] pulse high mark first frame.
TFPO/TMFPO/ TGAPCLK[3] TFPO/TMFPO/ TGAPCLK[2] TFPO/TMFPO/ TGAPCLK[1]
Output
Framer Transmit Frame Pulse/Multi-frame Pulse Reference (TFPO/TMFPO[3:1]). TFPO/TMFPO[3:1] valid when TEMUX configured framers setting OPMODE_SPEx[2:0] bits Configuration registers setting TXGAPEN Master Unchannelized Interface Options register.
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Function
RELEASED DATA SHEET PMC-1991437 ISSUE
PM8316 TEMUX
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
TDATI[3] TDATI[2] TDATI[1]
Input
Framer Transmit Data (TDATI[3:1]). TDATI[3:1] contain serial data transmitted when TEMUX configured framers setting OPMODE_SPEx[2:0] bits Configuration registers. TDATI[3:1] sampled rising edge associated TICLK TXGAPEN Master Unchannelized Interface Options register logic TXGAPEN logic then TDATI[3:1] sampled rising edge TGAPCLK. TDATI[3:1] configured sampled falling edge associated TICLK TGAPCLK setting TDATIFALL Master Unchannelized Interface Options register.
TGAPCLK[3:1] used sample associated TDATI[3:1] inputs.
mode, TGAPCLK gapped every TICLK cycles. G.832 mode, TGAPCLK gapped first bytes frame. G.751 mode, TGAPCLK gapped during frame alignment signal, remote alarm indication bit, national bit, justification service bits (bits Sets IV), optionally during bits available justification (bits determined PYLD&JUST Data Link Control register.
Name
Type
Function
RELEASED DATA SHEET PMC-1991437 ISSUE
PM8316 TEMUX
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
CMV8MCLK
Input
H-MVIP System Side Interfaces Common H-MVIP Clock (CMV8MCLK). common 8.192 Mbit/s H-MVIP data provides data clock receive transmit links configured operation 8.192 Mbit/s H-MVIP mode. CMV8MCLK used sample data MVID[1:21], MVED[1:21], CASID[1:21], CASED[1:21], CCSID[1:3], CCSED[1:3] TS0ID. CMV8MCLK nominally duty cycle clock with frequency 16.384 MHz. H-MVIP interfaces enabled SYSOPT[1:0] bits Global Configuration register. TEMUX configured H-MVIP operation, this clock tied high low.
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
TFPI/TMFPI[3:1] sampled rising edge associated TICLK. TFPI/TMFPI[3:1] configured sampled falling edge associated TICLK setting TDATIFALL Register 0x0202 0x100*N: Master Unchannelized Interface Options.
TMFPI[3:1] indicate position first each 4760-bit M-frame first each frame. TMFPI[3:1] required pulse every multiframe boundary. This selected setting TXMFPI Master Unchannelized Interface Options Registers.
TFPI[3:1] indicate position overhead bits each M-subframe first each G.751 G.832 frame. TFPI[3:1] required pulse every overhead bit.
TFPI/TMFPI[3] TFPI/TMFPI[2] TFPI/TMFPI[1]
Input
Framer Transmit Frame Pulse/Multiframe Pulse (TFPI/TMFPI[3:1]). TFPI/TMFPI[3:1] valid when TEMUX configured framers setting OPMODE_SPEx[2:0] bits Configuration registers.
Name
Type
Function
RELEASED DATA SHEET PMC-1991437 ISSUE
PM8316 TEMUX
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
H-MVIP interfaces enabled SYSOPT[1:0] bits Global Configuration registers. TEMUX configured H-MVIP operation, this clock tied high low.
CMMFP Master H-MVIP Interface Configuration register logic CMVFPB becomes multiframe pulse. Mulitframe alignment only relevant when F-bit being carried transparently egress direction alignment signaling required. support combination SLC96, CMVFPB must pulse multiple frames beginning frame. H-MVIP interfaces enabled SYSOPT[1:0] bits Global Configuration register. TEMUX configured H-MVIP operation, this frame pulse tied high low. CMVFPB frame pulse occurs multiples 125us sampled falling edge CMVFPC.
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
CMVFPB
Input
Common H-MVIP Frame Pulse (CMVFPB). active common frame pulse 8.192 Mbit/s HMVIP signals references beginning each frame links operating 8.192 Mbit/s H-MVIP mode.
CMVFPC used sample CMVFPB. CMVFPC nominally duty cycle clock with frequency 4.096 MHz. falling edge CMVFPC must aligned with falling edge CMV8MCLK with more than ±10ns skew.
CMVFPC
Input
Common H-MVIP Frame Pulse Clock (CMVFPC). common 8.192 Mbit/s H-MVIP frame pulse clock provides frame pulse clock receive transmit links configured operation 8.192 Mbit/s H-MVIP mode.
Name
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Function
RELEASED DATA SHEET PMC-1991437 ISSUE
PM8316 TEMUX
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
MVID[1] MVID[2] MVID[3] MVID[4] MVID[5] MVID[6] MVID[7] MVID[8] MVID[9] MVID[10] MVID[11] MVID[12] MVID[13] MVID[14] MVID[15] MVID[16] MVID[17] MVID[18] MVID[19] MVID[20] MVID[21]
Output
links mixed TUG-3/DS3 granularity. Each MVID[1:7], MVID[8:14] MVID[15:21] carries independent other groups seven. mode, MVID[7], MVID[14] MVID[21] unused.
MVID[x] aligned common H-MVIP 16.384 Mbit/s clock, CMV8MCLK, frame pulse clock, CMVFPC, frame pulse, CMVFPB. MVID[x] updated every second rising falling edge common H-MVIP 16.384Mb clock, CMV8MCLK, fixed common H-MVIP frame pulse clock, CMVFPC. updating edge CMV8MCLK selected CMVIDE Master H-MVIP Interface Configuration register.
H-MVIP Ingress Data (MVID[1:21]). MVID[x] carries recovered channels which have passed through elastic store. Each MVID[x] signal carries channels four complete E1s.
Name
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RELEASED DATA SHEET PMC-1991437 ISSUE
PM8316 TEMUX
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
CCSID[1] CCSID[2] CCSID[3]
Output Common Channel Signaling Ingress Data (CCSID[1:3]). mode, CCSID[1] carries common channel signaling channels extracted from each T1s. mode, CCSID[1:3] carries timeslots (15,16, from each E1s. CCSID formatted according H-MVIP standard.
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
CASID[1] CASID[2] CASID[3] CASID[4] CASID[5] CASID[6] CASID[7] CASID[8] CASID[9] CASID[10] CASID[11] CASID[12] CASID[13] CASID[14] CASID[15] CASID[16] CASID[17] CASID[18] CASID[19] CASID[20] CASID[21]
Output
CCSID[x] aligned common H-MVIP 16.384 Mbit/s clock, CMV8MCLK, frame pulse clock, CMVFPC, frame pulse, CMVFPB. CCSID updated every second rising falling edge CMV8MCLK fixed common H-MVIP frame pulse clock, CMVFPC. updating edge CMV8MCLK selected CMVIDE Master H-MVIP Interface Configuration register.
links mixed TUG-3/DS3 granularity. Each CASID[1:7], CASID[8:14] CASID[15:21] carries independent other groups seven. mode, CASID[7], CASID[14] CASID[21] unused.
CASID[x] aligned common H-MVIP 16.384 Mbit/s clock, CMV8MCLK, frame pulse clock, CMVFPC, frame pulse, CMVFPB. CASID[x] updated every second rising falling edge CMV8MCLK fixed common H-MVIP frame pulse clock, CMVFPC. updating edge CMV8MCLK selected CMVIDE Master H-MVIP Interface Configuration register.
Channel Associated Signaling Ingress Data (CASID[1:21]). Each CASID[x] signal carries four complete E1s. CASID[x] carries corresponding values channel carried MVID[x]. also carries framer alarm statuses.
Name
Type
Function
RELEASED DATA SHEET PMC-1991437 ISSUE
PM8316 TEMUX
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
MVED[1] MVED[2] MVED[3] MVED[4] MVED[5] MVED[6] MVED[7] MVED[8] MVED[9] MVED[10] MVED[11] MVED[12] MVED[13] MVED[14] MVED[15] MVED[16] MVED[17] MVED[18] MVED[19] MVED[20] MVED[21]
MVED[x] aligned common H-MVIP 16.384 Mbit/s clock, CMV8MCLK, frame pulse clock, CMVFPC, frame pulse, CMVFPB. MVID[x] sampled every second rising falling edge CMV8MCLK fixed common H-MVIP frame pulse clock, CMVFPC. sampling edge CMV8MCLK selected CMVEDE Master Common Ingress Serial H-MVIP Interface Configuration register. MVED[3] Schmitt triggered input. links mixed TUG-3/DS3 granularity. Each MVED[1:7], MVED[8:14] MVED[15:21] carries independent other groups seven. mode, MVED[7], MVED[14] MVED[21] unused.
Input
H-MVIP Egress Data (MVED[1:21]). egress data streams transmitted input these pins. Each MVED[x] signal carries channels four complete formatted according HMVIP standard.
TS0ID aligned common H-MVIP 16.384 Mbit/s clock, CMV8MCLK, frame pulse clock, CMVFPC, frame pulse, CMVFPB. TS0ID updated every second rising falling edge CMV8MCLK fixed common H-MVIP frame pulse clock, CMVFPC. updating edge CMV8MCLK selected CMVIDE Master H-MVIP Interface Configuration register.
TS0ID
Output Timeslot Ingress Data (TS0ID). mode, TS0ID carries first timeslot each frame.
Name
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RELEASED DATA SHEET PMC-1991437 ISSUE
PM8316 TEMUX
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
CCSED[1], CCSED[2], CCSED[3]
Input
Common Channel Signaling Egress Data (CCSED[1:3]). mode CCSED[1] carries common channel signaling channels transmitted each T1s. mode CCSED carries timeslots (15,16, transmitted each E1s. CCSED formatted according H-MVIP standard. CCSED aligned common H-MVIP 16.384 Mbit/s clock, CMV8MCLK, frame pulse clock, CMVFPC, frame pulse, CMVFPB. CCSED sampled every second rising falling edge CMV8MCLK fixed common H-MVIP frame pulse clock, CMVFPC. sampling edge CMV8MCLK selected CMVEDE Master H-MVIP Interface Configuration register.
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
CASED[1] CASED[2] CASED[3] CASED[4] CASED[5] CASED[6] CASED[7] CASED[8] CASED[9] CASED[10] CASED[11] CASED[12] CASED[13] CASED[14] CASED[15] CASED[16] CASED[17] CASED[18] CASED[19] CASED[20] CASED[21]
links mixed TUG-3/DS3 granularity. Each CASED[1:7], MVED[8:14] CASED[15:21] carries independent other groups seven. mode, CASED[7], CASED[14] CASED[21] unused.
CASED[x] aligned common H-MVIP 16.384 Mbit/s clock, CMV8MCLK, frame pulse clock, CMVFPC, frame pulse, CMVFPB. CASED[x] sampled every second rising falling edge CMV8MCLK fixed common H-MVIP frame pulse clock, CMVFPC. sampling edge CMV8MCLK selected CMVEDE Master H-MVIP Interface Configuration register.
Input
Channel Associated Signaling Egress Data (CASED[1:21]). Each CASED[x] signal carries four complete formatted according H-MVIP standard. CASED[x] carries corresponding values channel data carried MVED[x]. CASED[x] also present inband information control signaling insertion.
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RELEASED DATA SHEET PMC-1991437 ISSUE
PM8316 TEMUX
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
IFBWCLK[3:1] have maximum frequency 51.84 gapped required.
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
IFBWDAT[3] IFBWDAT[2] IFBWDAT[1]
IFBWDAT[3:1] sampled rising edge associated IFBWCLK input.
Input
Ingress Flexible Bandwidth Data (IFBWDAT[3:1]). These inputs present serial data insertion into System Drop (SDDATA[7:0]). Only bits which associated IFBWEN input sampled high accepted. Each data input associated with only used when associated configured carry fractional payload OPMODE_SPEx[2:0] bits Configuration registers. ordering big-endian, i.e. data presented SDDATA[7] received earlier time than data presented same byte SDDATA[0].
Each IFBWCLK samples associated IFBWDAT[3:1] IFBWEN[3:1] inputs rising edge.
IFBWCLK[3] IFBWCLK[2] IFBWCLK[1]
Input
Ingress Flexible Bandwidth Clocks (IFBWCLK[3:1]). IFBWCLK[3:1] clocks provide timing arbitrary bandwidth payload inserted into System Drop (SDDATA[7:0]). Each clock associated with only used when associated configured carry fractional payload OPMODE_SPEx[2:0] bits Configuration registers.
Port associated with Port associated with Port associated with
Flexible Bandwidth Ports
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RELEASED DATA SHEET PMC-1991437 ISSUE
PM8316 TEMUX
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
EFBWDREQ[3] EFBWDREQ[2] EFBWDREQ[1]
Input
Egress Flexible Bandwidth Data Requests (EFBWREQ[3:1]). data request input must asserted high EFBWCLK cycle each data required. response sampling EFWBDREQ[3:1] high, associated EFBWDAT output will either present available cycle later with accompanying assertion associated EFBWEN ignore request data ready. many applications (eg. frame relay ATM), every request will acknowledged with data. applications where source data fixed, permissible hold EFBWDREQ[3:1] high, which case EFBWEN identifies valid bytes. EFBWDREQ[3:1] sampled rising edge associated EFBWCLK input.
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
Each EFBWCLK samples associated EBWDREQ rising edge updates associated EFBWDAT] EFBWEN falling edge.
EFBWCLK[3:1] have maximum frequency 51.84 gapped required.
EFBWCLK[3] EFBWCLK[2] EFBWCLK[1]
Input
Egress Flexible Bandwidth Clocks (EFBWCLK[3:1]). EFBWCLK[3:1] clocks provide timing arbitrary bandwidth payload extracted from System (SADATA[7:0]). Each clock associated with only used when associated configured carry fractional payload OPMODE_SPEx[2:0] bits Configuration registers.
IFBWEN[3:1] sampled rising edge associated IFBWCLK input.
IFBWEN[3] IFBWEN[2] IFBWEN[1]
Input
Ingress Flexible Bandwidth Enables (IFBWEN[3:1]). logic high these inputs indicates valid associated IFBWDAT input. IFBWEN[3:1] inputs constrained such that maximum data rate each IFBWDAT[3:1] less than 48.96 Mbit/s.
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Type
Function
RELEASED DATA SHEET PMC-1991437 ISSUE
PM8316 TEMUX
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
RECVCLK3
RECVCLK2
RECVCLK1
Output
Recovered Clocks Recovered Clock (RECVCLK1). This clock output recovered de-jittered clock from framers framers. Recovered Clock (RECVCLK2). This clock output recovered de-jittered clock from framers framers. Recovered Clock (RECVCLK3). This clock output recovered de-jittered clock from framers framers.
Output
Output
EFBWEN[3:1] updated falling edge associated EFBWCLK input.
EFBWEN[3] EFBWEN[2] EFBWEN[1]
Output Egress Flexible Bandwidth Enables (EFBWEN[3:1]). logic high these outputs indicates valid associated EFBWDAT output. EFBWEN[3:1] will only asserted, with cycle latency, response sampled logic high associated EFBWDREQ, then only data available presenting associated EFBWDAT.
EFBWDAT[3:1] updated falling edge associated EFBWCLK input.
EFBWDAT[3] EFBWDAT[2] EFBWDAT[1]
Output Egress Flexible Bandwidth Data (EFBWDAT[3:1]). These outputs present serial data extracted from System (SADATA[7:0]). Only bits which associated EFBWEN output simultaneously high valid. Each data input associated with only used when associated configured carry fractional payload OPMODE_SPEx[2:0] bits Configuration registers. ordering big-endian, i.e. data received SADATA[7] transmitted earlier time than data received same byte SADATA[0].
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Function
RELEASED DATA SHEET PMC-1991437 ISSUE
PM8316 TEMUX
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
This input tied ground applications that RECVCLK1/2/3 outputs 2.048 clocks.
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
LREFCLK
Input
Line Reference Clock (LREFCLK). This signal provides reference timing SONET telecom interface. incoming byte interface telecom bus, LDC1J1V1, LDDATA[7:0], LDDP, LDPL, LDTPL, LDV5, LDAIS LAC1 sampled rising edge LREFCLK. outgoing byte interface, LADATA[7:0], LADP, LAPL, LAC1J1V1 LAOE/LATPL updated rising edge LREFCLK. This clock held Telecom interface unused. This clock nominally 19.44 +/-20ppm 77.76 +/-20ppm clock with duty cycle. This clock must phase locked SREFCLK external connected SREFCLK.
Telecom Line Side Interface
XCLK_E1
Input
Crystal Clock Input (XCLK_E1). This input clocks digital phase locked loop that performs jitter attenuation recovered clocks which drive RECVCLK1/2/3 outputs. XCLK_E1 nominally 49.152 32ppm, duty cycle clock when configured modes.
This input tied ground applications that RECVCLK1/2/3 outputs s1.544 clocks.
XCLK_T1
Input
Crystal Clock Input (XCLK_T1). This input clocks digital phase locked loop that performs jitter attenuation recovered clocks which drive RECVCLK1/2/3 outputs. XCLK_T1 nominally 37.056 32ppm, duty cycle clock.
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RELEASED DATA SHEET PMC-1991437 ISSUE
PM8316 TEMUX
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
LAC1
Input
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
LAC1 sampled rising edge LREFCLK.
LAC1 high mark first byte first transport envelope frame frame multiframe LADATA[7:0] bus. LAC1 need presented every occurrence multiframe.
Line Frame Pulse (LAC1). timing signal identifies frame multiframe boundaries Data LADATA[7:0].
expected held static.
Input
Line 77.76 select input determines expected frequency LREFCLK. low, LREFCLK expected 19.44 MHz. high, LREFCLK expected 77.76 data driven sampled every fourth cycle. Schmitt triggered input.
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Type
Function
RELEASED DATA SHEET PMC-1991437 ISSUE
PM8316 TEMUX
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
system with multiple TEMUX sharing same Line only device should have LAC1J1V1 connected. devices must configured TXPTR[9:0] bits SONET/SDH Transmit Pointer Configuration TTMP Telecom Interface Configuration registers same location. When high, LAC1J1V1 only valid (i.e. identifies first concatenated STM-4 data stream) LSTM[1:0] bits Master Configuration register (0x0006) "00". LAC1J1V1 updated rising edge LREFCLK.
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
LAC1J1V1
Output AA11 Line Composite Timing Signal (LAC1J1V1). composite timing signal identifies frame, payload tributary multiframe boundaries Line Data LADATA[7:0]. LAC1J1V1 pulses high with Line Payload Active signal LAPL mark first STS-1 (STM-0/AU3) identification byte equivalently Sidentification byte Optionally LAC1J1V1 signal pulses high with LAPL high mark path trace byte Optionally LAC1J1V1 signal pulses high byte indicate tributary multiframe boundaries.
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Type
Function
RELEASED DATA SHEET PMC-1991437 ISSUE
PM8316 TEMUX
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
Line Tributary Payload Active (LATPL). tributary payload active signal marks bytes carrying tributary payload. LATPL high during each tributary payload byte LADATA[7:0] bus. LATPL will during transport overhead, path overhead, bytes bytes. indicate pointer adjustments, LATPL will asserted appropriately during byte following byte tributary. default, LATPL only asserted during SONET/SDH tributaries assigned this device determined LAOE TTMP Tributary Control registers during byte positions. options, LATPL driven during transport overhead, bytes STM-1 when configured 77.76MHz operation time. LAOE/LATPL updated rising edge LREFCLK.
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
This intended control external multiplexer when multiple TEMUX driving Telecom during their individual tributaries. This same function accomplished with tristate drivers increased tolerance tributary configuration problems possible with external mux. This output controlled LAOE TTMP Tributary Control registers when egress VTPP bypassed. When egress VTPP bypassed TU-3 being mapped, LAOE high.
Line Output Enable (LAOE). output enable signal asserted high whenever Line being driven which co-coincident with Line outputs coming tri-state.
LAOE/LATPL
Tristate AB11 LATPLSEL SONET/SDH Master Egress Output VTPP Configuration register determines function this tristate output. When LATPLSEL logic signal LATPL. When LATPLSEL logic signal LAOE.
Name
Type
Function
RELEASED DATA SHEET PMC-1991437 ISSUE
PM8316 TEMUX
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
default, LADATA[7:0] only asserted during SONET/SDH tributaries assigned this device determined LAOE TTMP Tributary Control registers during (when LAJ1EN logic (when LAJ1EN logic byte positions; otherwise, high impedance. options, LADATA[7:0] driven during transport overhead, bytes STM-1 when configured 77.76MHz operation time.
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
LADATA[7:0] updated rising edge LREFCLK.
LADATA[0] LADATA[1] LADATA[2] LADATA[3] LADATA[4] LADATA[5] LADATA[6] LADATA[7]
Output Line Data (LADATA[7:0]). data Tristate contains SONET transmit payload data byte AA13 serial format. transport overhead bytes AB13 00h. phase relation (VC) transport frame determined AA12 composite timing signal LAC1J1V1 software programmable valid pointer offset. LADATA[7] most significant (corresponding each serial word, first transmitted).
Name
Type
Function
RELEASED DATA SHEET PMC-1991437 ISSUE
PM8316 TEMUX
HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER
LAPL
Output AA14 Line Payload Active (LAPL). payload active signal identifies payload bytes Tristate LADATA[7:0]. LAPL high during path overhead payload bytes during transport overhead bytes.
PROPRIETARY CONFIDENTIAL PMC-SIERRA CUSTOMERS' INTERNAL
LADP updated rising edge LREFCLK.
default, LAPL only asserted during SONET/SDH tributaries assigned this device determined LAOE TTMP Tributary Control registers during (when LAJ1EN logic (when LAJ1EN logic byte positions; otherwise, high impedance. options, LAPL driven during transport overhead, bytes STM-1 when configured 77.76MHz operation time. LAPL updated rising edge LREFCLK.
default, LADP only asserted during SONET/SDH tributaries assigned this device determined LAOE TTMP Tributary Control registers during (when LAJ1EN logic (when LAJ1EN logic byte positions; otherwise, high impedance. options, LADP driven during tra
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