Semiconductor ML9211 This version: Aug. 1999 ML9211 56-Bit D
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E2C0045-19-83 Semiconductor
Semiconductor ML9211
This version: Aug. 1999 ML9211
56-Bit Duplex/Triplex (1/2 duty duty) Controller/Driver with Digital Dimming
ML9211 full CMOS controller/driver Duplex Triplex (1/2 duty duty) vacuum fluorescent display tube. consists 56-segment driver multiplexed drive segments, 10-bit digital dimming circuit. ML9211 features selection master mode slave mode, therefore used expand segments driver with keyscan converter function. ML9211 provides interface with microcontroller only three signal lines: DATA CLOCK
FEATURES
Logic supply voltage (VDD) 5.5V Driver supply voltage (VDISP) Duplex/Triplex (1/2 duty duty) selectable DUP/TRI=1/2 duty selectable level DUP/TRI=1/3 duty selectable level Number display segments Max. 112-segment display (during duty mode) Max. 168-segment display (during duty mode) Master/Slave selectable M/S=Master mode selectable level M/S=Slave mode selectable level Interface with microcontroller Three lines: CLOCK, DATA 56-segment driver outputs IOH=-5mA VOH=VDISP-0.8V (SEG1 (can directly connected tube IOH=-10mA VOH=VDISP-0.8V (SEG38 require external resistors) IOL=500mA VOL=2V (SEG1 3-grid pre-driver outputs IOH=-5.0mA VOH=VDISP-0.8V (require external drivers) IOL=10mA VOL=2V Logic outputs IOH=-200mA VOH=VDD-0.8V IOL=200mA VOL=0.8V Built-in digital dimming circuit (10-bit resolution) Built-in oscillation circuit (external Built-in Power-On-Reset circuit Package options: 80-pin plastic (QFP80-P-1420-0.80-BK) Product name: ML9211GA 80-pin plastic (QFP80-P-1414-0.65-K) Product name: ML9211GP
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Semiconductor
ML9211
BLOCK DIAGRAM
GRID1 GRID2 GRID3
SEG1
SEG56
VDISP D-GND L-GND
Segment Driver
Grid Driver
Power Reset
Out1-56 Segment Control in1-56
in1-56
in1-56
Mode Select
in1-3
Out1-56 Segment Latch in1-56
Out1-56 Segment Latch in1-56
Out1-56 Segment Latch in1-56
CLOCK DATA Control
Out1-3 3bit Shift Register
Out1-56 56bit Shift Register
in1-10 Dimming Latch Out1-10
OSC0
10bit Digital Dimming
SYNC SYNC DUP/TRI Timing Generator
SYNC OUT1 SYNC OUT2
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Semiconductor
ML9211
INPUT OUTPUT CONFIGURATION
Schematic Diagram Driver Output Circuit
VDISP
VDISP OUTPUT
D-GND
D-GND
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Semiconductor
ML9211
CONFIGURATION (TOP VIEW)
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG37
VDISP
VDISP
SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1
SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 GRID1 GRID2 GRID3 D-GND
SYNC SYNC CLOCK DATA L-GND OSC0 DUP/TRI SYNC SYNC D-GND
connection 80-pin Plastic (QFP80-P-1420-0.80-BK)
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Semiconductor
SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 GRID1 GRID2 GRID3
ML9211
SEG39 SEG38 VDISP SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 VDISP SEG23 SEG22
SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2
D-GND SYNC SYNC CLOCK DATA L-GND OSC0 DUP/TRI SYNC SYNC D-GND SEG1
connection 80-pin Plastic (QFP80-P-1414-0.65-K)
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Semiconductor
ML9211
DESCRIPTIONS
QFP-1* QFP-2*
Symbol VDISP D-GND L-GND SEG1
Type
Description Power supply pins driver circuit. These should connected externally. Power supply logic drive. D-GND ground driver circuit. L-GND ground logic circuit. These should connected externally. Segment (anode) signal output pins tube. These pins directly connected tube. External circuit required. Segment (anode) signal output pins tube.These pins directly
SEG38 GRID1 GRID2 GRID3 CLOCK DATA
connected tube. External circuit required. Inverted Grid signal output pins. pre-driver, external circuit required.
Chip select input pin. Data transferred when level. Shift clock input pin. Serial data shifts rising edge CLOCK. Serial data input (positive logic). Data input shift register rising edge CLOCK signal. Duplex/Triplex operation select input pin. Duplex (1/2 duty) operation selected when this VDD. Triplex (1/3 duty) operation selected when this L-GND. Master/Slave mode select input pin. Master mode selected when this VDD. Slave mode selected when this L-GND. Dimming pulse input. When slave mode selected, connect this master side slave mode. pulse width segment output controlled input pulse width When master mode selected, input level this ignored. Connect this L-GND master mode. pulse width grids segment outputs controlled built-in 10-bit dimming circuit. Synchronous signal input. When slave mode selected, connect these pins master side SYNC pins. When master mode selected, input level these pins ignored. Connect these pins L-GND master mode. Dimming pulse output. Connect this slave side pin.
DUP/TRI
SYNC SYNC
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Semiconductor
ML9211
Symbol SYNC SYNC
QFP-1* QFP-2*
Type Synchronous signal output.
Description
Connect these pins slave side SYNC pins. oscillator connecting pins. Oscillation frequency depends display tubes used. details, refer ELECTRICAL CHARACTERISTICS. OSC0
OSC0
QFP-1: QFP80-P-1420-0.80-BK QFP-2: QFP80-P-1414-0.65-K
ABSOLUTE MAXIMUM RATING
Parameter Driver Supply Voltage Logic Supply Voltage Input Voltage Power Dissipation Storage Temperature Symbol VDISP TSTG Output Current Ta25°C Condition QFP80-P-1420-0.80-BK QFP80-P-1414-0.65-K SEG1 SEG38 GRID1 OUT, SYNC OUT1, SYNC OUT2 Ratings -0.3 -0.3 +6.5 -0.3 VDD+0.3 +150 -10.0 +2.0 -20.0 +2.0 -10.0 +20.0 -2.0 +2.0 Unit
RECOMMENDED OPERATING CONDITIONS
Parameter Driver Supply Voltage Logic Supply Voltage High Level Input Voltage Level Input Voltage Clock Frequency Oscillation Frequency Frame Frequency Operating Temperature Symbol VDISP fOSC Condition inputs except OSC0 inputs except OSC0 R=10KW±5%, C=27pF±5% R=10KW±5%, C=27pF±5% Duty Duty Min. 0.8VDD Typ. 13.0 Max. 18.0 0.2VDD Unit
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Semiconductor
ML9211
ELECTRICAL CHARACTERISTICS
Characteristics
Ta=-40 +85°C,VDISP =8.0 18.0V, VDD=4.5 5.5V Parameter High Level Input Voltage Level Input Voltage High Level Input Current Level Input Current Symbol Applied VOH1 High Level Output Voltage VOH2 VOH3 VOH4 VOL1 Level Output Voltage VOL2 VOL3 VOL4 Supply Current IDISP SEG1-37 SEG38-56 GRID1-3 SEG1-37 SEG38-56 GRID1-3 VDISP VDD=4.5V VDD=4.5V Condition VIH=VDD VIL=GND IOH1=-5mA VDISP=9.5V IOH2=-10mA IOH3=-5mA IOH4=-200mA IOL1=500mA VDISP=9.5V IOL2=500mA IOL3=10mA IOL4=200mA load R=10KW±5%, C=27pF±5%, Min. 0.8VDD -1.0 -1.0 VDISP-0.8 VDISP-0.8 VDISP-0.8 VDD-0.8 Max. 0.2VDD +1.0 +1.0 Unit
CLOCK, DATA SYNC SYNC M/S, DUP/TRI OUT, SYNC SYNC
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Semiconductor Characteristics
ML9211
Ta=-40 +85°C,VDISP =8.0 18.0V, VDD=4.5 5.5V Parameter Clock Frequency Clock Pulse Width Data Setup Time Data Hold Time Time Setup Time (CS-Clock) Hold Time (Clock-CS) Wait Time Output Slew Rate Time Rise Time Time Symbol tCSL tCSS tCSH tRSOFF tPRZ tPOF CL=100pF Condition tR=20% tF=80% Min. Max. Unit
Mounted unit Mounted unit, VDD=0.0V
TIMING DIAGRAM
Data Input Timing
tCSS 1/fC CLOCK DATA VALID VALID VALID VALID tCSH tCSL -0.8VDD -0.2VDD -0.8VDD -0.2VDD -0.8VDD -0.2VDD
Reset Timing
tPRZ tRSOFF tPOF -0.8VDD -0.0V -0.8VDD -0.0V
Driver Output Timing
-0.8VDISP -0.2VDISP
SEG1-56, GRID1-3
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Semiconductor Output Timing (Duplex Operation) *1bit time=4/fOSC (The dimming data 1016/1024 master mode)
2048bit times display cycle) GRID1 1016bit times 8bit times GRID2 1016bit times 1016bit times 8bit times
ML9211
VDISP 8bit times D-GND VDISP D-GND VDISP
GRID3 3bit times SEG1-56 1019bit times 5bit times 1019bit times 5bit times 1019bit times 1019bit times 5bit times SYNC OUT1 1019bit times 1029bit times 5bit times SYNC OUT2 1029bit times 1019bit times 5bit times 1019bit times 5bit times 1019bit times 5bit times 1019bit times 5bit times 1029bit times 5bit times 5bit times 5bit times 5bit times
D-GND VDISP D-GND L-GND L-GND L-GND
Output Timing (Triplex Operation) *1bit time=4/fOSC (The dimming data 1016/1024 master mode)
3072bit times display cycle) GRID1 1016bit times 8bit times GRID2 1016bit times 8bit times GRID3 3bit times SEG1-56 1019bit times 5bit times 1019bit times 5bit times 1019bit times 1019bit times 5bit times SYNC OUT1 1019bit times 1029bit times 5bit times SYNC OUT2 1029bit times 1019bit times 1016bit times 5bit times 1019bit times 5bit times 1019bit times 5bit times 1019bit times 5bit times 1019bit times 5bit times 5bit times 5bit times 5bit times D-GND VDISP D-GND VDISP D-GND L-GND L-GND L-GND 8bit times VDISP D-GND VDISP
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Semiconductor Output Timing (Duplex Operation) *1bit time=4/fOSC (The dimming data 64/1024 master mode)
2048bit times display cycle) GRID1 64bit times 960bit times GRID2 64bit times 960bit times 64bit times 960bit times
ML9211
VDISP D-GND VDISP D-GND VDISP
GRID3 3bit times 957bit times SEG1-56 67bit times 957bit times 67bit times 957bit times SYNC OUT1 67bit times 957bit times SYNC OUT2 1981bit times 67bit times 1981bit times 957bit times 1981bit times 67bit times 957bit times 67bit times 957bit times 67bit times 957bit times 67bit times 957bit times 957bit times 67bit times 957bit times 957bit times
D-GND VDISP D-GND L-GND L-GND L-GND
Output Timing (Triplex Operation) *1bit time=4/fOSC (The dimming data 64/1024 master mode)
3072bit times display cycle) GRID1 64bit times 960bit times GRID2 64bit times 960bit times GRID3 3bit times 957bit times SEG1-56 67bit times 957bit times 67bit times 957bit times SYNC OUT1 67bit times 957bit times SYNC OUT2 1981bit times 67bit times 1981bit times 957bit times 67bit times 67bit times 957bit times 67bit times 957bit times 67bit times 957bit times 67bit times 957bit times 957bit times 67bit times 957bit times 64bit times 957bit times D-GND VDISP D-GND VDISP D-GND L-GND L-GND L-GND 960bit times VDISP D-GND VDISP
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Semiconductor
ML9211
FUNCTIONAL DESCRIPTION
Power-on Reset When power turned ML9211 initialized internal power-on reset circuit. status internal circuit after initialization follows: contents shift registers latches "0". digital dimming duty cycle "0". segment outputs level. grid outputs High level. Data Transfer Method Data transferred between rising edge next falling edge chip select input. mode data, segment data dimming data written serial transfer method. serial data input shift register rising edge shift clock pulse. mode data must transferred after segment data dimming data succeedingly. When chip select input falls, internal LOAD signal automatically generated data loaded latches. Function Mode Function mode selected mode data M2). relation between function mode mode data follows:
FUNCTION MODE OPERATING MODE Segment Data GRID1-3 Input Segment Data GRID1 Input Segment Data GRID2 Input Segment Data GRID3 Input Digital Dimming Data Input FUNCTION DATA
Segment Data Input [Function Mode: ML9211 receives segment data when function mode selected. same segment data transferred segment data latches corresponding GRID same time when function mode selected. segment data transferred only segment data latch corresponding specified GRID when function mode selected. Segment output (SEG1 becomes High level (lighting) when segment data S56) "1". [Data Format] Input Data bits Segment Data bits Mode Data bits
Input Data
Segment Data (56bits)
Mode Data (3bits)
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Semiconductor [Bit correspondence between segment output segment data]
Segment data Segment data Segment data
ML9211
Digital Dimming Data Input [Function Mode: ML9211 receives digital dimming data when function mode selected. output duty changes range 0/1024 (0%) 1016/1024 (99.2%) each grid. 10-bit digital dimming data input from LSB. [Data Format] Input Data bits Digital Dimming Data: bits Mode Data bits
Input Data
Digital Dimming Data (10bits)
Mode Data (3bits) (MSB)
(LSB)
Dimming Data
Duty Cycle 0/1024 1/1024 1015/1024 1016/1024 1016/1024 1016/1024
Master Mode Master Mode selected when High level. master mode operation follows: input levels SYNC SYNC ignored, these pins should connected L-GND VDD. Brightness adjusted internal digital dimming circuit. segment Latch1 corresponding GRID1 selected internal timing generator.
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Semiconductor
ML9211
Slave Mode Slave Mode selected when level. slave mode operation follows: internal dimming circuit ignored. pulse width SEG1 controlled pulse width signal. segment Latch1 corresponding GRID1 selected SYNC SYNC signals. output levels GRID1 High level. output levels OUT, SYNC OUT1 SYNC OUT2 level.
[Correspondence between SYNC IN1, Segment Latch1 [Correspondence between SEG1
SYNC
SYNC
Segment Latch Latch1 Latch2 Latch3
GRID GRID1 GRID2 GRID3
Note: Low: Lights High: Lights
SEG1 High
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Semiconductor
Circuit duplex tube with segments Grid Anode)
APPLICATION CIRCUITS
VDISP
VDISP SEG1 SEG56 GRID1 GRID2 GRID3 SYNC SYNC
VDISP SEG1 SEG56 GRID1 GRID2 GRID3 SYNC SYNC
S110 S111 S112
ML9211 (MASTER)
DUP/TRI SYNC SYNC DATA CLOCK
ML9211 (SLAVE)
DUP/TRI SYNC SYNC DATA CLOCK
Microcontroller
Duplex Tube
D-GND
L-GND
L-GND
D-GND
ML9211
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Semiconductor
Circuit triplex tube with segments Grid Anode)
VDISP DUP/TRI SYNC SYNC DATA CLOCK
VDISP SEG1 SEG56 GRID1 GRID2 GRID3 SYNC SYNC
VDISP SEG1 SEG56 GRID1 GRID2 GRID3 SYNC SYNC
S110 S111 S112
ML9211 (MASTER)
ML9211 (SLAVE)
DUP/TRI SYNC SYNC DATA CLOCK
Microcontroller
Triplex Tube
L-GND
D-GND
L-GND
D-GND
ML9211
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Semiconductor
ML9211
NOTES TURNING POWER ON/OFF
Connect L-GND D-GND externally equal potential voltage. avoid wrong operations, turn driver power supply after turning logic power supply. Conversely, turn logic power supply after tuning driver power supply.
[Voltage] VDISP [Time]
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Semiconductor
ML9211
PACKAGE DIMENSIONS
(Unit QFP80-P-1420-0.80-BK
Mirror finish
Package material Lead frame material treatment Solder plate thickness Package weight
Epoxy resin alloy Solder plating more 1.27 TYP.
Notes Mounting Surface Mount Type Package SOP, QFP, TSOP, SOJ, (PLCC), surface mount type packages, which very susceptible heat reflow mounting humidity absorbed storage. Therefore, before perform reflow mounting, contact Oki's responsible sales person product name, package name, number, package code desired mounting conditions (reflow method, temperature times).
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Semiconductor
ML9211
(Unit QFP80-P-1414-0.65-K
Mirror finish
Package material Lead frame material treatment Solder plate thickness Package weight
Epoxy resin alloy Solder plating more 0.85 TYP.
Notes Mounting Surface Mount Type Package SOP, QFP, TSOP, SOJ, (PLCC), surface mount type packages, which very susceptible heat reflow mounting humidity absorbed storage. Therefore, before perform reflow mounting, contact Oki's responsible sales person product name, package name, number, package code desired mounting conditions (reflow method, temperature times).
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E2Y0002-29-62
NOTICE
information contained herein change without notice owing product and/or technical improvements. Before using product, please make sure that information being referred up-to-date. outline action examples application circuits described herein have been chosen explanation standard action performance product. When planning product, please ensure that external conditions reflected actual circuit, assembly, program designs. When designing your product, please product below specified maximum ratings within specified operating ranges including, limited operating voltage, power dissipation, operating temperature. assumes responsibility liability whatsoever failure unusual unexpected operation resulting from misuse, neglect, improper installation, repair, alteration accident, improper handling, unusual physical electrical stress including, limited exposure parameters beyond specified maximum ratings operation outside specified operating range. Neither indemnity against license third party's industrial intellectual property right, etc. granted connection with product and/or information drawings contained herein. responsibility assumed infringement third party's right which result from thereof. products listed this document intended general electronics equipment commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products authorized system application that requires special enhanced quality reliability characteristics system application where failure such system application result loss damage property, death injury humans. Such applications include, limited traffic automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, life-support systems. Certain products this document need government approval before they exported particular countries. purchaser assumes responsibility determining legality export these products will take appropriate necessary steps their expense these. part contents contained herein reprinted reproduced without prior permission. MS-DOS registered trademark Microsoft Corporation.
Copyright 1999 Electric Industry Co., Ltd.
Printed Japan
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