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Renesas Technology Corp. Hitachi Single-Chip Microcomputer H8/325


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Renesas Technology Home Page: www.renesas.com
Renesas Technology Corp.
Hitachi Single-Chip Microcomputer H8/325 Series H8/3257, H8/3256 H8/325, H8/324, H8/323, H8/322 Hardware Manual
Preface
H8/325 Series family high-performance single-chip microcomputers ideally suited embedded control industrial equipment. chips built around H8/300 core: highspeed processor. On-chip supporting modules provide ROM, RAM, types timers, ports, serial communication interface easy implementation compact, high-speed control systems. H8/325 Series offers selection on-chip memory. H8/3257: 60-kbyte ROM; 2-kbyte H8/3256: 48-kbyte ROM; 2-kbyte H8/325: 32-kbyte ROM; 1-kbyte H8/324: 24-kbyte ROM; 1-kbyte H8/323: 16-kbyte ROM; 512-byte H8/322: 8-kbyte ROM; 256-byte H8/3257, H8/3256, H8/325, H8/323, H8/322 chips available with either electrically programmable mask-programmable ROM. Manufacturers electrically programmable ZTAT(Zero Turn-Around Time*) version production fast start make software changes quickly, then switch over masked version full-scale production runs. This manual describes H8/325 Series hardware. Refer H8/300 Series Programming Manual detailed description instruction set. ZTAT registered trademark Hitachi, Ltd.
CONTENTS Section Overview
Overview. Block Diagram. Assignments Functions. 1.3.1 Arrangement. 1.3.2 Functions
Section Operating Modes Address Space
Overview. Mode Descriptions. Address Space 2.3.1 Access Speed 2.3.2 IOS. Mode System Control Registers (MDCR SYSCR). 2.4.1 Mode Control Register (MDCR) H'FFC5 2.4.2 System Control Register (SYSCR) H'FFC4
Section
Overview. 3.1.1 Features. Register Configuration. 3.2.1 General Registers. 3.2.2 Control Registers 3.2.3 Initial Register Values. Addressing Modes Data Formats. 3.4.1 Data Formats General Registers. 3.4.2 Memory Data Formats. Instruction 3.5.1 Data Transfer Instructions 3.5.2 Arithmetic Operations 3.5.3 Logic Operations 3.5.4 Shift Operations. 3.5.5 Manipulations 3.5.6 Branching Instructions. 3.5.7 System Control Instructions
3.5.8 Block Data Transfer Instruction States 3.6.1 Program Execution State 3.6.2 Exception-Handling State. 3.6.3 Power-Down State Access Timing Cycle 3.7.1 Access On-Chip Memory (RAM ROM) 3.7.2 Access On-Chip Register Field External Devices
Section Exception Handling
Overview. Reset 4.2.1 Overview 4.2.2 Reset Sequence 4.2.3 Disabling Interrupts after Reset. Interrupts. 4.3.1 Overview 4.3.2 Interrupt-Related Registers. 4.3.3 External Interrupts 4.3.4 Internal Interrupts 4.3.5 Interrupt Handling 4.3.6 Interrupt Response Time. Note Stack Handling.
Section Ports
Overview. Port Port Port Port Port Port Port
Section Parallel Handshaking Interface
Overview. 6.1.1 Features. 6.1.2 Block Diagram. 6.1.3 Input Output Pins 6.1.4 Register Configuration Register Descriptions. 6.2.1 Port Data Direction Register (P3DDR) 6.2.2 Port Data Register (P3DR) 6.2.3 Handshake Control/Status Register (HCSR). Operation 6.3.1 Output Timing Output Strobe Signal 6.3.2 Busy Signal Output Timing 6.3.3 Operation Software Standby Mode 6.3.4 Sample Application 6.3.5 Interrupts.
Section 16-Bit Free-Running Timer
Overview. 7.1.1 Features. 7.1.2 Block Diagram. 7.1.3 Input Output Pins 7.1.4 Register Configuration Register Descriptions. 7.2.1 Free-Running Counter (FRC) H'FF92 7.2.2 Output Compare Registers (OCRA OCRB) H'FF94 H'FF96. 7.2.3 Input Capture Register (ICR) H'FF98. 7.2.4 Timer Control Register (TCR) H'FF90. 7.2.5 Timer Control/Status Register (TCSR) H'FF91. 7.2.6 Noise Canceler Control Register (FNCR) H'FFFF. Interface Operation 7.4.1 Incrementation Timing. 7.4.2 Output Compare Timing. 7.4.3 Clear Timing 7.4.4 Input Capture Timing 7.4.5 Timing Input Capture Flag (ICF) Setting.
7.4.6 Setting Overflow Flag (OVF). Interrupts. Noise Canceler. Sample Application. Application Notes
Section 8-Bit Timers
Overview. 8.1.1 Features. 8.1.2 Block Diagram. 8.1.3 Input Output Pins 8.1.4 Register Configuration Register Descriptions. 8.2.1 Timer Counter (TCNT) H'FFC8 (TMR0), H'FFD0 (TMR1) 8.2.2 Time Constant Registers (TCORA TCORB) H'FFCA H'FFCB (TMR0), H'FFD2 H'FFD3 (TMR1). 8.2.3 Timer Control Register (TCR) H'FFC8 (TMR0), H'FFD0 (TMR1) 8.2.4 Timer Control/Status Register (TCSR) H'FFC9 (TMR0), H'FFD1 (TMR1). Operation 8.3.1 TCNT Incrementation Timing. 8.3.2 Compare Match Timing. 8.3.3 External Reset TCNT 8.3.4 Setting TCSR Overflow Flag Interrupts. Sample Application. Application Notes
Section Serial Communication Interface
Overview. 9.1.1 Features. 9.1.2 Block Diagram. 9.1.3 Input Output Pins 9.1.4 Register Configuration Register Descriptions. 9.2.1 Receive Shift Register (RSR) 9.2.2 Receive Data Register (RDR) H'FFDD 9.2.3 Transmit Shift Register (TSR). 9.2.4 Transmit Data Register (TDR) H'FFDB
9.2.5 Serial Mode Register (SMR) H'FFD8. 9.2.6 Serial Control Register (SCR) H'FFDA. 9.2.7 Serial Status Register (SSR) H'FFDC. 9.2.8 Rate Register (BRR) H'FFD9 Operation 9.3.1 Overview 9.3.2 Asynchronous Mode. 9.3.3 Synchronous Mode Interrupts. Application Notes
Section RAM.
10.1 10.2 10.3 10.4 Overview. Block Diagram. Enable (RAME) Operation 10.4.1 Expanded Modes (Modes 10.4.2 Single-Chip Mode (Mode
Section ROM.
11.1 Overview. 11.1.1 Block Diagram. 11.2 PROM Mode. 11.2.1 PROM Mode Setup 11.2.2 Socket Adapter Assignments Memory Map. 11.3 Programming 11.3.1 Selection Sub-Modes PROM Mode. 11.3.2 Writing Verifying 11.3.3 Notes Writing. 11.3.4 Reliability Written Data 11.3.5 Erasing Data 11.4 Handling Windowed Packages.
Section Power-Down State
12.1 Overview. 12.2 System Control Register: Power-Down Control Bits 12.3 Sleep Mode 12.3.1 Transition Sleep Mode.
12.3.2 Exit from Sleep Mode 12.4 Software Standby Mode. 12.4.1 Transition Software Standby Mode. 12.4.2 Exit from Software Standby Mode. 12.4.3 Sample Application Software Standby Mode 12.4.4 Notes Current Dissipation 12.5 Hardware Standby Mode 12.5.1 Transition Hardware Standby Mode. 12.5.2 Recovery from Hardware Standby Mode. 12.5.3 Timing Relationships.
Section E-Clock Interface
13.1 Overview.
Section Clock Pulse Generator
14.1 Overview. 14.1.1 Block Diagram. 14.2 Oscillator Circuit. 14.3 System Clock Divider.
Section Electrical Specifications
15.1 Absolute Maximum Ratings 15.2 Electrical Characteristics 15.2.1 Characteristics. 15.2.2 Characteristics. 15.3 Operational Timing. 15.3.1 Timing 15.3.2 Control Signal Timing 15.3.3 16-Bit Free-Running Timer Timing 15.3.4 8-Bit Timer Timing. 15.3.5 Serial Communication Interface Timing 15.3.6 Port Timing. 15.3.7 Parallel Handshake Interface Timing
Appendices Appendix Instruction
Instruction List. Operation Code Map. Number States Required Execution.
Appendix Register Field
Register Addresses Names. Register Descriptions.
Appendix States
States Each Mode
Appendix Timing Transition Recovery from Hardware Standby Mode Appendix Package Dimensions
Section Overview
Overview
H8/325 Series series single-chip microcomputers integrating core together with variety peripheral functions needed control systems. H8/300 high-speed processor featuring powerful bit-manipulation instructions, ideally suited realtime control applications. on-chip supporting modules include ROM, RAM, types timers (16-bit free-running timer 8-bit timer), serial communication interface, ports, parallel handshaking interface. on-chip memory sizes three chips H8/325 Series are: H8/3257: 60-kbyte ROM; 2-kbyte H8/3256: 48-kbyte ROM; 2-kbyte H8/325: 32-kbyte ROM; 1-kbyte H8/324: 24-kbyte ROM; 1-kbyte H8/323: 16-kbyte ROM; 512-byte H8/322: 8-kbyte ROM; 256-byte H8/325 Series operate single-chip mode expanded modes, depending memory requirements application. operating mode referred this manual mode (MCU: MicroComputer Unit). H8/3257, H8/3256, H8/325, H8/323, H8/322 available masked version, ZTATTM* version with electrically programmable that programmed user site. ZTAT registered trademark Hitachi, Ltd.
Table lists features H8/325 Series. Table 1-1. Features Feature Description General register architecture Eight 16-bit general registers, Sixteen 8-bit general registers High speed Maximum clock rate: Add/subtract: Multiply/divide: Concise, streamlined instruction instructions bytes long Register-register arithmetic logic operations Register-memory data transfer instruction Instruction features Multiply instruction bits bits) Divide instruction bits bits) Bit-accumulator instructions Register-indirect specification positions H8/3257 ROM: kbytes RAM: kbytes H8/3256 ROM: kbytes RAM: kbytes H8/325 ROM: kbytes RAM: kbyte H8/324 ROM: kbytes RAM: kbyte H8/323 ROM: kbytes RAM: bytes H8/322 ROM: kbytes RAM: bytes 16-bit free-running counter (also usable external event counting) compare outputs capture input Each channel has: 8-bit up-counter (also usable external event counting) time constant registers
Memory
16-Bit free-running timer module (FRT: channel) 8-Bit timer module channels)
Table 1-1. Features (cont.) Feature Serial communication interface (SCI: channels) ports Description Selection asynchronous synchronous modes Simultaneous transmit receive (full duplex operation) On-chip baud rate generator input/output pins which drive large current loads) input pins have programmable input pull-ups Built-in parallel handshaking available port
Parallel handshaking interface Interrupts Four external interrupt pins: NMI, IRQ0 IRQ2
Seventeen on-chip interrupt sources Operating modes Mode expanded mode with on-chip disabled Mode expanded mode with on-chip enabled Mode single-chip mode Power-down Sleep mode state Software standby mode Hardware standby mode Other features On-chip clock oscillator clock output Product lineup Type code Type code series) series) Package HD6473257C HD6473257VC 64-Pin windowed shrink (DC-64S) HD6473257P HD6473257VP 64-Pin shrink (DP-64S) HD6473257F HD6473257VF 64-Pin (FP-64A) HD6473257CP HD6473257VCP 68-Pin PLCC (CP-68) HD6433257P HD6433257VP 64-Pin shrink (DP-64S) HD6433257F HD6433257VF 64-Pin (FP-64A) HD6433257CP HD6433257VCP 68-Pin PLCC (CP-68) HD6473256P HD6473256VP 64-Pin shrink (DP-64S) HD6473256F HD6473256VF 64-Pin (FP-64A) HD6473256CP HD6473256VCP 68-Pin PLCC (CP-68) HD6433256P HD6433256VP 64-Pin shrink (DP-64S) HD6433256F HD6433256VF 64-Pin (FP-64A) HD6433256CP HD6433256VCP 68-Pin PLCC (CP-68)
PROM
Masked PROM
Masked
Table 1-1. Features (cont.) Feature Product lineup (cont.) Description Type code series) HD6473258C HD6473258P HD6473258F HD6473258CP HD6433258P HD6433258F HD6433258CP HD6413258P HD6413258F HD6413258CP HD6433248P HD6433248F HD6433248CP HD6473238P HD6473238F HD6473238CP HD6433238P HD6433238F HD6433238CP HD6413238P HD6413238F HD6413238CP HD6473228P HD6473228F HD6473228CP HD6433228P HD6433228F HD6433228CP
Type code series)
Package 64-Pin windowed shrink (DC-64S) 64-Pin shrink (DP-64S) 64-Pin (FP-64A) 68-Pin PLCC (CP-68) 64-Pin shrink (DP-64S) 64-Pin (FP-64A) 68-Pin PLCC (CP-68) 64-Pin shrink (DP-64S) 64-Pin (FP-64A) 68-Pin PLCC (CP-68) 64-Pin shrink (DP-64S) 64-Pin (FP-64A) 68-Pin PLCC (CP-68) 64-Pin shrink (DP-64S) 64-Pin (FP-64A) 68-Pin PLCC (CP-68) 64-Pin shrink (DP-64S) 64-Pin (FP-64A) 68-Pin PLCC (CP-68) 64-Pin shrink (DP-64S) 64-Pin (FP-64A) 68-Pin PLCC (CP-68) 64-Pin shrink (DP-64S) 64-Pin (FP-64A) 68-Pin PLCC (CP-68) 64-Pin shrink (DP-64S) 64-Pin (FP-64A) 68-Pin PLCC (CP-68)
PROM
Masked Masked PROM
Masked PROM
Masked
Block Diagram
Figure shows block diagram H8/325 Series.
XTAL EXTAL
Data (High)
Address
Clock pulse generator
STBY
H8/300
Data (Low)
P70/IS P71/OS P72/BUSY P73/IOS P74/AS P75/WR P76/RD P77/WAIT
P10/A0 P11/A1 P12/A2 P13/A3 P14/A4 P15/A5 P16/A6 P17/A7 P20/A8 P21/A9 P22/A10 P23/A11 P24/A12 P25/A13 P26/A14 P27/A15
PROM* masked ROM)
16-Bit free-running timer 8-Bit timer channels)
Port
Port
Port
Port
Port
P60/FTCI P61/FTOA P62/FTOB P63/FTI P64/IRQ0 P65/IRQ1 P66/IRQ2
Port
Memory size H8/3257 H8/3256 H8/325 H8/324 H8/323 H8/322 kbytes kbytes kbytes kbytes kbytes kbytes kbytes kbytes kbyte kbyte bytes bytes H8/3257, H8/3256, H8/325, H8/323, H8/322 available with PROM.
Figure 1-1. Block Diagram
P40/TMCI0 P41/TMO0 P42/TMRI0 P43/TMCI1 P44/TMO1 P45/TMRI1 P47/E
P50/TxD0 P51/RxD0 P52/SCK0 P53/TxD1 P54/RxD1 P55/SCK1
Figure
Port
Serial communication channels)
P30/D0 P31/D1 P32/D2 P33/D3 P34/D4 P35/D5 P36/D6 P37/D7
Assignments Functions
1.3.1 Arrangement Figure shows arrangement H8/325 Series DC-64S DP-64S packages. Figure shows arrangement FP-64A package. Figure shows arrangement CP-68 package.
/FTCI /FTOA /FTOB /FTI /IRQ /IRQ 6/IRQ XTAL EXTAL STBY /TMCI0 /TMO /TMRI0 /TMCI1 /TMO /TMRI1 /TxD /RxD /SCK /TxD /RxD /SCK
/WAIT /IOS /BUSY
Figure 1-2. Arrangement (DC-64S, DP-64S, View)
/FTOB
/FTOA
/IRQ
/IRQ
/IRQ
/FTCI
/FTI
XTAL EXTAL STBY /TMCI0 /TMO0 /TMRI0 /TMCI1 /TMO1 /TMRI1
/IOS
/BUSY
/SCK0
/SCK1
/WAIT
/TxD0
/RxD0
/TxD1
/RxD1
Figure 1-3. Arrangement (FP-64A, View)
7/A15 Fig.
PLCC-68
/FTOB
/FTOA
/IRQ
/IRQ
/IRQ
/FTCI
/FTI
XTAL EXTAL STBY /TMCI0 /TMO0 /TMRI0 /TMCI1 /TMO1 /TMRI1
/BUSY
/IOS
/SCK0
/SCK1
/WAIT
/TxD0
/RxD0
/TxD1
/RxD1
Figure 1-4. Arrangement (CP-68, View) 1.3.2 Functions
Fig.
Assignments Each Operating Mode: Table lists assignments pins DC-64S, DP-64S, FP-64A, CP-68 packages each operating mode.
7/A15
Table 1-2. Assignments Each Operating Mode DC-64S DP-64S
FP-64A
CP-68
Expanded modes Mode Mode P60/FTCI P60/FTCI P61/FTOA P61/FTOA P62/FTOB P62/FTOB P63/FTI P63/FTI P64/IRQ0 P64/IRQ0 P65/IRQ1 P65/IRQ1 P66/IRQ2 P66/IRQ2 XTAL XTAL EXTAL EXTAL STBY STBY P40/TMCI0 P40/TMCI0 P41/TMO0 P41/TMO0 P42/TMRI0 P42/TMRI0 P43/TMCI1 P43/TMCI1 P44/TMO1 P44/TMO1 P45/TMRI1 P45/TMRI1 P47/E P47/E P50/TxD0 P50/TxD0 P51/RxD0 P51/RxD0 P52/SCK0 P52/SCK0
Single-chip mode Mode P60/FTCI P61/FTOA P62/FTOB P63/FTI P64/IRQ0 P65/IRQ1 P66/IRQ2 XTAL EXTAL STBY P40/TMCI0 P41/TMO0 P42/TMRI0 P43/TMCI1 P44/TMO1 P45/TMRI1 P50/TxD0 P51/RxD0 P52/SCK0
PROM mode
Notes: Pins marked should left unconnected. PROM mode non-operating mode used programming on-chip ROM. section details.
Table 1-2. Assignments Each Operating Mode DC-64S DP-64S Notes:
FP-64A
CP-68
Expanded modes Mode Mode P53/TxD1 P53/TxD1 P54/RxD1 P54/RxD1 P55/SCK1 P55/SCK1 P70/IS P70/IS P73/IOS P73/IOS WAIT WAIT P27/A15 P26/A14 P25/A13 P24/A12 P23/A11 P22/A10 P21/A9 P20/A8 P17/A7 P16/A6 P15/A5 P14/A4 P13/A3 P12/A2
Single-chip mode Mode P53/TxD1 P54/RxD1 P55/SCK1 P70/IS P71/OS P72/BUSY
PROM mode EA14 EA13 EA12 EA11 EA10
Pins marked should left unconnected. PROM mode non-operating mode used programming on-chip ROM. section details.
Table 1-2. Assignments Each Operating Mode DC-64S DP-64S Notes:
FP-64A
CP-68
Expanded modes Mode Mode P11/A1 P10/A0
Single-chip mode Mode
PROM mode
Pins marked should left unconnected. PROM mode non-operating mode used programming on-chip ROM. section details.
Functions: Table gives concise description function each pin. Table 1-3. Functions Type Power Symbol Clock XTAL Name function Power: Connected power supply Connect both pins system power supply Ground: Connected ground Connect both pins system power supply Crystal: Connected crystal oscillator. crystal frequency must double desired system clock frequency. external clock input EXTAL pin, reverse-phase clock should input XTAL pin. External crystal: Connected crystal oscillator external clock. frequency external clock must double desired system clock frequency. section Clock Pulse Generator examples connections crystal external clock. System clock: Supplies system clock peripheral devices. Enable clock: Supplies clock peripheral devices. Reset: input causes chip reset. Standby: transition hardware standby mode power-down state) occurs when input received STBY pin. Address bus: Address output pins. Data bus: 8-Bit bidirectional data bus. Wait: Requests insert states into cycle when off-chip address accessed. Read: Goes indicate that reading external address. Write: Goes indicate that writing external address. Address Strobe: Goes indicate that there valid address address bus.
EXTAL
System control
STBY
Address Data control
WAIT
Table 1-3. Functions Type control Symbol Name function Select: Goes when accesses addresses H'FF00 H'FFFF expanded mode. used chip select signal replacing upper bits address when external devices mapped onto high addresses. NonMaskable Interrupt: Highest-priority interrupt request. NMIEG system control register determines whether interrupt requested rising falling edge input. Interrupt Request Maskable interrupt request pins. Mode: Input pins setting operating mode according table below. Mode Mode Mode Mode Description Expanded mode with on-chip disabled Expanded mode with on-chip enabled Single-chip mode
Interrupt signals
IRQ0 IRQ2 Operating MD1, mode control
16-Bit free- FTCI running timer FTOA, FTOB 8-Bit TMO0, timer TMO1 TMCI0, TMCI1 TMRI0, TMRI1
inputs these pins latched mode select bits (MDS1 MDS0) mode control register (MDCR) rising edge signal. counter Clock Input: Input external clock signal free-running timer. Output compare Output pins controlled comparators free-running timer. Input capture: Input capture free-running timer. 8-bit TiMer Output (channels Compare-match output pins 8-bit timers. 8-bit TiMer Clock Input (channels External clock input pins 8-bit timer counters. 8-bit TiMer Reset Input (channels High input these pins resets 8-bit timers.
Table 1-3. Functions Type Serial communication interface Symbol TxD0 TxD1 RxD0 RxD1 SCK0 SCK1 Name function Serial Transmit Data (channels Data output pins serial communication interface. Serial Receive Data (channels Data input pins serial communication interface. Serial ClocK (channels Input/output pins serial clock signals. Port 8-bit input/output port with programmable input pull-ups driving capability. direction each selected port data direction register (P1DDR). Port 8-bit input/output port with programmable input pull-ups driving capability. direction each selected port data direction register (P2DDR). Port 8-bit input/output port with programmable input pull-ups. direction each selected port data direction register (P3DDR). Port 8-bit input/output port with programmable input pull-ups. direction each (except P46) selected port data direction register (P4DDR). Port 6-bit input/output port with programmable input pull-ups. direction each selected port data direction register (P5DDR). Port 7-bit input/output port with programmable input pull-ups. direction each selected port data direction register (P6DDR). Port 8-bit input/output port with programmable input pull-ups. direction each selected port data direction register (P7DDR). Data Input/Output: Data input/output pins parallel handshaking interface. Input Strobe: Strobe input signal from external device. Output Strobe: Strobe output signal external device. Busy: Notifies external device that H8/325 Series chip ready receive data.
Generalpurpose
Parallel handshaking interface
BUSY
Section Operating Modes Address Space
Overview
H8/325 Series operates three modes numbered additional non-operating mode (mode used programming PROM version H8/325. mode selected inputs mode pins (MD1 MD0) instant when chip comes reset. indicated table 2-1, mode determines size address space usage on-chip on-chip RAM. ROMless versions (HD6413258, HD6413238) used only mode (expanded mode with on-chip disabled). Table 2-1. Operating Modes High High High High Mode Mode Mode Mode Mode Address space Expanded Expanded Single-chip On-chip Disabled Enabled Enabled On-chip Enabled* Enabled* Enabled
RAME system control register (SYSCR) cleared off-chip memory accessed instead. Modes expanded modes that permit access off-chip memory peripheral devices. maximum address space supported these externally expanded modes kbytes. mode (single-chip mode), only on-chip on-chip register field used. ports available general-purpose input output. Mode inoperative H8/325 Series. Avoid setting mode pins mode
Mode Descriptions
Mode (Expanded Mode without On-Chip ROM): Mode supports 64-kbyte address space most which off-chip. particular, interrupt vector table located off-chip memory. on-chip used. Software select whether on-chip RAM. Ports used address data lines control signals follows: Ports Address Port Data Port (partly): control signals Mode (Expanded Mode with On-Chip ROM): Mode supports 64-kbyte address space which includes on-chip ROM. Software select whether on-chip RAM, select usage pins ports Ports Address (see note) Port Data Port (partly): control signals Note: mode ports initially general-purpose input ports. Software must change desired pins output before using them address bus. section Ports details. Mode (Single-Chip Mode): this mode memory on-chip. Since off-chip memory accessed, there external address bus. ports available general-purpose input output.
Address Space
Figures show memory maps H8/3257, H8/3256, H8/325, H8/324, H8/323, H8/322 each three operating modes. on-chip register field consists control, status, data registers on-chip supporting modules ports. Off-chip addresses accessed only expanded modes. Access off-chip address single-chip mode does cause address error, data returned. 2.3.1 Access Speed On-chip accessed word bits) time states. "state" system clock cycle.) on-chip register field accessed byte time three states.
External memory accessed byte time three more states. basic cycle three states, additional wait states inserted request. 2.3.2 There gaps on-chip address space above on-chip RAM. Addresses H'FF80 H'FF8F, situated between on-chip register field, off-chip. Addresses H'FFA0 H'FFAF also off-chip. These addresses conveniently assigned external devices. simplify addressing devices these addresses, signal provided that goes when accesses addresses H'FF00 H'FFFF. signal used place upper bits address bus.
Mode Expand mode without on-chip H'0000 Vector table H'002F H'0030 H'002F H'0030 H'0000
Mode Expand mode with on-chip H'0000 Vector table H'002F H'0030
Mode Single-chip mode Vector table
On-chip ROM, Kbytes External address space H'EFFF H'F000 External address space H'F77F H'F780 H'F77F H'F780 H'F780 H'EFFF
On-chip ROM, Kbytes
On-chip RAM*, Kbytes
On-chip RAM*, Kbytes
On-chip RAM, Kbytes
H'FF7F H'FF80 H'FF8F H'FF90 H'FF9F H'FFA0 H'FFAF H'FFB0 H'FFFF
External address space
H'FF7F H'FF80 H'FF8F H'FF90 H'FF9F H'FFA0 H'FFAF H'FFB0 H'FFFF
H'FF7F
External address space
H'FF90 On-chip register field H'FF9F
External address space
On-chip register field
External address space
On-chip register field
On-chip register field
On-chip register field
H'FFB0 On-chip register field H'FFFF
External memory accessed these addresses when RAME system control register (SYSCR) cleared
Figure 2-1. H8/3257 Address Space
Fig.
Mode Expand mode without on-chip H'0000 Vector table H'002F H'0030 H'002F H'0030 H'0000
Mode Expand mode with on-chip H'0000 Vector table H'002F H'0030
Mode Single-chip mode Vector table
On-chip ROM, Kbytes External address space H'BFFF H'C000 External address space H'F77F H'F780 H'F77F H'F780 H'F780 H'BFFF
On-chip ROM, Kbytes
On-chip RAM*, Kbytes
On-chip RAM*, Kbytes
On-chip RAM, Kbytes
H'FF7F H'FF80 H'FF8F H'FF90 H'FF9F H'FFA0 H'FFAF H'FFB0 H'FFFF
External address space
H'FF7F H'FF80 H'FF8F H'FF90 H'FF9F H'FFA0 H'FFAF H'FFB0 H'FFFF
H'FF7F
External address space
H'FF90 On-chip register field H'FF9F
External address space
On-chip register field
External address space
On-chip register field
On-chip register field
On-chip register field
H'FFB0 On-chip register field H'FFFF
External memory accessed these addresses when RAME system control register (SYSCR) cleared
Figure 2-2. H8/3256 Address Space
Fig.
Mode Expand mode without on-chip H'0000 Vector table H'002F H'0030 H'002F H'0030 H'0000
Mode Expand mode with on-chip H'0000 Vector table H'002F H'0030
Mode Single-chip mode Vector table
On-chip ROM, Kbytes External address space H'7FFF H'8000 External address space H'FB7F H'FB80 H'FB7F H'FB80 H'FB80 H'7FFF
On-chip ROM, Kbytes
On-chip RAM*, Kbyte
On-chip RAM*, Kbyte
On-chip RAM, Kbyte
H'FF7F H'FF80 H'FF8F H'FF90 H'FF9F H'FFA0 H'FFAF H'FFB0 H'FFFF
External address space
H'FF7F H'FF80 H'FF8F H'FF90 H'FF9F H'FFA0 H'FFAF H'FFB0 H'FFFF
H'FF7F
External address space
H'FF90 On-chip register field H'FF9F
External address space
On-chip register field
External address space
On-chip register field
On-chip register field
On-chip register field
H'FFB0 On-chip register field H'FFFF
External memory accessed these addresses when RAME system control register (SYSCR) cleared
Figure 2-3. H8/325 Address Space
Fig.
Mode Expand mode without on-chip H'0000 H'002F H'0030 Vector table
Mode Expand mode with on-chip H'0000 Vector table H'002F H'0030
Mode Single-chip mode Vector table
H'0000 H'002F H'0030
On-chip ROM, Kbytes H'5FFF H'6000 Reserved External address space H'7FFF H'8000 H'5FFF
On-chip ROM, Kbytes
External address space
H'FB7F H'FB80 On-chip RAM, Kbyte H'FF7F H'FF80 H'FF8F H'FF90 H'FF9F H'FFA0 H'FFAF H'FFB0 H'FFFF
H'FB7F H'FB80 On-chip RAM, Kbyte H'FF7F H'FF80 H'FF8F H'FF90 H'FF9F H'FFA0 H'FFAF H'FFB0 H'FFFF
H'FB80 On-chip RAM, Kbyte H'FF7F
External address space
External address space
H'FF90 On-chip register field H'FF9F
External address space
On-chip register field
External address space
On-chip register field
On-chip register field
On-chip register field
H'FFB0 H'FFFF
On-chip register field
This area used external address space when RAME SYSCR Data read write permitted these modes.
Figure 2-4. H8/324 Address Space
Fig.
Mode Expand mode without on-chip H'0000 H'002F H'0030 Vector table
Mode Expand mode with on-chip H'0000 Vector table H'002F H'0030
Mode Single-chip mode Vector table
H'0000 H'002F H'0030
On-chip ROM, Kbytes H'3FFF H'4000 H'3FFF
On-chip ROM, Kbytes
External address space External address space
H'FD7F H'FD80 On-chip RAM*, bytes H'FF7F H'FF80 H'FF8F H'FF90 H'FF9F H'FFA0 H'FFAF H'FFB0 H'FFFF
H'FD7F H'FD80 On-chip RAM*, bytes H'FF7F H'FF80 H'FF8F H'FF90 H'FF9F H'FFA0 H'FFAF H'FFB0 H'FFFF
H'FD80 On-chip RAM, bytes H'FF7F
External address space
External address space
H'FF90 On-chip register field H'FF9F
External address space
On-chip register field
External address space
On-chip register field
On-chip register field
On-chip register field
H'FFB0 H'FFFF
On-chip register field
External memory accessed these addresses when RAME system control register (SYSCR) cleared
Figure 2-5. H8/323 Address Space
Fig.
Mode Expand mode without on-chip H'0000 H'002F H'0030 Vector table H'0000 H'002F H'0030 H'1FFF H'2000 H'3FFF
Mode Expand mode with on-chip H'0000 Vector table On-chip ROM, Kbytes Reserved
Mode Single-chip mode Vector table On-chip ROM, Kbytes
H'002F H'0030 H'1FFF
External address space
External address space
H'FD7F H'FD80 H'FE7F H'FE80 H'FF7F H'FF80 H'FF8F H'FF90 H'FF9F H'FFA0 H'FFAF H'FFB0 H'FFFF Reserved
H'FD7F H'FD80 H'FE7F H'FE80 H'FF7F H'FF80 H'FF8F H'FF90 H'FF9F H'FFA0 H'FFAF H'FFB0 H'FFFF Reserved
H'FD80 Reserved H'FE80 H'FF7F
On-chip RAM,*1 bytes
External address space
On-chip RAM, bytes
External address space
On-chip RAM, bytes
H'FF90 On-chip register field H'FF9F
External address space
On-chip register field
External address space
On-chip register field
H'FFB0 On-chip register field H'FFFF On-chip register field
On-chip register field
External memory accessed these addresses when RAME system control register (SYSCR) cleared Data read write permitted these modes.
Figure 2-6. H8/322 Address Space
Fig.
Mode System Control Registers (MDCR SYSCR)
control registers register field mode control register (MDCR) system control register (SYSCR). mode control register controls mode: operating mode H8/325 Series chip. system control register that enables disables on-chip RAM. Table lists attributes these registers. Table 2-2. Mode System Control Registers Name Mode control register System control register Abbreviation MDCR SYSCR Read/Write Address H'FFC5 H'FFC4
2.4.1 Mode Control Register (MDCR)-H'FFC5 Initial value Read/Write Initialized according inputs. MDS1 MDS0
Bits 2-Reserved: These bits cannot modified always read Bits 3-Reserved: These bits cannot modified always read Bits 0-Mode Select (MDS1 MDS0): These bits indicate values mode pins (MD1 MD0) latched rising edge signal. These bits read written. Coding Example: test whether operating mode MOV.B @H'FFC5, CMP.B #H'E5, comparison with H'E5 instead H'01 because bits always read
2.4.2 System Control Register (SYSCR)-H'FFC4 setting clearing system control register, software enable disable on-chip RAM. other bits system control register concern software standby mode valid edge signal. These bits will described section Exception Handling section Power-Down State. Initial value Read/Write SSBY STS2 STS1 STS0 NMIEG RAME
0-RAM Enable (RAME): This enables disables on-chip RAM. When on-chip disabled, accesses corresponding addresses directed off-chip. RAME initialized reset, enabling on-chip RAM. setting RAME altered sleep mode software standby mode. should cleared before entering hardware standby mode. section Power-Down State. RAME
Description on-chip disabled. on-chip enabled.
(Initial state)
Coding Example: disable on-chip RAM: BCLR @H'FFC4
Section
Overview
H8/325 Series generic H8/300 CPU: 8-bit central processing unit with speedoriented architecture featuring sixteen general registers. This section describes features functions, including concise description addressing modes instruction set. further details instructions, H8/300 Series Programming Manual. 3.1.1 Features main features H8/300 listed below. Two-way register configuration Sixteen 8-bit general registers, Eight 16-bit general registers Instruction with basic instructions, including: Multiply divide instructions Powerful bit-manipulation instructions Eight addressing modes Register direct (Rn) Register indirect (@Rn) Register indirect with displacement (@(d:16, Rn)) Register indirect with post-increment pre-decrement (@Rn+ @-Rn) Absolute address (@aa:8 @aa:16) Immediate (#xx:8 #xx:16) PC-relative (@(d:8, PC)) Memory indirect (@@aa:8) Maximum 64K-byte address space High-speed operation frequently-used instructions executed four states maximum clock rate 10MHz 16-bit register-register subtract: 0.2µs 8-bit multiply: 1.4µs 8-bit divide: 1.4µs Power-down mode SLEEP instruction
Register Configuration
Figure shows register structure CPU. There groups registers: general registers control registers.
(SP)
Stack Pointer
Program Counter UHUNZ CCR: Condition Code Register Carry flag Overflow flag Zero flag Negative flag Half-carry flag Interrupt mask User User
Figure 3-1. Registers 3.2.1 General Registers general registers used both data registers address registers. When used address registers, general registers accessed 16-bit registers R7). When used data registers, they accessed 16-bit registers, high bytes accessed separately 8-bit registers. also functions stack pointer, used implicitly hardware processing interrupts subroutine calls. assembly-language coding, also denoted letters indicated figure 3-2, (SP) points stack.
Unused area (R7) Stack area
Figure 3-2. Stack Pointer 3.2.2 Control Registers control registers include 16-bit program counter (PC) 8-bit condition code register (CCR). Program Counter (PC): This 16-bit register indicates address next instruction will execute. Each instruction accessed bits word), least significant ignored (always regarded Condition Code Register (CCR): This 8-bit register contains internal status information, including carry (C), overflow (V), zero (Z), negative (N), half-carry flags interrupt mask (I). 7-Interrupt Mask (I): When this "1," interrupts except masked. This automatically reset start interrupt handling. 6-User (U): This written read software purposes. 5-Half-Carry (H): This when ADD.B, ADDX.B, SUB.B, SUBX.B, NEG.B, CMP.B instruction causes carry borrow cleared otherwise. Similarly, when ADD.W, SUB.W, CMP.W instruction causes carry borrow cleared otherwise. used implicitly instructions. 4-User (U): This written read software purposes. 3-Negative (N): This indicates most significant (sign bit) result instruction.
2-Zero (Z): This indicate zero result cleared indicate nonzero result. 1-Overflow (V): This when arithmetic overflow occurs, cleared other times. 0-Carry (C): This used subtract instructions, indicate carry borrow most significant result Shift rotate instructions, store value shifted most significant least significant manipulation load instructions, accumulator
LDC, STC, ANDC, ORC, XORC instructions enable load store CCR, clear selected bits logic operations. Some instructions leave some flag bits unchanged. action each instruction flag bits shown Appendix A.1, "Instruction List." H8/300 Series Programming Manual further details.
3.2.3 Initial Register Values When reset, program counter (PC) loaded from vector table interrupt mask "1." other bits general registers initialized. particular, stack pointer (R7) initialized. prevent program crashes stack pointer should initialized software, first instruction executed after reset.
Addressing Modes
H8/325 supports eight addressing modes. Each instruction uses subset these addressing modes. Register Direct-Rn: register field instruction specifies 16-bit general register containing operand. most cases general register accessed 8-bit register. Only MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU bits bits), DIVXU bits bits) instructions have 16-bit operands. Register indirect-@Rn: register field instruction specifies 16-bit general register containing address operand. Register Indirect with Displacement-@(d:16, Rn): This mode, which used only instructions, similar register indirect instruction second word (bytes which added contents specified general register obtain operand address. MOV.W instruction, resulting address must even. Register Indirect with Post-Increment Pre-Decrement-@Rn+ @-Rn: Register indirect with Post-Increment-@Rn+ @Rn+ mode used with instructions that load registers from memory. similar register indirect mode, 16-bit general register specified register field instruction incremented after operand accessed. size increment depending size operand: MOV.B; MOV.W. MOV.W, original contents 16-bit general register must even. Register Indirect with Pre-Decrement-@-Rn @-Rn mode used with instructions that store register contents memory. similar register indirect mode, 16-bit general register specified register field instruction decremented before operand accessed. size decrement depending size operand: MOV.B; MOV.W. MOV.W, original contents 16-bit general register must even.
Absolute Address-@aa:8 @aa:16: instruction specifies absolute address operand memory. MOV.B instruction uses 8-bit absolute address form H'FFxx. upper bits assumed possible address range H'FF00 H'FFFF (65280 65535). MOV.B, MOV.W, JMP, instructions 16-bit absolute addresses.
Immediate-#xx:8 #xx:16: instruction contains 8-bit operand second byte, 16-bit operand third fourth bytes. Only MOV.W instructions contain 16-bit immediate values. ADDS SUBS instructions implicitly contain value immediate data. Some manipulation instructions contain 3-bit immediate data (#xx:3) second fourth byte instruction, specifying number. PC-Relative-@(d:8, PC): This mode used generate branch addresses instructions. 8-bit value byte instruction code added sign-extended value program counter contents. result must even number. possible branching range -126 +128 bytes (-63 words) from current address. Memory Indirect-@@aa:8: This mode used instructions. second byte instruction code specifies 8-bit absolute address from H'0000 H'00FF 255). word located this address contains branch address. Note that addresses H'0000 H'003D located vector table. address specified branch destination operand address MOV.W instruction, least significant regarded "0," causing word access performed address preceding specified address. section 3.4.2, "Memory Data Formats" further information.
Data Formats
H8/300 process 1-bit data, 4-bit (BCD) data, 8-bit (byte) data, 16-bit (word) data. manipulation instructions operate 1-bit data specified byte operand. arithmetic logic instructions except ADDS SUBS operate byte data. instruction perform decimal arithmetic adjustments byte data packed form. Each nibble byte treated decimal digit. MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU bits bits), DIVXU bits bits) instructions operate word data.
3.4.1 Data Formats General Registers Data sizes above stored general registers shown figure 3-3.
Data type 1-Bit data Register Data format Don't-care
1-Bit data
Don't-care
Byte data
Don't-care
Byte data Don't-care
Word data
4-Bit data
Don't-care
Upper digit Lower digit
4-Bit data Don't-care
Upper digit Lower digit
Figure 3-3. Register Data Formats Note: RnH: RnL: MSB: LSB:
Upper digit general register Lower digit general register Most significant Least significant
Fig.
3.4.2 Memory Data Formats Figure indicates data formats memory. Word data stored memory must always begin even address. word access least significant address regarded "0." address specified, address error occurs access performed preceding even address. This rule affects MOV.W instructions branching instructions, implies that only even addresses should stored vector table.
Data type Address Data format
1-Bit data Byte data
Address Address Even address address Even address address Even address address CCR: Condition Code Register Ignored when return
Word data
Upper bits Lower bits
Byte data (CCR) stack
CCR*
Word data stack
Figure 3-4. Memory Data Formats stack must always accessed word time. When pushed stack, identical copies pushed make complete word. When they returned, lower byte ignored. Fig.
Instruction
Table lists H8/325 Series instruction set. Table 3-1. Instruction Classification Function Data transfer Arithmetic operations Logic operations Shift manipulation Branch System control Block data transfer Instructions Types MOV, MOVTPE, MOVFPE, PUSH*1, POP*1 ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA, DAS, MULXU, DIVXU, CMP, AND, XOR, SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR, BLD, BILD, BST, BIST Bcc*2, JMP, BSR, JSR, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, EEPMOV Total
PUSH equivalent MOV.W @-SP. equivalent MOV.W @SP+, conditional branch instruction which represents condition code.
following sections give concise summary instructions each category, indicate patterns their object code. notation used defined next.
Operation Notation <EAs> (EAd) (EAs) #imm #xx:3 #xx:8 General register (destination) General register (source) General register General register field Effective address: general register memory location Destination operand Source operand Stack pointer Program counter Condition code register (negative) (zero) (overflow) (carry) Immediate data 3-Bit immediate data 8-Bit immediate data #xx:16 disp 16-Bit immediate data Operation field Displacement Absolute address Byte Word Addition Subtraction Multiplication Division logical logical Exclusive logical Move Exchange Condition field
3.5.1 Data Transfer Instructions Table describes data transfer instructions. Figure shows their object code formats. Table 3-2. Data Transfer Instructions Instruction Size* Function (EAs) (EAd) Moves data between general registers between general register memory, moves immediate data general register. @Rn, @(d:16, Rn), @aa:16, #xx:8 #xx:16, @-Rn, @Rn+ addressing modes available byte word data. @aa:8 addressing mode available byte data only. @-R7 @R7+ modes require word operands. specify byte size these modes. (EAd) Transfers data from general register memory synchronization with clock. (EAs) Transfers data from memory general register synchronization with clock. @-SP Pushes 16-bit general register onto stack. Equivalent MOV.W @-SP. @SP+ Pops 16-bit general register from stack. Equivalent MOV.W @SP+,
MOVTPE
MOVFPE
PUSH
Size: operand size Byte Word
@Rm, @(d:16, @(d:16, @Rm+ @-Rm @aa:8 @aa:8
disp.
abs. abs.
@aa:16 @aa:16 #xx:8 #xx:16
#imm.
#imm.
abs.
MOVFPE, MOVTPE MOVFPE: MOVTPE: PUSH,
Notation disp.: abs.: #imm.:
Operation field Direction field (0-load from; 1-store Register field Displacement Absolute address Immediate data
Figure 3-5. Data Transfer Instruction Codes
3.5.2 Arithmetic Operations Table describes arithmetic instructions. figure section 3.5.4, "Shift Operations" their object codes. Table 3-3. Arithmetic Instructions Instruction Size* Function #imm Performs addition subtraction data general registers, addition immediate data data general register. Immediate data cannot subtracted from data general register. Word data added subtracted only when both words general registers. #imm Performs addition subtraction with carry borrow byte data general registers, addition subtraction immediate data data general register. Increments decrements general register. #imm Adds subtracts immediate data from data general register. immediate data must decimal adjust Decimal-adjusts (adjusts packed BCD) addition subtraction result general register referring CCR. Performs 8-bit 8-bit unsigned multiplication data general registers, providing 16-bit result. Performs 16-bit 8-bit unsigned division data general registers, providing 8-bit quotient 8-bit remainder. #imm Compares data general register with data another general register with immediate data. Word data compared only between general registers. Obtains two's complement (arithmetic complement) data general register.
ADDX SUBX
ADDS SUBS MULXU
DIVXU
Size: operand size Byte Word
3.5.3 Logic Operations Table describes four instructions that perform logic operations. figure section 3.5.4, "Shift Operations" their object codes. Table 3-4. Logic Operation Instructions Instruction Size* Function #imm Performs logical operation general register another general register immediate data. #imm Performs logical operation general register another general register immediate data. #imm Performs logical exclusive operation general register another general register immediate data. (Rd) (Rd) Obtains one's complement (logical complement) general register contents.
3.5.4 Shift Operations Table describes eight shift instructions. Figure shows object code formats arithmetic, logic, shift instructions. Table 3-5. Shift Instructions Instruction SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR Size* Function shift Performs arithmetic shift operation general register contents. shift Performs logical shift operation general register contents. rotate Rotates general register contents. rotate through carry Rotates general register contents through (carry) bit.
Size: operand size Byte
ADD, SUB, ADDX, SUBX, MULXU, DIVXU
ADDS, SUBS, INC, DEC, DAA, DAS, NEG,
#imm.
ADD, ADDX, SUBX, (#xx:8)
#imm.
AND, (Rm)
AND, (#xx:8)
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR
Notation #imm.:
Operation field Register field Immediate data
Figure 3-6. Arithmetic, Logic, Shift Instruction Codes
3.5.5 Manipulations Table describes bit-manipulation instructions. Figure shows their object code formats. Table 3-6. Bit-Manipulation Instructions Instruction BSET Size* Function (<bit-No.> <EAd>) Sets specified general register memory "1." specified number, given 3-bit immediate data lower three bits general register. (<bit-No.> <EAd>) Clears specified general register memory "0." specified number, given 3-bit immediate data lower three bits general register. (<bit-No.> <EAd>) (<bit-No.> <EAd>) Inverts specified general register memory. specified number, given 3-bit immediate data lower three bits general register (<bit-No.> <EAd>) Tests specified general register memory sets clears flag accordingly. specified number, given 3-bit immediate data lower three bits general register. (<bit-No.> <EAd>) ANDs flag with specified general register memory. (<bit-No.> <EAd>)] ANDs flag with inverse specified general register memory. number specified 3-bit immediate data. (<bit-No.> <EAd>) flag with specified general register memory. (<bit-No.> <EAd>)] flag with inverse specified general register memory. number specified 3-bit immediate data. (<bit-No.> <EAd>) XORs flag with specified general register memory.
BCLR
BNOT
BTST
BAND BIAND
BIOR
BXOR
Size: operand size Byte
Table 3-6. Bit-Manipulation Instructions Instruction BIXOR Size* Function [(<bit-No.> <EAd>)] XORs flag with inverse specified general register memory. number specified 3-bit immediate data. (<bit-No.> <EAd>) Copies specified general register memory flag. (<bit-No.> <EAd>) Copies inverse specified general register memory flag. number specified 3-bit immediate data. (<bit-No.> <EAd>) Copies flag specified general register memory. (<bit-No.> <EAd>) Copies inverse flag specified general register memory. number specified 3-bit immediate data.
BILD
BIST
Size: operand size Byte
Notes Manipulation Instructions: BSET, BCLR, BNOT, BST, BIST read-modifywrite instructions. They read byte data, modify byte, then write byte back. Care required when these instructions applied registers with write-only bits port registers. Read Modify Write Read data byte specified address Modify data byte Write modified data byte back specified address
Example BCLR executed clear port data direction register (P4DDR) under following conditions. Input pin, Low, pull-up transistor P47: P46: Input pin, High, pull-up transistor P40: Output pins, intended purpose this BCLR instruction switch from output input.
Before Execution BCLR Instruction Input Input High Output Output Output Output Output Output
Input/output state Pull-up
Execution BCLR Instruction
BCLR.B @P4DDR
;clear data direction register
After Execution BCLR Instruction Input/output Output Output Output state High Pull-up
Output
Output
Output
Output
Input High
Explanation: execute BCLR instruction, begins reading P4DDR. Since P4DDR write-only register, read H'FF, even though true value H'3F. Next clears read data, changing value H'FE. Finally, writes this value (H'FE) back P4DDR complete BCLR instruction. result, P40DDR cleared "0," making input pin. addition, P47DDR P46DDR "1," making output pins. Example BSET executed port data register (P4DR) under following conditions. P47: Input pin, Low, pull-up transistor P46: Input pin, High, pull-up transistor P40: Output pins, intended purpose this BSET instruction switch output level from High.
Before Execution BSET Instruction Input/output state Pull-up Input Input High Output Output Output Output Output Output
Execution BSET Instruction
BSET.B @PORT4
;set data register
After Execution BSET Instruction Input/output state Pull-up Input Input High Output Output Output Output Output Output High
Explanation: execute BSET instruction, begins reading port Since input pins, reads level these pins directly, value data register. reads ("0") High ("1"). Since output pins, these pins reads value data register ("0"). therefore reads value port H'40, although actual value P4DR H'80. Next sets read data "1," changing value H'41. Finally, writes this value (H'41) back P4DR complete BSET instruction. result, "1," switching High output. addition, bits both modified, changing on/off settings pull-up transistors pins P46. Programming Solution: switching pull-ups example avoided reserving byte temporary register P4DR using follows. RAM0 symbol user-selected address temporary register.
Before Execution BSET Instruction
MOV.B MOV.B MOV.B #80, R0L, @RAM0 R0L, @PORT4
;write data (H'80) data register ;write temporary register (RAM0) ;write Input High Output Output Output Output Output Output
Input/output state Pull-up RAM0
Input
Execution BSET Instruction
BSET.B @RAM0
;set temporary register (RAM0)
After Execution BSET Instruction
MOV.B MOV.B @RAM0, R0L, @PORT4
;obtain value temporary register RAM0 ;write value Input High Output Output Output Output Output Output High
Input/output state Pull-up RAM0
Input
#imm. #imm.
BSET, BCLR, BNOT, BTST Operand: register direct (Rn) No.: immediate (#xx:3) Operand: register direct (Rn) No.: register direct (Rm)
Operand: register indirect (@Rn) No.: immediate (#xx:3) Operand: register indirect (@Rn) No.: register direct (Rm)
#imm.
abs. abs.
Operand: absolute (@aa:8) No.: immediate (#xx:3)
#imm. #imm.
Operand: absolute (@aa:8) No.: register direct (Rm) BAND, BOR, BXOR, BLD, Operand: register direct (Rn) No.: immediate (#xx:3)
Operand: register indirect (@Rn) No.: immediate (#xx:3)
#imm.
abs.
Operand: absolute (@aa:8) No.: immediate (#xx:3) BIAND, BIOR, BIXOR, BILD, BIST Operand: register direct (Rn) No.: immediate (#xx:3)
#imm. #imm.
Operand: register indirect (@Rn) No.: immediate (#xx:3) Operand: absolute (@aa:8) No.: immediate (#xx:3)
abs. #imm.
Notation abs.: #imm.:
Operation field Register field Absolute address Immediate data
Figure 3-7. Manipulation Instruction Codes
3.5.6 Branching Instructions Table describes branching instructions. Figure shows their object code formats. Table 3-7. Branching Instructions Instruction Size Function Branches condition true. Mnemonic (BT) (BF) (BHS) (BLO) Field 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description Always (True) Never (False) High Same Carry Clear (High Same) Carry (Low) Equal Equal Overflow Clear Overflow Plus Minus Greater Equal Less Than Greater Than Less Equal Condition Always Never CZ=0 CZ=1 NV=0 NV=1
Branches unconditionally specified address. Branches subroutine specified address. Branches subroutine specified displacement from current address. Returns from subroutine
disp.
(@Rm)
abs.
(@aa:16)
abs.
(@@aa:8)
disp.
(@Rm)
abs.
(@aa:16)
abs.
(@@aa:8)
Notation disp.: abs.:
Operation field Condition field Register field Displacement Absolute address
Figure 3-8. Branching Instruction Codes
3.5.7 System Control Instructions Table describes system control instructions. Figure shows their object code formats. Table 3-8. System Control Instructions Instruction SLEEP Size Function Returns from exception-handling routine. Causes transition power-down state. CCR, #imm Moves immediate data general register contents condition code register. Copies condition code register specified general register. #imm Logically ANDs condition code register with immediate data. #imm Logically condition code register with immediate data. #imm Logically exclusive-ORs condition code register with immediate data. Only increments program counter.
ANDC XORC
Size: operand size Byte
RTE, SLEEP,
LDC, (Rn)
#imm.
ANDC, ORC, XORC, (#xx:8)
Notation #imm.:
Operation field Register field Immediate data
Figure 3-9. System Control Instruction Codes 3.5.8 Block Data Transfer Instruction Table describes EEPMOV instruction. Figure 3-10 shows object code format. Table 3-9. Block Data Transfer Instruction/EEPROM Write Operation Instruction EEPMOV Size Function then repeat @R5+ @R6+ until else next; Moves data block according parameters general registers R4L, R4L: size block (bytes) starting source address starting destination address Execution next instruction starts soon block transfer completed.
EEPROM Notation Operation field
Figure 3-10. Block Data Transfer Instruction/EEPROM Write Operation Code Notes EEPMOV Instruction Note EEPMOV instruction block data transfer instruction. moves number bytes specified from address specified address specified
When setting make sure that final destination address R4L) does exceed H'FFFF. value must change from H'FFFF H'0000 during execution instruction.
H'FFFF allowed
Note will malfunction after EEPMOV instruction execution, following conditions. EEPMOV instruction performs block data transfer function. Condition When following conditions true: expanded mode (i.e. mode mode destination address EEPMOV instruction external area. least wait state inserted last write cycle destination address EEPMOV instruction.
Phenomenon H8/300 will malfunction after EEPMOV instruction execution. Counter Measures Software Circuitry Please take least counter measure from followings. Please EEPMOV when destination internal area (e.g. internal RAM). When destination external area, please avoid wait state insertion cycle. When case that wait state(s) required, please substitute EEPMOV other instructions follows: Example
LOOP:MOV.B @R5+, MOV.B R4H, ADDS LOOP
States
three states: program execution state, exception-handling state, power-down state. power-down state further divided into three modes: sleep mode, software standby mode, hardware standby mode. Figure 3-11 summarizes these states, figure 3-12 shows state transitions.
State
Program execution state executes successive program instructions. Exception-handling state transient state triggered reset interrupt. executes hardware sequence that includes loading program counter from vector table. Power-down state state which some chip functions stopped conserve power. Sleep mode Software standby mode Hardware standby mode
Figure 3-11. Operating States
Interrupt request
Program execution state Exception handling
SLEEP instruction with SSBY SLEEP instruction
Exception handling state
Sleep mode Interrupt request IRQ2 input strobe interrupt STBY=1 RES=0 Software standby mode Hardware standby mode Power-down state
Reset state
Notes: transition reset state occurs when goes Low, except when chip hardware standby mode. transition from state hardware standby mode occurs when STBY goes Low.
Figure 3-12. State Transitions 3.6.1 Program Execution State this state executes program instructions sequence. main program, subroutines, Fig. 3-12 interrupt-handling routines executed this state. 3.6.2 Exception-Handling State exception-handling state transient state that occurs when reset accepts interrupt. this state carries hardware-controlled sequence that prepares execute user-coded exception-handling routine. hardware exception-handling sequence does following: Saves program counter condition code register stack (except case reset). Sets interrupt mask condition code register "1." Fetches start address exception-handling routine from vector table. Branches that address, returning program execution state. section "Exception Handling," further information exception-handling state.
3.6.3 Power-Down State power-down state includes three modes: sleep mode, software standby mode, hardware standby mode. Sleep Mode: sleep mode entered when SLEEP instruction executed. halts, register contents remain unchanged on-chip supporting modules continue function. When interrupt reset signal received, returns through exception-handling state program execution state. Software Standby Mode: software standby mode entered SLEEP instruction executed while SSBY (Software Standby) system control register (SYSCR) set. on-chip supporting modules halt. on-chip supporting modules initialized, contents on-chip registers remain unchanged. port outputs also remain unchanged. Hardware Standby Mode: hardware standby mode entered when input STBY goes Low. chip functions halt, including port output. on-chip supporting modules initialized, on-chip contents held. section "Power-Down State" further information.
Access Timing Cycle
driven system clock period from rising edge system clock next referred "state." Memory access performed two-or three-state cycle described below. more detailed timing diagrams cycles, section "Electrical Specifications." 3.7.1 Access On-Chip Memory (RAM ROM) On-chip accessed cycle states designated Either byte word data accessed, 16-bit data bus. Figure 3-13 shows on-chip memory access cycle. Figure 3-14 shows associated states.
cycle
state
state
Internal address
Address
Internal Read signal Internal data (read) Read data
Internal Write signal
Internal data (write)
Write data
Figure 3-13. On-Chip Memory Access Cycle
cycle
state
state
Fig. 3-13
Address
Address
High High High Data bus: high impedance state
Figure 3-14. States during On-Chip Memory Access Cycle
Fig. 3-14
3.7.2 Access On-Chip Register Field External Devices on-chip register field (I/O ports, dual-port RAM, on-chip supporting module registers, etc.) external devices accessed cycle consisting three states: Only byte data accessed cycle, 8-bit data bus. Access word data instruction codes requires consecutive cycles (six states). Wait States: requested, additional wait states (TW) inserted between WAIT sampled center state Low, wait state inserted after WAIT also sampled center each wait state still Low, another wait state inserted. external device have number wait states inserted holding WAIT necessary duration. cycle MOVTPE MOVFPE instructions will described section "E-Clock Interface." Figure 3-15 shows access cycle on-chip register field. Figure 3-16 shows associated states. Figures 3-17 show read write access timing external devices.
cycle
state
state
state
Internal address
Address
Internal Read signal Internal data (read) Read data
Internal Write signal
Internal data (write)
Write data
Figure 3-15. On-Chip Register Field Access Cycle
cycle
state
state
state
Address
Address
High High High Data bus: high impedance state
Figure 3-16. States during On-Chip Register Field Access Cycle
Read cycle
Fig. 3-16
state
state
state
Address
Address
High
Data
Read data
Figure 3-17 (a). External Device Access Timing (read)
Fig. 3-17
Write cycle
state
state
state
Address
Address
High
Data
Write data
Figure 3-17 (b). External Device Access Timing (write)
Fig. 3-17
Section Exception Handling
Overview
H8/325 Series recognizes only kinds exceptions: interrupts reset. Table indicates their priority timing their hardware exception-handling sequence. ROMless versions (HD6413258, HD6413238) used only mode (expanded mode with on-chip disabled). Table 4-1. Reset Interrupt Exceptions Type exception Reset
Priority High
Interrupt
Timing exception-handling sequence When goes low, chip enters reset state immediately. hardware exception-handling sequence (reset sequence) begins soon goes high again. When interrupt requested, hardware exception-handling sequence (interrupt sequence) begins current instruction, current hardware exception-handling sequence.
Reset
4.2.1 Overview reset highest exception-handling priority. When goes low, current processing stops chip enters reset state. internal state registers on-chip supporting modules initialized. When returns from high, chip comes reset state reset exception-handling sequence. 4.2.2 Reset Sequence reset state begins when goes low. ensure correct resetting, power-on should held least 20ms. reset during operation, should held least system clock cycles. When returns from high, hardware carries following reset exception-handling sequence.
value mode pins (MD1 MD0) latched bits MDS1 MDS0 mode control register (MDCR). condition code register (CCR), mask interrupts. registers ports on-chip supporting modules initialized. loads program counter with first word vector table (stored addresses H'0000 H'0001) starts program execution.
should held when power switched off, well when power switched Figure indicates timing reset sequence when vector table reset routine located on-chip ROM. Figure indicates timing when they off-chip memory.
Vector fetch
Internal processing
Instruction prefetch
Internal address Internal Read signal Internal Write signal Internal data bits)
Reset vector address (H'0000) Starting address reset routine (contents H'0000-H'0001) First instruction reset routine
Figure 4-1. Reset Sequence (Mode Reset Routine On-Chip ROM)
Figure.
Vector fetch
Internal processing Instruction prefetch
Figure 4-2. Reset Sequence (Mode
bits)
(1),(3) Reset vector address: (1)=H'0000, (3)=H'0001
(2),(4) Starting address reset routine (contents reset vector): (2)=upper byte, (4)=lower byte
(5),(7) Starting address reset routine: (5)=(2)(4), (7)=(2)(4)+1
Figure.
(6),(8) First instruction reset routine: (6)=first byte, (8)=second byte
4.2.3 Disabling Interrupts after Reset interrupts, including NMI, disabled immediately after reset. first program instruction, located address specified vector table, therefore always executed. prevent program crashes, this instruction should initialize stack pointer (example: MOV.W #xx:16, SP). After execution this instruction, interrupt enabled. Other interrupts remain disabled until their enable bits
Interrupts
4.3.1 Overview There four input pins external interrupts (NMI, IRQ0 IRQ2). There also internal interrupts originating on-chip. features these interrupts are: internal external interrupts except masked CCR. IRQ0 IRQ2 rising-edge-sensed, falling-edge-sensed, level-sensed. type sensing selected each interrupt individually. edge-sensed, either rising falling edge selected. Interrupts individually vectored. software interrupt-handling routine does have determine what type interrupt occurred. Table lists interrupts their order priority gives their vector numbers addresses their entries vector table.
Table 4-2. Interrupts Address entry vector table H'0006 H'0007 H'0008 H'0009 H'000A H'000B H'000C H'000D H'000E H'000F H'0010 H'0011 H'0012 H'0013 H'0014 H'0015 H'0016 H'0017 H'0018 H'0019 H'001A H'001B H'001C H'001D H'001E H'001F H'0020 H'0021 H'0022 H'0023 H'0024 H'0025 H'0026 H'0027 H'0028 H'0029 H'002A H'002B H'002C H'002D H'002E H'002F
Interrupt source IRQ0 IRQ1 IRQ2 Port 16-Bit freerunning timer
8-Bit timer
8-Bit timer
Serial communication interface Serial communication interface
(Input strobe) (Input capture) OCIA (Output compare OCIB (Output compare FOVI (Overflow) CMI0A (Compare-match CMI0B (Compare-match OVI0 (Overflow) CMI1A (Compare-match CMI1B (Compare-match OVI1 (Overflow) ERI0 (Receive error) RXI0 (Receive end) TXI0 (Transmit end) ERI1 (Receive error) RXI1 (Receive end) TXI1 (Transmit end)
Priority High
Notes: H'0000 H'0001 contain reset vector. H'0002 H'0005 reserved H8/325 Series available user. 4.3.2 Interrupt-Related Registers interrupt controller refers three registers addition CCR. names attributes these registers listed table 4-3.
Table 4-3. Registers Read Interrupt Controller Name System control register sense control register enable register Abbreviation SYSCR ISCR Read/Write Address H'FFC4 H'FFC6 H'FFC7
System Control Register (SYSCR)-H'FFC4 Initial value Read/Write SSBY STS2 STS1 STS0 NMIEG RAME
(NMIEG) only read interrupt controller. 2-Nonmaskable Interrupt Edge (NMIEG): Determines whether nonmaskable interrupt generated falling rising edge input signal. NMIEG
Description interrupt generated falling edge NMI. interrupt generated rising edge NMI.
(Initial state)
section section Power-Down State information other SYSCR bits. Sense Control Register (ISCR)-H'FFC6 Initial value Read/Write IRQ2EG IRQ1EG IRQ0EG IRQ2SC IRQ1SC IRQ0SC
Bits 2-IRQ2 Sense Control (IRQ2SC IRQ2EG): These bits select input IRQ2 sensed.
IRQ2SC
IRQ2EG
Description level IRQ2 generates interrupt request.
(Initial state)
falling edge IRQ2 generates interrupt request. rising edge IRQ2 generates interrupt request.
Bits 1-IRQ1 Sense Control (IRQ1SC IRQ1EG): These bits select input IRQ1 sensed. IRQ1SC IRQ1EG
Description level IRQ1 generates interrupt request.
(Initial state)
falling edge IRQ1 generates interrupt request. rising edge IRQ1 generates interrupt request.
Bits 0-IRQ0 Sense Control (IRQ0SC IRQ0EG): These bits select input IRQ0 sensed. IRQ0SC IRQ0EG
Description level IRQ0 generates interrupt request.
(Initial state)
falling edge IRQ0 generates interrupt request. rising edge IRQ0 generates interrupt request.
Enable Register (IER)-H'FFC7 Initial value Read/Write IRQ2E IRQ1E IRQ0E
Bits 2-IRQ0 IRQ2 Enable (IRQ0E IRQ2E): These bits enable disable IRQ0, IRQ1, IRQ2 interrupts individually.
IRQiE
Description IRQi disabled. IRQi enabled.
(Initial state)
Edge-sensed interrupt signals latched enabled) held until interrupt served. They latched even interrupt mask CCR, even bits IRQ0E IRQ2E cleared Level-sensed interrupts latched. 4.3.3 External Interrupts external interrupts IRQ0 IRQ2. While waiting these interrupts, possible conserve power entering software standby mode. When interrupt arrives, chip will recover automatically program execution state, handle interrupt, then continue executing main program. section Power-Down State further information software standby mode. NMI: nonmaskable interrupt generated rising falling edge input signal regardless whether (interrupt mask) CCR. valid edge selected NMIEG system control register. highest priority always accepted soon current instruction ends, unless current instruction ANDC, ORC, XORC, instruction. When interrupt accepted interrupt mask bit) set, handling routine cannot interrupted except another NMI. vector number entry located address H'0006 vector table. IRQ0 IRQ2: These interrupt signals level-sensed sensed rising falling edge input, selected ISCR bits. These interrupts masked collectively CCR, enabled disabled individually setting clearing bits enable register. When these interrupts accepted, mask further interrupts (except NMI). These interrupts second priority NMI. Among them, IRQ0 highest priority IRQ2 lowest priority. Interrupts IRQ0 IRQ2 depend whether pins IRQ0 IRQ2 input output pins. When using external interrupts IRQ0 IRQ2, clear corresponding bits these pins input state.
4.3.4 Internal Interrupts Seventeen internal interrupts requested on-chip supporting modules. them masked when set. addition, they enabled disabled bits control registers on-chip supporting modules. When these interrupts accepted, mask further interrupts (except NMI). Power conserved waiting internal interrupt sleep mode, which halts on-chip supporting modules continue run. When interrupt arrives, returns program-execution state, services interrupt, then resumes execution main program. section Power-Down State further information sleep mode. input strobe interrupt (ISI) also waited software standby mode. chip recovers from software standby mode when input strobe interrupt requested. internal interrupt signals received interrupt controller generated from flag bits registers on-chip supporting modules. interrupt controller does reset these flag bits when accepting interrupt. vector numbers priority order these interrupts, table 4-2. Note: When disabling internal interrupts, note following points. interrupt mask before disabling internal interrupt clearing interrupt flag. instruction that disables clears internal interrupt executed while interrupt mask cleared interrupt requested during execution instruction, resolves this conflict follows: more other interrupts also requested, other interrupt with highest priority served. other interrupt requested, branches reset address. Example: sample program disabling output compare interrupt shown below. OCIAE should cleared only when this example. BCLR ANDC #80, @TCR #7F, Disable output compare interrupt Clear
Note: Interrupt requests detected immediately after ANDC, ORC, XORC, instructions. 4.3.5 Interrupt Handling Figure shows block diagram interrupt controller. Figure flowchart showing operation interrupt controller sequence which interrupt accepted. This sequence outlined below. interrupt controller receives interrupt request signal. Interrupt request signals generated input, other interrupt sources enabled. When notified interrupt, interrupt controller scans interrupt signals priority order selects with highest priority. (See table priority order.) Other requested interrupts remain pending. interrupt controller accepts interrupt NMI, another interrupt cleared interrupt interrupt held pending. When interrupt accepted, after completion current instruction, first then pushed onto stack. figure 4-5. stacked indicates address first instruction executed after return from interrupt-handling routine. interrupt controller sets masking further interrupts except during interrupt-handling routine. interrupt controller generates vector address interrupt loads word this address into program counter.
timing this sequence shown figure case which program vector table on-chip stack on-chip RAM.
interrupt IRQ0 flag IRQ0E
Interrupt controller
IRQ0 interrupt Priority decision
Interrupt request
Vector number
ADIE
interrupt (CCR)
Figure 4-3. Block Diagram Interrupt Controller
H161 H8/337 Fig.
Program execution
Interrupt request present? IRQ0 IRQ1
CCR? Save Save
Pending
Program Counter CCR: Condition Code Register
masking interrupts except
Interrupt mask
software interrupt-handling routine
Figure 4-4. Hardware Interrupt-Handling Sequence
Figure.
SP-4 SP-3 SP-2 SP-1 SP(R7) Stack area
SP(R7) SP+1 SP+2 SP+3 SP+4
(upper byte) (lower byte) Even address
Before interrupt accepted Pushed onto stack Program counter Condition code register Stack pointer Ignored return.
After interrupt accepted
Notes: contains address first instruction executed after return. Registers must saved restored word access even address.
Figure 4-5. Usage Stack Interrupt Handling
Figure.
Interrupt accepted Interrupt priority decision. Wait Instruction Internal instruction. fetch processing Interrupt request signal Vector table fetch
Stack
Instruction fetch (first instruction Internal interrupt-handling process- routine)
Internal address
Internal Read signal Internal Write signal
Internal 16-bit data
(10)
Instruction prefetch address (Pushed Instruction executed return from Instruction prefetch address (Pushed stack.stack. Instruction executed return from interrupt-handling routine.) interrupt-handling routine.) Instruction code (Not executed) Instruction code (Not executed) Instruction prefetch address executed) Instruction prefetch address (Not (Not executed) SP-2 SP-2 SP-4 SP-4 Address vector table entry Address vector table entry Vector table entry (address first instruction interrupt-handling routine) Vector table entry (address first instruction interrupt-handling routine) (10) First instruction interrupt-handling routine (10) First instruction interrupt-handling routine
Figure 4-6. Timing Interrupt Sequence
Figure.
4.3.6 Interrupt Response Time Table indicates time that elapses from interrupt request signal until first instruction software interrupt-handling routine executed. Since H8/325 Series accesses on-chip memory bits time, very fast interrupt service obtained placing interrupt-handling routines on-chip stack on-chip RAM. Table 4-4. Number States before Interrupt Service Number states On-chip memory External memory 17*2 12*2 12*2 53*2
Reason wait Interrupt priority decision Wait completion current instruction*1 Save Fetch vector Fetch instruction Internal processing Total
Notes:
These values apply current instruction EEPMOV, MOVFPE, MOVTPE instruction. wait states inserted external memory access, these values longer. internal interrupts.
Note Stack Handling
word access, least significant address always assumed stack always accessed word access. Care should taken keep even value stack pointer (general register R7). PUSH MOV.W @-SP MOV.W @SP+, instructions push registers stack. Setting stack pointer value cause programs crash. Figure shows example damage caused when stack pointer contains address.
H'FEFC H'FEFD
H'FEFF
instruction
MOV.B R1L, @-R7
H'FEFF
improperly stored beyond stack
lost
Upper byte program counter Lower byte program counter General register Stack pointer
Figure 4-7. Example Damage Caused Setting Address Although consists only byte, treated word data when pushed stack. hardware interrupt exception-handling sequence, identical bytes pushed onto Figure. stack make complete word. When popped from stack instruction, loaded from byte stored even address. byte stored address ignored.
Section Ports
Overview
H8/325 Series seven parallel ports, including: Five 8-bit input/output ports-ports 7-bit input/output port-port 6-bit input/output port-port ports have programmable input pull-ups. Ports drive LEDs. Input output memory-mapped. views each port data register (DR) located register field high address space. Each port also data direction register (DDR) which determines which pins used input which output. Output: send data output port, selects output data direction register writes desired data data register, causing data held latch. latch output drives through buffer amplifier. reads data register output port, obtains data held latch rather than actual level pin. Input: read data from port, selects input data direction register reads data register. This causes input logic level placed directly internal data bus. There intervening input latch, except port when parallel handshaking used. Pull-Up: pull-ups input pins controlled follows. turn pull-up transistor pin, software must first clear data direction make input pin, then write data that pin. pull-up turned writing data bit, data direction bit. pull-ups also turned reset entry hardware standby mode. data direction registers write-only registers; their contents invisible CPU. reads data direction register bits read regardless their true values. Care required manipulation instructions used clear data direction bits. note manipulation instructions section 3.5.5, Manipulations. Auxiliary Functions: addition their general-purpose input/output functions, ports have auxiliary functions. Most auxiliary functions software-selectable must enabled setting bits control registers. When selected, auxiliary function usually replaces general-purpose input/output function, some cases both functions operate simultaneously. Table summarizes auxiliary functions ports.
Table 5-1. Auxiliary Functions Input/Output Ports Port Port Port Port Port Port Port Port Auxiliary functions Address (low) Address (high) Data parallel handshaking data lines System clock clock output, 8-bit timer input output Serial communication interface Free-running timer input output, IRQ2 IRQ0 control parallel handshaking control
(Note (Note (Note
Notes: Selected automatically mode software-selectable mode Data function selected automatically modes
Port
Port 8-bit input/output port that also provides bits address bus. function port depends mode indicated table 5-2. Table 5-2. Functions Port Mode Address (low) Mode Input port Address (low) A0)* Mode Input/output port
Depending settings data direction register: 0-input pin; 1-address Pins port drive single load 90-pF capacitive load when they used output pins. They also drive light-emitting diodes Darlington pair.
Table details port registers. Table 5-3. Port Registers Name Port data direction register Port data register Abbreviation P1DDR P1DR Read/Write Initial value H'FF (mode H'00 (modes H'00 Address H'FFB0 H'FFB2
Port Data Direction Register (P1DDR)-H'FFB0 Mode Initial value Read/Write Modes Initial value Read/Write P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR
P1DDR 8-bit register that selects direction each port functions output corresponding P1DDR input cleared Port Data Register (P1DR)-H'FFB2 Initial value Read/Write
P1DR 8-bit register containing output data pins P10, controlling their input pullups. Pull-Ups: available input pins modes Software turn pullup writing P1DR, turn writing pull-ups automatically turned output pins modes pins mode Mode mode (expanded mode without on-chip ROM), port automatically used address output. port data direction register unwritable. bits P1DDR automatically cannot cleared
Mode mode (expanded mode with on-chip ROM), usage port selected pin-by-pin basis. used general-purpose input data direction cleared address output data direction Mode single-chip mode port general-purpose input/output port. Reset: reset clears P1DDR P1DR placing pins input state with pull-ups off. mode when chip comes reset P1DDR making pins address output pins. Hardware Standby Mode: pins placed high-impedance state with pull-ups off. Software Standby Mode: P1DDR P1DR remain their previous state. Address output pins low. General-purpose output pins continue output data P1DR. pull-ups input pins depending values P1DR. Figure shows schematic diagram port
Hardware standby
Mode Reset P1nDDR WP1D Internal lower address Internal data
Mode
Reset P1nDR
Mode
WP1D: Write Port WP1: Write Port RP1: Read Port Set-priority
Figure 5-1. Port Schematic Diagram
Port
Port 8-bit input/output port that also provides high bits address bus. function port depends mode indicated table 5-4.
Figure
Table 5-4. Functions Port Mode Address (high) (A15 Mode Input port Address (high) (A15 A8)* Mode Input/output port
Depending settings data direction register: 0-input pin; 1-address
Pins port drive single load 90-pF capacitive load when they used output pins. They also drive light-emitting diodes Darlington pair. Table details port registers. Table 5-5. Port Registers Name Port data direction register Port data register Abbreviation P2DDR P2DR Read/Write Initial value H'FF (mode H'00 (modes H'00 Address H'FFB1 H'FFB3
Port Data Direction Register (P2DDR)-H'FFB1 Mode Initial value Read/Write Modes Initial value Read/Write
P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR
P2DDR 8-bit register that selects direction each port functions output corresponding P2DDR input cleared Port Data Register (P2DR)-H'FFB3 Initial value Read/Write
P2DR 8-bit register containing output data pins P20, controlling their input pullups. Pull-Ups: available input pins modes Software turn pullup writing P2DR, turn writing pull-ups automatically turned output pins modes pins mode
Mode mode (expanded mode without on-chip ROM), port automatically used address output. port data direction register unwritable. bits P2DDR automatically cannot cleared Mode mode (expanded mode with on-chip ROM), usage port selected pin-by-pin basis. used general-purpose input data direction cleared address output data direction Mode single-chip mode port general-purpose input/output port. Reset: reset clears P2DDR P2DR placing pins input state with pull-ups off. mode when chip comes reset P2DDR making pins address output pins. Hardware Standby Mode: pins placed high-impedance state with pull-ups off. Software Standby Mode: P2DDR P2DR remain their previous state. Address output pins low. General-purpose output pins continue output data P2DR. pull-ups input pins depending values P2DR. Figure shows schematic diagram port
Hardware standby
Mode Reset P2nDDR WP2D Internal address Internal data
Mode
Reset P2nDR
Mode
WP2D: Write Port WP2: Write Port RP2: Read Port Set-priority
Figure 5-2. Port Schematic Diagram
Port
Port 8-bit input/output port that also provides external data data pins parallel handshaking interface. function port depends mode indicated Figure table 5-6. further information parallel handshaking, section Parallel Handshaking Interface. Table 5-6. Functions Port Mode Data Mode Data Mode General-purpose input/output port parallel handshaking port
Pins port drive single load 90-pF capacitive load when they used output
pins. They also drive Darlington pair. Table details port registers. Table 5-7. Port Registers Name Port data direction register Port data register Abbreviation P3DDR P3DR Read/Write Initial value H'FF H'00 Address H'FFB4 H'FFB6
Port Data Direction Register (P3DDR)-H'FFB4 Initial value Read/Write P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR
P3DDR 8-bit register that selects direction each port functions output corresponding P3DDR input cleared Port Data Register (P3DR)-H'FFB6 Initial value Read/Write
P3DR 8-bit register containing output data pins mode controlling their input pull-ups. Pull-Ups: available input pins mode Software turn pull-up writing P3DR, turn writing pull-ups automatically turned output pins mode pins modes Modes expanded modes, port automatically used data bus. values P3DDR P3DR ignored. Mode single-chip mode, port used general-purpose input/output port, parallel-handshaking input output port.
Input Latches: pins port have input latches which enabled handshake control/status register (HCSR) mode When input data latched falling edge input strobe (IS) signal held input strobe latch until read. When cleared input data passed through input strobe latch without being held. section Parallel Handshaking Interface further information. Reset Hardware Standby Mode: P3DDR P3DR cleared parallel handshaking functions disabled. pins placed input (high-impedance) state with pull-ups off. Software Standby Mode: P3DDR P3DR remain their previous state. modes pins placed input (high-impedance) state. mode pins remain their previous input output state. Figure shows schematic diagram port
Mode Mode Reset P3nDDR WP3D Mode P3nDR Mode Internal data input Reset
External address write
Reset WP3D: Write Port WP3: Write Port RP3: Read Port
External address read
Input latch
Control logic
Figure 5-3. Port Schematic Diagram
Port
Port 8-bit input/output port that also provides input output pins 8-bit timers output pins system clock clock. functions depend mode Figure output select bits timer control/status registers. Table lists functions.
Table 5-8. Port Functions Usage port Timer clock Functions TMCI0 TMO0
TMRI0
TMCI1
TMO1
TMRI1
clock clock
section 8-Bit Timer Module details timer output select bits. Pins port drive single load 90-pF capacitive load when they used output pins. They also drive Darlington pair. Table details port registers. Table 5-9. Port Registers Name Port data direction register Port data register Abbreviation P4DDR P4DR Read/Write Initial value H'80 (modes H'00 (mode H'00 Address H'FFB5 H'FFB7
Port Data Direction Register (P4DDR)-H'FFB5 Modes Initial value Read/Write Mode Initial value Read/Write P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR P41DDR P40DDR
P4DDR 8-bit register that selects direction each port functions output corresponding P4DDR input cleared
Port Data Register (P4DR)-H'FFB7 Initial value Read/Write
P4DR 8-bit register containing output data pins P40, controlling their input pullups. When reads P4DR, output pins (P4DDR reads value P4DR latch, input pins (P4DDR obtains logic level directly from pin, bypassing P4DR latch. This also applies pins used timer clock input output. Pull-Ups: available input pins, including timer input pins, modes. Software turn pull-up writing P4DR, turn writing pull-ups automatically turned output pins. Pins P40, P42, P43, P45: indicated table 5-8, these pins used general-purpose input output, input 8-bit timer clock reset signals. When used timer signal input, P4DDR should normally cleared otherwise timer will receive value P4DR. input pull-up desired, P4DR should also cleared Pins P44: indicated table 5-8, these pins used general-purpose input output, 8-bit timer output. Pins used timer output unaffected values P4DDR P4DR, their pull-ups automatically turned off. P46: modes (expanded modes) this used system clock output, regardless value P46DDR. pull-up automatically turned off. mode (single-chip mode) this used general-purpose input P46DDR cleared system clock output P46DDR cannot used general-purpose output. P47: modes (expanded modes) used clock output P47DDR general-purpose input P47DDR cleared cannot used general-purpose output. mode (single-chip mode) used general-purpose input/output.
Reset: P4DDR P4DR 8-bit timer control registers initialized, making pins into input port pins with pull-ups off. When chip comes reset into singlechip mode (mode also become input port pins with pull-ups off. When chip comes reset into expanded mode (mode system clock clock output P47. Hardware Standby Mode: pins placed high-impedance state with pull-ups off. Software Standby Mode: 8-bit timer control registers initialized P4DDR P4DR remain their previous states. Pins become input output port pins depending setting P4DDR. Pins remain their previous states, with system clock output remaining high clock output remaining low. pull-ups input pins depending values P4DR. Figures show schematic diagrams port
Reset P4nDDR WP4D Reset P4nDR Internal data 8-bit timer module Counter clock input Counter reset input Figure
WP4D: Write Port WP4: Write Port RP4: Read Port
Figure 5-4. Port Schematic Diagram (Pins P40, P42, P43, P45)
Reset P4nDDR WP4D Reset P4nDR Internal data
8-Bit timer module Output enable 8-Bit timer output
WP4D: Write Port WP4: Write Port RP4: Read Port
Figure 5-5. Port Schematic Diagram (Pins P44)
Figure
Hardware standby
Mode
Reset P46DDR WP4D Reset P46DR
Internal data
WP4D: Write Port WP4: Write Port RP4: Read Port
Figure 5-6. Port Schematic Diagram (Pin P46)
Figure
Mode Mode Reset
Hardware standby P47DDR Mode WP4D Reset P47DR Mode Internal data
WP4D: Write Port WP4: Write Port RP4: Read Port
Figure 5-7. Port Schematic Diagram (Pin P47)
Port
Port 6-bit input/output port that also provides input output pins serial communication interface. functions depend control bits serial control registers. Pins used serial communication available general-purpose input/output. Table 5-10 lists functions, which same both expanded single-chip modes.
Figure
Table 5-10. Port Functions (Modes Usage port Serial communication functions TxD0 RxD0
SCK0
TxD1
RxD1
SCK1
section Serial Communication Interface details serial control bits. Pins used serial communication interface switched between input output without regard values data direction register. Pins port drive single load 30-pF capacitive load when they used output pins. They also drive Darlington pair. Table 5-11 details port registers. Table 5-11. Port Registers Name Port data direction register Port data register Abbreviation P5DDR P5DR Read/Write Initial value H'C0 H'C0 Address H'FFB8 H'FFBA
Port Data Direction Register (P5DDR)-H'FFB8 Initial value Read/Write P55DDR P54DDR P53DDR P52DDR P51DDR P50DDR
P5DDR 8-bit register that selects direction each port functions output corresponding P5DDR input cleared Port Data Register (P5DR)-H'FFBA Initial value Read/Write
P5DR 8-bit register containing output data pins P50, controlling their input pullups. When reads P5DR, output pins (P5DDR reads value P5DR latch, input pins (P5DDR obtains logic level directly from pin, bypassing P5DR latch. This also applies pins used serial communication. Pull-Ups: available input pins, including serial communication input pins. Software turn pull-up writing P5DR, turn writing pull-ups automatically turned output pins.
Pins P53: These pins used general-purpose input output, output serial transmit data (TxD). When used output, these pins unaffected values P5DDR P5DR, their pull-ups automatically turned off. Pins P54: These pins used general-purpose input output, input serial receive data (RxD). When used input, these pins unaffected P5DDR P5DR, except that software turn their pull-ups clearing their data direction bits setting their data bits Pins P55: These pins used general-purpose input output, serial clock input output (SCK). When used output, these pins unaffected P5DDR P5DR. When these pins used input, software turn their pull-ups clearing their data direction bits setting their data bits Reset Hardware Standby Mode: P5DDR P5DR cleared serial control registers initialized. pins placed input port (high-impedance) state with pull-ups off. Software Standby Mode: serial control registers initialized P5DDR P5DR remain their previous states. pins become input output port pins depending setting P5DDR. Output pins output values P5DR. pull-ups input pins depending values P5DR. Figures 5-10 show schematic diagrams port
Reset P5nDDR WP5D Reset P5nDR Output enable Serial data Internal data
module
WP5D: Write Port WP5: Write Port RP5: Read Port
Figure 5-8. Port Schematic Diagram (Pins P53)
Figure
Reset P5nDDR WP5D Internal data Figure Reset P5nDR Input enable
module
Serial data WP5D: Write Port Write Port RP5: Read Port
Figure 5-9. Port Schematic Diagram (Pins P54)
Reset P5nDDR WP5D Internal data Reset P5nDR
module Clock input enable
Clock output enable Clock output
Clock input WP5D: Write Port WP5: Write Port RP5: Read Port
Figure 5-10. Port Schematic Diagram (Pins P55)
Port
Port 7-bit input/output port that also provides input output pins free-running timer, interrupt request input pins (IRQ0 IRQ2). functions depend control bits free-running timer control registers enable register. Pins used timer interrupt functions available general-purpose input/output. Table 5-12 lists functions, which same both expanded single-chip modes.
Figure 5-10
Table 5-12. Port Functions Usage functions (Modes port Timer/interrupt FTCI FTOA FTOB
IRQ0
IRQ1
IRQ2
section Exception Handling section Free-Running Timer Module details free-running timer interrupts. Pins port drive single load 90-pF capacitive load when they used output pins. They also drive Darlington pair. Table 5-13 details port registers. Table 5-13. Port Registers Name Port data direction register Port data register Abbreviation P6DDR P6DR Read/Write Initial value H'80 H'80 Address H'FFB9 H'FFBB
Port Data Direction Register (P6DDR)-H'FFB9 Initial value Read/Write P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR
P6DDR 8-bit register that selects direction each port functions output corresponding P6DDR input cleared Port Data Register (P6DR)-H'FFBB Initial value Read/Write
P6DR 8-bit register containing output data pins P60, controlling their input pullups. When reads P6DR, output pins (P6DDR reads value P6DR latch, input pins (P6DDR obtains logic level directly from pin, bypassing P6DR latch. This also applies pins used input output timer interrupt signals.
Pull-Ups: available input pins, including pins used input timer interrupt signals. Software turn pull-up writing P6DR, turn writing pull-ups automatically turned output pins. Pins P63: indicated table 5-12, these pins used general-purpose input output, input free-running timer clock input capture signals. When used free-running timer input, P6DDR should cleared otherwise free-running timer will receive value P6DR. input pull-up desired, P6DR should also cleared P62: These pins used general-purpose input output, output compare signals (FTOA FTOB) free-running timer. When used FTOA FTOB output, these pins unaffected values P6DDR P6DR, their pull-ups automatically turned off. Pins P66: These pins used general-purpose input output, input interrupt request signals (IRQ0 IRQ2). When they used interrupt request input, their data direction bits should normally cleared that value P6DR will generate interrupts. Reset Hardware Standby Mode: P6DDR P6DR cleared Timer output interrupt request input disabled. pins placed input port (high-impedance) state with pull-ups off. Software Standby Mode: free-running timer control registers initialized P6DDR, P6DR, interrupt control registers remain their previous states. pins become input output port pins interrupt request pins depending settings P6DDR enable register. Output pins output values P6DR. pull-ups input pins depending values P6DR. Figures 5-11 5-13 shows schematic diagrams port
Reset P6nDDR Internal data Free-running timer module Input-capture input, Counter clock input WP6D Reset P6nDR
WP6D: Write Port WP6: Write Port RP6: Read Port
Figure 5-11. Port Schematic Diagram (Pins P63)
Figure 5-11
Reset P6nDDR WP6D Reset P6nDR Output enable Output-compare output Internal data
Free-running timer module
WP6D: Write Port WP6: Write Port RP6: Read Port
Figure 5-12. Port Schematic Diagram (Pins P62)
Figure 5-12
Reset P6nDDR WP6D Reset P6nDR Internal data IRQ0 input IRQ1 input IRQ2 input WP6D: Write Port WP6: Write Port RP6: Read Port enable register IRQ0 enable IRQ1 enable IRQ2 enable Figure 5-13
Figure 5-13. Port Schematic Diagram (Pins P64, P65, P66)
Port
Port 8-bit input/output port that also provides control signals expanded modes), parallel handshaking control signals. Table 5-14 lists functions.
Table 5-14. Port Functions Expanded modes input/output input input/output input/output input output output output output WAIT input Single-chip mode input/output input input/output output input/output BUSY output input/output input/output input/output input/output input/output
Pins port drive single load 90-pF capacitive load when they used output pins. Table 5-15 details port registers. Table 5-15. Port Registers Name Port data direction register Port data register Abbreviation P7DDR P7DR Read/Write Initial value H'00 H'00 Address H'FFBC H'FFBE
Port Data Direction Register (P7DDR)-H'FFBC Initial value Read/Write P77DDR P76DDR P75DDR P74DDR P73DDR P72DDR P71DDR P70DDR
P7DDR 8-bit register that selects direction each port functions output corresponding P7DDR input cleared Port Data Register (P7DR)-H'FFBE Initial value Read/Write
P7DR 8-bit register containing output data pins P70, controlling their input pullups. When reads P7DR, output pins (P7DDR reads value P7DR latch, input pins (P7DDR obtains logic level directly from pin, bypassing P7DR latch. This also applies pins used control signal input output. Pull-Ups: available input pins, including pins used input WAIT signals. Software turn pull-up writing P7DR, turn writing pull-ups automatically turned output pins. P70: used general-purpose input output, input input strobe (IS) parallel handshake signal. When used input, P70DDR should cleared that output from P7DR will cause unintended strobes. input pull-up desired, P70DR should also cleared Pins P72: modes (expanded modes), these pins used general-purpose input output. mode (single-chip mode), these pins used general-purpose input output output BUSY parallel handshake signals, depending bits handshake control/status register. section Parallel Handshaking Interface, further information. Pins used parallel handshaking output unaffected values P7DDR P7DR, their pull-ups automatically turned off. P73: modes (expanded modes) used output P73DDR general-purpose input P73DDR cleared cannot used general-purpose output. mode (single-chip mode), used general-purpose input output. Pins P74, P75, P76: modes (expanded modes), these pins used output control signals. They unaffected values P7DDR P7DR, their pull-ups automatically turned off. mode (single-chip mode), these pins used general-purpose input output. P77: modes this used input WAIT control signal. unaffected values P7DDR P7DR, except that software turn pull-up clearing data direction setting data
mode (single-chip mode), this used general-purpose input output. Reset: single-chip mode (mode reset initializes pins port general-purpose input state with pull-ups off. expanded modes (modes initialized input port pins, initialized their control functions. Hardware Standby Mode: pins placed high-impedance state with pull-ups off. Software Standby Mode: pins remain their previous state. this means high output state. Figures 5-14 5-18 show schematic diagrams port
Reset P70DDR Internal data input WP7D: Write Port WP7: Write Port RP7: Read Port Figure 5-14 WP7D Reset P70DR
Figure 5-14. Port Schematic Diagram (Pin P70)
Reset P7nDDR WP7D Reset P7nDR Internal data
Handshake control status register output BUSY output
WP7D: Write Port WP7: Write Port Read Port
Figure 5-15. Port Schematic Diagram (Pins P72)
Figure 5-15
Reset P73DDR WP7D Mode Reset P73DR Mode output Internal data Figure 5-16
WP7D: Write Port WP7: Write Port RP7: Read Port
Figure 5-16. Port Schematic Diagram (Pin P73)
Hardware standby
Mode
Reset P7nDDR WP7D Internal data
Mode
Reset P7nDR
Mode
output output output
WP7D: Write Port WP7: Write Port RP7: Read Port
Figure 5-17. Port Schematic Diagram (Pins P74, P75, P76)
Figure 5-17
Mode
Reset P77DDR Internal data WAIT input Figure 5-18 WP7D Reset
P77DR
WP7D: Write Port WP7: Write Port RP7: Read Port
Figure 5-18. Port Schematic Diagram (Pin P77)
Section Parallel Handshaking Interface
Overview
single-chip mode (mode H8/325 Series chips interface another device parallel handshaking, using port 6.1.1 Features Built-in latch circuits Data input port latched falling edge signal. Strobe signal output strobe signal output line when port written read. Busy signal output busy signal output BUSY line from time when data latched falling edge until latched data read, unlocking latch. Input strobe interrupt input strobe interrupt generated falling edge signal. Recovery from software standby mode input strobe interrupt used recover from software standby mode.
6.1.2 Block Diagram Figure block diagram parallel handshaking interface.
BUSY Control logic HCSR
interrupt signal Input latch Reset Reset Port WP3: Write Port RP3: Read Port WP3D: Write Port WP3D
Figure 6-1. Block Diagram Parallel Handshaking Interface
Figure
Internal data
6.1.3 Input Output Pins Table lists input output pins used parallel handshaking interface. Table 6-1. Input Output Pins Parallel Handshaking Interface Name Data input/output pins Input strobe Output strobe Busy Abbreviation BUSY Function Data input output Strobe input data Strobe output data Busy signal
6.1.4 Register Configuration Table lists information about parallel handshaking interface registers. Table 6-2. Register Configuration Name Port data direction register Port data register Handshake control/status register Abbreviation P3DDR P3DR HCSR Initial value H'00 H'00 H'03 Address H'FFB4 H'FFB6 H'FFFE
Register Descriptions
6.2.1 Port Data Direction Register (P3DDR) Initial value Read/Write P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR
parallel handshaking interface input, clear P3DDR H'00. output, P3DDR H'FF. bits individually. Section 5.4, Port further information.
6.2.2 Port Data Register (P3DR) Initial value Read/Write
When parallel handshaking interface used output (P3DDR H'FF), P3DR stores output data. port read, P3DR data obtained. When parallel handshaking interface used input (P3DDR H'00), P3DR separate latches reading writing. data written P3DR control input pull-ups. When P3DR read, data obtained from separate input latches input strobe flag (ISF) directly from input pins cleared Section 5.4, Port further information. 6.2.3 Handshake Control/Status Register (HCSR) Initial value Read/Write ISIE
HCSR 8-bit register containing control status information parallel handshaking. reset hardware standby modes, HCSR initialized H'03. software standby mode retains previous value. 7-Input Strobe Flag (ISF): Indicates that input strobe signal (IS) gone low. read-only that cleared hardware. strobe input. cleared when port data register written read. (The handshake control/status register must read first.)
Description clear ISF, must read HCSR after been then read write port data register (P3DR). falling edge
(Initial value)
6-Input Strobe Interrupt Enable (ISIE): Enables disables handshake interrupt request (ISI). ISIE
Description handshake interrupt request (ISI) disabled. handshake interrupt request (ISI) enabled.
(Initial value)
5-Output Strobe Enable (OSE): Enables disables output output strobe signal. expanded modes (modes
Description output strobe signal disabled. output strobe signal enabled.
(Initial value)
4-Output Strobe Select (OSS): Selects whether generate output strobe signal when port data register (P3DR) written, when read.
Description output strobe signal output when P3DR read. output strobe signal output when P3DR written.
(Initial value)
3-Latch Enable (LTE): Controls input latches port expanded modes (modes When input data latched falling edge data retained input latch until port data register (P3DR) read, after which next data latched.
Description Port input data latched. Port input data latched falling edge
(Initial value)
2-Busy Enable (BSE): This enables disables output busy signal. expanded modes (modes ISIE
Description Busy signal output disabled. Busy signal output enabled.
(Initial value)
Bits 0-Reserved: These bits cannot modified always read
Operation
6.3.1 Output Timing Output Strobe Signal output strobe signal output when port data register (P3DR) written read. output strobe signal goes seventh system clock cycle after P3DR written read, remains eight system clock cycles, then goes high. Figure shows output strobe signal output after P3DR written (when Note following point when reading writing P3DR twice consecutively. P3DR written read once, then written read again within states, output strobe signal output second write read. Figure shows example this when
Port write
Port
system clocks system clocks
Figure 6-2. Output Strobe Output Timing (When
Port write
Port write
Port
output
Figure 6-3. Output Strobe Output Timing (Consecutive Writing Port When 6.3.2 Busy Signal Output Timing busy signal remains from fall input strobe signal until data latched port have been read, unlocking latch. Figure shows example. While busy signal low, data input port latched, even input strobe signal goes again.
Port read
BUSY
Figure 6-4. Busy Signal Output Timing 6.3.3 Operation Software Standby Mode software standby mode, BUSY output pins retain their previous states. timing output strobe signal, entire time during when chip software standby mode counted zero system clock cycles. Figure shows example.
Port write
Port Same data held Software standby mode Clock settling time system clocks Same state held
Figure 6-5. Output Strobe Timing Software Standby Mode When ISIE bits handshake control/status register (HCSR) both high-to-low transition signal occurs during software standby mode, input strobe interrupt requested chip recovers from software standby mode handle interrupt. parallel handshaking interface input, port input data also latched. either ISIE cleared then high-to-low transitions signal ignored during software standby mode. 6.3.4 Sample Application Figure shows example which parallel handshaking interface used interconnect H8/325 chips. Figure shows interface timing.
H8/325 (sending chip)
H8/325 (receiving chip)
Figure 6-6. Sample Usage Parallel Handshaking Interface
Sending H8/325 Receiving H8/325
Write P3DR Interrupt request Read HCSR Read P3DR
Interrupt request
Read HCSR
Write P3DR
H8/325 (sending chip)
H8/325 (receiving chip)
P3DR: Port data register HCSR: Handshake control/Status register
Figure 6-7. Parallel Handshaking Interface Timing Chart (Example) sending receiving H8/325s their HCSR bits follows: Sending H8/325: ISIE Receiving H8/325: ISIE sending H8/325 writes transmit data port data register (P3DR). This generates output strobe signal, notifying receiving H8/325 data output. receiving H8/325 receives strobe input strobe line latches data port generating input strobe interrupt. receiving H8/325 reads HCSR, then reads received data from P3DR. This clears generates output strobe signal, notifying sending H8/325 that data have been received. input strobe line sending H8/325 goes low, setting generating input strobe interrupt. sending H8/325 reads HCSR, then writes next transmit data P3DR. next data send, should read P3DR.) This clears generates output strobe signal. process returns step 6.3.5 Interrupts Regardless operating mode value bit, always when input changes from high low. ISIE input strobe interrupt (ISI) requested. software standby mode, must also set. section 6.3.3, Operation Software Standby Mode.
Section 16-Bit Free-Running Timer
Overview
H8/325 Series on-chip 16-bit free-running timer (FRT) module that uses 16-bit freerunning counter time base. Applications module include rectangular-wave output independent waveforms), input pulse width measurement, measurement external clock periods. 7.1.1 Features features free-running timer module listed below. Selection four clock sources free-running counter driven internal clock source external clock input (enabling external event counter). independent comparators Each comparator generate independent waveform. Input capture current count captured rising falling edge (selectable) input signal. Counter cleared under program control free-running counter cleared compare-match Four interrupt sources Compare-match input capture, overflow interrupts requested independently. Noise canceler built-in noise canceler remove high-frequency noise from pulse signal input input capture pin. 7.1.2 Block Diagram Figure shows block diagram free-running timer.
External clock source FTCI Clock select
Internal clock sources Clock Comparematch OCRA (H/L)
Comparator
FTOA FTOB
Overflow Clear Module data interface (H/L) Internal data
Comparematch Control logic
Comparator
OCRB (H/L)
Capture
(H/L)
TCSR
OCIA OCIB FOVI Interrupt signals Legend OCRA: OCRB: FRC: ICR: TCSR: TCR:
Output Compare Register Output Compare Register Free-Running Counter Input Capture Register Timer Control/Status Register Timer Control Register
Figure 7-1. Block Diagram 16-Bit Free-Running Timer
Figure7-1
7.1.3 Input Output Pins Table lists input output pins free-running timer module. Table 7-1. Input Output Pins Free-Running Timer Module Name Counter clock input Output compare Output compare Input capture Abbreviation FTCI FTOA FTOB Input Output Output Input Function Input external free-running counter clock signal Output controlled comparator Output controlled comparator Input capture trigger
7.1.4 Register Configuration Table lists registers free-running timer module. Table 7-2. Register Configuration Initial value H'00 H'00 H'00 H'00 H'FF H'FF H'FF H'FF H'00 H'00 H'FC
Name Timer control register Timer control/status register Free-running counter (high) Free-running counter (low) Output compare register (high) Output compare register (low) Output compare register (high) Output compare register (low) Input capture register (high) Input capture register (low) noise canceler control register
Abbreviation TCSR OCRA OCRA OCRB OCRB FNCR
R/(W)*
Address H'FF90 H'FF91 H'FF92 H'FF93 H'FF94 H'FF95 H'FF96 H'FF97 H'FF98 H'FF99 H'FFFF
Software write clear bits cannot write these bits.
Register Descriptions
7.2.1 Free-Running Counter (FRC) H'FF92
Initial value Read/ Write 16-bit readable/writable up-counter that increments internal pulse generated from clock source. clock source selected clock select bits (CKS1 CKS0) timer control register (TCR). When overflows from H'FFFF H'0000, overflow flag (OVF) timer control/status register (TCSR) Because 16-bit register, temporary register (TEMP) used when written read. section 7.3, Interface

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