Embedded Processor ADSP-BF531/BF532/BF533 External Memory Control
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Preliminary Technical DatFEATURES High-Performance Blackfin Processor 16-Bit MACs, 40-Bit ALUs, Four 8-Bit Video ALUs, 40-Bit Shifter RISC-Like Register Instruction Model Ease Programming Compiler-Friendly Support Advanced Debug, Trace, Performance- Monitoring Core with On-chip Voltage Regulation V-Tolerant 160-Ball Mini-BGA 176-Lead LQFP Packages MEMORY 148K Bytes On-Chip Memory: Bytes Instruction SRAM/Cache Bytes Instruction SRAM Bytes Instruction Bytes Data SRAM/Cache Bytes Data SRAM Bytes Scratchpad SRAM Dual-Channel Memory Controllers Memory Management Unit Providing Memory Protection
Embedded Processor ADSP-BF531/BF532/BF533
External Memory Controller with Glueless Support SDRAM, SRAM, FLASH, Flexible Memory Booting Options From SPI, External Memory, Internal PERIPHERALS Parallel Peripheral Interface (PPI)/GPIO, Supporting ITU-R Video Data Formats Dual-Channel, Full-Duplex Synchronous Serial Ports, Supporting Eight Stereo Channels Channel Controller SPI-compatible Port Three Timer/Counters with Support UART with Support IrDA® Event Handler Real-Time Clock Watchdog Timer Debug/JTAG Interface On-Chip Capable Frequency Multiplication
FUNCTIONAL BLOCK DIAGRAM
JTAG TEST EMULATION
EVENT CONTROLLER/ CORE TIMER
WATCHDOG TIMER
VOLTAGE REGULATOR
INSTRUCTION MEMORY DATA MEMORY
REAL TIME CLOCK UART PORT IrDA
TIMER0, TIMER1, TIMER2 CORE SYSTEM INTERFACE GPIO
CONTROLLER SERIAL PORTS
BOOT
PORT
EXTERNAL PORT FLASH, SDRAM CONTROL
REV.
This information applies product under development. characteristics specifications subject change without notice. Analog Devices assumes obligation regarding future manufacturing unless otherwise agreed writing. Technology Way, P.O.Box 9106, Norwood, 02062-9106, U.S.A. Tel:781/329-4700 www.analog.com Fax:781/326-8703 ©Analog Devices,Inc., 2003
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GENERAL NOTE
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This data sheet provides preliminary information Blackfinprocessors.1
GENERAL DESCRIPTION
clean, orthogonal RISC-like microprocessor instruction set, single-instruction, multiple-data (SIMD) multimedia capabilities into single instruction-set architecture. ADSP-BF53x Processors completely code compatible, differing only with respect their performance onchip memory. Specific performance memory configurations shown Table
ADSP-BF53x Processors members Blackfin family products, incorporating Analog Devices/Intel Micro Signal Architecture (MSA). Blackfin processors combine dual-MAC state-of-the-art signal processing engine, advantages Table Processor Comparison ADSP-BF531
ADSP-BF532
ADSP-BF533
Maximum performance Instruction SRAM/Cache Instruction SRAM Instruction Data SRAM/Cache Data SRAM Scratchpad
MHz/ MMACs bytes bytes bytes bytes bytes
MHz/ MMACs bytes bytes bytes bytes bytes
MHz/ 1200 MMACs bytes bytes bytes bytes bytes
integrating rich industry-leading system peripherals memory, Blackfin processors platform choice next-generation applications that require RISC-like programmability, multimedia support leading-edge signal processing integrated package.
Portable Low-Power Architecture
Blackfin processors provide world-class power management performance. Blackfin processors designed power voltage design methodology feature Dynamic Power Management, ability vary both voltage frequency operation significantly lower overall power consumption. Varying voltage frequency result substantial reduction power consumption, compared with just varying frequency operation. This translates into longer battery life portable appliances.
System Integration
Clock, Watchdog Timer. This functions satisfies wide variety typical system support needs augmented system expansion capabilities part. addition these general-purpose peripherals, ADSP-BF53x Processor contains high-speed serial parallel ports interfacing variety audio, video, modem codec functions; interrupt controller flexible management interrupts from on-chip peripherals external sources; power management control functions tailor performance power characteristics processor system many application scenarios. peripherals, except general-purpose I/O, Real-Time Clock, timers, supported flexible structure. There also separate memory channel dedicated data transfers between processor's various memory spaces, including external SDRAM asynchronous memory. Multiple on-chip buses running provide enough bandwidth keep processor core running along with activity on-chip external peripherals. ADSP-BF53x Processor includes on-chip voltage regulator support ADSP-BF53x Processor Dynamic Power Management capability. voltage regulator provides range core voltage levels from single 2.25 input. voltage regulator bypassed user's discretion.
Blackfin Processor Core
ADSP-BF53x Processors highly integrated system-ona-chip solutions next generation digital communication consumer multimedia applications. combining industrystandard interfaces with high performance signal processing core, users develop cost-effective solutions quickly without need costly external components. system peripherals include UART port, port, serial ports (SPORTs), four general purpose timers (three with capability), realtime clock, watchdog timer, Parallel Peripheral Interface.
ADSP-BF53x Processor Peripherals
ADSP-BF53x Processor contains rich peripherals connected core several high bandwidth buses, providing flexibility system configuration well excellent overall system performance (see block diagram Page general-purpose peripherals include functions such UART, Timers with (Pulse Width Modulation) pulse measurement capability, general purpose flag pins, Real-Time
shown Figure page Blackfin processor core contains 16-bit multipliers, 40-bit accumulators, 40bit ALUs, four video ALUs, 40-bit shifter. computation units process 8-bit, 16-bit, 32-bit data from register file. compute register file contains eight 32-bit registers. When performing compute operations 16-bit operand data, register file operates independent 16-bit registers. operands compute operations come from multiported register file instruction constant fields. REV.
Blackfin trademark Analog Devices, Inc.
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ADSP-BF53x
Each perform 16-bit 16-bit multiply each cycle, accumulating results into 40-bit accumulators. Signed unsigned formats, rounding, saturation supported. ALUs perform traditional arithmetic logical operations 16-bit 32-bit data. addition, many special instructions included accelerate various signal processing tasks. These include operations such field extract population count, modulo multiply, divide primitives, saturation rounding, sign/exponent detection. video instructions include byte alignment packing operations, 16bit 8-bit adds with clipping, 8-bit average operations, 8bit subtract/absolute value/accumulate (SAA) operations. Also provided compare/select vector search instructions. certain instructions, 16-bit operations performed simultaneously register pairs 16-bit high half 16-bit half compute register). also using second ALU, quad 16-bit operations possible.
40-bit shifter perform shifts rotates used support normalization, field extract, field deposit instructions. program sequencer controls flow instruction execution, including instruction alignment decoding. program flow control, sequencer supports relative indirect conditional jumps (with static branch prediction), subroutine calls. Hardware provided support zero-overhead looping. architecture fully interlocked, meaning that programmer need manage pipeline when executing instructions with data dependencies. address arithmetic unit provides addresses simultaneous dual fetches from memory. contains multiported register file consisting four sets 32-bit Index, Modify, Length, Base registers (for circular buffering), eight additional 32-bit pointer registers (for C-style indexed stack manipulation).
ADDRESS ARITHMETIC UNIT
DAG0
DAG1
SEQUENCER
ALIGN
DECODE CONTROL UNIT
LOOP BUFFER
BARREL SHIFTER
DATA ARITHMETIC UNIT
Figure Blackfin Processor Core
Blackfin processors support modified Harvard architecture combination with hierarchical memory structure. Level (L1) memories those that typically operate full processor speed with little latency. level, instruction memory holds instructions only. data memories hold data, dedicated scratchpad data memory stores stack local variable information.
addition, multiple memory blocks provided, offering configurable SRAM cache. Memory Management Unit (MMU) provides memory protection individual tasks that operating core protect system registers from unintended access.
REV.
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architecture provides three modes operation: User mode, Supervisor mode, Emulation mode. User mode restricted access certain system resources, thus providing protected software environment, while Supervisor mode unrestricted access system core resources. Blackfin processor instruction been optimized that 16-bit opcodes represent most frequently used instructions, resulting excellent compiled code density. Complex instructions encoded into 32-bit opcodes, representing fully featured multifunction instructions. Blackfin processors support limited multi-issue capability, where 32-bit instruction issued parallel with 16-bit instructions, allowing programmer many core resources single instruction cycle. Blackfin processor assembly language uses algebraic syntax ease coding readability. architecture been optimized conjunction with C/C++ compiler, resulting fast efficient software implementations.
Memory Architecture
0xFFFF FFFF CORE REGISTERS BYTE) 0xFFE0 0000 SYSTEM REGISTERS BYTE) 0xFFC0 0000 RESERVED 0xFFB0 1000 SCRATCHPAD SRAM BYTE) RESERVED 0xFFA1 4000 INSTRUCTION SRAM CACHE (16K BYTE) 0xFFA1 0000 INSTRUCTION SRAM (64K BYTE) 0xFFA0 0000 RESERVED 0xFF90 8000 DATA BANK SRAM CACHE (16K BYTE) 0xFF90 4000 DATA BANK SRAM (16K BYTE) 0xFF90 0000 RESERVED 0xFF80 8000 DATA BANK SRAM CACHE (16K BYTE) 0xFF80 4000 DATA BANK SRAM (16K BYTE) 0xFF80 0000 RESERVED 0xEF00 0000 0x2040 0000 ASYNC MEMORY BANK BYTE) 0x2030 0000 ASYNC MEMORY BANK BYTE) 0x2020 0000 ASYNC MEMORY BANK BYTE) 0x2010 0000 ASYNC MEMORY BANK BYTE) 0x2000 0000 RESERVED 0x0800 0000 SDRAM MEMORY (16M BYTE 128M BYTE) 0x0000 0000
EXTERNAL MEMORY INTERNAL MEMORY
0xFFB0 0000
RESERVED
ADSP-BF53x Processor views memory single unified byte address space, using 32-bit addresses. resources, including internal memory, external memory, control registers, occupy separate sections this common address space. memory portions this address space arranged hierarchical structure provide good cost/performance balance some very fast, low-latency on-chip memory cache SRAM, larger, lower-cost performance off-chip memory systems. Figure page Figure page Figure page memory system primary highest-performance memory available Blackfin processor. off-chip memory system, accessed through External Interface Unit (EBIU), provides expansion with SDRAM, flash memory, SRAM, optionally accessing 132M bytes physical memory. memory controller provides high-bandwidth datamovement capability. perform block transfers code data between internal memory external memory spaces.
Internal (On-chip) Memory
Figure ADSP-BF533 Internal/External Memory
third memory block byte scratchpad SRAM which runs same speed memories, only accessible data SRAM cannot configured cache memory.
External (Off-Chip) Memory
External memory accessed EBIU. This 16-bit interface provides glueless connection bank synchronous DRAM (SDRAM) well four banks asynchronous memory devices including FLASH, EPROM, ROM, SRAM, memory mapped devices. PC133-compliant SDRAM controller programmed interface 128M bytes SDRAM. asynchronous memory controller programmed control four banks devices with very flexible timing parameters wide variety devices. Each bank occupies byte segment regardless size devices used, that these banks will only contiguous each fully populated with byte memory.
Memory Space
ADSP-BF53x Processor three blocks on-chip memory providing high-bandwidth access core. first instruction memory, consisting bytes SRAM, which bytes configured four-way set-associative cache. This memory accessed full processor speed. second on-chip memory block data memory, consisting banks bytes each. Each memory bank configurable, offering both Cache SRAM functionality. This memory block accessed full processor speed.
Blackfin processors define separate space. resources mapped through flat 32-bit address space. Onchip devices have their control registers mapped into memory-mapped registers (MMRs) addresses near byte address space. These separated into smaller blocks, which contains control MMRs core functions, other which contains registers needed setup REV.
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0xFFFF FFFF CORE REGISTERS BYTE) 0xFFE0 0000 SYSTEM REGISTERS BYTE) 0xFFC0 0000 RESERVED 0xFFB0 1000 SCRATCHPAD SRAM BYTE)
INTERNAL MEMORY
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ADSP-BF53x
0xFFFF FFFF CORE REGISTERS BYTE) 0xFFE0 0000 SYSTEM REGISTERS BYTE) 0xFFC0 0000 RESERVED 0xFFB0 1000 SCRATCHPAD SRAM BYTE) 0xFFB0 0000 RESERVED INSTRUCTION SRAM CACHE (16K BYTE) 0xFFA1 0000 RESERVED 0xFFA0 C000 INSTRUCTION SRAM (16K BYTE) 0xFFA0 8000 INSTRUCTION (32K BYTE) 0xFFA0 0000 RESERVED 0xFF90 8000 RESERVED 0xFF90 4000 RESERVED 0xFF80 8000 DATA BANK SRAM CACHE (16K BYTE) 0xFF80 4000 RESERVED 0xEF00 0000 0x2040 0000 ASYNC MEMORY BANK BYTE) 0x2030 0000 ASYNC MEMORY BANK BYTE) 0x2020 0000 ASYNC MEMORY BANK BYTE) 0x2010 0000 ASYNC MEMORY BANK BYTE) 0x2000 0000 RESERVED 0x0800 0000 SDRAM MEMORY (16M BYTE 128M BYTE) 0x0000 0000
EXTERNAL MEMORY INTERNAL MEMORY
0xFFB0 0000 RESERVED 0xFFA1 4000 INSTRUCTION SRAM CACHE (16K BYTE) 0xFFA1 0000 INSTRUCTION SRAM (32K BYTE) 0xFFA0 8000 INSTRUCTION (32K BYTE) 0xFFA0 0000 RESERVED 0xFF90 8000 DATA BANK SRAM CACHE (16K BYTE) 0xFF90 4000 RESERVED 0xFF80 8000 DATA BANK SRAM CACHE (16K BYTE) 0xFF80 4000 RESERVED 0xEF00 0000 0x2040 0000 ASYNC MEMORY BANK BYTE) 0x2030 0000 ASYNC MEMORY BANK BYTE) 0x2020 0000 ASYNC MEMORY BANK BYTE) 0x2010 0000 ASYNC MEMORY BANK BYTE) 0x2000 0000 RESERVED 0x0800 0000 SDRAM MEMORY (16M BYTE 128M BYTE) 0x0000 0000
0xFFA1 4000
EXTERNAL MEMORY
RESERVED
RESERVED
Figure ADSP-BF532 Internal/External Memory Figure ADSP-BF531 Internal/External Memory
control on-chip peripherals outside core. MMRs accessible only supervisor mode appear reserved space on-chip peripherals.
Booting
ADSP-BF53x Processor contains small boot kernel, which configures appropriate peripheral booting. ADSPBF53x Processor configured boot from boot memory space, processor starts executing from on-chip boot ROM. more information, Booting Modes Page
Event Handling
Non-Maskable Interrupt (NMI) event generated software watchdog timer input signal processor. event frequently used power-down indicator initiate orderly shutdown system. Exceptions Events that occur synchronously program flow (i.e., exception will taken before instruction allowed complete). Conditions such data alignment violations undefined instructions cause exceptions. Interrupts Events that occur asynchronously program flow. They caused input pins, timers, other peripherals, well explicit software instruction. Each event type associated register hold return address associated return-from-event instruction. When event triggered, state processor saved supervisor stack. ADSP-BF53x Processor Event Controller consists stages, Core Event Controller (CEC) System Interrupt Controller (SIC). Core Event Controller works with System Interrupt Controller prioritize control system events. Conceptually, interrupts from peripherals enter into SIC, then routed directly into generalpurpose interrupts CEC.
event controller ADSP-BF53x Processor handles asynchronous synchronous events processor. ADSP-BF53x Processor provides event handling that supports both nesting prioritization. Nesting allows multiple event service routines active simultaneously. Prioritization ensures that servicing higher-priority event takes precedence over servicing lower-priority event. controller provides support five different types events: Emulation emulation event causes processor enter emulation mode, allowing command control processor JTAG interface. Reset This event resets processor.
REV.
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Core Event Controller (CEC)
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Default Mapping
Table System Interrupt Controller (SIC) (Continued) Peripheral Interrupt Event
supports nine general-purpose interrupts (IVG15-7), addition dedicated interrupt exception events. these general-purpose interrupts, lowest-priority interrupts (IVG15-14) recommended reserved software interrupt handlers, leaving seven prioritized interrupt inputs support peripherals ADSP-BF53x Processor. Table describes inputs CEC, identifies their names Event Vector Table (EVT), lists their priorities.
Table Core Event Controller (CEC) Priority Highest) Event Class Entry
Emulation/Test Control Reset Non-Maskable Interrupt Exception Reserved Hardware Error Core Timer General Interrupt General Interrupt General Interrupt General Interrupt General Interrupt General Interrupt General Interrupt General Interrupt General Interrupt
IVHW IVTMR IVG7 IVG8 IVG9 IVG10 IVG11 IVG12 IVG13 IVG14 IVG15
Channel (SPORT Channel (SPORT Channel (SPORT Channel (SPI) Channel (UART Channel (UART Timer Timer Timer Interrupt Interrupt Channels (Memory Stream Channels (Memory Stream Software Watchdog Timer
Event Control
IVG9 IVG9 IVG9 IVG10 IVG10 IVG10 IVG11 IVG11 IVG11 IVG12 IVG12 IVG13 IVG13 IVG13
ADSP-BF53x Processor provides user with very flexible mechanism control processing events. CEC, three registers used coordinate control events. Each register bits wide: Interrupt Latch Register (ILAT) ILAT register indicates when events have been latched. appropriate when processor latched event cleared when event been accepted into system. This register updated automatically controller, written only when corresponding IMASK cleared. Interrupt Mask Register (IMASK) IMASK register controls masking unmasking individual events. When IMASK register, that event unmasked will processed when asserted. cleared IMASK register masks event, preventing processor from servicing event even though event latched ILAT register. This register read written while supervisor mode. (Note that general-purpose interrupts globally enabled disabled with instructions, respectively.) Interrupt Pending Register (IPEND) IPEND register keeps track nested events. IPEND register indicates event currently active nested some level. This register updated automatically controller read while supervisor mode.
System Interrupt Controller (SIC)
System Interrupt Controller provides mapping routing events from many peripheral interrupt sources prioritized general-purpose interrupt inputs CEC. Although ADSP-BF53x Processor provides default mapping, user alter mappings priorities interrupt events writing appropriate values into Interrupt Assignment Registers (IAR). Table describes inputs into default mappings into CEC.
Table System Interrupt Controller (SIC) Peripheral Interrupt Event Default Mapping
Wakeup Error Error SPORT Error SPORT Error Error UART Error Real-Time Clock Channel (PPI) Channel (SPORT
IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG7 IVG8 IVG8 IVG9
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REV.
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allows further control event processing providing three 32-bit interrupt control status registers. Each register contains corresponding each peripheral interrupt events shown Table Page Interrupt Mask Register (SIC_IMASK)- This register controls masking unmasking each peripheral interrupt event. When register, that peripheral event unmasked will processed system when asserted. cleared register masks peripheral event, preventing processor from servicing event. Interrupt Status Register (SIC_ISR) multiple peripherals mapped single event, this register allows software determine which peripheral event source triggered interrupt. indicates peripheral asserting interrupt, cleared indicates peripheral asserting event. Interrupt Wakeup Enable Register (SIC_IWR) enabling corresponding this register, peripheral configured wake processor, should core idled when event generated. (see Dynamic Power Management Page 10.) Because multiple interrupt sources single generalpurpose interrupt, multiple pulse assertions occur simultaneously, before during interrupt processing interrupt event already detected this interrupt input. IPEND register contents monitored interrupt acknowledgement. appropriate ILAT register when interrupt rising edge detected (detection requires core clock cycles). cleared when respective IPEND register set. IPEND indicates that event entered into processor pipeline. this point will recognize queue next rising edge event corresponding event input. minimum latency from rising edge transition generalpurpose interrupt IPEND output asserted three core clock cycles; however, latency much higher, depending activity within state processor.
Controllers
ADSP-BF53x Processor controller supports both 1dimensional (1D) 2-dimensional (2D) transfers. transfer initialization implemented from registers from sets parameters called descriptor blocks. capability supports arbitrary column sizes elements elements, arbitrary column step sizes elements. Furthermore, column step size less than step size, allowing implementation interleaved data streams. This feature especially useful video applications where data deinterleaved fly. Examples types supported ADSP-BF53x Processor controller include: single, linear buffer that stops upon completion circular, auto-refreshing buffer that interrupts each full fractionally full buffer using linked list descriptors using array descriptors, specifying only base address within common page addition dedicated peripheral channels, there memory channels provided transfers between various memories ADSP-BF53x Processor system. This enables transfers blocks data between memories- including external SDRAM, ROM, SRAM, flash memory- with minimal processor intervention. Memory transfers controlled very flexible descriptor-based methodology standard register-based autobuffer mechanism.
Real-Time Clock
ADSP-BF53x Processor Real-Time Clock (RTC) provides robust digital watch features, including current time, stopwatch, alarm. clocked 32.768 crystal external ADSP-BF53x Processor. peripheral dedicated power supply pins that remain powered clocked even when rest processor low-power state. provides several programmable interrupt options, including interrupt second, minute, hour, clock ticks, interrupt programmable stopwatch countdown, interrupt programmed alarm time. 32.768 input clock frequency divided down signal prescaler. counter function timer consists four counters: 60-second counter, 60-minute counter, 24-hour counter, 32,768-day counter. When enabled, alarm function generates interrupt when output timer matches programmed value alarm control register. There alarms: first alarm time day. second alarm time that day. stopwatch function counts down from programmed value, with one-second resolution. When stopwatch enabled counter underflows, interrupt generated.
ADSP-BF53x Processor multiple, independent controllers that support automated data transfers with minimal overhead processor core. transfers occur between ADSP-BF53x Processor's internal memories DMA-capable peripherals. Additionally, transfers accomplished between DMA-capable peripherals external devices connected external memory interfaces, including SDRAM controller asynchronous memory controller. DMA-capable peripherals include SPORTs, port, UART, PPI. Each individual DMA-capable peripheral least dedicated channel.
REV.
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Like other peripherals, wake ADSPBF53x Processor from low-power state upon generation wakeup event. Connect pins RTXI RTXO with external components shown Figure
RTXO
timer units used conjunction with UART measure width pulses data stream provide auto-baud detect function serial channel. timers generate interrupts processor core providing periodic events synchronization, either system clock count external signals. addition three general-purpose programmable timers, fourth timer also provided. This extra timer clocked internal processor clock typically used system tick clock generation operating system periodic interrupts.
Serial Ports (SPORTs)
IPTE IFIC
ADSP-BF53x Processor incorporates dual-channel synchronous serial ports (SPORT0 SPORT1) serial multiprocessor communications. SPORTs support following features: capable operation. Bidirectional operation Each SPORT sets independent transmit receive pins, enabling eight channels stereo audio. Buffered (8-deep) transmit receive ports Each port data register transferring data words from other processor components shift registers shifting data data registers. Clocking Each transmit receive port either external serial clock generate own, frequencies ranging from (fSCLK/131,070) (fSCLK/2) Word length Each SPORT supports serial data words from bits length, transferred most-significantbit first least-significant-bit first. Framing Each transmit receive port with without frame sync signals each data word. Frame sync signals generated internally externally, active high low, with either pulsewidths early late frame sync. Companding hardware Each SPORT perform A-law µ-law companding according recommendation G.711. Companding selected transmit and/or receive channel SPORT without additional latencies. operations with single-cycle overhead Each SPORT automatically receive transmit multiple buffers memory data. processor link chain sequences transfers between SPORT memory. Interrupts Each transmit receive port generates interrupt upon completing transfer data word after transferring entire data buffer buffers through DMA. Multichannel capability Each SPORT supports channels 1024-channel window compatible with H.100, H.110, MVIP-90, HMVIP standards. REV.
Figure External Components Watchdog Timer
ADSP-BF53x Processor includes 32-bit timer that used implement software watchdog function. software watchdog improve system availability forcing processor known state through generation hardware reset, non-maskable interrupt (NMI), general-purpose interrupt, timer expires before being reset software. programmer initializes count value timer, enables appropriate interrupt, then enables timer. Thereafter, software must reload counter before counts zero from programmed value. This protects system from remaining unknown state where software, which would normally reset timer, stopped running external noise condition software error. configured generate hardware reset, watchdog timer resets both core ADSP-BF53x Processor peripherals. After reset, software determine watchdog source hardware reset interrogating status watchdog timer control register. timer clocked system clock (SCLK), maximum frequency fSCLK.
Timers
There four general-purpose programmable timer units ADSP-BF53x Processor. Three timers have external that configured either Pulse Width Modulator (PWM) timer output, input clock timer, mechanism measuring pulse widths periods external events. These timers synchronized external clock input pin, external clock input PPI_CLK pin, internal SCLK.
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Serial Peripheral Interface (SPI) Port
ADSP-BF53x Processor SPI-compatible port that enables processor communicate with multiple SPI-compatible devices. interface uses three pins transferring data: data pins (Master Output-Slave Input, MOSI, Master InputSlave Output, MISO) clock (Serial Clock, SCK). chip select input (SPISS) lets other devices select processor, seven chip select output pins (SPISEL7-1) processor select other devices. select pins reconfigured Programmable Flag pins. Using these pins, port provides full-duplex, synchronous serial interface, which supports both master/slave modes multimaster environments. port's baud rate clock phase/polarities programmable (see Figure integrated controller, configurable support transmit receive data streams. SPI's controller only service unidirectional accesses given time.
SCLK Clock Rate SPIBAUD where SPIBAUD 65,535 Figure Clock Rate Calculation
UART port's baud rate (see Figure serial data format, error code generation status, interrupts programmable: Supporting rates ranging from (fSCLK/ 1,048,576) (fSCLK/16) bits second. Supporting data formats from to12 bits frame. Both transmit receive operations configured generate maskable interrupts processor.
SCLK UART Clock Rate where 65,536 Figure UART Clock Rate Calculation
conjunction with general-purpose timer functions, autobaud detection supported. capabilities UART further extended with support Infrared Data Association (IrDA®) Serial Infrared Physical Layer Link Specification (SIR) protocol.
Programmable Flags (PFx)
During transfers, port simultaneously transmits receives serially shifting data serial data lines. serial clock line synchronizes shifting sampling data serial data lines.
UART Port
ADSP-BF53x Processor bi-directional, generalpurpose Programmable Flag (PF15-0) pins. Each programmable flag individually controlled manipulation flag control, status interrupt registers: Flag Direction Control Register Specifies direction each individual input output. Flag Control Status Registers ADSP-BF53x Processor employs "write modify" mechanism that allows combination individual flags modified single instruction, without affecting level other flags. Four control registers provided. register written order flag values, register written order clear flag values, register written order toggle flag values, register written order specify flag value. Reading flag status register allows software interrogate sense flags. Flag Interrupt Mask Registers Flag Interrupt Mask Registers allow each individual function interrupt processor. Similar Flag Control Registers that used clear individual flag values, Flag Interrupt Mask Register sets bits enable interrupt function, other Flag Interrupt Mask register clears bits disable interrupt function.
ADSP-BF53x Processor provides full-duplex Universal Asynchronous Receiver/Transmitter (UART) port, which fully compatible with PC-standard UARTs. UART port provides simplified UART interface other peripherals hosts, supporting full-duplex, DMA-supported, asynchronous transfers serial data. UART port includes support data bits, stop bits, none, even, parity. UART port supports modes operation: (Programmed I/O) processor sends receives data writing reading I/O-mapped UART registers. data double-buffered both transmit receive. (Direct Memory Access) controller transfers both transmit receive data. This reduces number frequency interrupts required transfer data from memory. UART dedicated channels, transmit receive. These channels have lower default priority than most channels because their relatively service rates.
REV.
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pins defined inputs configured generate hardware interrupts, while output pins triggered software interrupts. Flag Interrupt Sensitivity Registers Flag Interrupt Sensitivity Registers specify whether individual pins level- edge-sensitive specify-if edgesensitive-whether just rising edge both rising falling edges signal significant. register selects type sensitivity, register selects which edges significant edge-sensitivity.
Parallel Peripheral Interface
Output Mode
This mode used transmitting video other data with three output frame syncs. Typically, single frame sync appropriate data converter applications, whereas three frame syncs could used sending video with hardware signaling.
Mode Descriptions
ITU-R modes intended suit wide variety video capture, processing, transmission applications. Three distinct sub-modes supported: Active Video Only Mode Vertical Blanking Only Mode Entire Field Mode
Active Video Only Mode
ADSP-BF53x Processor provides Parallel Peripheral Interface (PPI) that connect directly parallel converters, video encoders decoders, other general purpose peripherals. consists dedicated input clock pin, frame synchronization pins, data pins. input clock supports parallel data rates fSCLK/2 MHz, synchronization signals configured either inputs outputs. supports variety general purpose ITU-R modes operation. general purpose mode, provides half-duplex, bi-directional data transfer with bits data. frame synchronization signals also provided. ITUR mode, provides half-duplex, bi-directional transfer 10-bit video data. Additionally, on-chip decode embedded start-of-line (SOL) start-of-field (SOF) preamble packets supported.
General Purpose Mode Descriptions
This mode used when only active video portion field interest blanking intervals. will read data between Active Video (EAV) Start Active Video (SAV) preamble symbols, data present during vertical blanking intervals. this mode, control byte sequences stored memory; they filtered PPI. After synchronizing start Field will ignore incoming samples until sees code. user specifies number active video lines frame PPI_Count register).
Vertical Blanking Interval Mode
this mode, only transfers vertical blanking interval (VBI) data.
Entire Field Mode
modes intended suit wide variety data capture transmission applications. Three distinct submodes supported: Input Mode Frame Syncs data inputs into PPI. Frame Capture Mode Frame Syncs outputs from PPI, data inputs. Output Mode Frame Syncs data outputs from PPI.
Input Mode
this mode, entire incoming stream read through PPI. This includes active video, control preamble sequences, ancillary data that embedded horizontal vertical blanking intervals. Data transfer starts immediately after synchronization Field
Dynamic Power Management
This mode intended applications, well video communication with hardware signaling. simplest form, PPI_FS1 external frame sync input that controls when read data. PPI_DELAY allows delay PPI_CLK cycles) between reception this frame sync initiation data reads. number input data samples userprogrammable defined contents PPI_Count register. Data widths 16-bits supported, programmed PPI_CONTROL register.
Frame Capture Mode
ADSP-BF53x Processor provides four operating modes, each with different performance/power profile. addition, Dynamic Power Management provides control functions dynamically alter processor core supply voltage, further reducing power dissipation. Control clocking each ADSP-BF53x Processor peripherals also reduces power consumption. Table summary power settings each mode.
Full-On Operating Mode Maximum Performance
Full-On mode, enabled bypassed, providing capability maximum operational frequency. This power-up default execution state which maximum performance achieved. processor core enabled peripherals full speed.
Active Operating Mode Moderate Power Savings
This mode allows video source(s) slave (e.g., frame capture). ADSP-BF53x Processor controls when read from video source(s). PPI_FS1 HSYNC output PPI_FS2 VSYNC output.
Active mode, enabled bypassed. Because bypassed, processor's core clock (CCLK) system clock (SCLK) input clock (CLKIN) frequency. REV.
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this mode, CLKIN CCLK multiplier ratio changed, although changes realized until Full-On mode entered. access available appropriately configured memories. Active mode, possible disable through Control register (PLL_CTL). disabled, must re-enabled before transitioning Full-On Sleep modes.
Table Power Settings Bypassed Core Clock (CCLK) System Clock (SCLK)
separate from other I/O, processor take advantage Dynamic Power Management, without affecting other devices.
Table Power Domains Power Domain Range
internal logic, except internal logic crystal other
VDDINT VDDRTC VDDEXT
Full Active Sleep Deep Sleep
Enabled Enabled/Disabled Enabled Disabled
Enabled Enabled Disabled Disabled
Enabled Enabled Enabled Disabled
power dissipated processor largely function clock frequency processor square operating voltage. example, reducing clock frequency results reduction power dissipation, while reducing voltage reduces power dissipation more than 40%. Further, these power savings additive, that clock frequency supply voltage both reduced, power savings dramatic. Dynamic Power Management feature ADSP-BF53x Processor allows both processor's input voltage (VDDINT) clock frequency (fCCLK) dynamically controlled. explained above, savings power dissipation modeled following equations:
Power Savings Factor DDINTRED CCLKRED DDINTNOM CCLKNOM
Mode
Sleep Operating Mode High Power Savings
Sleep mode reduces power dissipation disabling clock processor core (CCLK). system clock (SCLK), however, continue operate this mode. Typically external event activity will wake processor. When Sleep mode, assertion wakeup will cause processor sense value BYPASS Control register (PLL_CTL). BYPASS disabled, processor will transition Full mode. BYPASS enabled, processor will transition Active mode. When Sleep mode, system access memory supported.
Deep Sleep Operating Mode Maximum Power Savings
Power Savings Power Savings Factor 100%
Deep Sleep mode maximizes power savings disabling clocks processor core (CCLK) synchronous peripherals (SCLK). Asynchronous peripherals, such RTC, still running will able access internal resources external memory. This powered-down mode only exited assertion reset interrupt (RESET) asynchronous interrupt generated RTC. When Deep Sleep mode, assertion RESET asynchronous interrupt causes processor transition Full mode.
Power Savings
where variables equations are: fCCLKNOM nominal core clock frequency fCCLKRED reduced core clock frequency VDDINTNOM nominal internal supply voltage VDDINTRED reduced internal supply voltage TNOM duration running fCCLKNOM TRED duration running fCCLKRED
Voltage Regulation
shown Table ADSP-BF53x Processor supports three different power domains. multiple power domains maximizes flexibility, while maintaining compliance with industry standards conventions. isolating internal logic ADSP-BF53x Processor into power domain,
ADSP-BF53x Processor provides on-chip voltage regulator that generate processor core voltage levels (0.7V 1.2V) from external 2.25 supply. Figure shows typical external components required complete power management system. regulator controls internal logic voltage levels programmable with Voltage Regulator Control Register (VR_CTL) increments regulator also disabled bypassed user's discretion.
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VDDEXT 2.25V 3.6V INPUT VOLTAGE RANGE
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DYNAMI MODIFICATION ON-THE-FLY
DYNAMIC MODI CATION REQUIRES SEQUENCING
VDDINT
ZHCS1000
CLKIN
NDS8434
1:15
CCLK
SCLK
VROUT1-0
SCLK CCLK SCLK
EXTERNAL COMPONENTS NOTE: VROUT1-0 SHOULD TIED TOGETHER EXTERNALLY
Figure Frequency Modification Methods
Figure Voltage Regulator Circuit Clock Signals
ADSP-BF53x Processor clocked external crystal, sine wave input, buffered, shaped clock derived from external clock oscillator. external clock used, should compatible signal must halted, changed, operated below specified frequency during normal operation. This signal connected processor's CLKIN pin. When external clock used, XTAL must left unconnected. Alternatively, because ADSP-BF53x Processor includes on-chip oscillator circuit, external crystal used. crystal should connected across CLKIN XTAL pins, with capacitors connected shown Figure Capacitor values dependent crystal type should specified crystal manufacturer. parallelresonant, fundamental frequency, microprocessor-grade crystal should used.
on-chip peripherals clocked system clock (SCLK). system clock frequency programmable means SSEL3-0 bits PLL_DIV register. values programmed into SSEL fields define divide ratio between output (VCO) system clock. SCLK divider values through Table illustrates typical system clock ratios:
Table Example System Clock Ratios Signal Name SSEL3-0 Divider Ratio VCO/SCLK Example Frequency Ratios (MHz) SCLK
0001 0110 1010
10:1
maximum frequency system clock fSCLK. Note that divisor ratio must chosen limit system clock frequency maximum fSCLK. SSEL value changed dynamically without lock latencies writing appropriate values divisor register (PLL_DIV). core clock (CCLK) frequency also dynamically changed means CSEL1-0 bits PLL_DIV register. Supported CCLK divider ratios shown Table This programmable core clock capability useful fast core frequency modifications.
Table Core Clock Ratios Signal Name CSEL1-0 Divider Ratio VCO/CCLK Example Frequency Ratios CCLK
CLKIN
XTAL
CLKOUT
Figure External Crystal Connections
shown Figure page core clock (CCLK) system peripheral clock (SCLK) derived from input clock (CLKIN) signal. on-chip capable multiplying CLKIN signal user programmable multiplication factor (bounded specified minimum maximum frequencies). default multiplier 10x, modified software instruction sequence. On-the-fly frequency changes effected simply writing PLL_DIV register.
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Booting Modes
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ADSP-BF53x Processor three mechanisms (listed Table automatically loading internal instruction memory after reset. fourth mode provided execute from external memory, bypassing boot sequence.
Table Booting Modes BMODE1-0 Description
augment boot modes, secondary software loader provided that adds additional booting mechanisms. This secondary loader provides capability boot from 16-bit FLASH memory, fast FLASH, variable baud rate, other sources.
Instruction Description
Execute from 16-bit external memory (Bypass Boot ROM) Boot from 8-bit flash Boot from serial (8-bit address range) Boot from serial (16-bit address range)
BMODE pins Reset Configuration Register, sampled during power-on resets software-initiated resets, implement following modes: Execute from 16-bit external memory Execution starts from address 0x2000 0000 with 16-bit packing. boot bypassed this mode. configuration settings slowest device possible (3-cycle hold time; 15-cycle access times; 4-cycle setup). Boot from 8-bit external FLASH memory 8-bit FLASH boot routine located boot memory space using Asynchronous Memory Bank configuration settings slowest device possible (3-cycle hold time; 15-cycle access times; 4-cycle setup). Boot from serial EEPROM (8-bit addressable) uses output select single EPROM device, submits read command address 0x00, begins clocking data into beginning instruction memory. 8-bit addressable SPI-compatible EPROM must used. Boot from serial EEPROM (16-bit addressable) uses output select single EPROM device, submits read command address 0x0000, begins clocking data into beginning instruction memory. 16-bit addressable SPI-compatible EPROM must used. each boot modes, 10-byte header first read from external memory device. header specifies number bytes transferred memory destination address. Multiple memory blocks loaded boot sequence. Once blocks loaded, program execution commences from start instruction SRAM. addition, Reset Configuration Register application code bypass normal boot sequence during software reset. this case, processor jumps directly beginning instruction memory. REV.
Blackfin processor family assembly language instruction employs algebraic syntax designed ease coding readability. instructions have been specifically tuned provide flexible, densely encoded instruction that compiles very small final memory size. instruction also provides fully featured multifunction instructions that allow programmer many processor core resources single instruction. Coupled with many features more often seen microcontrollers, this instruction very efficient when compiling source code. addition, architecture supports both user (algorithm/application code) supervisor (O/S kernel, device drivers, debuggers, ISRs) modes operation, allowing multiple levels access core processor resources. assembly language, which takes advantage processor's unique architecture, offers following advantages: Seamlessly integrated DSP/CPU features optimized both 8-bit 16-bit operations. multi-issue load/store modified-Harvard architecture, which supports 16-bit four 8-bit load/store pointer updates cycle. registers, I/O, memory mapped into unified byte memory space, providing simplified programming model. Microcontroller features, such arbitrary bitfield manipulation, insertion, extraction; integer operations 16-, 32-bit data-types; separate user supervisor stack pointers. Code density enhancements, which include intermixing 32-bit instructions mode switching, code segregation). Frequently used instructions encoded bits.
Development Tools
ADSP-BF53x Processor supported with complete CROSSCOREsoftware hardware development tools, including Analog Devices emulators VisualDSP++development environment. same emulator hardware that supports other Blackfin DSPs also fully emulates ADSPBF53x Processor. VisualDSP++ project management environment lets programmers develop debug application. This environment includes easy assembler (which based algebraic syntax), archiver (librarian/library builder), linker, loader, cycle-accurate instruction-level simulator, C/C++ compiler, C/C++ runtime library that includes mathematical functions. point these tools C/C++ code efficiency. compiler been developed efficient transla13
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tion C/C++ code processor assembly. processor architectural features that improve efficiency compiled C/C++ code. VisualDSP++ debugger number important features. Data visualization enhanced plotting package that offers significant level flexibility. This graphical representation user data enables programmer quickly determine performance algorithm. algorithms grow complexity, this capability have increasing significance designer's development schedule, increasing productivity. Statistical profiling enables programmer intrusively poll processor running program. This feature, unique VisualDSP++, enables software developer passively gather important code execution metrics without interrupting realtime characteristics program. Essentially, developer identify bottlenecks software quickly efficiently. using profiler, programmer focus those areas program that impact performance take corrective action. Debugging both C/C++ assembly programs with VisualDSP++ debugger, programmers can: View mixed C/C++ assembly code (interleaved source object information). Insert breakpoints. conditional breakpoints registers, memory, stacks. Trace instruction execution. Perform linear statistical profiling program execution. Fill, dump, graphically plot contents memory. Perform source level debugging. Create custom debugger windows. VisualDSP++ IDDE lets programmers define manage software development. dialog boxes property pages programmers configure manage Blackfin development tools, including color syntax highlighting VisualDSP++ editor. This capability permits programmers Control development tools process inputs generate outputs. Maintain one-to-one correspondence with tool's command line switches. VisualDSP++ Kernel (VDK) incorporates scheduling resource management tailored specifically address memory timing constraints programming. These capabilities enable engineers develop code more effectively, eliminating need start from very beginning, when developing application code. features include Threads, Critical Unscheduled regions, Semaphores, Events, Device flags. also supports Priority-based, Preemptive, Cooperative, Time-Sliced scheduling approaches. addition, designed scalable. application does specific feature, support code that feature excluded from target system.
Because library, developer decide whether not. integrated into VisualDSP++ development environment, also used standard command line tools. When used, development environment assists developer with many error-prone tasks assists managing system resources, automating generation various based objects, visualizing system state, when debugging application that uses VDK. VCSE Analog Devices technology creating, using, reusing software components (independent modules substantial functionality) quickly reliably assemble software applications. Download components from drop them into application. Publish component archives from within VisualDSP++. VCSE supports component implementation C/C++ assembly language. Expert Linker visually manipulate placement code data embedded system. View memory utilization color-coded graphical form, easily move code data different areas processor external memory with drag mouse, examine time stack heap usage. Expert Linker fully compatible with existing Linker Definition File (LDF), allowing developer move between graphical textual environments. Analog Devices emulators IEEE 1149.1 JTAG Test Access Port ADSP-BF53x Processor processor monitor control target board processor during emulation. emulator provides full speed emulation, allowing inspection modification memory, registers, processor stacks. intrusive in-circuit emulation assured processor's JTAG interface-the emulator does affect target system loading timing. addition software hardware development tools available from Analog Devices, third parties provide wide range tools supporting Blackfin processor family. Hardware tools include Blackfin processor plug-in cards. Third party software tools include libraries, real-time operating systems, block diagram design tools.
Designing Emulator-Compatible Processor Board (Target)
Analog Devices family emulators tools that every system developer needs test debug hardware software systems. Analog Devices supplied IEEE 1149.1 JTAG Test Access Port (TAP) each JTAG processor. emulator uses access internal features processor, allowing developer load code, breakpoints, observe variables, observe memory, examine registers. processor must halted send data commands, once operation been completed emulator, processor system running full speed with impact system timing. these emulators, target board must include header that connects processor's JTAG port emulator.
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details target board design issues including mechanical layout, single processor connections, multiprocessor scan chains, signal buffering, signal termination, emulator logic, EE-68: Analog Devices JTAG Emulation Technical Reference Analog Devices site (www.analog.com)-use site search "EE-68." This document updated regularly keep pace with improvements emulator support.
Table Descriptions Name Function
DESCRIPTIONS
ADSP-BF53x Processor definitions listed Table order maintain maximum functionality reduce package size count, some pins have dual, multiplexed functionality. cases where functionality reconfigurable, default state shown plain text, while alternate functionality shown italics.
Memory Interface ADDR19-1 DATA15-0 ABE1-0/SDQM1-0 Asynchronous Memory Control AMS3-0 ARDY2 Synchronous Memory Control SRAS SCAS SCKE CLKOUT SA10 Timers TMR0 TMR1/PPI_FS1 TMR2/PPI_FS2
Address Async/Sync Access Data Async/Sync Access Byte Enables/Data Masks Async/Sync Access Request Grant Grant Hang Bank Select Hardware Ready Control Output Enable Read Enable Write Enable Address Strobe Column Address Strobe Write Enable Clock Enable Clock Output Bank Select Timer Timer 1/PPI Frame Sync1 Timer 2/PPI Frame Sync2
Parallel Peripheral Interface Port/GPIO PF0/SPISS Programmable Flag 0/SPI Slave Select Input PF1/SPISEL1/TMRCLK Programmable Flag 1/SPI Slave Select Enable 1/External Timer Reference PF2/SPISEL2 Programmable Flag 2/SPI Slave Select Enable PF3/SPISEL3/PPI_FS3 Programmable Flag 3/SPI Slave Select Enable 3/PPI Frame Sync PF4/SPISEL4/PPI15 Programmable Flag 4/SPI Slave Select Enable PF5/SPISEL5/PPI14 Programmable Flag 5/SPI Slave Select Enable PF6/SPISEL6/PPI13 Programmable Flag 6/SPI Slave Select Enable PF7/SPISEL7/PPI12 Programmable Flag 7/SPI Slave Select Enable PF8/PPI11 Programmable Flag 8/PPI PF9/PPI10 Programmable Flag 9/PPI PF10/PPI9 Programmable Flag 10/PPI PF11/PPI8 Programmable Flag 11/PPI PF12/PPI7 Programmable Flag 12/PPI PF13/PPI6 Programmable Flag 13/PPI PF14/PPI5 Programmable Flag 14/PPI PF15/PPI4 Programmable Flag 15/PPI
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Table Descriptions (Continued) Function
PPI3-0 PPI_CLK Serial Ports RSCLK0 RFS0 DR0PRI DR0SEC TSCLK0 TFS0 DT0PRI DT0SEC RSCLK1 RFS1 DR1PRI DR1SEC TSCLK1 TFS1 DT1PRI DT1SEC Port MOSI MISO UART Port Real Time Clock RTXI2 RTXO JTAG Port TRST Clock CLKIN XTAL Mode Controls RESET NMI2 BMODE1-0 Voltage Regulator VROUT1-0
PPI3-0 Clock SPORT0 Receive Serial Clock SPORT0 Receive Frame Sync SPORT0 Receive Data Primary SPORT0 Receive Data Secondary SPORT0 Transmit Serial Clock SPORT0 Transmit Frame Sync SPORT0 Transmit Data Primary SPORT0 Transmit Data Secondary SPORT1 Receive Serial Clock SPORT1 Receive Frame Sync SPORT1 Receive Data Primary SPORT1 Receive Data Secondary SPORT1 Transmit Serial Clock SPORT1 Transmit Frame Sync SPORT1 Transmit Data Primary SPORT1 Transmit Data Secondary Master Slave Master Slave Clock UART Receive UART Transmit Crystal Input Crystal Output JTAG Clock JTAG Serial Data JTAG Serial Data JTAG Mode Select JTAG Reset Emulation Output Clock/Crystal Input Crystal Output Reset Non-maskable Interrupt Boot Mode Strap External Drive
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Table Descriptions (Continued) Function
Supplies VDDEXT VDDINT VDDRTC
Power Supply Core Power Supply Real Time Clock Power Supply External Ground
This should always pulled HIGH when used. This should always pulled when used.
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SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
Parameter Parameter Minimum Nominal Maximum Unit
VDDINT VDDEXT VDDRTC TAMBIENT
Internal Supply Voltage External Supply Voltage Real Time Clock Power Supply Voltage High Level Input Voltage2, VDDEXT =maximum Level Input Voltage2, VDDEXT =minimum Ambient Operating Temperature Industrial Commercial
2.25 2.25 -0.3
1.26
Specifications subject change without notice. ADSP-BF53x Processor tolerant (always accepts maximum VIH), voltage compliance outputs, VOH) depends input VDDEXT, because (maximum) approximately equals VDDEXT (maximum). This tolerance applies bi-directional pins (DATA15-0, TMR2-0, PF15-0, PPI3-0, RSCLK1-0, TSCLK1-0, RFS1-0, TFS1-0, MOSI, MISO, SCK) input only pins (BR, ARDY, PPI_CLK, DR0PRI, DR0SEC, DR1PRI, DR1SEC, RTXI, TCK, TDI, TMS, TRST, CLKIN, RESET, NMI, BMODE1-0).
ELECTRICAL CHARACTERISTICS
Parameter1 Test Conditions Minimum Maximum Unit
IOZH IOZL
High Level Output Voltage
Level Output Voltage2 High Level Input Current3 Level Input Current4 Three-State Leakage Current4 Three-State Leakage Current5 Input Capacitance5,
VDDEXT =3.0V, -0.5 VDDEXT =3.0V, VDDEXT =maximum, maximum VDDEXT =maximum, VDDEXT maximum, maximum VDDEXT maximum, MHz, TCASE 25°C,
Specifications subject change without notice. Applies output bidirectional pins. Applies input pins. Applies three-statable pins. Applies signal pins. Guaranteed, tested.
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ABSOLUTE MAXIMUM RATINGS
Internal (Core) Supply Voltage1 (VDDINT) -0.3 +1.5 External (I/O) Supply Voltage1 (VDDEXT) -0.3 +4.0 Input Voltage1 -0.5 Output Voltage Swing1 -0.5 VDDEXT +0.5 Load Capacitance1,2 .200 Core Clock (CCLK)1 ADSP-BF533 ADSP-BF532/BF531. Peripheral Clock (SCLK)1 Storage Temperature Range1 Lead Temperature seconds)1
Stresses greater than those listed above cause permanent damage device. These stress ratings only. Functional operation device these other conditions greater than those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability. proper SDRAM controller operation, maximum load capacitance 3.3V) 2.5V) ADDR, DATA, ABE/SDQM, CLKOUT, SCKE, SA10, SRAS, SCAS, SWE, SMS.
SENSITIVITY
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although ADSP-BF53x Processor features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
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Table Table describe timing requirements ADSP-BF53x Processor clocks. Take care selecting MSEL, SSEL, CSEL ratios exceed maximum core clock, system clock Voltage Controlled Oscillator (VCO) operating frequencies, described ABSOLUTE MAXIMUM RATINGS. Table describes Phase-Locked Loop operating conditions.
Table Core System Clock Requirements-ADSP-BF533 Parameter Minimum Maximum Unit
tCCLK1.2 tCCLK1.1 tCCLK1.0 tCCLK0.9 tCCLK0.8 tCCLK0.7 tSCLK
Core Cycle Period (VDDINT =1.2 V-5%) Core Cycle Period (VDDINT =1.1 V-5%) Core Cycle Period (VDDINT =1.0 V-5%) Core Cycle Period (VDDINT =0.9 V-5%) Core Cycle Period (VDDINT =0.8 V-5%) Core Cycle Period (VDDINT =0.7 V-5%) System Clock Period
1.67 Maximum (7.5 tCCLKNN
Table Core System Clock Requirements-ADSP-BF532/531 Parameter Minimum Maximum Unit
tCCLK1.2 tCCLK1.1 tCCLK1.0 tCCLK0.9 tCCLK0.8 tCCLK0.7 tSCLK
Core Cycle Period (VDDINT =1.2 V-5%) Core Cycle Period (VDDINT =1.1 V-5%) Core Cycle Period (VDDINT =1.0 V-5%) Core Cycle Period (VDDINT =0.9 V-5%) Core Cycle Period (VDDINT =0.8 V-5%) Core Cycle Period (VDDINT =0.7 V-5%) System Clock Period
Maximum (7.5 tCCLKNN
Table Phase-Locked Loop Operating Conditions Parameter Minimum Maximum Unit
Voltage Controlled Oscillator (VCO) Frequency
Maximum CCLK
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Clock Reset Timing
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Table Figure describe clock reset operations. ABSOLUTE MAXIMUM RATINGS Page combinations CLKIN clock multipliers must select core/peripheral clocks excess 600/133 MHz.
Table Clock Reset Timing Parameter Minimum Maximum Unit
Timing Requirements tCKIN CLKIN Period CLKIN Pulse1 tCKINL tCKINH CLKIN High Pulse1 RESET Asserted Pulsewidth Low2 tWRST Switching Characteristics CLKOUT Period3 tSCLK
30.0 10.0 10.0 tCKIN
100.0
Applies bypass mode non-bypass mode. Applies after power-up sequence complete. power-up, processor's internal phase-locked loop requires more than 2000 CLKIN cycles, while RESET asserted, assuming stable power supplies CLKIN (not including start-up time external clock oscillator). figure below shows ratio between tCKIN tSCLK, ratio many programmable options. more information, System Design chapter ADSP-BF533 Processor Hardware Reference.
tCKIN
CLKIN
tCKINL
RESET
tCKINH tWRST
tSCLKD
CLKOUT
tSCLK
Figure Clock Reset Timing
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Asynchronous Memory Read Cycle Timing Table Asynchronous Memory Read Cycle Timing Parameter Minimum Maximum Unit
Timing Requirements tSDAT DATA15-0 Setup Before CLKOUT tHDAT DATA15-0 Hold After CLKOUT tSARDY ARDY Setup Before CLKOUT tHARDY ARDY Hold After CLKOUT Switching Characteristic Output Delay After CLKOUT1 Output Hold After CLKOUT
Output pins include AMS3-0, ABE1-0, ADDR19-1, AOE, ARE.
SETUP CYCLES
PROGRAMMED READ ACCESS CYCLES
ACCESS EXTENDED CYCLES
HOLD CYCLE
CLKOUT
AMSx
ABE1-0 ADDR19-1
ADDRESS
tSDAT tHDAT
DATA15-0 READ
tSARDY
ARDY
tHARDY
tHARDY
Figure Asynchronous Memory Read Cycle Timing
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Asynchronous Memory Write Cycle Timing Table Asynchronous Memory Write Cycle Timing Parameter Minimum Maximum Unit
Timing Requirements tSARDY ARDY Setup Before CLKOUT ARDY Hold After CLKOUT tHARDY tDDAT DATA15-0 Disable After CLKOUT tENDAT DATA15-0 Enable After CLKOUT Switching Characteristic Output Delay After CLKOUT1 Output Hold After CLKOUT
Output pins include AMS3-0, ABE1-0, ADDR19-1, DATA15-0, AOE, AWE.
SETUP CYCLES
PROGRAMMED WRITE ACCESS CYCLES
ACCESS EXTENDED CYCLE
HOLD CYCLE
CLKOUT
AMSx
ABE1-0 ADDR19-1
ADDRESS
tENDAT
DATA15-0 WRITE DATA
tDDAT
tSARDY
ARDY
tHARDY
Figure Asynchronous Memory Write Cycle Timing
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SDRAM Interface Timing Table SDRAM Interface Timing Parameter Minimum Maximum Unit
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Timing Requirement tSSDAT DATA Setup Before CLKOUT DATA Hold After CLKOUT tHSDAT Switching Characteristic CLKOUT Period tSCLK tSCLKH CLKOUT Width High CLKOUT Width tSCLKL tDCAD Command, ADDR, Data Delay After CLKOUT1 tHCAD Command, ADDR, Data Hold After CLKOUT1 tDSDAT Data Disable After CLKOUT Data Enable After CLKOUT tENSDAT
Command pins include: SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
tSCLK
CLKOUT
tSCLKH
SSDAT tHSDAT
DATA (IN)
SCLKL
DCAD tENSDAT
DATA(OUT)
tHCAD
tDCAD
CMND ADDR (OUT)
tHCAD
NOTE: COMMAND SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
Figure SDRAM Interface Timing
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External Port Request Grant Cycle Timing
Table Figure describe external port request grant operations.
Table External Port Request Grant Cycle Timing Parameter, Minimum Maximum Unit
Timing Requirements asserted CLKOUT high setup CLKOUT high de-asserted hold time Switching Characteristics CLKOUT high xMS, address, RD/WR disable CLKOUT xMS, address, RD/WR enable tDBG CLKOUT high asserted setup tEBG CLKOUT high de-asserted hold time tDBH CLKOUT high asserted setup CLKOUT high de-asserted hold time tEBH
These preliminary timing parameters that based worst-case operating conditions. loads these timing parameters
CLKOUT
AMSx
ADDR19-1 ABE1-0
tDBG
tEBG
tDBH
tEBH
Figure External Port Request Grant Cycle Timing
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Parallel Peripheral Interface Timing
Table Figure page Figure page Figure page describe Parallel Peripheral Interface operations.
Table Parallel Peripheral Interface Timing Parameter Minimum Maximum Unit
Timing Requirements tPCLKW PPI_CLK Width Frame Capture Input Modes Output Mode PPI_CLK Period1 tPCLK Frame Capture Input Modes Output Mode Timing Requirements Input Frame Capture Modes tSDRE Receive Data Setup Before PPI_CLK2 tHDRE Receive Data Hold After PPI_CLK2 Input Delay After PPI_CLK tIDFSE Delay Between Assertion Valid Data (Input Mode) tIFS1D Switching Characteristics Output Frame Capture Modes Output Delay After PPI_CLK3 tODFSE tDDTE Transmit Data Delay After PPI_CLK3 Output Mode) Transmit Data Hold After PPI_CLK3 tHDTE tOFS1D Delay Between Assertion Valid Data Delay Between Assertion4 tFS12
10.0 15.0 25.0 65535 12.0 12.0
PPI_CLK periods PPI_CLK periods PPI_CLK periods
65536
PPI_CLK frequency cannot exceed fSCLK/2 Referenced sample edge. Referenced drive edge. period must integer multiple period.
I_CLK
PPI_
MENT ELEM
CLOCK FRAME OLARI PROGRAM MABLE. PPI_ DELAY THIS ELEM FIRST DATA WORD FRAMED PI_FS BELONGS VIOUS FRAM
Figure Output Mode Frame Capture Timing
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ELEM ELEM ELEM
NOTE ELEM I_FS VIOU
Figure Input Timing
PPI_CLK
PPI_FS1
tFS12
PPI_FS2
PPI_FS3
Figure General Purpose Frame Capture Output Mode Timing
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Serial Ports Table Serial Ports-External Clock Parameter Minimum Maximum Unit
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Timing Requirements tSFSE TFS/RFS Setup Before TSCLK/RSCLK1 tHFSE TFS/RFS Hold After TSCLK/RSCLK1 tSDRE Receive Data Setup Before RSCLK1 tHDRE Receive Data Hold After RSCLK1 tSCLKEW TSCLK/RSCLK Width TSCLK/RSCLK Period tSCLKE
15.0
Referenced sample edge.
Table Serial Ports-Internal Clock Parameter Minimum Maximum Unit
Timing Requirements tSFSI TFS/RFS Setup Before TSCLK/RSCLK1 tHFSI TFS/RFS Hold After TSCLK/RSCLK1 tSDRI Receive Data Setup Before RSCLK1 tHDRI Receive Data Hold After RSCLK1 tSCLKEW TSCLK/RSCLK Width tSCLKE TSCLK/RSCLK Period
15.0
Referenced sample edge.
Table Serial Ports-External Clock Parameter Minimum Maximum Unit
Switching Characteristics tDFSE TFS/RFS Delay After TSCLK/RSCLK (Internally Generated TFS/RFS)1 tHOFSE TFS/RFS Hold After TSCLK/RSCLK (Internally Generated TFS/RFS)1 tDDTE Transmit Data Delay After TSCLK1 tHDTE Transmit Data Hold After TSCLK1
10.0 10.0
Referenced drive edge.
Table Serial Ports-Internal Clock Parameter Minimum Maximum Unit
Switching Characteristics TFS/RFS Delay After TSCLK/RSCLK (Internally Generated TFS/RFS)1 tDFSI tHOFSI TFS/RFS Hold After TSCLK/RSCLK (Internally Generated TFS/RFS)1 Transmit Data Delay After TSCLK1 tDDTI Transmit Data Hold After TSCLK1 tHDTI tSCLKIW TSCLK/RSCLK Width
Referenced drive edge.
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Parameter
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Maximum Unit
Table Serial Ports-Enable Three-State Minimum
Switching Characteristics Data Enable Delay from External TSCLK1 tDTENE tDDTTE Data Disable Delay from External TSCLK1 tDTENI Data Enable Delay from Internal TSCLK tDDTTI Data Disable Delay from Internal TSCLK1
12.0
Referenced drive edge.
Table External Late Frame Sync Parameter Minimum Maximum Unit
Switching Characteristics tDDTLFSE Data Delay from Late External External with 01,2 tDTENLFSE Data Enable from late 01,2
10.5
enable valid follow tDDTENFS tDDTLFSE. external RFS/TFS setup RSCLK/TSCLK tSCLKE/2 then tDDTLSCK tDTENLSCK apply, otherwise tDDTLFSE tDTENLFS apply.
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DATA RECEIVE- INTERNAL CLOCK DRIVE EDGE SAMPLE EDGE
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SAMPLE EDGE
DATA RECEIVE- EXTERNAL CLOCK DRIVE EDGE
tSCLKIW
RSCLK RSCLK
tSCLKEW
tDFSE tHOFSE
tDFSE tSFSI tHFSI
tHOFSE
tSFSE
tHFSE
tSDRI
tHDRI
tSDRE
tHDRE
NOTE: EITHER RISING EDGE FALLING EDGE RCLK, TCLK USED ACTIVE SAMPLING EDGE. DATA TRANSMIT- INTERNAL CLOCK DRIVE EDGE SAMPLE EDGE DATA TRANSMIT- EXTERNAL CLOCK DRIVE EDGE SAMPLE EDGE
tSCLKIW
TSCLK TSCLK
tSCLKEW
tDFSI tHOFSI
tDFSE tSFSI tHFSI
tHOFSE
tSFSE
tHFSE
tDDTI tHDTI
tDDTE tHDTE
NOTE: EITHER RISING EDGE FALLING EDGE RCLK TCLK USED ACTIVE SAMPLING EDGE. DRIVE EDGE TSCLK (EXT) ("LATE", EXT.) TSCLK RSCLK DRIVE EDGE
tDDTEN
DRIVE EDGE TSCLK (INT) ("LATE", INT.) TSCLK RSCLK DRIVE EDGE
tDDTTE
tDDTIN
tDDTTI
Figure Serial Ports
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EXTERNAL WITH
DRIVE RSCLK
SAMPLE
DRIVE
tSFSE/I
tHOFSE/I
tDDTE/I tDDTENFS
tHDTE/I
tDDTLFSE
LATE EXTERNAL
DRIVE TSCLK
SAMPLE
DRIVE
tSFSE/I
tHOFSE/I
tDDTE/I tDDTENFS
tHDTE/I
tDDTLFSE
Figure External Late Frame Sync (Frame Sync Setup tSCLKE/2)
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EXTERNAL WITH MCE=1, MFD=0 DRIVE SAMPLE DRIVE
RSCLK
tSFSE/I
tHOFSE/I
tDDTE/I tDTENLSCK
tHDTE/I
tDDTLSCK
LATE EXTERNAL DRIVE SAMPLE DRIVE
TSCLK
tSFSE/I
tHOFSE/I
tDDTE/I tDTENLSCK
tHDTE/I
tDDTLSCK
Figure External Late Frame Sync (Frame Sync Setup tSCLKE/2)
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Serial Peripheral Interface (SPI) Port-Master Timing
Table Figure describe port master operations.
Table Serial Peripheral Interface (SPI) Port-Master Timing Parameter Minimum Maximum Unit
Timing Requirements tSSPID Data input valid edge (data input setup) tHSPID sampling edge data input invalid Switching Characteristics tSDSCIM SPISELx first edge (x=0 tSPICHM Serial clock high period tSPICLM Serial clock period tSPICLK Serial clock period Last edge SPISELx high (x=0 tHDSM Sequential transfer delay tSPITDM tDDSPID edge data valid (data delay) tHDSPID edge data invalid (data hold)
2tSCLK-1.5 2tSCLK-1.5 2tSCLK-1.5 4tSCLK-1.5 2tSCLK-1.5 2tSCLK-1.5
SPISELx (OUTPUT)
tSDSCIM
(CPOL (OUTPUT)
tSPICHM
tSPICLM
tSPICLK
tHDSM
tSPITDM
tSPICLM
(CPOL (OUTPUT)
tSPICHM
tDDSPID
MOSI (OUTPUT) CPHA=1 MISO (INPUT)
tHDSPID
tSSPID
VALID
tHSPID
tSSPID
VALID
tHSPID
tDDSPID
MOSI (OUTPUT) CPHA=0 MISO (INPUT)
tHDSPID
tSSPID
VALID
tHSPID
VALID
Figure Serial Peripheral Interface (SPI) Port-Master Timing
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Serial Peripheral Interface (SPI) Port-Slave Timing
Table Figure describe port slave operations.
Table Serial Peripheral Interface (SPI) Port-Slave Timing Parameter Minimum Maximum Unit
Timing Requirements tSPICHS Serial clock high period tSPICLS Serial clock period tSPICLK Serial clock period Last edge SPISS asserted tHDS tSPITDS Sequential Transfer Delay SPISS assertion first edge tSDSCI tSSPID Data input valid edge (data input setup) tHSPID sampling edge data input invalid Switching Characteristics tDSOE SPISS assertion data active tDSDHI SPISS deassertion data high impedance tDDSPID edge data valid (data delay) tHDSPID edge data invalid (data hold)
2tSCLK-1.5 2tSCLK-1.5 4tSCLK-1.5 2tSCLK-1.5 2tSCLK-1.5 2tSCLK-1.5
SPISS (INPUT)
tSPICHS
(CPOL (INPUT)
tSPICLS
tSPICLK
tHDS
tSPITDS
tSDSCI
(CPOL (INPUT)
tSPICLS
tSPICHS
tDSOE
tDDSPID tHDSPID tDDSPID tDSDHI
MISO (OUTPUT) CPHA=1 MOSI (INPUT)
tSSPID
VALID
tHSPID
tSSPID
tHSPID
VALID
tDSOE
MISO (OUTPUT) CPHA=0 MOSI (INPUT)
tDDSPID
tDSDHI
tHSPID tSSPID
VALID VALID
Figure Serial Peripheral Interface (SPI) Port-Slave Timing
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Universal Asynchronous Receiver-Transmitter (UART) Port-Receive Transmit Timing
Figure describes UART port receive transmit operations. maximum baud rate SCLK/16. shown Figure there some latency between generation internal UART interrupts external data operations. These latencies negligible data transmission rates UART.
CLKOUT (SAMPLE CLOCK)
DATA(5-8) STOP
RECEIVE INTERNAL UART RECEIVE INTERRUPT
UART RECEIVE DATA STOP; CLEARED FIFO READ
START DATA(5-8) STOP (1-2)
TRANSMIT INTERNAL UART TRANSMIT INTERRUPT UART TRANSMIT PROGRAM; CLEARED WRITE TRANSMIT
Figure UART Port-Receive Transmit Timing
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Timer Cycle Timing
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Table Figure describe timer expired operations. input signal asynchronous "width capture mode" "external clock mode" absolute maximum input frequency fSCLK/2 MHz.
Table Timer Cycle Timing Parameter Minimum Maximum Unit
Timing Characteristics Timer Pulsewidth Input Low1 Timer Pulsewidth Input High1 Switching Characteristic tHTO Timer Pulsewidth Output2
(232-1)
SCLK cycles SCLK cycles SCLK cycles
minimum pulsewidths apply TMRx input pins width capture external clock modes. They also apply PPI_CLK input pins output mode. minimum time tHTO cycle, maximum time tHTO equals (232-1) cycles.
CLKOUT
tHTO
TMRx (PWM OUTPUT MODE)
TMRx (WIDTH CAPTURE EXTERNAL CLOCK MODES)
Figure Timer PWM_OUT Cycle Timing
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Programmable Flags Cycle Timing
Table Figure describe programmable flag operations.
Table Programmable Flags Cycle Timing Parameter Minimum Maximum Unit
Timing Requirement tWFI Flag input pulsewidth Switching Characteristic tDFO Flag output delay from CLKOUT
tSCLK
CLKOUT
tDFO
(OUTPUT) FLAG OUTPUT
tWFI
(INPUT) FLAG INPUT
Figure Programmable Flags Cycle Timing
REV.
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Table JTAG Port Timing Parameter Minimum Maximum Unit
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JTAG Test Emulation Port Timing
Table Figure describe JTAG port operations.
Timing Parameters tTCK Period tSTAP TDI, Setup Before High tHTAP TDI, Hold After High System Inputs Setup Before Low1 tSSYS tHSYS System Inputs Hold After Low1 TRST Pulsewidth2 tTRSTW Switching Characteristics Delay from tDTDO tDSYS System Outputs Delay After Low3
cycles
System Inputs=DATA15-0, ARDY, TMR2-0, PF15-0, PPI_CLK, RSCLK0-1, RFS0-1, DR0PRI, DR0SEC, TSCLK0-1, TFS0-1, DR1PRI, DR1SEC, MOSI, MISO, SCK, RESET, NMI, BMODE1-0, PP3-0. Maximum System Outputs=DATA15-0, ADDR19-1, ABE1-0, AOE, ARE, AWE, AMS3-0, SRAS, SCAS, SWE, SCKE, CLKOUT, SA10, SMS, TMR2-0, PF150, RSCLK0-1, RFS0-1, TSCLK0-1, TFS0-1, DT0PRI, DT0SEC, DT1PRI, DT1SEC, MOSI, MISO, SCK, BGH, PPI3-0.
tTCK
tSTAP
tHTAP
tDTDO
tSSYS
SYSTEM INPUTS
tHSYS
tDSYS
SYSTEM OUTPUTS
Figure JTAG Port Timing
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160-LEAD PINOUT
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Table lists pinout signal name. Table Page lists pinout lead number.
Table 160-Lead Lead Assignment (Alphabetically Signal) Signal Lead Number Signal Lead Number Signal Lead Number Signal Lead Number
ABE0 ABE1 ADDR1 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 ADDR17 ADDR18 ADDR19 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 AMS0 AMS1 AMS2 AMS3 ARDY BMODE0 BMODE1 CLKIN CLKOUT DATA0 DATA1 DATA10 DATA11
DATA12 DATA13 DATA14 DATA15 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DR0PRI DR0SEC DR1PRI DR1SEC DT0PRI DT0SEC DT1PRI DT1SEC
MISO MOSI PF10 PF11 PF12 PF13 PF14 PF15 PPI0 PPI1 PPI2 PPI3 PPI_CLK RESET RFS0 RFS1 RSCLK0 RSCLK1 RTXI RTXO SA10 SCAS
SCKE SRAS TFS0 TFS1 TMR0 TMR1 TMR2 TRST TSCLK0 TSCLK1 VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDEXT VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT VDDRTC VROUT0 VROUT1 XTAL
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Lead Number Signal
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Lead Number Signal
Table 160-Lead Lead Assignment (Numerically Lead Number) Lead Number Signal Lead Number Signal
VDDEXT PF10 PF11 PF14 PPI2 RTXO RTXI XTAL CLKIN VROUT0 PF12 PF13 PPI3 PPI1 VDDRTC VROUT1 SCKE CLKOUT PF15 VDDEXT PPI0 PPI_CLK RESET VDDEXT
SCAS MOSI VDDEXT VDDINT VDDEXT SRAS TFS1 MISO DT1SEC VDDINT VDDINT SA10 ARDY AMS0 TSCLK1 DT1PRI DR1SEC VDDEXT AMS2 AMS1 RSCLK1 RFS1 DR1PRI VDDEXT AMS3
DT0PRI DT0SEC TFS0 ABE1 ABE0 TSCLK0 DR0SEC RFS0 VDDEXT VDDINT VDDEXT ADDR4 ADDR1 DR0PRI TMR2 ADDR7 ADDR5 ADDR2 RSCLK0 TMR0 VDDINT VDDEXT VDDINT VDDEXT ADDR8 ADDR6 ADDR3 TMR1
DATA12 DATA9 DATA6 DATA3 DATA0 ADDR15 ADDR9 ADDR10 ADDR11 TRST BMODE0 DATA13 DATA10 DATA7 DATA4 DATA1 ADDR16 ADDR14 ADDR13 ADDR12 VDDEXT BMODE1 DATA15 DATA14 DATA11 DATA8 DATA5 DATA2 ADDR19 ADDR18 ADDR17
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KEY: VDDINT VDDEXT
VDDRTC VROUT
Figure 160-Ball Metric Configuration (Top View)
KEY: VDDINT VDDEXT
VDDRTC VROUT
Figure 160-Ball Metric Configuration (Bottom View)
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OUTLINE DIMENSIONS
Dimensions outline dimension figure Page shown millimeters.
160-Lead Metric Plastic Ball Grid Array (mini-BGA) (BC-160)
12.00
CORNER INDEX AREA
BALL INDICATOR 10.40
VIEW
0.80 BALL PITCH BOTTOM VIEW 0.85
1.70
DETAIL
SEATING PLANE 0.40 (NOTE NOTES DIMENSIONS MILLIMETERS. COMPLIES WITH JEDEC REGISTERED OUTLINE MO-205, VARIATION MINIMUM BALL HEIGHT 0.25.
0.12 0.55 0.50 COPLANARITY 0.45 BALL DIAMETER
DETAIL
176-LEAD LQFP (ST-176-1)
26.00 24.00
0.75 0.60 0.45
0.27 0.22 0.17
SEATING PLANE 0.08 LEAD COPLANARITY 0.15 0.05
1.45 1.40 1.35 1.60
DETAIL
0.50 LEAD PITCH VIEW (PINS DOWN)
DETAIL
NOTES: DIMENSIONS MILLIMETERS. ACTUAL POSITION EACH LEAD WITHIN 0.08 IDEAL POSITION, WHEN MEASURED LATERAL DIRECTION. CENTER DIMENSIONS NOMINAL.
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Table Part Number Ambient Temperature Range Maximum Instruction Rate Operating Voltage
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ADSP-BF53x
ORDERING GUIDE
ADSP-BF533SKBC-600 ADSP-BF533SBBC-500 ADSP-BF532SBBC-400 ADSP-BF532SBST-300 ADSP-BF531SBBC-400 ADSP-BF531SBST-300
internal, internal, internal, internal, internal, internal,
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