L64733/34 chipset designed specifically meet needs satellite broadcast
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L64733/L64734 Tuner Satellite Receiver Chipset
L64733/34 chipset designed specifically meet needs satellite broadcast digital compliant with European digital video broadcast (DVB-S) standard technical specifications systems. chipset forms complete "L-Band bits" system. typical application L64733/34 chipset satellite digital reception accordance with 421. Figure shows L64733/34 chipset satellite receiver implemented typical satellite receiver set-top decoder box. Figure Block Diagram Set-Top Decoder Using L64733/34 Chipset
Optional DRAM 256K L64733/L64734 Chipset Satellite (Loop Through) L64733 L64734 [7:0] Optional Decryption Engine
Transport Demux
High-Speed Port
Microprocessor Data Address
VCXO
Microprocessor
Audio Oversampling Clock
NTSC S-Video L-Speaker R-Speaker
NTSC Encoder
CCIR601VIDEO
Audio/Video Decoder Audio/Video SDRAM 256K 256K
Audio
AUDIO
64/32
L64733/34 chipset consists L64734 Satellite Receiver L64733 Tuner on-chip synthesizer. Figure shows simplified block diagram this chipset.
August 2000
Copyright 1999, 2000 Logic Corporation. rights reserved.
Figure
Select Input Output
L64733/34 Simplified Block Diagram
L64733
Switch Synthesizer, Mixer, DownConverter
Baseband Filter
Control Signals Control Modules Synthesizer Filter
IOUT
QOUT
L64734
Dual
Demodulator
Host Microcontroller
Microcontroller Interface
Error Correction
Descrambler
MPEG Output
L64734:
generates control signals L64733 synthesizer, using frequency information programmed into L64734 configuration registers controls programming low-pass filters L64733 generates dual control voltages two-stage automatic gain control L64733
L64733 Tuner directly down-converts satellite signal from L-band baseband.
L64733/L64734 Tuner Satellite Receiver Chipset
Figure shows more detailed chipset block diagram. Figure Detailed Chipset Block Diagram
L64733 Xtal 4-7.26 Tank Circuit Switch Phase Detect. Charge Pump External Loop Filter
Quadrature Down-Converter
DualModulus Prescaler PSOUT
FDOUB INSEL
FLCLK
QOUT
PLLIN
AGC1
AGC2
L64734 Synthesizer Control Module Control Carrier Loop Control BPSK/QPSK Demodulator Timing Loop Control Filter Control Module
DEMI Dual Interpolator/Decimation Filter Matched Filter
Output Control
DEMQ
Microcontroller Data Address (from L64734 on-chip PLL) Decoder Pipeline External Microcontroller Interface
Microcontroller Data Address Channel Output (MPEG-2 Transport Stream)
Descrambler
ReedSolomon Decoder
Convolutional Deinterleaver
ReedSolomon Synchronizer
Viterbi Decoder
Viterbi Synchronizer
L64733/L64734 Tuner Satellite Receiver Chipset
IOUT
L64733 directly accepts L-Band signal input from satellite feed. L64733 handles fully loaded raster transponder signals from 2175 MHz. internally matched except DC-blocking capacitor, requires matching network between cable connector L64733 input pins. L64733 uses L64734 INSEL signal select appropriate function (Normal Loop-Through mode). signal goes variable gain stage, which controlled L64734 AGC1 signal. L64734 adjusts AGC1 conjunction with AGC2 maximize signal while maintaining proper levels baseband outputs (IOUT QOUT). signal then goes mixers quadrature demodulator. mixers with local oscillator signals that offset degrees from another. quadrature demodulator performs direct frequency conversion signal baseband while splitting signal into quadrature signal paths. baseband signals pass through pair variable-gain amplifiers that controlled AGC2 pin, which, turn controlled L64734. signals then filtered through pair 7th-order filters anti-aliasing. filter shape 7th-order Butterworth, followed single-pole delay equalizer. filter cut-off frequency, which controlled L64734 FLCLK signal, related baud rate. filtered baseband output signals differential output stages IOUTp, IOUTn, QOUTp QOUTn. baseband outputs L64733 L64734, where they digitized analog-to-digital converter (ADC). outputs then BPSK/QPSK demodulator, where they filtered. demodulator then sends them L64734 decoder pipeline, which outputs MPEG-2 transport stream. frequency synthesizer functionality split between L64733 L64734. Synthesizer Control Module resides L64734; generates control signals L64733 Tuner frequency synthesizer. Synthesizer Control Module also contains some programmable counters that part synthesizer feedback loop. L64733 contains many analog functions frequency synthesizer, well local oscillator crystal reference oscillator. Tuning oscillator signals generated mixers
L64733/L64734 Tuner Satellite Receiver Chipset
range from 925-2175 MHz, with step size when using 4-MHz crystal reference. on-chip tuning frequency 1088 MHz. tune channels from 925-1086 MHz, L64734 disables frequency doubler block) L64733. tune channels from 1086 2175 MHz, L64734 enables frequency doubler. requires external resonant tank circuit, which includes varactor diodes vary frequency oscillation. signal goes Prescaler block before passed L64734 differentially through PSOUTp PSOUTn pins. L64734 MODp MODn differential signals control divider ratio Prescaler block. L64734 dynamically changes divide ratio ensure that tuning step size affected divider. L64734 contains programmable counters further divide signal frequency before signal back L64733 through PLLINp PLLINn pins. crystal reference oscillator frequency divided eight, then phase detector. phase detector generates current signal proportional difference phase between PLLINp, PLLINn, divided crystal frequency. charge pump circuit (which controls pins external transistor buffer L64733 against tuning voltage generate current. current filtered, through discrete loop filter, converted tuning voltage that drives external varactor diodes tank circuit. complete frequency controlled loop formed, frequency varied changing frequency divider ratios L64734 registers. Figure page more details regarding external circuitry VCO, crystal oscillator, charge pump, tank circuitry, entire frequency-controlled loop. chipset provides maximum integration flexibility system designers minimum cost. number external components required build system minimal because synthesizer, variable rate filters, clock carrier loops integrated into devices.
L64733/L64734 Tuner Satellite Receiver Chipset
Features Benefits
System Features
Direct down-conversion Integrated programmable cut-off low-pass filters variable-rate operation Dual optimizing performance with respect intermodulation noise Integrated synthesizer Integrated quadrature amplitude phase imbalance compensation loop-through
Chipset Features
Supports system specifications BPSK/QPSK demodulation rates from Mbaud Matched filter (square root raised cosine filter with roll-off factor 35%) Anti-aliasing filters operation from Mbaud without switching external filters need low-pass filters On-chip digital clock synchronization On-chip digital carrier synchronization, featuring frequency sweep capability signal acquisition Auto-acquisition demodulator mode tuner control through on-chip microcontroller Integrated Phase-Locked Loop (PLL) clock synthesis, allowing fundamental mode crystal Fast channel switching mode Power estimation control Programmable Viterbi decoder module rates 1/2, 2/3, 3/4, 5/6, 6/7, Reed-Solomon decoder (204/188), (146/130) Auto-synchronization Viterbi decoder
L64733/L64734 Tuner Satellite Receiver Chipset
Programmable synchronization deinterleaver, Reed-Solomon decoder, descrambler error monitoring channel performance measurements Deinterleaver (DVB DSS) Serial host interface compatible with Logic Serial Control interface Power-down mode On-chip dual differential 6-bit ADCs Supports Synchronous Parallel Interface protocol data output
Chipset Interconnections
Figure shows interconnections between L64733 L64734. Figure Chipset Interconnection Diagram
L64733 PLLINp PLLINn MODp MODn FDOUB FLCLK INSEL AGC1 AGC2 CPG1 CPG2 XTLOUT PSOUTp PSOUTn IOUTp IOUTn QOUTp QOUTn PLLINp PLLINn MODp MODn FDOUB FLCLK INSEL AGC1 AGC2 XCTR[0] XCTR[1] XOIN PSOUTp PSOUTn IVINp IVINn QVINp QVINn L64734
Control Signals
Control Signals
Prescaler Signals
Prescaler Signals
Channel Data Signals
Channel Data Signals
L64733/L64734 Tuner Satellite Receiver Chipset
L64733 Signal Descriptions
This section describes L64733 signals. Figure shows interface diagram L64733. Names signals that active-LOW designated with suffix (for example, ERROROUTn). Names differential signals designated with suffix noninverting side (for example, QOUTp), with suffix inverting side (for example, QOUTn). Figure L64733 Interface Diagram
RFINn Signals RFINp RFOUT XTLn CFLT TANKn TANKp VRLO XTLp XTLOUT IOUTn IOUTp QOUTn QOUTp PSOUTn PSOUTp AGC1 AGC2 CPG1 CPG2 FDOUB FLCLK IDCn IDCp INSEL MODn MODp PLLINn PLLINp QDCn QDCp
Oscillator Signals
Control Signals
Channel Data Signals
Prescaler Signals
Charge Pump Signals
shown Figure L64733 following major interfaces:
Oscillator Control Channel Data Prescaler Charge Pump
L64733/L64734 Tuner Satellite Receiver Chipset
following signal descriptions listed according major interface groups. Within each group, signals described alphabetic order.
Signals
L64733 accept input signal loop through RFOUT. This controlled on-chip switch. RFINn, RFINp Input Input RFIN differential signals form input. Connect RFINp signal through series capacitor video connector RFINn signal through series resistor capacitor ground. RFOUT Output Output RFOUT signal output that active when INSEL input deasserted. When active, signal RFOUT copy RFIN signal.
Oscillator Signals
L64733 internal oscillators: crystal oscillator tank oscillator. CFLT Bias Voltage Bypass Bidirectional Figure page information connect CFLT pin.
TANKn, TANKp Oscillator Tank Port Input Figure page information connect TANKp TANKn pins. VRLO Local Oscillator Regulator Bypass Bidirectional Figure page information connect VRLO pin. Crystal Oscillator Port Input Connect XTLp XTLn pins shown Figure page
XTLn, XTLp
L64733/L64734 Tuner Satellite Receiver Chipset
XTLOUT
Crystal Output This signal provides buffered clock reference frequency driving L64734 XOIN pin.
Control Signals
following signals, some which generated L64734 control mode operation L64733 AGC1 Automatic Gain Control Input AGC1 signal high-impedance input from L64734; controls circuitry. AGC1 voltage range from Automatic Gain Control Input AGC2 signal high-impedance input from L64734; controls circuitry. Charge Pump Gain CPG[2:1] signals charge pump gain according following table.
Charge Pump Current (typ), CPG1 CPG2 HIGH -0.1 -0.3 -0.6 -1.8
AGC2
CPG[2:1]
Input
FDOUB
Frequency Doubler Input When FDOUB signal asserted, L64733 local oscillator frequency internally doubled mixers. When FDOUB signal deasserted, oscillator frequency doubled before being mixers. Filter Clock Input FLCLK signal low-amplitude, self-biased clock input. frequency FLCLK signal multiplied baseband filter's frequency. I-Channel Offset Correction Input Connect larger) capacitor between IDCp IDCn signals.
FLCLK
IDCn, IDCp
L64733/L64734 Tuner Satellite Receiver Chipset
INSEL
Port Input Select Input When INSEL signal asserted, L64733 normal mode. When INSEL signal deasserted, L64733 Loop-Through mode. this mode, RFIN signal looped through RFOUT signal, L64733 local oscillator shut off.
MODn, MODp Prescaler Modulus Input differential signals form PECL input that sets prescaler modulus. When MODp signal positive with respect MODn signal, prescaler modulus (divide 32). When MODn signal positive with respect MODp signal, prescaler modulus (divide 33). PLLINn, PLLINp Phase Detector Input PLLIN differential signals form phase detector input connected L64734 PLLINp PLLINn output signals. L64734 PLLINp PLLINn descriptions subsection entitled "Synthesizer Control Interface" page QDCn, QDCp Q-Channel Offset Correction Input Connect larger) capacitor between QDCp QDCn signals.
Channel Data Signals
This section describes channel data signals from L64733 L64734. IOUTn, IOUTp I-Channel Baseband Data Output IOUT differential signals form in-phase data provided L64734. QOUTn, QOUTp Q-Channel Baseband Data Output QOUT differential signals form quadrature-phase data provided L64734.
L64733/L64734 Tuner Satellite Receiver Chipset
Prescaler Signals
following signals prescaler outputs from L64733 L64734. PSOUTn, PSOUTp Prescaler Output These differential signals L64733 prescaler outputs. programmable counters L64734 clocked rising edge PSOUT signal.
Charge Pump Signals
following signals outputs from L64733 charge pump. Charge Pump Output Connect signal shown Figure page Feedback Charge Pump Transistor Drive Output Connect signal shown Figure page
L64733/L64734 Tuner Satellite Receiver Chipset
L64734 Signal Descriptions
This section provides detailed information L64734 signals. Figure shows interface diagram L64734. Figure L64734 Interface Diagram
IVINp IVINn QVINp QVINn IBYPASS[5:0] QBYPASS[5:0] XOIN XOOUT LCLK PLLAGND PLLVDD PLLVSS PCLK IDDTn RESET XCTR_IN XCTR[3:0] AGC1 AGC2 FLCLK INSEL BCLKOUT CO[7:0] COEn DVALIDOUT ERROROUTn FSTARTOUT INTn SADR[1:0] SDATA SCLK FDOUB PSOUTp PSOUTn MODp MODn PLLINp PLLINn VREF_LVDS RESO_LVDS VREFP VREFN ADCVSSI ADCVSSQ ADCVDDI ADCVDDQ VMID
Channel Interface
Channel Data Output Interface
Channel Clock Interface
Microcontroller Interface
Interface
Synthesizer Control Interface
Control Signals Interface
Control Interface Tuner Control Interface
Interface
shown Figure L64734 following major interfaces:
Channel Channel Clock Control Signals
L64733/L64734 Tuner Satellite Receiver Chipset
Control Channel Data Output Microcontroller Synthesizer Control Tuner Control
following signal descriptions listed according major interface groups.
Channel Interface
Channel Interface input path L64734 satellite receiver. IVIN QVIN streams, respectively, from satellite tuner circuit. signal strobes data signals. IBYPASS[5:0] Channel Data Input IBYPASS[5:0] signals form digital channel data input bus, which supplies Stream L64734 when bypassed. Bypass controlled through setting particular register bits L64734. IVINn, IVINp Channel Data Input These differential signals form analog received channel data input bus, which supplies stream L64734.
QBYPASS[5:0] Channel Data Input QBYPASS[5:0] signals form digital received channel data input bus, which supplies Stream L64734 when bypassed. Bypass controlled through setting particular register bits L64734. QVINn, QVINp Channel Data Input QVINn QVINp differential signals form analog received channel data input bus, which supplies stream L64734.
L64733/L64734 Tuner Satellite Receiver Chipset
Channel Clock Interface
Channel Clock Interface consists clock crystal oscillator signals. XOIN Input Clock Input This functionality been assigned XOIN pin. Crystal Oscillator Input XOIN used crystal oscillator external reference clock input. crystal normally connected XOIN pin. This also driven XOOUT from L64733. When using external strobe bypass data into L64734, connect clock input this pin. Crystal Oscillator This crystal oscillator output pin. Output
XOOUT
Phase-Locked Loop (PLL) Interface
internal generates signals operate ADC, demodulator, modules. LCLK Decimated Clock Output Output L64734 internal clock generation module generates LCLK signal. LCLK derived dividing value CLK_DIV2 register parameter. Input Input signal input internal voltagecontrolled oscillator. normally connected output external filter circuit. Clock Output Output L64734 internal clock synthesis module generates PCLK signal. driven reference crystal connected between XOIN XOOUT pins. clock synthesis module configured generate PCLK rate that appropriate data rates. Analog Ground Input PLLAGND analog ground module; normally connected system ground plane.
PCLK
PLLAGND
L64733/L64734 Tuner Satellite Receiver Chipset
PLLVDD
Power Input PLLVDD power supply module; normally connected system power (VDD) plane. Ground Input PLLVSS ground module; normally connected system ground plane.
PLLVSS
Control Signals Interface
Control Signals interface controls operation L64734; associated with particular interface. IDDTn Test Input IDDTn Logic internal test pin. IDDTn normal operation. Reset Input This active-HIGH signal resets internal data paths. Reset timing asynchronous device clocks. Reset does affect configuration registers. Control Input Input XCTR_IN external input control pin. sensed reading XCTR_IN register bit. Control Output/Sync Status Flag Output This signal indicates synchronization status three synchronization modules L64734 XCTR[3] field Group modules Viterbi decoder, Reed-Solomon deinterleaver (DI/RS), descrambler. three synchronization outputs, asserting XCTR[3] signal indicates that synchronization been achieved sync module chosen using SSS[1:0] register bits. When deasserted, signal indicates out-ofsynchronization condition. Control Output Output XCTR[2:0] pins external output control pins. They programming particular register bits. XCTR[2] mapped CPG1, XCTR[0] multiplexed with CPG2, when used with L64733 Tuner When on-chip serializer used generate serial 3-wire protocol XCTR[2:0] pins, mapping XCTR[2] XCTR[1] SCL, XCTR[0] SDA.
RESET
XCTR_IN
XCTR[3]
XCTR[2:0]
L64733/L64734 Tuner Satellite Receiver Chipset
Analog-to-Digital Converter (ADC) Interface
module converts incoming IVIN QVIN signals into internal 6-bit digital representation processing. following pins support module. ADCVDDI/Q Power Input These analog power supply pins module; they normally connected system power (VDD) plane. Analog Ground Input These analog ground pins module; they normally connected system ground plane. Reference Voltage, Positive Input/Output reference voltage generated on-chip bandgap-based generator. Bypass using capacitor. Reference Voltage, Negative Input/Output reference voltage generated on-chip bandgap-based generator. Bypass using capacitor. Reference Voltage, Middle Input/Output reference voltage generated on-chip bandgap-based generator. Bypass using capacitor.
ADCVSSI/Q
VREFP
VREFN
VMID
Control Interface
Control interface contains signals used power control. AGC1, AGC2 Power Control Signals Output AGC1 AGC2 signals positive modulated output used power control. These signals each drive external passive filter that feeds gain control stage dual-stage AGC. single-stage AGC, AGC1 used.
L64733/L64734 Tuner Satellite Receiver Chipset
Channel Data Output Interface
Channel Data Output interface output path from L64734. typically connected input transport demultiplexer set-top decoder application. BCLKOUT Byte Clock Output This signal indicates valid data bytes CO[7:0] when L64734 Parallel Channel Output mode. This signal cycles once every valid output data byte. used transport demultiplexer latch output data from L64734 BCLKOUT rate. Disregard BCLKOUT signal when L64734 Serial Channel Output mode. Channel Data Output CO[7:0] signals form decoded output data port. When (Group APR17), L64734 operates Parallel Channel Output mode. this mode, L64734 outputs channel data eight-bitwide parallel data CO[7:0] signals. Serial Channel Output mode L64734 outputs channel data serial data CO[0]. data latched every clock cycle. chronological ordering Serial Channel output mode oldest, newest. Channel Output Enable Input When asserted, COEn signal enables ERROROUTn, CO[7:0], DVALIDOUT, BCLKOUT, FSTARTOUT signals. Operation receiver continues regardless state COEn signal. Valid Data Output DVALIDOUT signal indicates that CO[7:0] signals contain corrected channel data. data valid CO[7:0] signals when DVALIDOUT signal asserted. DVALIDOUT asserted during propagated check bytes. DVALIDOUT signal deasserted after FEC_RST register (Group
CO[7:0]
COEn
DVALIDOUT
ERROROUTn Error Detection Flag Output L64734 asserts ERROROUTn signal beginning frame that contains uncorrectable error; deasserts ERROROUTn frame
L64733/L64734 Tuner Satellite Receiver Chipset
error condition removed. ERROROUTn signal exactly aligned with output data stream; asserted after FEC_RST register set. FSTARTOUT Frame Start Output Output L64734 asserts FSTARTOUT signal during first every frame with valid data Serial Channel output mode, during first byte Parallel Channel output mode. FSTARTOUT valid only when DVALIDOUT signal asserted. FSTARTOUT signal deasserted after FEC_RST register set.
Microcontroller Interface
Microcontroller interface connects L64734 external microcontroller. INTn Interrupt Output L64734 asserts INTn when internal, unmasked interrupt flag set. INTn signal remains asserted long interrupt condition persists interrupt flag masked. Serial Address Input SADR[1:0] signals programmable bits serial address L64734. Serial Clock Bidirectional This serial clock two-wire serial protocol. Serial Data Bidirectional This serial data two-wire serial protocol.
SADR[1:0]
SCLK SDATA
Synthesizer Control Interface
Synthesizer Control interface lets L64734 control L64733 frequency synthesizer. FDOUB Frequency Doubler Output When FDOUB asserted, frequency doubler L64733 Tuner enabled. When FDOUB deasserted, frequency doubler disabled. This output register programming.
L64733/L64734 Tuner Satellite Receiver Chipset
MODn, MODp Modulus Selector Output These signals low-voltage differential signals from L64734 modulus selector programmable counter (A). signals clocked PSOUT. positive MODp with respect MODn selects divide dual modulus prescaler L64733 Tuner negative MODp with respect MODn selects divide Counter programmed count down from particular value register programming. PLLINn, PLLINp Differential Counter Output These signals low-voltage differential signals from L64734 programmable synthesizer counter (M). signals clocked PSOUT. PLLINp positive with respect PLLINn PSOUT cycle. repetition rate reference crystal. counter programmed count down from particular value register programming. PSOUTn, PSOUTp Prescaler Output Output These signals differential signals L64734 from L64733. programmable counters L64734 clocked rising edge PSOUT signal. RESO_LVDS LVDS Buffers Precision Resistor Output RESO_LVDS output must connected resistor (6.8 ±5%) that controls swing LVDSOUT buffers used drive differential signals MODp, MODn, PLLINp, PLLINn. Connect other side resistor ground. VREF_LVDS LVDS Buffers Reference Voltage Input VREF_LVDS input ±10% voltage level that controls common mode voltage LVDSOUT buffers used drive differential signals MODp, MODn, PLLINp, PLLINn.
L64733/L64734 Tuner Satellite Receiver Chipset
Tuner Control Interface
Tuner Control interface contains signals that control L64733 Tuner FLCLK Filter Control Clock Output FLCLK output programmable integer value divider clocked demodulator sampling clock, PCLK. division ratio programmed with register bits. frequency FLCLK multiplied cutoff programmable low-pass filters L64733. Input Select Output When INSEL asserted, L64733 tuner selects normal mode. When INSEL deasserted, L64733 selects Loop-Through mode.
INSEL
Typical Operating Circuit
Figure diagram typical operating circuit chipset, including external components. external components shown. L64733/34 Evaluation Board User's Guide complete schematic details.
L64733/L64734 Tuner Satellite Receiver Chipset
Figure
Typical Operating Circuit
L64733/L64734 Tuner Satellite Receiver Chipset
6.8K Varactors Stripline Inductors
SADR[1] SADR[0] SDATA SCLK INTn RESET PSOUTn PSOUTp PLLINn PLLINp RESO_LVDS VREF_LVDS MODn MODp
BC847
CFLT XTLn XTLp GND1 RFINn RFINp GND1 GNDSUB1 QDCn QDCp
L64733
PLLINn PLLINp MODn MODp GND1 IOUTp IOUTn QOUTp QOUTn FDOUB FLCLK
Filter
0.01
ADCVDDI IVINp IVINn ADCVSSI VREFP VMID VREFN ADCVDDQ QVINp QVINn ADCVSSQ FDOUB FLCLK INSEL AGC2 AGC1 XCTR[1] XCTR[0] XCTR[2] XCTR[3] XCTR_IN IBYPASS[5]
L64734
PLLVSS PLLAGND PLLVDD PCLK LCLK CO[0] CO[1] CO[2] CO[3] CO[4] CO[5] CO[6] CO[7] BCLKOUT DVALIDOUT FSTARTOUT ERROROUTn COEn IDDTn
PSOUTp PSOUTn GND1 GND1 TANKn VRLO TANKp GND1 INSEL AGC2 AGC1 CPG2 XTLOUT CPG1 RFOUT GND1 GNDSUB1 IDCp IDCn
XOOUT XOIN QBYPASS[0] QBYPASS[1] QBYPASS[2] QBYPASS[3] QBYPASS[4] QBYPASS[5] IBYPASS[0] IBYPASS[1] IBYPASS[2] IBYPASS[3] IBYPASS[4]
Notes: ground connections L64733 provided through metal plate under rather than direct connection ground pins PCB. external components shown. Refer L64733/34 Evaluation Board User's Guide complete details.
Specifications
This section contains electrical, timing, mechanical specifications L64733/34 chipset.
L64733 Electrical Specifications
This section contains electrical parameters L64733. Table lists absolute maximum values. Exceeding values listed cause damage L64733. Table gives recommended operating supply voltage temperature. Table gives characteristics. Table gives characteristics. Table summarizes pins. Table
Symbol
L64733 Absolute Maximum Rating (Referenced VSS)
Parameter Supply Voltage Continuous power dissipation Derating above Operating temperature Junction temperature Storage Temperature Junction Ambient Thermal Resistance2 Limits1 -0.5 +7.0 1.05 +150 +165 27.6 +300 Units mW/°C °C/watt
Lead temperature (soldering sec)
Note that ratings this table those beyond which permanent device damage likely occur. these values limits normal device operation. junction ambient thermal resistance ePad TQFP package, four-layer board.
L64733/L64734 Tuner Satellite Receiver Chipset
Table
Recommended Operating Conditions
Limits1 Units
Symbol Parameter Supply Voltage Operating Ambient Temperature Range (Commercial)
normal device operation, adhere limits this table. Sustained operation device conditions exceeding these values, even they within absolute maximum rating limits, result permanent device damage impaired device reliability. Device functionality stated limits guaranteed recommended operating conditions exceeded.
Table
Parameter
Characteristics L647331
Condition Units
Power Supply Power Supply Voltage Power Supply Current Digital Control Inputs CPG1, CPG2, INSEL, FDOUB Input Logic Level HIGH Input Logic Level Input Bias Current specs 4.75 5.25
Slew-Limited Digital Clock Inputs FLCLK FLCLK Input Level FLCLK Input Level HIGH FLCLK Input Resistance/Leakage Current series resistor between L64734 FLCLK pin. L64734 generates normal CMOS levels 1.85 1.45
Fast Digital Clock Inputs MODp, MODn, PLLINp, PLLINn MODp, MODn, PLLINp, PLLINn Common Mode Input Range (VCM) MODp, MODn, PLLINp, PLLINn Input Voltage MODp, MODn, PLLINp, PLLINn differential swing around VCM. Need external termination 1.08 1.32
-100
(Sheet
L64733/L64734 Tuner Satellite Receiver Chipset
Table
Parameter
Characteristics L647331 (Cont.)
Condition MODp, MODn, PLLINp, PLLINn differential swing around VCM. Need external termination MODp, MODn, PLLINp, PLLINn Units
MODp, MODn, PLLINp, PLLINn Input Voltage HIGH MODp, MODn, PLLINp, PLLINn Input Current
Digital Clock Outputs PSOUTp, PSOUTn PSOUTp, PSOUTn Common Mode Output Range (VCM) PSOUTp, PSOUTn Output Voltage PSOUTp, PSOUTn Output Voltage HIGH Synthesizer Prescaler Ratio HIGH Reference Divider Ratio Charge Pump Output HIGH Current CPG1, CPG2 CPG1, CPG2 CPG1, CPG2 CPG1, CPG2 Charge Pump Output Current CPG1, CPG2 CPG1, CPG2 CPG1, CPG2 CPG1, CPG2 Charge Pump Output Leakage Current Charge Pump Positive-toNegative Current Matching (Sheet self-biased 0.08 0.24 0.48 1.44 -0.12 -0.36 -0.72 -2.16 -0.1 -0.3 -0.6 -1.8 0.12 0.36 0.72 2.16 -0.08 -0.24 -0.48 -1.44 PSOUTp, PSOUTn differential swing around VCM. Driving PECL Load (±10 PSOUTp, PSOUTn differential swing around VCM. Driving PECL Load (±10 2.16 -215 2.64 -150
L64733/L64734 Tuner Satellite Receiver Chipset
Table
Parameter
Characteristics L647331 (Cont.)
Condition Units
Charge Pump Output Transistor Base Current Drive Analog Control Inputs AGC1, AGC2 Input Bias Current
Baseband Outputs IOUTp, IOUTn, QOUTp, QOUTn Output Swing IOUTp, IOUTn, QOUTp, QOUTn Common Mode Voltage IOUTp, IOUTn, QOUTp, QOUTn Offset Voltage (Sheet symbol rates below MSymbols/s, maximum input power might subject shifting down roughly log(15/Rs[MSymbols/s]) channel bandwidth reduction. Loaded with differential across IOUTp, IOUTn, QOUTp, QOUTn 0.65 0.85
L64733/L64734 Tuner Satellite Receiver Chipset
Table
Parameter
Characteristics L64733
Condition Units
Front RFIN Input Frequency Range RFIN Single-Carrier Input Power AGC1 Range AGC2 Range RFIN referred (front-end contributions) Meets following specs level needed produce 0.59 AGC1 AGC2 AGC1 gain input level (0.59 output), AGC2 maximum gain (VAGC2 signals MHz, @2175 @1550 @925 2175 -251
Baseband Compression Point RFIN Referred Noise Figure RFIN Worst Case Return Loss Leakage Power RFIN Second Harmonic Rejection Half-Harmonic Rejection Harmonic Rejection1, Loop Through Gain
IOUTp, IOUTn, QOUTp, QOUTn have signal within filter PRFIN dBm, maximum gain AGC1, AGC2 Complex source" subject board, connector parasitics. 2150 MHz, subject board layout LO-generated harmonic RFIN-generated harmonic
15.5 11.5
@2175 @1550 @925
(Sheet
L64733/L64734 Tuner Satellite Receiver Chipset
Table
Parameter
Characteristics L64733 (Cont.)
Condition PRFIN @2175 @1550 @925 12.0 Units
RFIN referred (when Loop-Through enabled) Noise Figure Worst-Case Return Loss Baseband IOUTp, IOUTn, QOUTp, QOUTn Differential Output Voltage Swing IOUTp, IOUTn, QOUTp, QOUTn Output Impedance Baseband Highpass Point Nominal Cutoff Frequency Range Nominal Baseband Frequency Response Cutoff Frequency Accuracy Quadrature Gain Error Quadrature Phase Error Synthesizer Crystal Frequency Range XTLOUT Voltage Levels XTLOUT Level (Sheet
Subject board connector parasitics
differential load, IOUTp, IOUTn, QOUTp, QOUTn. Expect from each side, IOUTp, IOUTn, QOUTp, QOUTn. 0.22 caps connected from IDCp IDCn, QDCp QDCn. point filter
14.5 FFLCLK
Deviation from ideal 7th-order Butterworth, measure 0.7. Include front-end tilt effects Measured point @31.4
-0.5
-5.5
Includes effects from baseband filters Measure
Measured
7.26
L64733/L64734 Tuner Satellite Receiver Chipset
Table
Parameter
Characteristics L64733 (Cont.)
Condition Must assert level within this time period ensure that next PSOUT period gives correct count. Delay with respect rising edge PSOUT (previous count). Units
MODp, MODn Delay
PLLINp, PLLINn With respect rising edge PSOUT. MODp, MODn Hold Time This means that PSOUT need continue asserted after given correct count. Local Oscillator Tuning Range Phase Noise, Including Doubler. Subject tank implementation. offset. Depends loop gain. offset. Depends loop gain. offset Buffer Frequency Range when overdriven external Input Port VSWR Over Band, when overdriven external Required external Input Power Range (Sheet FDOUB
1180 2175
dBc/ dBc/ dBc/
2175 MHz. Assume series resistors TANKp TANKn pins Differential drive into TANKp, TANKn. source.
harmonic rejection MHz. L63733 available with half-harmonic specification guaranteed typical. Contact your Logic sales representative further information.
L64733/L64734 Tuner Satellite Receiver Chipset
Table
Mnemonic AGC1 AGC2 CFLT CPG[2:1] FDOUB FLCLK IDCp IDCn INSEL IOUTp IOUTn MODp MODn PLLINp PLLINn PSOUTp PSOUTn QDCp QDCn QOUTp QOUTn RFINp
L64733 Description Summary
Description Automatic Gain Control Automatic Gain Control Bias Voltage Bypass Charge Pump Charge Pump Gain Feedback Charge Pump Transistor Drive Frequency Doubler Filter Clock I-Channel Offset Correction (noninverting) I-Channel Offset Correction (inverting) Port Input Select I-Channel Baseband Data (noninverting) I-Channel Baseband Data (inverting) Prescaler Modulus (noninverting) Prescaler Modulus (inverting) Phase Detector (noninverting) Phase Detector (inverting) Prescaler (noninverting) Prescaler (inverting) Q-Channel Offset Correction (noninverting) Q-Channel Offset Correction (inverting) Q-Channel Baseband Data (noninverting) Q-Channel Baseband Data (inverting) Input (noninverting) Type Input Input Bidirectional Output Input Output Input Input Input Input Input Output Output Input Input Input Input Output Output Input Input Output Output Input
(Sheet
L64733/L64734 Tuner Satellite Receiver Chipset
Table
Mnemonic RFINn RFOUT TANKp TANKn VRLO XTLp XTLn XTLOUT
L64733 Description Summary (Cont.)
Description Input (inverting) Output (Loop-Through) Oscillator Tank Port (noninverting) Oscillator Tank Port (inverting) Local Oscillator Regulator Bypass Crystal Oscillator Port (noninverting) Crystal Oscillator Port (inverting) Crystal Type Input Output Input Input Bidirectional Input Input Output
(Sheet
L64734 Electrical Specifications
This section contains electrical parameters L64734. Table lists absolute maximum values. Exceeding values listed cause damage L64734. Table gives recommended operating supply voltage temperature conditions. Table shows capacitance. Table gives characteristics. Table summarizes pins. Table L64734 Absolute Maximum Rating (Referenced VSS)
Limits1 -0.3 +3.9 -1.0 +0.3 -1.0 +125 Units
Symbol Parameter TSTG Supply Voltage LVTTL Input Voltage Compatible Input Voltage Input Current Storage Temperature Range (Plastic)
Note that ratings this table those beyond which permanent device damage likely occur. these values limits normal device operation.
L64733/L64734 Tuner Satellite Receiver Chipset
Table
L64734 Recommended Operating Conditions
Limits1 +3.14 3.47 +125 21.7 Units °C/watt °C/watt
Symbol Parameter Supply Voltage Operating Ambient Temperature Range (Commercial) Junction Temperature Junction Ambient Thermal Resistance2 Junction Case Thermal Resistance3
normal device operation, adhere limits this table. Sustained operation device conditions exceeding these values, even they within absolute maximum rating limits, result permanent device damage impaired device reliability. Device functionality stated limits guaranteed recommended operating conditions exceeded. junction ambient thermal resistance PQFPt (U4) package, four-layer board. junction case thermal resistance valid only measurements isothermal environment including board package.
Table
Symbol COUT
L64734 Capacitance
Parameter1 Input Capacitance Output Capacitance Units
Measurement conditions clock frequency MHz.
L64733/L64734 Tuner Satellite Receiver Chipset
Table
Symbol
Characteristics L64734
Parameter Supply Voltage Input Voltage Input Voltage HIGH LVTTL Com/Ind/Mil Temp Range compatible Condition1 -0.5 Max, -1.0, -2.0, -4.0, -6.0, -8.0, -12.0 1.0, 2.0, 4.0, 6.0, 8.0, 12.0 Max, VOUT -215 -215 -384 -384 Units
IIPU IIPD
Switching Threshold Input Current Leakage Input Current Leakage with Pull-up Input Current Leakage with Pull-down Output Voltage HIGH Output Voltage 3-State Output Leakage Current Quiescent Supply Current
Dynamic Supply Current Mbaud, rate 3/4, Midpoint PSOUTp, PSOUTn inputs Input Voltage HIGH level (DC) PSOUTp PSOUTn
VIH_PECL
(Sheet
L64733/L64734 Tuner Satellite Receiver Chipset
Table
Symbol VIL_PECL IIL_PECL IIH_PECL
Characteristics L64734 (Cont.)
Parameter Input Voltage level (DC) Input current Input HIGH current Condition1 PSOUTp PSOUTn PLLINp/PLLINn, MODp/MODn signals PLLINp/PLLINn, MODp/MODn signals 1.253 1.030 1.373 1.032 1.437 1.059 Units
VRESO_LVDS Output Voltage RESO_LVDS VOH_LVDS VOL_LVDS Output Voltage HIGH level (DC) Output Voltage level (DC)
(Sheet Specified ambient temperature over specified range.
Table
Mnemonic ADCVDDI/Q ADCVSSI/Q AGC1, AGC2 BCLKOUT CO[7:0] COEn DVALIDOUT
L64734 Description Summary
Description Power Analog Ground Power Control Byte Clock Input Clock Channel Data Channel Output Enable Valid Data Error Detection Flag Frequency Doubler Type Input Input Outputs Output Input Output Input Output Output Output
ERROROUTn FDOUB (Sheet
L64733/L64734 Tuner Satellite Receiver Chipset
Table
Mnemonic FLCLK FSTARTOUT IBYPASS[5:0] IDDTn INSEL INTn IVINn, IVINp LCLK
L64734 Description Summary (Cont.)
Description Filter Control Clock Frame Start Output Channel Data (ADC bypassed) Test Input Select Interrupt Channel Data Decimated Clock Output Input Modulus Selector Clock Output Analog Ground Differential Counter Power Ground Type Output Output Input Input Output Output Input Output Input Outputs Output Input Outputs Input Input Outputs Input Input Input Output Input Bidirectional Bidirectional Input
MODp, MODn PCLK PLLAGND PLLINp, PLLINn PLLVDD PLLVSS
PSOUTp, PSOUTn Prescaler Output QBYPASS[5:0] QVINn, QVINp RESET RESO_LVDS SADR[1:0] SCLK SDATA VREF_LVDS (Sheet Channel Data (ADC bypassed) Channel Data Reset LVDS Buffers Precision Resistor Serial Address Serial Clock Serial Data LVDS Buffers Reference Voltage
L64733/L64734 Tuner Satellite Receiver Chipset
Table
Mnemonic VREFP VREFN VMID XCTR_IN XCTR[3:0] XOIN XOOUT
L64734 Description Summary (Cont.)
Description Reference Voltage, Positive Reference Voltage, Negative Reference Voltage, Middle Control Input Control Output/Sync Status Flag Crystal Oscillator Crystal Oscillator Type Input/Output Input/Output Input/Output Input Output Input Output
(Sheet
L64734 Timing
This section includes timing information L64734. During testing, HIGH inputs driven inputs driven transitions between HIGH, LOW, invalid states, timing measurements made shown Figure Figure Test Load Waveform Standard Outputs
Test Point
Output
3-state outputs, timing measurements made from point which output turns OFF. output when voltage greater than less than output when voltage less than greater than shown Figure
L64733/L64734 Tuner Satellite Receiver Chipset
Figure
Test Point
Test Load Waveforms 3-State Outputs
Iref
Output
Vref Vref
Iref
Synchronous timing shown Figure Synchronous inputs must have setup hold relationship with respect clock signal that samples them. Synchronous outputs have delay from clock edge that asserts them. Figure L64734 Synchronous Timing
PCLK BCLKOUT INPUTS OUTPUTS
reset pulse requirements shown Figure Figure L64734 RESET Timing Diagram
RESET
L64733/L64734 Tuner Satellite Receiver Chipset
Figure shows relationship L64734 3-state signals COEn signal. Figure
COEn FSTARTOUT ERROROUTn DVALIDOUT BCLKOUT
L64734 3-State Delay Timing
Figure shows relationship L64733 PSOUTp PSOUTn prescaler signals signals back L64733 from L64734 control synthesizer. Figure L64734 Synchronous Timing Synthesizer Control
PSOUTn PSOUTp PLLINp, MODp PLLINn, MODn
L64733/L64734 Tuner Satellite Receiver Chipset
numbers first column Table refer timing parameters shown preceding figures. parameters timing tables apply capacitive load Table
Parameter tCYCLE tPWH tPWL
L64734 Timing Parameters
Description Clock Cycle PCLK Clock Pulse Width HIGH Clock Pulse Width Input Setup Time Input Hold Output Delay from PCLK, serial mode Output Delay from BCLKOUT, parallel mode Reset Pulse Width HIGH Wake-Up Time Delay from COEn 11.1 33.31 Units PCLK cycles cycles cycles
tODS tODP tRWH tDLY
tCYCLE_PS Clock Cycle PSOUTp, PSOUTn clock tPWH_PS tPWL_PS tOD_PS PSOUT Clock Pulse Width HIGH PSOUT Clock Pulse Width Output Delay from PSOUT
Minimum (sampling clock MHz).
L64733/L64734 Tuner Satellite Receiver Chipset
L64733/34 Chipset Ordering Part Marking Information
L64733 L64734 ordered set. Table gives ordering information chipset. Table L64733/34 Chipset Ordering Information
Package Type 48-pin TQFP 100-pin PQFPt Operating Range Commercial Commercial
Order Number L64733B L64734C-45
Table gives part marking information chips. Table
Part L64733 rev.
L64733 L64734 Part Marking Information
Production Chip Marking 64733 MAX2104 YYWW+ESD MAXIM L64734C-45 Receiver YYWW+ESD Assy 65060A1 OAS515U4FAA Country Origin
L64734 rev.
tables figures that follow provide pinouts mechanical drawings each package chipset.
L64733/L64734 Tuner Satellite Receiver Chipset
L64733 Pinout Packaging Information
Pinouts
Figure gives pinout 48-pin TQFP L64733 package. Figure L64733 48-Pin TQFP Pinout
PLLINn PLLINp MODn MODp IOUTp IOUTn QOUTp QOUTn FDOUB FLCLK PSOUTp PSOUTn TANKn VRLO TANKp
L64733/L64734 Tuner Satellite Receiver Chipset
CFLT XTLn XTLp RFINn RFINp GNDSUB QDCn QDCp
View
INSEL AGC2 AGC1 CPG2 XTLOUT CPG1 RFOUT GNDSUB IDCp IDCn
Mechanical Drawing
Figure mechanical drawing 48-pin TQFP L64733 package. Figure L64733 48-Pin TQFP Mechanical Drawing
VIEW D1/2 E1/2 MIN. BOTTOM VIEW
MAX. EXPOSED CORNER DETAIL
EVEN LEAD SIDES DETAIL
PLACES 11-13° MIN. DATUM PLANE -H0.08 MIN. 0-7° 0.20 MIN. 0.09/0.20 0.09/0.16 1.00 REF. DETAIL DETAIL
DETAIL
0.08/0.20 0.25 GAUGE PLANE
WITH LEAD FINISH
BASE METAL
Notes: dimensioning tolerancing conform Ansi Y14.5-1982. Datum plane located mold parting line coincident with lead, where lead exits plastic body bottom parting line. Dimensions include mold protrusion. allowable mold protrusion 0.254 dimensions. package smaller than bottom package 0.15 millimeters. Dimension does include dambar protrusion. Allowable dambar protrusion shall 0.08 total excess dimension maximum material condition. Controlling dimension: millimeter. Maximum allowable thickness assembled this package family 0.30 millimeters. This outline conforms Jedec Publication Registration MO-136, variations Exposed shall coplanar with bottom package within mils (0.05 mm). Metal area exposed shall within nominal size.
JEDEC VARIATION DIMENSIONS MILLIMETERS MIN. 0.05 0.95 NOM. 0.10 1.00 9.00 BSC. 7.00 BSC. 9.00 BSC. 7.00 BSC. 0.60 BSC. 0.22 0.20 MAX. 1.20 0.15 1.05
0.45 0.14 0.17 0.17
0.75
0.27 0.23
L64733/L64734 Tuner Satellite Receiver Chipset
L64734 Pinout Packaging Information
Pinouts
Figure gives pinout 100-pin PQFPt L64734 package. Figure L64734 100-Pin PQFPt Pinout
PLLVSS PLLAGND PLLVDD PCLK LCLK CO[0] CO[1] CO[2] CO[3] CO[4] CO[5] CO[6] CO[7] BCLKOUT DVALIDOUT FSTARTOUT ERROROUTn COEn IDDTn
ADCVDDI IVINp IVINn ADCVSSI VREFP VMID VREFN ADCVDDQ QVINp QVINn ADCVSSQ FDOUB FLCLK INSEL AGC2 AGC1 XCTR[1] XCTR[0] XCTR[2] XCTR[3] XCTR_IN IBYPASS[5]
SADR[1] SADR[0] SDATA SCLK INTn RESET PSOUTn PSOUTp PLLINn PLLINp RESO_LVDS VREF_LVDS MODn MODp
View
XOOUT XOIN QBYPASS[0] QBYPASS[1] QBYPASS[2] QBYPASS[3] QBYPASS[4] QBYPASS[5] IBYPASS[0] IBYPASS[1] IBYPASS[2] IBYPASS[3] IBYPASS[4]
L64733/L64734 Tuner Satellite Receiver Chipset
Mechanical Drawings
Figure mechanical drawing 100-pin PQFPt L64734 package. Figure 100-Pin PQFPt (U4) Mechanical Drawing
Important:
This drawing might latest version. board layout manufacturing, obtain most recent engineering drawings from your Logic marketing representative requesting outline drawing package code
L64733/L64734 Tuner Satellite Receiver Chipset
Figure
100-Pin PQFPt (U4) Mechanical Drawing (Cont.)
Important:
This drawing might latest version. board layout manufacturing, obtain most recent engineering drawings from your Logic marketing representative requesting outline drawing package code
L64733/L64734 Tuner Satellite Receiver Chipset
Notes
L64733/L64734 Tuner Satellite Receiver Chipset
Notes
L64733/L64734 Tuner Satellite Receiver Chipset
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