Highest Performance, Highest Density, Programmable CMOS ASICs GF250FPr

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Highest Performance, Highest Density, Programmable CMOS ASICs GF250FPr

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GF250F ProASIC Product Family
Highest Performance, Highest Density, Programmable CMOS ASICs GF250FProASICproduct family highest performance highest gate count programmable ASICs released GateFieldportfolio. GF250F family offers reprogrammable ASIC solutions applications consumer, computer communications markets. Figure ProASIC 50,000 Gate Device
150,000 available gates provide increased system integration 15-20% speed increase over GF200F product improves system performance Distributed memory compilation register files FIFOs ensures optimally placed memory Non-volatile flash technology retains programming during power cycles fine-grained architecture provides synthesis source compatibility with gate arrays Package options, including CPGA, MQUAD, eSBGA, meet wide range system requirements Full compatibility with industry standard design methodology tools improves design productivity Sign-off industry-leading third party verification tools simplifies design process compliant target master cores enable easy interfacing industry standard buses Compilable JTAG support facilitates boundary-scan insertion Programmable security helps prevent customer-owned intellectual property (IP) reverse engineering
GF250F ProASIC Data Sheet Page
Table GF250F ProASIC Product Family
Part Type GF250F025 GF250F050 GF250F100 Total Gates 25,000 50,000 100,000 Usable Gates 12,000 22,000 46,000 Compilable Bits 1.2K 1r/1w 2.5K 1r/1w 5.1K 1r/1w 7.5K 1r/1w flip-flops 3,000 6,000 12,000 18,000 Maximum Pins
GF250F150 150,000 70,000 Contact your sales representative product availability.
Process Technology
GF250F ProASIC family achieves non-volatility re-programmability through underlying process technology; advanced flash-based, 0.5µm channel length CMOS technology. Standard CMOS design techniques used implement logic control functions resulting highly predictable performance gate array compatibility. Flash memory bits distributed throughout each device providing non-volatile, reconfigurable interconnect programming. GateField manufactures GF250F conjunction with wafer fabrication partner, Rohm Semiconductor, Kyoto, Japan. GF250F process employs I-line lithography produce stateof-the-art products optimized performance, density high-reliability. GF250F ProASIC product utilizes proprietary architecture that results granularity comparable gate arrays. Unlike SRAM-based FPGAs, GF250F products utilize lookup tables architectural mapping during design. Synthesizing directly gates streamlines design flow, increases design productivity eliminates dependencies upon vendor specific design tools. GF250F device core consists programmable tiles. Each tile configured specific logic function (i.e. inverter, NAND gate, gate, etc.) programming interconnect switches. This directly analogous metal mask programming more "gates" gate array core. Gates larger functions connected together same manner utilizing three levels routing hierarchy shown figure Switches programmed connect signal lines appropriate macrocell inputs outputs. Dedicated highperformance lines connected needed fast, low-skew clock distribution throughout core. core tiles configurable gates, flip-flops distributed memory. Maximum core efficiency possible virtually design. Figure GF250F Device Core Architecture
ProASIC GF250F Product Architecture
GF250F ProASIC Data Sheet Page
Macrocell Library
GF250F products' macrocell library provides functional granularity equivalent gate arrays. library includes simple gates, complex gates storage elements such flip-flops latches. sampling breadth functionality provided table Every effort been made create "synthesis friendly" library. Many versions every cell type exist which allows Synopsys' Design Compiler tool maximum flexibility selecting best cell each situation during synthesis. This results optimum performance maximum silicon efficiency. addition, speed grades available: (-4) standard grade (-3) high-performance grade. Table Sample Macrocell Library Listing Cell Name NAND2 AND2 NOR3 MUX2L OA21 XOR2 DFFL Delay (ns)1 Description Inverter 2-Input NAND 2-Input 3-Input Multiplexor with Active Select 2-Input into 2-Input 2-Input Exclusive Active Latch (HL/LH) Negative Edge-Triggered D-type Flip-flop (HL/LH) 2.15 1.88 1.02 1.57 1.47 1.54 1.71 1.89/2.22 1.89/2.22 1.66 1.45 0.79 1.22 1.14 1.19 1.32 1.41/1.66 1.41/1.66
Assumes standard loads.
Distributed Memory Compiler
GF250F ProASIC family allows small register files FIFOs compiled utilizing functionality core tiles. This enables memory placed whenever wherever needed relation surrounding logic. part ASICmastersoftware suite, MEMORYmastersoftware accepts inputs from designer number words bits, preferred origin orientation, targeted device. MEMORYmaster produces netlist complete with estimated timing design simulation purposes hard-macro layout ensuring dense, fast memories. After layout, actual delay data back-annotated into hardmacro design file final simulation. Register Files Compiled register files have independent read write ports. read port asynchronous ensuring data available soon possible after read address change. write operation compiled level-sensitive edge-sensitive. Figure schematic representation register file. Figure Schematic Representation Register File
wAddr0 rAddr0 wData0 wData1
Decoders
Bit0
Bit1 Word0
Word1
GF250F ProASIC Data Sheet Page
rData0
rData1
FIFO Compiled FIFOs have independent read write ports well address inputs. FIFO automatically keeps track address. Figure shows schematic FIFO file. Figure Schematic Representation FIFO File
full
Init Write
empty
Read
wData1 wData0 rData1
rData0
Additional information GateField's memory compiler technology found MEMORYmaster application note.
Clock Distribution
High performance, skew clock distribution networks extremely important addressing today's high performance designs. GF250F family designed provide optimum programmable clock performance. Each device contains four primary clock inputs. Each clock input programmable access every tile throughout chip. These four inputs individually programmed separate clocks operating within particular regions core programmed operation throughout entire core. skew between flip-flops clock less than 1ns. programming options four primary clock paths extensive. delay path from clock input flip-flop chip virtually identical. shown figure each clock distribution path branches into equal regions. Then, using GF250F100 family member example, each region further branches into over localized clock nets. branch programmed primary clock used other clock signals other signal that requires skew. Through programming, designer implement four global skew clock nets, regional clock nets, over local clock nets, various combinations global, regional local clock nets. Table provides performance specifications different clocking implementations.
GF250F ProASIC Data Sheet Page
Figure GF250F100 Clock Distribution
Table Sample Clock Distribution Specification Worst Case Skew(ns) Typ. Operating Frequency1(MHz) Max. Loads 3,000 6,000 12,000 18,000 Prop Delay (ns)
Device GF250F025 GF250F050 GF250F100 GF250F150
Actual frequency dependent upon design (i.e. levels logic)
Programmable I/Os
GF250F family I/Os programmed input, output bi-directional. programmed input buffers offer following flexibility: voltage levels CMOS voltage levels Pull-up resistor I/Os programmed output buffers offer following flexibility: Selectable drive strengths Selectable slew rates Three-state Internal driver I/Os programmed bi-directional buffers offer following flexibility: voltage levels CMOS voltage levels Pull-up resistor Selectable drive strengths Selectable slew rates Three-state I/Os include protection designed prevent latchup.
I/Os
GF250F ProASIC Data Sheet Page
I/Os
Peripheral Component Interconnect (PCI) programmable simplifies interfacing industry-standard, revision 2.1, buses. programmed interfacing. addition, hard-cores available simulation layout ensure that timing requirements met. Synthesizable core descriptions allow design portability migration standard ASICs. more information support, refer GateField application note.
ASIC Design Environment
GF250F ProASIC product design environment provides significant advantages design engineer program manager. utilizes same robust VHDL Verilog descriptions that targeted gate arrays standard cells. This frees designer from limitations special idiosyncrasies imposed upon FPGA vendors. Furthermore, GateField does require special FPGA tools synthesis so-called "architectural mapping." Standard ASIC tools such Design Compiler, VSS, Verilog QuickSim VCS, Motive, Leonardo, etc. supported. This streamlines design environment enables design team focus single suite design tools, whether design targeted gate arrays programmable ASICs. ProASIC design flow also ensures seamless transition your ASIC vendor choice should production volumes warrant migration gate array standard cell product. shown figure with identical HDL, identical design tools flow, migration ASICs high volume production greatly simplified. Conversely, migration from ASICs GateField's ProASIC technology also unburdened traditional FPGA design requirements. Supported environments include Mentor Graphics (Falcon Framework 8.5), Synopsys (Design Compiler 3.5a later), Quad Design Technologies (Motive later), Viewlogic Systems (Powerview 5.1) Exemplar (Leonardo 4.0.3). Figure Common Design Environment Simplifies Migrations
Design Environment
ProASIC Logic Synthesis ASIC
Simulation Timing Analysis
ProASIC Place Route
ASIC Place Route
Production
Production
Once design been synthesized, simulated timing analysis performed, ready place route. facilitate this activity, GateField created desktop software package, ASICmasterTM, which ideally suited busy engineer. integral part ProASIC design flow (figure ASICmaster runs workstations. accepts standard ASIC formatted netlists, performs place route design into selected device provides back annotated delay information simulation. This accomplished through software's easy interface. Within minutes, average design engineer will running.
GF250F ProASIC Data Sheet Page
Figure ProASIC Design Flow
Description
ASIC Environment
ProASIC Libraries
Synthesis Optimization
Test Insertion
Gate Level Netlist
Memory Compiler
Simulation Timing Analysis
Place Route
Device Programming
ASICmaster
ASICmaker
GateField Environment User's Desktop ASICmaster software also contains very powerful interactive layout capabilities experienced user. Preferred placement, routing changes custom clock tree configurations possible. Once design finalized, layout down-loaded into GateField's ASICmakerdevice programmer, shown figure ProASIC part programming. ASICmaker device programmer supports interchangeable modules each package type available In-System-Programming module facilitate reprogramming ProASIC devices already resident board system. ASICmaster ASICmaker tools ensure fast efficient programmable ASIC implementations novice expert user. Figure ASICmaker Device Programmer
Package Thermal Characteristics
GF250F ProASIC family available number package types. Packages selected based high count, reliability factors superior thermal characteristics. ability package conduct heat away from silicon, through package surrounding expressed terms thermal resistance. This junction-to-ambient thermal resistance measured degrees Celsius/Watt represented Theta (JA). lower thermal resistance, easier package dissipate heat. maximum allowed power package function maximum junction temperature (TJ), maximum ambient operating temperature (TA), junction-to-ambient thermal resistance (JA). Maximum junction temperature maximum temperature active surface 110° defined
function rate flow contact with package, linear feet minute
GF250F ProASIC Data Sheet Page
(lfpm). When estimated power consumption exceeds maximum allowed power, other means cooling must used, such increasing flow rate. junction-to-case thermal resistance Theta (JC) lowest possible thermal resistance device. defined where temperature measured dead center package power
following tables list packages used GF250F products under several different operating conditions. Table Thermal Characteristics CPGA Package
Package CPGA391 Table
Still 20.2
lfpm Flow 12.7
lfpm Flow
Thermal Characteristics MQUAD Package
Package MQUAD208 Table
Still
lfpm Flow 10.6
lfpm Flow
Thermal Characteristics eSBGA Package
Package
Still
lfpm Flow
lfpm Flow
eSBGA352 eSBGA560
0.34-0.72 0.20-0.30
9.9-11.3 8.5-9.1
9.6* 7.3*
8.7* 6.5*
Forced convection watts.
Calculating Power Dissipation
GF250F device power calculated same manner CMOS gate arrays includes both static active component. active component function both number tiles utilized speed. calculate power dissipation, formula: where ISTATIC IOUTPUT ILOGIC ISTATIC static current. IOUTPUT ILOGIC current outputs switching. current internal logic signals switching.
static power (ISTATIC) amount current drawn when inputs switching. This equal Quiescent Supply Current IDDQ specified under Characteristics. Active power includes both current outputs switching current internal logic signals switching.
IOUTPUT where
IDCi)
capacitance output pad. voltage swing output pad.
GF250F ProASIC Data Sheet Page
IDCi
switching frequency output pad. number outputs. average load each pad, any.
most cases IOUTPUT approximated this formula, measured IOUTPUT Ctyp favg where Ctyp favg number active outputs. typical capacitance load output. average voltage swing. average switching frequency outputs. Typically this less than clock frequency.
ILOGIC represented this formula, measured ILOGIC where 0.35 effective gate GateField parts. GF250F products value number gates used design, thousands. operating frequency MHz. fraction devices active each clock edge. varies different designs, 0.15 conservative commonly used value.
GF250F050 design that 22,000 used gates, active outputs, average load clock, creating average switching frequency MHz, power calculation appears below. ISTATIC IOUTPUT ILOGIC 0.35 0.15
Therefore 346) Delay Derating timing characteristics GF250F ProASIC devices similar those traditional gate arrays. Delays function macrocells used design output loading/fanout each cell. While actual delays function final placement routing, typical values delays used make good approximations delays prior implementation. Each macrocell description includes typical values intrinsic load dependent delays. Device performance varies factor process, temperature voltage. tables figures below show nominal timing values given macrocell library change function these three variables. Table Process Derating Factor Worst Case Typical
Best Case
Table Combined Temperature Voltage Derating Factor Commercial* Industrial* Best Case Worst Case Best Case Worst Case 0.85 1.42 0.66 1.49
GF250F ProASIC Data Sheet Page
*Remarks: Commercial Industrial5V
110°C 110°C
GF250F ProASIC Data Sheet Page
Calculating Critical Path Delays
Figure shows temperature derating factor given junction temperature. Figure shows voltage derating factor given supply voltage. Figure Temperature Derating Figure Voltage Derating
estimate delay particular cell, following equation used: Delay Intrinsic (Drive Load) Wire Delay
Note: obtain most accurate timing data, figures generated ASICmaster after completing place route.
where
fanout
Load
Input loading
estimate wire delay particular net, following equation used: Delay 0.56 0.29 1.47 0.22
where out. These values, that nets will faster than this prediction. Here example estimated delay calculation. sample circuit below, estimated delay from SIGNAL1 SIGNAL2, when SIGNAL2 rising, typical case wire loading, calculated using following formula.
Figure Example Circuit Estimated Delay Calculation
tPLH L3)) 0.83 Intrinsic Delay (tPLH) AND2. 0.05 Drive Delay (tPLH) AND2. Input Loading BUFFERB. Input Loading OR2. Input Loading OR2. 1.43 Wire Delay from Wire Delay table fanout typical case, 0.56 0.29
GF250F ProASIC Data Sheet Page
DelayAY tPLH 0.83 [0.05 (1.1 2.6)] 1.43 2.59
GF250F ProASIC Data Sheet Page
Specifications
Electrical specifications GF250F devices provided this section. Table lists absolute maximum ratings technology. Table lists recommended operating conditions GF250F products. Table Absolute Maximum Rating (Referenced VSS) Parameter Supply Voltage Input Voltage Input Current Storage Temperature (Ceramic) Storage Temperature (Plastic)
Symbol TSTG TSTG
Limits1 -0.3 -0.3 VDD+0.3 +150 +125
Unit
I/Os comply with Peripheral Component Interface Specification version 2.1.
Table Recommended Operating Conditions Parameter Operating Ambient Temperature Junction Temperature Supply Voltage (over junction temperature range)
Symbol
Limits1 -4.75 5.25
Unit
Adherence limits this table required normal device operation. Sustained operation device conditions exceeding these values result permanent device damage impaired device reliability.
Table lists characteristics GF250F products input output buffers. Table Characteristics Buffers Symbol Parameter Voltage Input CMOS Voltage Input High CMOS Switching Threshold Input Current CMOS with pull-up Voltage Output High Cell IOB6 Cell IOB12 Voltage Output Cell IOB6 Cell IOB12 Three-state Leakage Current Output Short Circuit Current Quiescent Supply Current Input Capacitance Output Capacitance Condition Min. Typ. Max. 0.3*VDD 0.7*VDD CMOS VIN=VDD VIN=VSS IOH=-1mA IOH=-6mA IOH=-12mA IOL=1mA IOL=6mA IOL=12mA VO=VDD VDD=Max, VO=VDD VDD=Max, VO=VSS VIN=VDD Input Buffer Input Buffer VDD-0.1
±0.1 -100
Unit
-300
IDDQ COUT
±0.1
-200
GF250F ProASIC Data Sheet Page
Packaging Data
This section provides packaging information ProASIC GF250F products. Table shows maximum signal pins available package tpye. Table Maximum Signal Pins Available MQUAD Device GF250F025 GF250F050 GF250F100 GF250F150 Pins I/Os Pins eSBGA I/Os Pins CPGA I/Os
Following mechanical drawings each package. 391-Pin CPGA Package Mechanical Drawings
GF250F ProASIC Data Sheet Page
208-Pin MQUAD Package Mechanical Drawings
GF250F ProASIC Data Sheet Page
352-Pin eSBGA Package Mechanical Drawings
GF250F ProASIC Data Sheet Page
560-Pin eSBGA Package Mechanical Drawings
GF250F ProASIC Data Sheet Page
Ordering Information (Part Number Description) PRODUCT CODING GFXXXFYYY-XYYYZ-X XXXF GateField Field Programmable Product Family Number gates thousands (leading zeros where applicable) Package Code (see list below) Package pins Manufacturing Grade (see below) Speed reference indicator positive integer) Package Code List: MQUAD Metal Quad Flatpack eSBGA enhanced Super Ball Grid Array CPGA Ceramic Grid Array Manufacturing Grade: Commercial Example: GF150F050-M208C-4
GateField Sales Offices
Location Domestic Zycad Corp. Zycad Corp. Zycad Corp. Zycad Corp. California Massechuetts Jersey Texas Phone 510-249-5757 508-303-3627 201-989-2900 972-789-8124 International Zycad Ltd. Zycad sarl Zycad GmbH Zycad Japan Intellect, Inc. Zycad Corp. Location England France Germany Japan Korea Taiwan Phone 01344-51515 01-46-105016 089-9624260 045-471-1500 02-568-0221 03-572-8850
Manufacturing Reps
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GF250F ProASIC Data Sheet Page
Zycad division
47100 Bayside Parkway Fremont, 94538-9942 (800) 818-5052 (510) 249-5757 (510) 623-4484 gfinfo@gatefield.com www.gatefield.com
1997 Zycad Corporation 5/97 Zycad Corporation registered trademark GateField trademark Zycad Corporation. GateField logo, GF200F, GF250F, ProASIC, ASICmaster, ASICmaker, MEMORYmaster trademarks GateField, Zycad division. other trademarks owned their respective holders. Zycad Corporation reserves right make changes products services herein time without notice. Zycad does assume responsibility liability arising application product service described herein, except expressly agreed writing Zycad; does purchase, lease, product service from Zycad convey license under patent rights, copyrights, trademark rights, other intellectual property rights Zycad third parties.
GF250F ProASIC Data Sheet Page

Highest Performance, Highest Density, Programmable CMOS ASICs GF250FPr

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