AN400.1 Author: Daniel Clifton Introduction Intersil HS

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AN400.1 Author: Daniel Clifton Introduction Intersil HS

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Using HS-3282 ARINC Interface Circuit
AN400.1
Author: Daniel Clifton
Introduction
Intersil HS-3282 high performance CMOS programmable interface circuit that designed meet requirements ARlNC Specification 429, similarly encoded, time multiplexed serial data protocols. simple efficient design allows HS-3282 used without major complications variety applications. setting internal control register, HS-3282 programmed operate different data rates with different word lengths, transmit either even parity. device also programmed operate with without unique address (SDI source/destination identifier), with without self test mode implemented. Although HS3282 designed transmit receive high-speed data rates (100K 12.5K BPS), standard baud rates 9600 1200 implemented reducing input clock frequency. timing requirements HS3282 make compatible with 8086 microprocessor other similarly based systems operating 5MHz less. Designed meet critical needs today's advanced aircraft, HS-3282 cornerstone reliability systems that cannot tolerate wide margin error.
Receiver Operation Incoming data from line receiver from self test circuit) shifted into data shift register word timer edge sensitive basis. This results high data rate tolerance; although ARlNC specification requires least tolerance, HS-3282 least ±10% tolerance data rates. order prevent reception errors, word timer designed disable reset receiver upon reception consecutive null times consecutive data times), re-enable receiver after four additional null times. word proper length (and SDl) been received this time, word will latched flag corresponding receiver will signal host that valid word ready fetched. (For most efficient operation, flags should used generate interrupt requests host system.) should noted that parity that stored receiver latch different than parity word that received. This because parity that stored receiver latch actually parity flag, indicating status parity word that received: parity word received odd, parity flag will logic "0"; parity word received even, parity flag will logic "1". Once word ready fetched, read host system 16-bit parts over bi-directional strobing appropriate line twice, once with line read "word once with line high read "word preferred, "word read before "word line held long pulse while input toggled select first word then other.) actual ARlNC contents these 16-bit "words" contents 25-bit word length) shown data sheet. should noted that flag will reset unless both words read. Transmitter Operation mentioned data sheet, transmitter FIFO that hold eight data words. Although HS-3282 inputs, PL2, used write data into FIFO, data actually entered into FlFO until second input (PL2) pulsed low. Therefore, first half each data word must written HS-3282 first. Then, when input pulsed write second half word, proper data will transferred into FIFO. HS-3282 transmitter designed transmit data sets containing from eight 25-bit words. primary importance that transmitter FIFO disturbed while this transmission taking place; therefore, systems should designed disallow writing FIFO while transmission taking place. only exception this rule that words written into FIFO while first word (only) being transmitted; transmission second word started before TX/R returned high state, FIFO must remain undisturbed until entire transmission sequence completed TX/R flag goes high.
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Functional Operation HS-3282
order clarify expand basic details given data sheet, following information been provided point some particularities HS-3282. Clock Frequencies receiver output signals, D/R1 D/R2, have minimum pulse width clock period. Because this, when using slower clock rate than 1MHz drive HS-3282, these outputs remain state microseconds after data receivers fetched. This could cause same data fetched more than once these outputs used drive state sensitive interrupt requests; therefore, necessary edge sensitive interrupt requests, mentioned typical application HS-3282 below. Bi-Directional Data Data transfer from host accomplished 16-bit bidirectional, three-stated bus. control this completely internal HS-3282. When data written transmitter control word register, automatically enabled input; when data read from receivers, automatically enabled output; other times, high impedance state will interfere with external operations. Setting Control Word Register When high transition occurs CWSTR pin, data eleven most significant bits bidirectional latched into control word register. location function each these bits shown data sheet.
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Application Note
TX/R flag becomes useful here interrupt request output host system, signaling that FIFO ready another data words. also primary importance that ENTX input remain high duration transmission sequence integrity data FIFO will broken. This best accomplished feeding TX/R flag through inverter back into ENTX input. This application will enable transmitter soon first word written into FIFO, keep enabled until transmission sequence completed; since most host systems operate much greater speeds than transmitter, additional seven words could easily written into FIFO while first word still being transmitted. value parity written into FIFO makes difference since transmitter sets parity transmission time according type parity that been programmed transmit. Lightning Protection Although driver been protected 100mW fuse capable sinking short periods time (100ms) internal zener diodes which saturate about 8.7V, interface circuit such protection receiver inputs. Because possibility lighting strike aircraft, additional protection should used protect both HS3282 driver from high voltage spikes. External avalanche diodes with high power ratings (five watts) should used clamp about ±6.8V. This will prevent fuse zeners driver from being burned current surges, will keep voltage level inputs receiver within acceptable limits.
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Typical Application HS-3282
following example shows possible interface HS-3282 with host system. Although different applications require different approaches, most systems will have requirements similar those that have been here. Logical Control shown Figure support circuitry necessary integrate HS-3282 into system primarily involves logic circuit drive control inputs. most cases, this achieved using microprocessor control signals address lines conjunction with decoded chip select line (data enable) line. During READ operations, particular function (EN1 EN2) selected when proper address present while line low; note that second address used select either word word line used signal place data bus. Therefore, read operations, only timing requirement host system must meet minimum pulse 200ns plus propagation delay enable gates. During write operations, line inverted used instead line enable particular function (CWSTR, PL1, PL2) previously selected address bus. Since minimum data hold time HS-3282 0ns, timing requirement write operations, besides minimum 200ns pulse, minimum data disenable delay equal total propagation delay caused function enable gates.
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CWSTR A3-A7 CHIP SELECT DECODE FUNCTION SELECT DECODE FUNCTION ENABLE TX/R D/R1 D/R2 ENTX HS-3282
INTERRUPT REQUESTS
FIGURE TYPICAL HOST HS-3282 INTERFACE LOGIC
Application Note
Address Decoding system shown, transmitter FIFO decoded addresses (first word) (second word), control word register writing these addresses will load corresponding registers HS-3282. Receiver latch addresses (first word) (second word), Receiver latch addresses (first word) (second word); reading these addresses will load data from corresponding receiver latch HS-3282. Note that address line connected directly input HS-3282 perform receiver latch word select function. Since impossible write receiver latches read transmitter FIFO control word register, addresses read functions overlap addresses write functions without presenting problem. Table
TABLE TYPICAL HS-3282 FUNCTIONAL DECODING ADDRESS (1st Word) (2nd Word) CWSTR (1st Word) CWSTR (2nd Word)
INTERRUPT FETCH DATA FROM RCVR. LATCH RESPOND SIGNIFY UNAVAILABLE WRITE CONTROL WORD SIGNIFY AVAILABLE
DATA
DATA BUFFER
AVAILABLE
DATA BUFFER LOAD HS-3282 FIFO
Interrupts most efficient operation, system incorporating HS-3282 should provide conditions which device generate interrupt requests host system. both receivers being used, then minimum three interrupt vectors needed: (TX/R) signal data transmission, each receivers (D/R) signal presence valid word ready fetched. Since TX/R signal remain high indeterminate periods time while transmitter inactive, requests should received host edge sensitive basis. Software Requirements flowchart simple algorithm that host system could exercise monitor functions HS-3282 shown Figure order begin, HS-3282 must initialized with control word, then host should some flag system memory indicate that transmitter available. data ready transmitted, host should store data temporary buffer until transmitter becomes available. this time, data taken from buffer loaded into transmitter FIFO (eight 32-bit words maximum). After loading FIFO, host should reset flag system memory mentioned previously indicate that transmitter longer available. Unless interrupt received this time, host move other tasks continue storing data temporary buffer shown broken arrow). interrupt received, data read from receiver latch corresponding action taken. TX/R interrupt received, transmitter available flag should once again, ready data buffer could written into FlFO.
TX/R INTERRUPT
FIGURE SIMPLE HS-3282 DRIVER ALGORITHM
Adapting HS-3282 8-Bit Data
Although designed 16-bit data bus, HS-3282 used systems with 8-bit data adding external components. following example shows this done. Logical Control Figure shows circuitry necessary integrate HS-3282 into system that utilizes 8-bit data bus. circuit very similar Figure primary difference being addition logic circuitry necessary drive input/output latches. primary purpose this additional circuitry latch high order byte data that host system accomplish each 16-bit data transfer with HS-3282 using separate 8-bit operations. Each latches serves specific purpose: output latch provides HS-3282 with high order byte during write operations (PL1, PL2, CWSTR), input latch receives high order byte during read operations (EN1 EN2). outputs these latches should three-stated avoid contention. least significant address used activate latches onto host system data whenever host system performing high order byte operations,
Application Note
this same address inverted added input each function enable gates prevent HS-3282 from being activated same time. During order byte operations, outputs function enable gates used activate latches onto high order byte bidirectional HS-3282, allowing instantaneously transfer full 16-bit word. Since latches automatically activated unison with during order byte operations, high order byte must handled first during write operations that proper data will present output latch when lower byte written BlU. Conversely, order byte must handled first during read operations since high order byte automatically strobed into input latch when order byte read. Timing requirements increased additional logic gates; read operations require minimum pulse equal 200ns plus propagation delays logic gates, one-shot, input latch; write operations require minimum delay from address valid enable equal propagation delays gates minimum pulse 200ns plus propagation delays gates output latch. Note that shots used drive strobes latches. This necessary that falling edge strobe occurs while data still active bus; otherwise, propagation delays additional gates would cause latches close after data been disenabled. Address Decoding system Figure will have same functional addresses system Figure except that this case each particular byte each register address. Therefore, FIFO still located addresses (first word, byte) (second word, byte); however, high bytes must addressed (first word) (second word). receivers addressed same shown Table high speed capability high reliability make especially useful scientific real time operations where large volume data gathering time critical transmission control signals required. These qualities, combination with simplicity with which device incorporated into system, make HS-3282 wise choice wide spectrum applications.
ARINC Specification Brief Overview
ARlNC Specification 429, otherwise known Mark Digital Information Transfer System (DITS), definition standards used extensively transport industry transfer digital data between avionics systems elements. Systems utilizing this standard have been installed wide range aircraft including Boeing 737, 747, 757, 767; European Airbus; Bell Helicopter; large number small aircraft. Replacing earlier ARINC Specification which standardized various forms serial transmission developed during emergent period digital avionics technology, Specification eliminates much previous confusion defining standard single form serial transmission. According Specification 429, digital data transmitted differential signal over uni-directional composed twisted shielded wires. data sent 32-bit words, each word containing parity eight-bit label that defines flight function which remaining data pertains. This data, encoded either numeric (binary BCD) alphabetic (ISO format, further divided into various fields according label type. order completely standardize communication prevent conflicts, flight functions have been assigned particular label data format. ARlNC Specification 429, defining single standard transfer digital information, eliminates need complex interfaces between avionics systems produced different manufacturers. This provides those avionics components that conform this standard with virtual "plug-in" capability, gives such components certain measure universality. more information about this specification, contact Aeronautical Radio, Inc., 2551 Riva Road, Annapolis, Maryland 21401.
Conclusion
Although designed ARINC applications, HS-3282 interface circuit very versatile device, capable serving type communications purpose.
TABLE TYPICAL HS-3282 FUNCTIONAL DECODING USING 8-BIT DATA ADDRESS Byte Byte Word High Byte High Byte Word Byte Byte Word High Byte High Byte Word CWSTR Byte Byte Word CWSTR High Byte High Byte Word CWSTR Byte Byte Word CWSTR High Byte High Byte Word
Application Note
D0-7 OUTPUT LATCH INPUT LATCH BD8-15
CWSTR A3-A7 CHIP SELECT DECODE FUNCTION SELECT DECODE FUNCTION ENABLE TX/R D/R1 D/R2 ENTX HS-3282
INTERRUPT REQUESTS
FIGURE TYPICAL HOST HS-3282 INTERFACE LOGIC USING 8-BIT DATA
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Intersil products sold description only. Intersil Corporation reserves right make changes circuit design, software and/or specifications time without notice. Accordingly, reader cautioned verify that data sheets current before placing orders. Information furnished Intersil believed accurate reliable. However, responsibility assumed Intersil subsidiaries use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Intersil subsidiaries.
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AN400.1 Author: Daniel Clifton Introduction Intersil HS

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