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CMOS 160-BIT SEGMENT DRIVER HIGH VOLTAGE DRIVER DESCRIPTION


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Graphics SED1742/44
CMOS 160-BIT SEGMENT DRIVER HIGH VOLTAGE DRIVER
DESCRIPTION
SED1742/SED1744 matrix segment (column) driver driving high-capacity panels duty cycles higher than 1/100 1/500). features wide range voltages. upper lower drive voltages (V0, independent chip supplies. This enables drive bias voltages supplied from external source. device uses daisy-chain enable system which decreases power consumption eliminates need separate enable signals each driver. SED1742/44 used conjunction with SED1743 (160-bit common driver) drive large-capacity matrix panel.
FEATURES Low-power high-speed CMOS technology 160-bit segment (column) driver High-speed data .4-bit (SED1742) 8-bit (SED1744) Duty cycle .1/100 1/500 Adjustable drive voltages Unbiased display function Adjustable offset bias according VDDH Shift clock frequency .12MHz Ability adjust offset bias source from Daisy chain enable support enable signal controller required Wide range voltage Supply voltage .2.7 5.5V Package.TAB (TOA) bump (D1B)
439-1.0
S-MOS Systems, Inc. River Oaks Parkway Jose, 95134 Tel: (408) 922-0200 Fax: (408) 922-0238
SED1742/44
June 1997 SYSTEM BLOCK DIAGRAM
D0~D3 D0~D7 (SED1744) XSCL YSCL
CONTR
SED1742 SED1743
SED1742
SED1743
DUTY: 1/480
SED1743
S-MOS Systems, Inc. River Oaks Parkway Jose, 95134 Tel: (408) 922-0200 Fax: (408) 922-0238
439-1.0
SED1742/44
June 1997 BLOCK DIAGRAM SED1742
VDDH
160-bit driver
160-bit Level shifter D0~D3 XSCL EIO1 20-bit Enable shift register EIO2 160-bit Latch
160-bit Data register
439-1.0
S-MOS Systems, Inc. River Oaks Parkway Jose, 95134 Tel: (408) 922-0200 Fax: (408) 922-0238
SED1742/44
June 1997 BLOCK DIAGRAM SED1744
VDDH
160-bit driver
160-bit Level shifter D0~D7 XSCL EIO1 10-bit Enable shift register EIO2 160-bit Data register 160-bit Latch
S-MOS Systems, Inc. River Oaks Parkway Jose, 95134 Tel: (408) 922-0200 Fax: (408) 922-0238
439-1.0
SED1742/44
June 1997 DESCRIPTION
Name (SED1742) (SED1744) XSCL EI01, EI02 Function crystal segment (column) output output varies trailing edge. Display data input Display data input Display data shift clock input (triggered trailing edge) Display data latch pulse input (triggered trailing edge) Enable I/O. input output according input level. output reset input when 160-bit data fetch complete. Shift direction selection terminal control input (SED1744) When data input this sequence terminals (D0, D7), relation between data segment output shown table below.
(SEG Output) Output Input Input Output
Note: VCC, VDDH TEST Power Source Power Source
relation between data segment output determined independently number shift locks.
Input signal electrify liquid crystal drive output Logic power source. GND: VCC: Liquid crystal drive power source VDDH: GND: VDDH VDDH, VDDH Forced blank input signal forces output level level. Test input normally level.
439-1.0
S-MOS Systems, Inc. River Oaks Parkway Jose, 95134 Tel: (408) 922-0200 Fax: (408) 922-0238
SED1742/44
June 1997 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings Parameter
Supply voltage range Supply voltage Supply voltage Input voltage Output voltage output current Operating temperature Storage temperature Storage temperature Logic supply Segment driver supply voltage range 25°C Symbol VDDH Topr Tstg1 Tstg2 VDDH +7.0 +45.0 VDDH +0.3 +0.3 +0.3 +150 +150
Unit
VDDH
Notes:
voltage based Voltage should satisfy condition: VDDH GND. storage temperature specified single chip storage temperature mounting. WARNING: externally broken logic system power source floats decreases below while voltage applied liquid crystal drive system power source. Special care should taken power source sequence when turning system power
S-MOS Systems, Inc. River Oaks Parkway Jose, 95134 Tel: (408) 922-0200 Fax: (408) 922-0238
439-1.0
SED1742/44
June 1997 Electrical Characteristics
Parameter Logic supply voltage Operation voltage recommended Segment driver input supply voltage Segment driver input supply voltage Segment driver input supply voltage Segment driver input supply voltage High-level input voltage Low-level input voltage High-level output voltage Low-level utput voltage Symbol VDDH VDDH Function Value recommended Value recommended Value recommended Condition Terminal VDDH VDDH EIO1, EIO2, SED1742 SED1744 XSCL, SHL, 14.0 VDDH 7/9VDDH 0.8VCC 40.0 VDDH 2/9VDDH Unit
0.2VCC
EIO1, EIO2 SED1742 SED1744 XSCL, SHL, EIO1, EIO2
Low-level input leakage current
Input: leakage current output Static current
ILI/O IGND
VDDH 14.0 40.0 VCC, DVON= 0.5V condition recommended VDDH=+30.0V VDDH=+20.0V
Output resistance
RSEG
O159
439-1.0
S-MOS Systems, Inc. River Oaks Parkway Jose, 95134 Tel: (408) 922-0200 Fax: (408) 922-0238
SED1742/44
Parameter Symbol Condition +5.0 VCC, GND, fXSCL =5.38 MHz, =33.6 kHz, Input data: Display checkered, load +3.0 Other condi tions: same +5.0 Average Operation current consumed VDDH +30.0 +5.0 +4.0 +26.0 Other conditions: same +5.0 Terminal Unit
Average Operation current consumed
IDDH
VDDH
Input capacitance
Freq.=1 MHz, 25°C Single chip
SED1742 SED1744 XSCL, SHL, EIO1, EIO2
terminal capacity
CI/O
Notes:
voltage based Voltage should satisfy condition: VDDH GND.
S-MOS Systems, Inc. River Oaks Parkway Jose, 95134 Tel: (408) 922-0200 Fax: (408) 922-0238
439-1.0
SED1742/44
June 1997 Operating Voltage Range
maximum supply voltage, VDDH depends shown following figure. Specify VDDH voltage within operation.
VDDH
Operation voltage range
439-1.0
S-MOS Systems, Inc. River Oaks Parkway Jose, 95134 Tel: (408) 922-0200 Fax: (408) 922-0238
SED1742/44
June 1997 Electrical Characteristics
Input Timing Characteristics
tWLH XSCL D0~D3: SED1742 D0~D7: SED1744 EIO1,2 (IN) tWCH tWCL
tSUE
Note: Adjust timing pulse input high-speed operation, excluding clock XSCL.
S-MOS Systems, Inc. River Oaks Parkway Jose, 95134 Tel: (408) 922-0200 Fax: (408) 922-0238
439-1.0
SED1742/44
(VCC ±10%, 75°C) Parameter XSCL cycle XSCL high-level pulse width XSCL low-level pulse width Data setup time Data hold time XSCL rise time XSCL breaking time high-level pulse width Symbol tWCH tWCL tWLH Condition Unit
Note: tWLH defines time duration when XSCL
(VCC 75°C) Parameter XSCL cycle XSCL high-level pulse width XSCL low-level pulse width Data setup time Data hold time XSCL rise time XSCL breaking time high-level pulse width delay allowance time setup time Symbol tWCH tWCL tWLH tSUE Condition Unit
Note: tWLH defines time duration when XSCL
439-1.0
S-MOS Systems, Inc. River Oaks Parkway Jose, 95134 Tel: (408) 922-0200 Fax: (408) 922-0238
SED1742/44
June 1997 Output Timing Characteristics
tFRSD XSCL EIO1,2 (OUT) tDCL tLSD
(VCC +5.0 ±10%, VDDH 14.0 40.0 Parameter reset time output delay time output delay time output delay time Symbol tDCL tLSD tFRSD Condition (EIO) (On) Unit
(VCC +5.0 ±10%, VDDH 14.0 40.0 Parameter reset time output delay time output delay time output delay time Symbol tDCL tLSD tFRSD Condition (EIO) (On) Unit
S-MOS Systems, Inc. River Oaks Parkway Jose, 95134 Tel: (408) 922-0200 Fax: (408) 922-0238
439-1.0
SED1742/44
June 1997 Timing Diagrams 1/240 Duty Cycle
Latch data
XSCL
Notes: circled numerals denote position device chain. cycle XSCL should lengthened satisfy when high-speed data transfer takes place.
439-1.0
S-MOS Systems, Inc. River Oaks Parkway Jose, 95134 Tel: (408) 922-0200 Fax: (408) 922-0238
SED1742/44
Latch data
S-MOS Systems, Inc. River Oaks Parkway Jose, 95134 Tel: (408) 922-0200 Fax: (408) 922-0238
439-1.0
SED1742/44
June 1997 FUNCTIONAL DESCRIPTION Enable Shift Register
enable shift register bi-directional shift register, where shift direction selected SHL. also used latch data from data into data register. effect shift direction input data sequence shown following table. Data Sequence Shift Direction Outputs O159 O158 O157 Shift Direction EIO1 Output Input EIO2 Input Output
When enable signal inactive, SED1742 standby mode with internal clock stopped data held LOW. When multiple SED1742s used, enable input first device should connected ground enable input each successive device should connected enable output preceding device. When data bits have been latched into SED1742, enable output edge goes LOW, eliminating need external control circuit.
Data Register
data register converts input data into parallel display driver data under control enable shift register.
439-1.0
S-MOS Systems, Inc. River Oaks Parkway Jose, 95134 Tel: (408) 922-0200 Fax: (408) 922-0238
SED1742/44
June 1997 APPLICATION NOTES Voltage Levels
recommended method generating drive voltages, with voltage divider between VDDH VGND, buffered with voltage followers. lower drive level, necessarily VGND, separate pins used voltage levels when op-amps used. maximum voltage differential between VGND 2.5V recommended since driver efficiency decreases differential increases. Connect when using op-amps. resistances voltage divider resistors should possible within power supply constraints. Note that fluctuations IDDH cause dips VDDH supply. device will damaged voltage dips below point where relationship VDDH (V0) VGND breaks down. stabilized power supply required when using resistor network.
Data Latch
data latch latches data into level shifter falling edge
Level Shifter
level shifter converts logic-level signals from latch into driver input voltage levels.
Drivers
drivers generate drive waveforms. output voltages determined polarity signal, shown following table. Driver Output Voltage Input Data
care
Output Voltage (VDDH)
S-MOS Systems, Inc. River Oaks Parkway Jose, 95134 Tel: (408) 922-0200 Fax: (408) 922-0238
439-1.0
SED1742/44
June 1997 Power-Up Power-Down Precautions
driver circuitry operates high voltage, care should taken when applying removing power SED1742 prevent damage. driver supply applied when logic supply either connected below 2.9V, excess current will flow into SED1742 damage device. Normal operation guaranteed correct power-up power-down sequences followed. Power-Up Sequence: Power should applied before, same time power applied driver circuitry. Power-Down Sequence: Power should removed from after, same time power removed from driver circuitry. SED1742 also damaged output drivers start operating before driver supplies stabilize. should held hold driver outputs until driver supplies have stabilized. extra precaution, insert fast-blow fuse series with driver supply.
439-1.0
S-MOS Systems, Inc. River Oaks Parkway Jose, 95134 Tel: (408) 922-0200 Fax: (408) 922-0238
SED1742/44
June 1997 LAYOUT SED1742D1B
D1742D1B
(0,0)
Chip Size Chip Thickness Pitch
7.30mm 4.48mm 525mm 25mm 108mm (Min.)
Gold bump dimensions (SED1742D1B): Size Size Size 20mm (pads 1~15, 39~183) 20mm (pads 16~33, 20mm (pads 34~37)
S-MOS Systems, Inc. River Oaks Parkway Jose, 95134 Tel: (408) 922-0200 Fax: (408) 922-0238
439-1.0
SED1742/44
June 1997 COORDINATES
Name O145 O146 O147 O148 O149 O150 O151 O152 O153 O154 O155 O156 O157 O158 O159 EIO2 EIO1 XSCL TEST VDDH Coordinates 1034 1195 1357 1550 1712 Name Coordinates 1820 1929 2037 2145 2253 2362 2470 2578 2687 2795 2903 3012 3120 3228 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 Name Coordinates 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3195 3087 2978 2870 2762 2553 2545 2437 2328 2220 2112 2004 1895 1787 1679 1570 1462 1354 1245 1137 1029 1083 1191 1300 1408 1516 1625 1733 1841 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 Name O100 O101 O102 O103 O104 O105 O106 O107 O108 O109 O110 O111 O112 O113 O114 O115 O116 O117
unit:
Coordinates 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 1841 1733 1625 1516 1408 1300 1191 1083
439-1.0
S-MOS Systems, Inc. River Oaks Parkway Jose, 95134 Tel: (408) 922-0200 Fax: (408) 922-0238
SED1742/44
Name O118 O119 O120 O121 O122 O123 O124 Coordinates Name O125 O126 O127 O128 O129 O130 O131 Coordinates Name O132 O133 O134 O135 O136 O137 O138 Coordinates Name O139 O140 O141 O142 O143 O144 Coordinates
S-MOS Systems, Inc. River Oaks Parkway Jose, 95134 Tel: (408) 922-0200 Fax: (408) 922-0238
439-1.0
SED1742/44
June 1997 LAYOUT SED1744D1B
D17441B
(0,0)
Chip Size Chip Thickness Pitch
7.30mm 4.48mm 525mm 25mm 108mm (Min.)
Gold bump dimensions (SED1744sD1B): Size Size Size 20mm (pads 1~15, 39~183) 20mm (pads 16~33, 20mm (pads 34~37)
439-1.0
S-MOS Systems, Inc. River Oaks Parkway Jose, 95134 Tel: (408) 922-0200 Fax: (408) 922-0238
SED1742/44
June 1997 COORDINATES
Name O145 O146 O147 O148 O149 O150 O151 O152 O153 O154 O155 O156 O157 O158 O159 EIO2 EIO1 XSCL TEST VDDH Coordinates 1034 1195 1357 1550 1712 Name Coordinates 1820 1929 2037 2145 2253 2362 2470 2578 2687 2795 2903 3012 3120 3228 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 Name Coordinates 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3195 3087 2978 2870 2762 2553 2545 2437 2328 2220 2112 2004 1895 1787 1679 1570 1462 1354 1245 1137 1029 1083 1191 1300 1408 1516 1625 1733 1841 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 Name O100 O101 O102 O103 O104 O105 O106 O107 O108 O109 O110 O111 O112 O113 O114 O115 O116 O117
unit:
Coordinates 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 1841 1733 1625 1516 1408 1300 1191 1083
S-MOS Systems, Inc. River Oaks Parkway Jose, 95134 Tel: (408) 922-0200 Fax: (408) 922-0238
439-1.0
SED1742/44
June 1997 COORDINATES (CONT.)
Name O118 O119 O120 O121 O122 O123 O124 Coordinates Name O125 O126 O127 O128 O129 O130 O131 Coordinates Name O132 O133 O134 O135 O136 O137 O138 Coordinates Name O139 O140 O141 O142 O143 O144
unit:
Coordinates
439-1.0
S-MOS Systems, Inc. River Oaks Parkway Jose, 95134 Tel: (408) 922-0200 Fax: (408) 922-0238
SED1742/44
June 1997 SED1742 TAPE-CARRIER PACKAGE Tape-Carrier Pinout
SEG159 EIO2 EIO1 XSCL TEST VDDH SEG0
S-MOS Systems, Inc. River Oaks Parkway Jose, 95134 Tel: (408) 922-0200 Fax: (408) 922-0238
439-1.0
SED1742/44
June 1997 Tape-Carrier Dimensions
35.00
0.025 28.98 0.015
0.01
12.2
12.2
4.75
SEG159 EIO2
1.98
EIO1
-11.51 -5.755
NCx2 SEG159
15.860
2.50
(0.18P 165) 0.09 29.7
0.08 NCx2
(P1.0
26.00
TEST VDDH
0.06
XSCL
11.51 5.755
SEG0
0.60
8.62
5.15
0.40
2.42
5.13
0.97
0.15
0.80
0.06
0.02
0.09
0.02
0.09
439-1.0
0.52
1.00
15.86
0.03
15.86
0.40
0.03
S-MOS Systems, Inc. River Oaks Parkway Jose, 95134 Tel: (408) 922-0200 Fax: (408) 922-0238
SED1742/44
June 1997 SED1744 TAPE-CARRIER PACKAGE Tape-Carrier Pinout
SEG159 EIO2 EIO1 XSCL TEST VDDH SEG0
S-MOS Systems, Inc. River Oaks Parkway Jose, 95134 Tel: (408) 922-0200 Fax: (408) 922-0238
439-1.0
SED1742/44
June 1997 Tape-Carrier Dimensions
35.00
0.025 28.98 0.015
0.01
12.2
12.2
4.75
SEG159 EIO2
1.98
EIO1
-11.51 -5.755
NCx2 SEG159
15.860
2.50
(0.18P 165) 0.09 29.7
0.08 NCx2
(P1.0
26.00
TEST VDDH
0.06
XSCL
11.51 5.755
SEG0
0.60
8.62
5.15
0.40
2.42
5.13
0.97
0.15
0.80
0.06
0.02
0.09
0.02
0.09
439-1.0
0.52
1.00
15.86
0.03
15.86
0.40
0.03
S-MOS Systems, Inc. River Oaks Parkway Jose, 95134 Tel: (408) 922-0200 Fax: (408) 922-0238
SED1742/44
S-MOS assumes responsibility liability errors inaccuracies contained information herein information portion thereof application, including claim copyright patent infringement direct, indirect, special consequential damages. There warranties extended granted this document. information herein subject change without notice from S-MOS. June 1997 Copyright 1997 S-MOS Systems, Inc. Printed U.S.A. RDG.
S-MOS Systems, Inc. River Oaks Parkway Jose, 95134 Tel: (408) 922-0200 Fax: (408) 922-0238
439-1.0

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