SED1743 CMOS 160-bit Common Driver Power SED1743 common driv
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SED1743
SED1743
CMOS 160-bit Common Driver Power
SED1743 common driver high-resolution dot-matrix panels, which incorporates driver outputs. designed conjunction with SED1742 SED1744 column drivers. SED1743 features wide range drive voltages. upper lower drive voltages, independent chip supplies. This enables drive bias voltages supplied from external source. result, SED1743 compatible with large range panels. SED1743 uses daisy-chain enable system which decreases power consumption eliminates need separate enable signals each driver. SED1743 operates from 5.5V supply available both chip packages tape-carrier packages (TCPs). FEATURES
common drive outputs Pin-selectable output shift direction Adjustable drive voltages Duty cycles 1/480 Zero-bias display disable function
Silicon-gate CMOS technology typical output impedance drive voltages 5.5V supply Chip (SED1743D1B) tape-carrier (SED1743T0A) packages
SYSTEM BLOCK DIAGRAM
VDDH
160-Segment Driver
160-bit Level Shifter
DIO1 YSCL 2-bit Bidirectional Shift Register
DIO2
Clock Stopped Detector
SED1743
BLOCK DIAGRAM
VDDH
driver, 160-bit
Level shifter, 160-bit DIO1 YSCL Clock stop detector Two-way shift register 2-bit
DIO2
SED1743
DESCRIPTION Terminal Name DIO2 DIO1 Function Common (row) output liquid crystal display
DI01 DI02 data onput/output bi-directional shift register; either selected input output setting. 2-bit two-way shift register scan pulse input sets terminal input output. output varies YSCL trailing edge. input terminal scan pulse when configuration used.
Q'ty
Shift register mode selection input (DI3 input) 160, also connect Serial data shift clock input; negative edge triggered Shift direction select input (Output shift direction) DIO1 DIO2 Input Output Output Input
YSCL
VCC, VDDH
Power Source Power Source
Common drive signal polarity select input Logic power source. GND: VCC: Liquid crystal drive power source GND: VDDH: VDDH (V0) VDDH, VDDH Display blanking input Low-level input sets common outputs level. Stop detector clock input Signal input AND-ed with stop detect output, equipped with internal pull-down resistor charge hold terminal, Capacitor externally mounted between charge hold terminal, Capacitor resistor externally mounted between Clock stop detector output NAND gate input internal pull-down resistor NAND gate input NAND gate output Scan pulse input when mode
SED1743
ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings
Parameter Supply voltage range Supply voltage Supply voltage Input voltage Output voltage output current Operating temperature Storage temperature Storage temperature
Symbol VDDH Topr Tstg Tstg
Ratings -0.3 +7.0 -0.3 +45.0 -0.3 VDDH +0.3 -0.3 +0.3 -0.3 +0.3 +150 +100
Unit
VDDH (V0)
Notes: voltage based storage temperature specified single chip storage temperature mounting. Voltage should satisfy condition: VDDH (V0) GND. CAUTION: externally broken logic system power source floats decreases below VCC=2.6 while voltage applied liquid crystal drive system power source. Special care should betaken power source sequence when turning system power off.
Recommended Operating Conditions Parameter Logic supply voltage Segment driver supply voltage range Symbol VDDH Rating
25°C Unit 25°C
Parameter Logic supply voltage Segment driver supply voltage range
Symbol VDDH
Rating
Unit
SED1743
Electrical Characteristics (Unless otherwise specified, GND=V5=0V,
Parameter Logic supply voltage
Operation voltage recommended
+5.0V ±10%, 75°C) 0.65
1/9VDDH
Symbol VDDH
Condition
Terminal VDDH VDDH
DIO1, DIO2, DI3, SEL, YSCL, SHL,
8/9VDDH
Unit
Common driver supply voltage VDDH (V0) Function Common driver supply voltage Value recommended Common driver supply voltage Value recommended High level input voltage level input voltage High level output voltage level output voltage Low-level input leakage current
High-level input leakage current
0.8VCC
ILI/O IGND RCOM
0.2VCC
-0.3 DIO1, DIO2 -0.4
OP1,
DI3, SEL, YSCL, SHL,
VDDH 14.0 40.0 VCC,
0.5V
IP2,
DIO1, DIO2
Input/Output leak current Static current Output resistance
O159
VDDH=+30.0V VDDH=+20.0V
condition recommended
Average operation current consumed
+5.0 VCC, GND, fXSCL =33.6 kHz, Input data: 1/480, load -VCC +3.0 Other condition: Same VDDH +30.0 +28.0 +2.0 +0.0 +5.0 Other condition: same
VDDH
Average operation current consumed
IDDH
Input capacitance
Freq.=1 MHz, 25°C Single chip
DI3, SEL, YSCL, SHL,
terminal capacity
CI/O
DIO1, DIO2
SED1743
Operation Voltage Range voltage, maximum supply
DDH, depends shown following figure. Specify VDDH voltage within VCC-VDDH operation.
VDDH
Operation voltage range
Electrical Characteristics Input Timing Characteristics
tDFR YSCL DIO1,2 (IN) tWCLH tWCLL
tCCL
(VCC ±10%, 75°C) Parameter YSCL cycle YSCL high-level pulse width YSCL low-level pulse width Data setup time Data hold time delay allowance time Input signal rise time Input signal breaking time Symbol Condition -300 +300 Unit
tCCL tWCLH tWCLL tDFR
SED1743
(VCC 75°C) Parameter YSCL cycle YSCL high-level pulse width YSCL low-level pulse width Data setup time Data hold time delay allowance time Input signal rise time Input signal breaking time Symbol Condition -400 Unit
tCCL tWCLH tWCLL tDFR
Output Timing Characteristics
tpdCFR YSCL DIO1,2 (OUT) (COM) tdT2 tpdCINH tpdDOCL tpdCCL
tdT1
SED1743
(VCC +5.0 ±10%, VDDH 40.0 Unit VDDH 14.0 40.0 4C2R2 cycle
Parameter YSCL YSCL output delay time output delay time output delay time output delay time output delay time output release time output delay time output release time
Symbol
Condition
tpdDOCL tpdCCL tpdCINH tpdCFR tdT1 tdT2
Parameter YSCL YSCL output delay time output delay time output delay time output delay time output delay time output release time output delay time output release time
Symbol
(VCC VDDH 140.0 28.0 Condition Unit VDDH 14.0 40.0 4C2R2 cycle
tpdDOCL tpdCCL tpdCINH tpdCFR tdT1 tdT2
Note: Scan Start Pulse C2R2, Clock stop detector circuit.
SED1743
Timing Diagrams 1/240 Duty Cycle
frame (240 lines) DIO1
YSCL
lines DIO2 lines
SED1743
FUNCTIONAL DESCRIPTION Shift Register
shift register bi-directional shift register, where shift direction selected SHL. effect shift direction input data sequence shown following table. Data Sequence Shift Direction Outputs Shift Direction DIO1 DIO2 Input Output Output Input
O159
O158
O157
used select operating mode shift register. When HIGH, mode selected. When LOW, mode selected.
Level Shifter level shifter converts logic-level signals from latch into driver input voltage levels. Drivers drivers generate drive waveforms. output voltages determined polarity signal, shown following table. Driver Output Voltage Input Data
don't care
Output Voltage (VDDH)
APPLICATION NOTES Voltage Levels
recommended method generating drive voltages, with voltage divider between VDDH VGND, buffered with voltage followers. lower drive level, necessarily VGND, separate pins used voltage levels when op-amps used. maximum voltage differential between VGND 2.5V recommended since driver efficiency decreases differential increases. Connect when using op-amps. resistances voltage divider resistors should possible within power supply constraints. Note that fluctuations IDDH cause dips VDDH supply. device will damaged voltage dips below point where relationship VDDH (V0) VGND breaks down. stabilized power supply required when using resistor network.
SED1743
Clock Monitor panel damaged signal applied segments. This situation occur when drive clock stops while power applied display. clock monitor circuit detects this condition sends LOW. connected INH, display protected from damage.
Power-Up Power-Down Precautions driver circuitry operates high voltage, care should taken when applying removing power SED1743 prevent damage. driver supply applied when logic supply either connected below 2.9V, excess current will flow into SED1742 damage device. Normal operation guaranteed correct power-up power-down sequences followed. Power-Up Sequence: Power should applied before, same time power applied driver circuitry. Power-Down Sequence: Power should removed from after, same time power removed from driver circuitry. SED1743 also damaged output drivers start operating before driver supplies stabilize. should held hold driver outputs until driver supplies have stabilized. additional protective measure, insert fast-blow fuse series with driver supply.
Clock Monitor Circuit clock monitor circuit sets whenever clock signals from controller stops. Connecting ensures that does flow into panel.
SED1743 (No.
DIO1
SED1743 (No.
DISP
SED1742/44
typically several determined while monitoring OP1. should much larger than Typical values under various signal conditions shown following table. Input Signal .1µF .1µF
Notes: 17.8 duty 0.14% 40.4 duty 0.35% 3.53 duty When clock monitor feature required, IP1, IP2, LOW, leave OP1, OPEN.
SED1743
CIRCUIT DIAGRAM REFERENCE
(Combination SED1742 with SED1743)
VDDH
YSCL
SED1743 DIO1
DIO2 SED1743 DIO1
(YDL)
DIO2 SED1743 DIO1 DIO2 SED1742 EIO1 EIO2
(1/480 DUTY)
SED1742 EIO1 EIO2
SED1742 EIO1 EIO2
SED1742 EIO1 EIO2
XSCL
(Combination SED1744 with SED1743)
VDDH
YSCL
SED1743 DIO1
DIO2 SED1743 DIO1 DIO2 SED1743 DIO1 DIO2 SED1744 EIO1 EIO2 XSCL
(YDL)
(1/480 DUTY)
SED1744 EIO1 EIO2
SED1744 EIO1 EIO2
SED1744 EIO1 EIO2
SED1743
LAYOUT SED1742/3/4 (D1B Version)
Chip Size 7.30mm 4.48mm Pitch 108µm (Min.) Chip Thickness 525µm 25µm Bump Bump Size Bump Size Bump Size Bump Height 72µm 93µm 93µm 106µm 93µm 93µm 28µm (Pad Nos. 1~15, 39~183) (Pad Nos. 16~33, (Pad Nos. 34~37)
SED1743
COORDINATES
Name DIO2 DIO1 YSCL VDDH -3228 -3120 -3012 -2903 -2795 -2687 -2578 -2470 -2362 -2253 -2145 -2037 -1929 -1820 -1712 -1550 -1417 -1284 -1151 -1018 -885 -752 -619 -486 -353 -220 1034 1195 1357 1550 1712 1820 -2064 -2064 -2064 -2064 -2064 -2064 -2064 -2064 -2064 -2064 -2064 -2064 -2064 -2064 -2064 -2058 -2058 -2058 -2058 -2058 -2058 -2058 -2058 -2058 -2058 -2058 -2058 -2058 -2058 -2058 -2058 -2058 -2058 -2026 -2026 -2026 -2026 -2058 -2064 -2064 Name 1929 2037 2145 2253 2362 2470 2578 2687 2795 2903 3012 3120 3228 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 3474 -2064 -2064 -2064 -2064 -2064 -2064 -2064 -2064 -2064 -2064 -2064 -2064 -2064 -1841 -1733 -1625 -1516 -1408 -1300 -1191 -1083 -975 -866 -758 -650 -542 -433 -325 -217 -108 Name 3474 3474 3474 3474 3474 3474 3474 3474 3195 3087 2978 2870 2762 2653 2545 2437 2328 2220 2112 2004 1895 1787 1679 1570 1462 1354 1245 1137 1029 -162 1083 1191 1300 1408 1516 1625 1733 1841 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064
SED1743
Name
-271 -379 -487 -596 -704 -812 -921 -1029 -1137 -1245 -1354 -1462 -1570 -1679 -1787 -1895 -2004 -2112 -2220 -2328 -2437 -2545 -2653 -2762 -2870 -2978 -3087 -3195 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474
2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 2064 1841 1733 1625 1516 1408 1300 1191 1083
Name
-3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474 -3474
-108 -217 -325 -433 -542 -650 -758 -866 -975 -1083 -1191 -1300 -1408 -1516 -1625 -1733 -1841
SED1743
TAPE CARRIER PACKAGE PINOUT
DIO2 DIO1 YSCL VDDH
TAPE CARRIER PACKAGE DIMENSIONS
Cleanly- punched hole 15.88±0.03 29.7±0.06 (0.18P 165) W:0.09 0.15 15.88±0.03
0.97 12.2 5.15
0.025 28.98±0.015
0.4-2
0.525 5.13
0.78
2.42
11.51 -5.755
12.2
1.00 1.98
0.40 4.75 0.01 26.00 0.06 (P1.00 W:0.4
0.06 0.02
0.09 0.02 0.09
1.00
8.62
0.40
15.860 11.51 -5.755
origin
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