CMOS MATRIX HIGH DUTY DRIVER High Voltage Resistant 80-bit 1/300
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SED1601
CMOS MATRIX HIGH DUTY DRIVER
High Voltage Resistant 80-bit 1/300 Display Duty Output 1/100 CMOS High Voltage Resistant Process
SED1601 80-output matrix segment (column) driver driving high-capacity panel duty cycles higher than 1/100 1/300). wide range driving voltages. architecture SED1601, driving voltage, isolated from supply. This provides ability adjust offset bias independently VDD. These unique features allow SED1601 interface with variety panels. SED1601 does require controller output enable signal implement daisy chain technology. This provides easy interfacing with controllers such SED1330, SED1351, SED1335 SED1341. SED1601 used conjunction with SED1610 driver) SED1630 (68-bit driver) SED1631 (100 driver) SED1632 (86-bit driver), SED1633 (100-bit driver) SED1634 (100-bit driver) drive large-capacity matrix panel.
FEATURES
Low-power CMOS technology 80-bit segment (column) driver High-speed 8-bit Duty cycle 1/100 1/300 Output shift direction selectable Shift clock frequency 6.5MHz Ability adjust offset bias source from
Daisy chain enable support enable signal controller required Wide range voltage -12V -28V Supply voltage 5.0V QFP5-100 Package DIE: padpin (F(D) chip
SYSTEM BLOCK DIAGRAM
XSCL YSCL
CONTR
SED1601 SED1630
SED1601
SED1601
SED1601
DUTY: 1/136
SED1630
SED1601
BLOCK DIAGRAM
Level Shifter
Voltage Control
Driver
EIO1 EIO2 XSCL
Register Data Control
Register
Enable Control
Clock Generator
PINOUT
SEG79 SEG78 SEG77 SEG76 SEG75 SEG74 SEG73 SEG72 SEG71 SEG70 SEG69 SEG68 SEG67 SEG66 SEG65 SEG64 SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50
EIO2 XSCL EIO1
SEG79
SEG0 SEG1 SEG2
SED1601
Index
SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30
SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29
SED1601
DESCRIPTION Name SEG0 SEG79 XSCL EI01, EI02 Function driving segment (column) outputs. Each output changes falling edge Display data inputs. Shift clock display data (falling edge trigger). Latch pulse display data (falling edge trigger). Enable I/O, which controlled input. Output reset automatically falls when bits data taken Shift direction selection control. When data input pins (D7, respectively, following relation established between data segment outputs: VDD, Power Supplies Power Supplies Output Intput Input Output
signal driving outputs. Logic circuit power. driving power. VDD: (GND) VSS: -5.0
ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings
(VDD Parameter Supply voltage Supply voltage Supply voltage Input voltage Output voltage Output current Output current Allowable power dissipation Operating temperature Storage temperature Soldering temperature, time Symbol IOSEG Topr Tstg Tsol Ratings -7.0 +0.3 -30.0 +0.3 -0.3 +0.3 -0.3 +0.3 -0.3 +0.3 +150 260°C, lead) Unit
must always satisfy condition:
SED1601
Electrical Characteristics Parameter Symbol ILI/O -0.6 -12.0 -28.0 VDD, -20.0V Output resistance RSEG Recommended value Recommended value Recommended value Condition
(Unless otherwise specified, -5.0 10%, 75°C)
EI01, EI02, XSCL,
-5.5 -28.0 -2.5 0.2VSS -0.4
-5.0
-4.5 -12.0 -8.0 0.8VSS VSS+0.4
Unit
Operating voltage Recommended voltage Minimum operating voltage Operating voltage Operating voltage Operating voltage input voltage input voltage output voltage output voltage Input leakage current Stand-by current
EI01, EI02
XSCL, SHL,
EI01, EI02
IDDS
|VON| 0.5V -14.0V SEG0 SEG79 -8.0V
-5.0 VSS, fXSCL 1.92 kHz, Frame period Input data: Inverted bit; No-load -5.0 -4.0 -16.0 -20.0 other conditions same ISSO1
Current dissipation
ISSO1
Current dissipation
ISSO2
Input capacitance
CI/O
25°C
XSCL, SHL,
15.0
EI01, EI02
SED1601
Electrical Characteristics Parameter XSCL period XSCL pulse width XSCL pulse width Data setup time Data hold time XSCL-rise LP-rise time XSCL-fall LP-fall time LP-rise XSCL-rise time LP-fall XSCL-fall time pulse width pulse width Allowable delay time Enable setup time Enable hold time Enable setup time Enable hold time Input signal rise time Input signal fall time Symbol Conditions
(VSS -5.0 ±10%, 75°C) -500 Unit
tCCL tWCLH tWCLL tWLPH tWLPL tDFR tsuEIH thEIH tsuEIL thEIL
Note: specifications provided prevent malfunction which occur when noise mixed with slow-down signal. assure high-speed XSCL, both must satisfy following relation:
tCCL (tWCLH tWCLL)
SED1601
Timing Chart Input Timing
XSCL
output
output
through each show cascade number driver.
tWLPH tDFR tWLPL tCCL tWCLH tWCLL
XSCL
tsuEIH
thEIL thEIH tsuEIL
EIO1 EIO2
SED1601
Output Timing
XSCL
tpdEOLLP tpdEOHCL tpdSLP tpdSFR
-0.5V +0.5V
tpdEOLCL
EIO1 EIO2 output
(VSS -5.0 ±10%, 75°C) Parameter (LP-rise disable) time (XSCL-fall disable) time (XSCL-fall enable) time (LP-fall output) time output) delay time Symbol Conditions XSCL -12.0 -28.0 Unit
tpdEOLLP tpdEOLCL tpdEOHCL tpdSLP tpdSFR
SED1601
EXAMPLE APPLICATION (SED1601) (for MATRIX LCD)
CONTROLLER
YSCL DIO1 DIO2 SED1630
SED1630
YSCL DIO1 DIO2
MATRIX PANEL
YSCL DIO1 DIO2 SED1630
SED1601
SED1601
SED1601
XSCL
XSCL
VSSH XSCL
Note: sure connect current limiter resistor. Also, connect decoupling capacitors (0.01µF) near pins each noise protection.
XSCL
EIO2 EIO1
EIO2 EIO1
EIO2 EIO1
SED1601
LAYOUT (SED1601DAA)
(0,0)
(0,0)
Chip Size Pitch Dimension Chip Thickness
6.20mm 4.59mm 0.18mm (MIN.) 0.1mm 0.1mm 0.4mm±0.025mm
SED1601
COORDINATES (SED1601DAA)
Name SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 -2700 -2503 -2306 -2109 -1912 -1714 -1534 -1354 -1174 -994 -813 -633 -453 -273 1169 1349 1529 1709 1907 2104 2301 2498 2695 2925 2925 2925 2925 2925 2925 2925 2925 2925 2925 -2120 -2120 -2120 -2120 -2120 -2120 -2120 -2120 -2120 -2120 -2120 -2120 -2120 -2120 -2120 -2120 -2120 -2120 -2120 -2120 -2120 -2120 -2120 -2120 -2120 -2120 -2120 -2120 -2120 -2120 -1895 -1669 -1443 -1217 -991 -811 -631 -450 -270 Name SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 2925 2925 2925 2925 2925 2925 2925 2925 2925 2925 2685 2498 2301 2104 1907 1709 1529 1349 1169 -273 -453 -633 -813 -994 -1174 -1354 -1534 -1714 -1912 -2109 -2306 -2503 -2700 1217 1443 1689 1896 2120 2120 2120 2120 2120 2120 2120 2120 2120 2120 2120 2120 2120 2120 2120 2120 2120 2120 2120 2120 2120 2120 2120 2120 2120 2120 2120 2120 2120 2120 Name SEG0 SEG29 SEG50 SEG79 -2925 2925 2925 -2925 -2120 -2120 2120 2120 Name EIO2 XSCL EIO1 -2925 -2925 -2925 -2925 -2925 -2925 -2925 -2925 -2925 -2925 -2925 -2925 -2925 -2925 -2925 -2925 -2925 -2925 -2925 -2925 1896 1669 1443 1217 -270 -450 -631 -811 -991 -1217 -1443 -1669 -1895
These pads located corner: Nos. 30F, 51F, 80F. They have same function Nos.
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