CMOS 80-SEGMENT DRIVER High Voltage Output 80-bit 1/300 Display D
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SED1600
CMOS 80-SEGMENT DRIVER
High Voltage Output 80-bit 1/300 Display Duty 1/100
SED1600 matrix segment (column) driver driving high-capacity panel duty cycles higher than 1/100 1/300). wide range driving voltages. architecture SED1600, driving voltage, isolated from supply. This provides ability adjust offset bias independently VDD. These unique features allow SED1600 interface with variety panels. SED1600 does require controller output enable signal implement daisy chain technology. This provides easy interfacing with controllers such SED1330, SED1351, SED1335, SED1341. SED1600 used conjunction with SED1610 (86-row driver), SED1630 (68-bit driver), SED1631 (100-row driver), SED1632 (86-bit driver), SED1633 (100-bit driver), SED1634 (100bit driver) drive large-capacity matrix panel. FEATURES
Low-power CMOS technology 80-bit segment (column) driver High-speed 4-bit data with enable chain technology Duty cycle 1/100 1/300 Shift clock frequency 6MHz Ability adjust offset bias source from
Daisy chain enable support Selectable output shift direction enable signal controller required Wide range voltage -28V Supply voltage 5.0V Package QFP5-100
DIE:
chip (DAA) bump (DAB)
SYSTEM BLOCK DIAGRAM
XSCL YSCL
CONTR
SED1600F
SED1600F
DRIVER 100~300
n*80 DUTY: 1/100 1/300
SED1600
BLOCK DIAGRAM
Level Shifter
Voltage Control
Driver
Register
EIO1 EIO2 XSCL
Data Control
Register
Enable Control
Clock Generator
PINOUT
SEG79 SEG78 SEG77 SEG76 SEG75 SEG74 SEG73 SEG72 SEG71 SEG70 SEG69 SEG68 SEG67 SEG66 SEG65 SEG64 SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50
EIO2 XSCL EIO1
SEG79
SEG0 SEG1 SEG2
Index
SED1600
SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30
SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29
Connection
SED1600
DESCRIPTION Name SEG0 SEG79 XSCL EI01, EI02 Function driving segment (column) outputs Each output changes falling edge Display data inputs. Shift clock display data (falling edge trigger). Latch pulse display data (falling edge trigger). Enable I/O, which controlled input Output reset automatically falls when bits data taken Shift direction selection control. When data input pins (D3, respectively, following relation established between data segment outputs: VDD, Power Supplies Power Supplies Output Input Input Output
signal driving outputs. Logic circuit power. driving power. VDD: (GND) VSS: -5.0
ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings
(VDD Symbol IOSEG Topr Tstg Tsol Ratings -7.0 +0.3 -30.0 +0.3 -0.3 +0.3 -0.3 +0.3 -0.3 +0.3 +150 260°C, lead) Unit
Parameter Supply voltage Supply voltage Supply voltage Input voltage Output voltage Output current Output current Allowable power dissipation Operating temperature Storage temperature Soldering temperature, time
must always satisfy condition
SED1600
Electrical Characteristics Parameter Symbol ILI/O -0.6 -12.0 -28.0 VDD, -20.0V Output resistance RSEG Recommended value Recommended value Recommended value Condition
(Unless otherwise specified, -5.0 10%, 85°C)
EI01, EI02, XSCL,
-5.5 -28.0 -2.5 0.2VSS -0.4
-5.0
-4.5 -12.0 -8.0 0.8VSS VSS+0.4
Unit
Operating voltage Recommended voltage Minimum operating voltage Operating voltage Operating voltage Operating voltage input voltage input voltage output voltage output voltage Input leakage current Stand-by current
EI01, EI02
XSCL, SHL,
EI01, EI02
IDDS
|VON| 0.5V -14.0V SEG0 SEG79 -8.0V
-5.0 VSS, fXSCL =1.92 kHz, Frame period Input data: Inverted bit, No-load -5.0 -4.0 -16.0 -20.0 other conditions same ISSO1
Current dissipation
ISSO1
Current dissipation
ISSO2
Input capacitance
CI/O
25°C
XSCL, SHL,
15.0
EI01, EI02
SED1600
Electrical Characteristics Parameter XSCL period XSCL pulse width XSCL pulse width Data setup time Data hold time XSCL-rise LP-rise time XSCL-fall LP-fall time LP-rise XSCL-rise time LP-fall XSCL-fall time pulse width pulse width Allowable delay time Enable setup time Enable hold time Enable setup time Enable hold time Input signal rise time Input signal fall time Symbol Conditions
(VSS -5.0 ±10%, 85°C) -500 Unit
tCCL tWCLH tWCLL tWLPH tWLPL tDFR tsuEIH thEIH tsuEIL thEIL
Note: specifications provided prevent malfunction which occur when noise mixed with slowdown signal. assure high-speed XSCL, both must satisfy following relation: tCCL (tWCLH tWCLL)
SED1600
Timing Chart Input Timing
XSCL
output
output
through each show cascade number driver.
tWLPH tDFR tWLPL tCCL tWCLH tWCLL
XSCL
tsuEIH
thEIL thEIH tsuEIL
EIO1 EIO2
SED1600
Output Timing
XSCL
tpdEOLLP tpdEOHCL tpdSLP tpdSFR
-0.5V +0.5V
tpdEOLCL
EIO1 EIO2 output
(VSS -5.0 ±10%, 85°C) Parameter (LP-rise disable) time (XSCL-fall disable) time (XSCL-fall enable) time (LP-fall output) time output) delay time Symbol Conditions XSCL -12.0 -28.0 Unit
tpdEOLLP tpdEOLCL tpdEOHCL tpdSLP tpdSFR
SED1600
EXAMPLE APPLICATION (SED1600) (for MATRIX LCD)
CONTROLLER (SED1330, SED1341)
YSCL DIO1 DIO2 SED1630
SED1630
YSCL DIO1 DIO2
MATRIX PANEL
YSCL DIO1 DIO2
SED1600
XSCL
XSCL
SED1600
VSSH XSCL
Note: sure connect current limiter resistor. Also, connect decoupling capacitors (0.01µF) near pins each noise protection.
SED1600
XSCL
EIO2 EIO1
EIO2 EIO1
EIO2 EIO1
SED1600
LAYOUT COORDINATION SED1600DAA PAD)
(0,0)
D1600DAA
Chip Specification Chip size pitch Chip thickness surface area
Dimension (mm) 5.59 3.50 0.160 min. 0.40 ±0.025 0.10mm
Name SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33
(µm) -2461 -2261 -2069 -1886 -1709 -1538 -1366 -1203 -1040 -880 -720 -560 -400 -240 1040 1203 1366 1538 1709 1885 2069 2261 2461 2632 2632 2632 2632
(µm) -1588 -1588 -1588 -1588 -1588 -1588 -1588 -1588 -1588 -1588 -1588 -1588 -1588 -1588 -1588 -1588 -1588 -1588 -1588 -1588 -1588 -1588 -1588 -1588 -1588 -1588 -1588 -1588 -1588 -1588 -1548 -1374 -1206 -1040
Name SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67
(µm) 2632 2632 2632 2632 2632 2632 2632 2632 2632 2632 2632 2632 2632 2632 2632 2632 2461 2261 2069 1885 1709 1538 1366 1203 1040 -240 -400
(µm) Name (µm) -881 SEG68 -560 -721 SEG69 -720 -561 SEG70 -880 -401 SEG71 -1040 -241 SEG72 -1203 SEG73 -1366 SEG74 -1538 SEG75 -1709 SEG76 -1885 SEG77 -2069 SEG78 -2261 SEG79 -2461 1039 EI02 -2632 1204 -2632 1372 -2632 1546 -2632 1588 -2632 1588 (D4) -2632 1588 (D5) -2632 1588 (D6) -2632 1588 (D7) -2632 1588 -2632 1588 -2632 1588 -2632 1588 -2632 1588 -2632 1588 -2632 1588 -2632 1588 XSCL -2632 1588 -2632 1588 -2632 1588 EI01 -2632 1588 1588
(µm) 1588 1588 1588 1588 1588 1588 1588 1588 1588 1588 1588 1588 1546 1372 1204 1039 -241 -401 -561 -721 -881 -1041 -1206 -1374 -1548
SED1600DAB PAD)
Name SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 (µm) -2227 -2074 -1920 -1766 -1613 -1459 -1305 -1152 -998 -845 -691 -538 -384 -230 1152 1305 1459 1613 1766 1920 2074 2227 2381 2622 2622 2622 (µm) -1578 -1578 -1578 -1578 -1578 -1578 -1578 -1578 -1578 -1578 -1578 -1578 -1578 -1578 -1578 -1578 -1578 -1578 -1578 -1578 -1578 -1578 -1578 -1578 -1578 -1578 -1578 -1578 -1578 -1578 -1578 -1346 -1188 -1030 Name SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 (µm) 2622 2622 2622 2622 2622 2622 2622 2622 2622 2622 2622 2622 2622 2622 2622 2381 2227 2074 1920 1766 1613 1459 1305 1152 -230 -384 (µm) Name (µm) -871 SEG68 -538 -713 SEG69 -691 -554 SEG70 -845 -396 SEG71 -998 -238 SEG72 -1152 SEG73 -1305 SEG74 -1459 SEG75 -1613 SEG76 -1766 SEG77 -1920 SEG78 -2074 SEG79 -2227 1030 EI02 -2381 1188 -2622 1346 -2622 1578 -2622 1578 -2622 1578 (D4) -2622 1578 (D5) -2622 1578 (D6) -2622 1578 (D7) -2622 1578 -2622 1578 -2622 1578 -2622 1578 -2622 1578 -2622 1578 -2622 1578 -2622 1578 XSCL -2622 1578 -2622 1578 -2622 1578 EI01 -2381 1578 1578 (µm) 1578 1578 1578 1578 1578 1578 1578 1578 1578 1578 1578 1578 1578 1346 1193 1039 -223 -388 -553 -718 -886 -1039 -1193 -1346 -1578
153.6µ Pitch
153.6µ Pitch
168µ 153.6µ 164.8µ Pitch Pitch
(0,0) D1600DAB
20/1
153.6µ Pitch
Chip Specification Chip size pitch Chip thickness
Dimension (mm) 5.59 3.50 0.153 min. 0.525 ±0.025
158.4µ Pitch
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