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Transceiver PRELIMINARY INFORMATION July 2003 FEATURES


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IS11LV5210
Transceiver
PRELIMINARY INFORMATION July 2003
FEATURES
Complete fully Integrated radio transceiver lowest-cost silicon CMOS power consumption: 40mA 50mA Direct up-conversion stable modulation index Clean Transmit output needs minimum filtering Nominal Receiver sensitivity: Low-IF approach minimize offset Leakage very low, Built-in AutoTune circuitry analog filters external balun switch required Fully digital baseband interface Flexible power management minimizing current consumption 7x7mm package with minimum parasitics component ISSI's RFIC Transceiver family
IS11LV5210 low-cost, fully integrated CMOS radio frequency (RF) transceiver, optimized applications globally available 2.4~2.5 band. contains transmit, receive, functions, including resonator, thus minimizing need external components. synthesizer designed fast hopping ease use, requiring only external loop filter. on-chip reference divider accepts integer reference frequencies between 10~20 MHz, channel spacing. transmit section features digitally adjustable output power ranging from approx. dBm. Nominal mark space deviation ±167 kHz. modulation yields transmit data rates from kbps Mbps max.). spurious signals, internal Gaussian filtering transmit data, ease regulatory compliance. superhetrodyne receiver comprised LNA, active image-reject down-converter, "low-IF" amplifier/limiter chain. bandwidth typically MHz. demodulation completely internal, utilizing digital delay-line discriminator architecture. receiver used applications requiring data rates from kbps Mbps max.) IS11LV5210 also features fully digital baseband interface, greatly simplifying interface commonly used microprocessors ASICs. Internal block antenna means only low-cost bandpass filter needed between antenna longer battery life, power consumption minimized providing separate power controls transmit, receive, PLL, VCO, sections, well sleep mode reduce standby battery usage. This product available 48-lead JEDEC standard package, featuring exposed bottom best characteristics.
Copyright 2003 Integrated Silicon Solution, Inc. rights reserved. ISSI reserves right make changes this specification products time without notice. ISSI assumes liability arising application information, products services described herein. Customers advised obtain latest version this device specification before relying published information before placing orders products.
Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774
PRELIMINARY INFORMATION Rev. 07/21/03
IS11LV5210
Block Diagram
+2.5
RANSMITTER
Dual
with Gaussian
Data Sampler
digital baseband interface
Data
BDATA1
Antenna
BnPW
BDCLK
REQUENCY OURCES
Antenna
BDDATA
3-wire
2400 2482
Synthesizer
Analog (APLL)
freq. control
Digital State Machine
BnDEN
BXTLEN
BPKTCTL Ext. loop filt.
BRCLK
ECEIVER
Estimator Digital Demod.
2-way
Filter
Limiter
Image rej. mixer
oscillator/ buffer
OSCIN
Xtal Xtal Osc.
Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774
Rev. 07/21/03
IS11LV5210
Absolute Maximum Ratings
Ratings
Parameter Symbol
Operating Temperature Storage Temperature Supply Voltage Applied Voltages Other Pins Input Level Output Load mismatch (Z0=50) TSTORAGE VSUPPLY VOTHER -0.3
Rating
+125 +3.0 +3.0
Unit
VSWROUT
10:1
VSWR
Notes:
Absolute Maximum Ratings indicate limits beyond which damage device occur. Recommended operating conditions indicate conditions which device intended functional, guarantee specific performance limits. guaranteed specifications test conditions, Electrical Characteristics section below. These devices electro-static sensitive. Devices should transported stored anti-static containers. Equipment personnel contacting devices need properly grounded. Cover work benches with grounded conductive mats.
Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774
Rev. 07/21/03
IS11LV5210
Electrical Characteristics
following specifications guaranteed 2.50 0.25 VDC, unless otherwise noted: Parameter Symbol Specification Units Test Condition Notes
Current Consumption Current Consumption IDD_TX
POUT nominal output power
Current Consumption Current Consumption IDLE
IDD_RX IDD_SB
Synthesizer VCO: (see Reg. Synthesizer VCO: (see Reg. Clock (pin still applied Clock (pin removed Clock (pin still applied
IDD_SYNTH
Current Consumption SLEEP Current Consumption STATE (BnPWR=0)
IDD_SLP IDD_ST0 IDD_ST0n
Digital Inputs Logic input high Logic input Input Capacitance Input Leakage Current Digital Outputs Logic output high Logic output Output Capacitance C_OUT C_IN I_LEAK_IN
Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774
Rev. 07/21/03
IS11LV5210
Symbol Specification Units Test Condition Notes
Parameter
Output Leakage Current Rise/Fall Time Clock Signals BRCLK output frequency
I_LEAK_OUT T_RISE_OUT
BRCLK
Depends Register setting: Always either during always. Same OSCIN frequency tolerance Required error-free register reading, writing. serial (3wire bus) clock freq. range.
BRCLK tolerance
T_BRCLK
BDCLK rise, fall time
BDCLK frequency range
BDCLK
Overall Transceiver Operating Frequency Range Input mismatch Output mismatch Receive Section F_OP VSWR_I VSWR_O 2400 <2:1 <2:1 2482 VSWR VSWR Z0=50 Z0=50 BDATA1 pin, using baseband clock recovery. 0.1%: Meas. antenna
Receiver sensitivity
Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774
Rev. 07/21/03
IS11LV5210
Symbol Specification Units Test Condition Notes
Parameter
Maximum useable signal Input order intercept point Data (Symbol) rate IIP3
Must integer number microseconds. 0.1%
Minimum Carrier Interference ratio Co-Channel Interference Adjacent Interference, 1MHz offset Adjacent Interference, 2MHz offset Adjacent Interference, 3MHz offset Image Frequency Interference CI_cochannel CI_1 CI_2 CI_3 CI_Image
desired signal. desired signal. desired signal. desired signal. desired signal. Image freq. always higher than desired signal. desired signal. Always higher than desired signal. Meas. with ceramic filter ant. pin:
Adjacent (1MHz) interference image
CI_Image_11
Out-of-Band Blocking
2000 2000 2400 2500 3000
OBB_1 OBB_2 OBB_3
Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774
Rev. 07/21/03
IS11LV5210
Symbol Specification Units Test Condition Notes
Parameter
3000 12.75 Transmit Section
OBB_4
Register bits (Power level
Output Power
Pout
Power Level Meas. antenna
Modulation Characteristics Frequency Deviation In-Band Spurious Emission FDEV Peak deviation Integrated over 1MHz channel. IBS_2 IBS_3
offset offset Out-of-Band Spurious Emission, Operation 30MHz 1GHz 1GHz 12.75GHz 1.8GHz 1.9GHz 5.15GHz 5.3GHz Section Typical Lock range Frequency Tolerance
OBS_O_1 OBS_O_2 OBS_O_3 OBS_O_3
Excludes desired signal.
FVCO
2330
2550
Same OSCIN frequency tolerance
Channel (Step) Size Phase Noise
-115
dBc/Hz dBc/Hz offset offset
Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774
Rev. 07/21/03
IS11LV5210
Symbol Specification Units Test Condition Notes
Must integer multiple MHz. Min. voltage level needed fully functional PLL's, coupled into 1.25 1.25 THOP Vp-p Vp-p Vp-p Vp-p Vp-p Vp-p frequency change, settle within kHz. IDLE state. Synthesizer OBS_1 OBS_2
Parameter
OSCIN Reference Frequency
OSCIN Voltage required
Sine wave wave
Sine wave wave
Sine wave Sine wave
Settling Time
Out-of-Band Spurious Emission 30MHz 1GHz 1GHz 12.75GHz
Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774
Rev. 07/21/03
IS11LV5210
Description
Name
PA_EN TX/RX TEST
Type
Description
CONNECT. Power supply voltage. Ground connection. Power supply voltage. Ground connections. Input/output pin, antenna. Ground connection. Power supply voltage. Ground connection. Power supply voltage. Ground Connection. Power supply voltage. Ground Connection. CONNECT. Reserved factory test. Ground Connections Outputs either 1MHz symbol clock, APLL output.
Interface
BRCLK
Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774
Rev. 07/21/03
IS11LV5210
Name
BPKTCTL
Type
Description
transmit state this turns PA_ON receiving high signal from baseband. receive state, this controls estimation behavior different states: state used estimation fast acquisition high state used slower fixed estimation.
Interface
(Reserved) RXCLK
CONNECT. Receiver symbol clock recovery output. Fixed fundamental rate. Useful oversampling BDATA1 data output. CONNECT. Reserved factory test. This sets chip into SLEEP state supplying signal.
TEST-SE
BXTLEN
TEST3 BnDEN
Reserved factory test. Enable line 3wire bus. Active low.
Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774
Rev. 07/21/03
IS11LV5210
Name
TEST4
Type
Description
CONNECT. Reserved factory test.
Interface
BDDATA
Data line 3wire bus.
TEST5
CONNECT. Reserved factory test. Clock line 3wire bus.
BDCLK
BnPWR
When BnPWR low, chip will state power consumption very low. When raised high, BnPWR used turn chip, restoring registers their default value. transmit state, this receives transmit data from baseband 1MHz data rate. receive state, this sends receive data baseband 1MHz data rate. Data transferred rising edge BRCLK. Power supply voltage. Ground connection. Power supply voltage.
BDATA1
Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774
Rev. 07/21/03
IS11LV5210
Name
TEST6,
Type
Description
CONNECT. Reserved factory test. Crystal oscillator input.
Interface
XTL_OSCIN
Exposed
PLL_LPF
Power supply voltage. Ground connection. loop filter. Ground connection. Power supply voltage. Ground connection.
Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774
Rev. 07/21/03
IS11LV5210
Serial Register Interface
additional information, please refer Application Note AN5000
Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774
Rev. 07/21/03
IS11LV5210
Field Device Address Read/Write Register Address Data Field Comments Always Write, Read. registers configured "WRITE" mode, outputs it's register contents "READ" mode.
3-Wire Protocol
Bits (A7:A5) (A4:A0) (D15:D0)
Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774
Rev. 07/21/03
IS11LV5210
State Diagram
additional information, please refer Application Note AN5000.
Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774
Rev. 07/21/03
IS11LV5210
Detailed Register Information
16DC Estimator Control (Write/Read) Register (Default =0x1000)
Name
(reserved) BPKTCTL_TC_DC [1:0]
Description
(reserved) time constant estimation circuit, after BPKTCTL asserted. Please note setting select fixed offset value that calculated before BPKTCTL asserted. register also.
TC_DC [1:0]
time constant estimation circuit, before BPKTCTL asserted. Reserved
Reserved
BPKTCTL_TC_DC [1:0]
Symbols
Fixed offset value (requires register setting)
TC_DC [1:0]
Symbols
Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774
Rev. 07/21/03
IS11LV5210
Name
(reserved) RD_LNA_GAIN
Synthesizer Status (Read only) Register
Description
(reserved) 2-bit Gain Control dB/step. Baseband read back gain controlled local circuit. RF_SYNTH_LOCK original output signal from synthesizer indicate lock status. Reserved
RF_SYNTH_LOCK
Reserved
Configure (Write/Read) Register (Default 0x0406)
Name
(reserved) PGA_PARA_OW
Description
(reserved) When indicates BBIC overwrites adjustment value (reserved) When indicates BBIC overwrites adjustment value. DC_PARA_OW allow chip track frequency drift receive input signal.
(reserved) DC_PARA_OW
Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774
Rev. 07/21/03
IS11LV5210
Name
RF_STATE[4:0] RD_PGA [2:0]
RFIC State (Read only) Register
Description
Read status finite state machine. 3-bit control (-10/+40 dynamic range. Baseband read back setting, which controlled local circuit. 8-bit RSSI value with time constant baseband. value read long term averaging control transmit power
RSSI_LTERM [7:0]
RF_STATE
Binary [4:0] 00000 00001 00010 00011 00100 00101 01000 01001 01010 01011 10000 10001 10010 10011 10100 10101 10110 10111 11000 Decimal
STATE
PwrOnWaitXTL HoldXTL Idle Sleep SleepWaitXTL RXPLLWait1 RXPLLWait2 RXWideFilt RXNarrowFilt WaitDataSync1 WaitDataSync2 DataSync EnblePA1 EnblePA2 TXData DisablePA1 DisablePA2 DisablePA3
Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774
Rev. 07/21/03
IS11LV5210
Name
(reserved) WT_LNA_GAIN[1:0]
Receiver Control (Write/Read) Register (Default 0x0030)
Description
(reserved) 2-bit Gain Control dB/step. Active only when PGA_PARA_OW register set. normal operation, receive gains controlled local circuit. 3-bit control (-10/+40 dynamic range dB/step. Active only when PGA_PARA_OW register set. normal operation, receive gain controlled local circuit.
WT_PGA [2:0]
WT_LNA_GAIN [1:0]
Gain (dB)
Defined
WT_PGA [2:0]
Gain (dB)
Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774
Rev. 07/21/03
IS11LV5210
Name
SYNTH_ON_DELAY_CN T[4:0]
RFIC Control (Write/Read) Register (Default 0x4D0C)
Description
state WAIT DATA SYNC, oscillator will enabled first. There time offset controlled counter SYNTH_ON_DELAY_CNT. When counter counts zero SYNTH_IDLE_OFF synthesizer will enabled. Each time increment
(reserved) REG_PROTECT
(reserved) used protect registers from accidental change. REG_PROTECT (default), only registers this REG_PROTECT bit, modified. REG_PROTECT registers modified.
RX_DELAY
Receive delays from receiving synthesizer program register start transmit BDATA1 BBIC. Each time increment
Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774
Rev. 07/21/03
IS11LV5210
Name
DC_LONGTERM [15:0]
Estimator (Read only) Register
Description
16-bits compliment offset long-term averaged value. Baseband read back offset long-term averaged value estimated local estimator circuit.
Synthesizer, Tx/Rx Control (Write/Read) Register (Default 0x0030)
Name
Reserved SWALLOW [4:0]
Description
5-Bits Synthesizer Swallow counter. synthesizer will programmed directly with Register [13:9] Register [6:0]. Valid only when RF_PLL_DIRECT (register Enable Transmit Sequence state machine control. Note that TX_EN RX_EN cannot HIGH same time. Enable Receive Sequence state machine control. Note that TX_EN RX_EN cannot HIGH same time.
TX_EN
RX_EN
Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774
Rev. 07/21/03
IS11LV5210
Name
RF_PLL[6:0]
Description
When RF_PLL_DIRECT (register synthesizer will programmed directly, using both Register [13-9] Register [6:0]. Register [6:0] used 7-bit synthesizer program counter. When RF_PLL_DIRECT (register these bits channel number. Transmit receive carrier frequency will 2402+ PLL_CH_NO. this case, SWALLOW bits will ignored.
RF_PLL_CH_NO [6:0]
Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774
Rev. 07/21/03
IS11LV5210
Name
(reserved) APLL_ID [4:0]
APLL Control (Write/Read) Register (Default 0x1676)
Description
(reserved) 5-bit APLL input divider counter. Input divider APLL_ID (reserved)
(reserved)
RFIC Control (Write/Read) Register (Default 0x6803)
Name
SYNTH_ID [4:0]
Description
Synthesizer input reference clock divider, ranging from valid) (reserved) Transmit power level (reserved) Analog power-down mode. When APLL power-off Selects BRCLK output signal: BRCLK_SEL (default), BRCLK always outputs 12MHz APLL output. BRCLK_SEL BRCLK outputs TXCLK MHz).
(reserved) PA_CTRL [2:0] (reserved) APLL_PD
BRCLK_SEL
(reserved)
(reserved)
Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774
Rev. 07/21/03
IS11LV5210
PA_CTRL (Power level) Typical Power Amplifier Output Level,
Binary [2:0]
Decimal
Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774
Rev. 07/21/03
IS11LV5210
Name
(reserved)
Reserved (Write/Read) Register (Default 0x0004)
Description
(reserved)
On-chip Oscillator (Write/Read) Register (Default 0x4040)
Name
(reserved) XTAL_OSC_EN
Description
(reserved) When set, enable internal oscillator circuit.
In-chip Oscillator (Write/Read) Register (Default 0x9000)
Name
XTAL_EX_TUNE[2:0] (reserved) XTAL_LOAD[2:0] XTAL_BIAS_EN (reserved)
Description
Fine tune external Xtal.(default 100) (reserved) wafer xtal load when set. switch bias point when (reserved)
Reserved (Write/Read) Register (Default 0x0000)
Name
(reserved)
Description
(reserved)
Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774
Rev. 07/21/03
IS11LV5210
Name
TX_MOD_OFF_DELAY
Timing (Write/Read) Register (Default 0x0200)
Description
These registers initial value counter modulator power-off control. counter begins decrease zero just after that turn PA-OFF state, modulator turn when zero reached. Each time increment (reserved)
(reserved)
Reserved (Write/Read) Register (Default 0X7193)
Name
(reserved)
Description
(reserved)
Reserved (Write/Read) Register (Default 0XC9CF)
Name
(reserved)
Description
(reserved)
Reserved (Write/Read) Register (Default D3D7)
Name
(reserved)
Description
(reserved)
Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774
Rev. 07/21/03
IS11LV5210
Name
SOFTWARE_CNTL
Control (Write/Read) Register (Default 0x0000
Description
this enable software control transmit sequencing modulator, switch, based values TX_MOD_ON_DELAY, TX_PA_ON_DELAY TX_SW_ON_DELAY respectively. Default setting select hardware state machine control sequencing.
DC_CNTL[1:0]
select fixed offset value after BPKTCTL asserted; however, this value computed before preamble period opposed setting 13-12 Register select symbols time constant compute offset values after BPKTCTL asserted. select enable BPKTCTL_DC_TC (bit 1312 Register setting.
Reserved TX_MOD_ON_DELAY [7:0] SOFTWARE_CTRL this delay from rising edge BPKTCTL, Modulator turning SOFTWARE_CTRL this sets timing delay Modulator turning after BPKTCTL asserted. Each time increment
Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774
Rev. 07/21/03
IS11LV5210
Name
(reserved)
Reserved (Write/Read) Register (Default 0x83E0)
Description
(reserved)
Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774
Rev. 07/21/03
IS11LV5210
Name
(reserved) RF_VCO_IDLE_OFF
Synthesizer Control (Write/Read) Register (Default 0x0962)
Description
(reserved) RF_VCO_IDLE_OFF will shutdown while state machine Idle state. This saves power, longer settling time required when automatically powered Transmit Receive. RF_VCO_IDLE_OFF stays even when state machine Idle state. While this consumes more power, there extra settling time required when transmit receive desired.
SYNTH_IDLE_OFF
SYNTH_IDLE_OFF synthesizer will shutdown while state machine Idle state. This saves power, longer settling time required when synthesizer automatically powered Transmit Receive. SYNTH_IDLE_OFF synthesizer stays even when state machine Idle state. While this consumes more power, there extra settling time required when transmit receive desired.
Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774
Rev. 07/21/03
IS11LV5210
Name
RF_PLL_DIRECT
Description
RF_PLL_DIRECT transmit receive carrier frequency will programmed MHz, with Register [6:0] [13:9]. RF_PLL_DIRECT transmit receive carrier frequency will programmed channel number. Carrier frequency PLL_RF_FREQ_BASE PLL_CH_NO.
PLL_RF_FREQ_BASE
RF_PLL_DIRECT this sets frequency channel Default 2402 MHz. RF_PLL_DIRECT this value ignored.
Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774
Rev. 07/21/03
IS11LV5210
Name
TX_PA_ON_DELAY
Timing Control (Write/Read) Register (Default 0x0A02)
Description
SOFTWARE_CTRL this delay from Modulator turning turning SOFTWARE_CTRL this sets timing delay turning after BPKTCTL asserted. Each time increment
TX_PA_OFF_DELAY
These registers initial value counter power-off control. When state PA-OFF counter decreases zero, will turn OFF. Each time increment
Timing Control (Write/Read) Register (Default 0x0302)
Name
TX_SW_ON_DELAY
Description
SOFTWARE_CTRL this delay from turning switch position. SOFTWARE_CTRL this sets timing delay Switch after BPKTCTL asserted. Each time increment
(reserved)
(reserved)
Manufacture's Code (Read only) Register 30(0x8E8E)
Name
ID_CODE_L [15:0]
Description
Lower 16-bit Manufacture's code.
Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774
Rev. 07/21/03
IS11LV5210
Name
ID_CODE_L [31:16]
Manufacture's Code (Read only) Register 31(0x10C0)
Description
Upper 16-bit Manufacture's code.
Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774
Rev. 07/21/03
IS11LV5210
Typical Application
Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774
Rev. 07/21/03
IS11LV5210
Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774
Rev. 07/21/03

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