What terms circuit associated with EasyPLL? below terms circuit.

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What terms circuit associated with EasyPLL? below terms circuit.

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Frequently Asked Questions Questions Relating EasyPLL
What terms circuit associated with EasyPLL? below terms circuit.
Terms
T3/T1 Fcomp Fout KVCO Xtal Ratio filter poles Comparison Frequency Output Frequency Gain (Tuning Sensitivity) Phase Detector/Charge Pump Gain divider Value Phased-Locked Loop divider Value Root Mean Square. Used here reference phase noise. Voltage Controlled Oscillator Crystal Reference Frequency Phase Margin True Closed Loop Bandwidth
Circuit
KVCO Xtal Fout
Fcom
choose loop bandwidth? design loop filter order meet lock time requirement? Click `help' button next Loop Bandwidth pop-up help menu will tell pick loop bandwidth.
Aren't calculations wrong? same values when using other programs. Welcome world approximations. Approximations rules thumb introduce unnecessary errors, often used order simplify arithmetic. EasyPLL uses minimal amount approximations STANDARD design mode, uses approximations (except continuous time approximation) ULTIMATE method. simulation section uses approximations loop bandwidth, phase margin, poles. What's this stuff? case second order filter, both these numbers refer true loop bandwidth system. However, case third order loop filter, becomes true loop bandwidth, only approximation this. following relationship approximately true: This means that specifying instead makes actual design closer design target, doing this make this program seem inconsistent with other programs. approximately calculated simulation section make EasyPLL program seem more consistent. What design rules used loop filter? What's difference between STANDARD ULTIMATE design rules? There example loop filter designed with both STANDARD ULTIMATE methods this document. user toggle between these loop filter design rules advanced settings screen. more tuning voltage broadband VCO? What about Active Filters? order this, necessary make active loop filter. This done with transistors, amp. possible method with shown below. When using this method, always STANDARD loop filter design rules choose National that current voltage noise, multiply gain gain configuration.
Configuration with Gain Vtune
National Part Number LM833 LM6132 LM6142 LM6152
Supply Voltage (Volts)
Noise Voltage (nV/sqrt(Hz))
Noise Current (pA/sqrt(Hz)) 0.16 0.22 0.34
about more detailed PLL/VCO schematic? Both datasheet evaluation board instructions available National's website give typical schematics. What's this T3/T1 stuff? case second order filter, T3/T1 hopefully there confusion. There actually only pole, case third order filter, non-zero helps attenuate reference spurs. other design methods, user typically specifies added attenuation desired, this determines value However, this causes loop bandwidth shrink. turns that optimal spurious attenuation filter with fixed true loop bandwidth, occurs when However, makes sense design order less peaking more desirable component values. makes sense design added benefit using third order filter application specific, viewed typing "-1" T3/T1 ratio access help screens.
prescalers work? bother with them first place? Prescalers necessary order divide high frequency signal lower frequency signal. They used that only high-frequency portion chip requires higher frequency, higher current, higher cost process. most standard architecture dual modulus prescaler. this, voltage initially divided down (where Prescaler Size). Every cycles, (swallow) counter decreased thus taking A*(P counts. During this, (programmable) counter also counting down thus counts. This takes additional (B-A)*P cycles count down zero, thus: A*(P+1)+(B-A)*P necessary otherwise counter will function properly. calculated follows: (div means divide with remainder) (mod means modulus, remainder)
Counter Counter ounter
XTAL
1/(P+1)
Loop ilter
printout from screen? Select `print' command from your browser. Where report bugs EasyPLL program? Report bugs this program customer response group 1-800-272-9959.
Questions Relating Simulation/Performance
Phase Noise Simulated? shown that noise sources were independent comparison frequency, then phase noise would vary 20*log(N), since multiplies voltage noise In-Band sources. However, phase detector produces noise proportional 10*log (Comparison Frequency), this usually dominant noise source. concept normalized phase detector noise floor refers what phase noise extrapolates value comparison frequency Call this number Noise Floor. Then Phase Noise
Noise Floor 10*log (Comparison Frequency) 20*log(N)
phase noise vary little based factors such charge pump gain, state other side dual PLL), layout, crystal noise, many other sources. noise calculated follows: First noise floor calculated:
Noise Floor Noise Floor 10*log (Comparison Frequency)
This noise multiplied square closed loop transfer function integrated from times loop bandwidth. square root resulting integral taken multiplied 180/. Lock Time Simulated? simulate lock time, true complete closed loop transfer function multiplied step function. poles zero's found this broken into proper fractions (This involves solving order polynomial). inverse Laplace Transform taken transform response time domain response. This method makes approximations except continuous time approximation. poles zero closed loop transfer function disregarded, then lock time approximated with formula stated below:
Lock Time seconds Higher Frequency Lower Frequency Frequency tolerance. i.e. Acceptable frequency error.
Natural Frequency Damping Factor
Kvco
about spurs? Reference Spurs undesired signals that occur frequencies that equal comparison frequency away from carrier. They also occur multiples reference frequency also submultiples fractional being used. They usually caused modulation tuning line. This modulation caused factors such charge pump mismatch charge pump leakage. lower comparison frequencies KHz) cause these spurs tends leakage through charge pump, VCO, other components board. higher comparison frequencies KHz), dominant cause these tends charge pump mismatch. EasyPLL does predict reference spur levels, since they vary based many factors. Instead, EasyPLL only gives indication much lower third order loop filter make reference spurs. Spurs also caused crosstalk board, decoupling power supplies chip crosstalk from other undesired noise sources that unrelated PLL.
What's this loop bandwidth bandwidth stuff? Defined below terms related bandwidth: Loop Bandwidth This frequency which magnitude open loop transfer, G(s), function equal one.
Kvco
Bandwidth This frequency which magnitude Closed Loop Transfer function equal one. equation Closed Loop transfer function shown below: loop bandwidth visible spectrum analyzer. view this, note that phase noise will start some value, increase gently some peak value, start decreasing. After phase noise peak, point which phase noise equal close phase noise value bandwidth. loop bandwidth equal bandwidth case where phase margin degrees. phase margin less than degrees, loop bandwidth slightly less than bandwidth, phase margin exceeds degrees, loop bandwidth slightly larger than bandwidth. Bandwidth This frequency which magnitude closed loop transfer function equal always larger than bandwidth loop bandwidth. What's meaning significance optimization index? optimization index measure well filter optimized. optimized, meant that phase margin (180 plus phase open loop transfer function) such that maximum frequency equal loop bandwidth. This shown simulation that this yields fastest lock time among loop filters same design parameters.
Questions Relating Performance Problems
Phase Noise worse than expected. There could many reasons phase noise program will list these reasons after simulates phase noise. Below list common things impact phase noise phase noise prediction. Miscalculation phase noise using highest charge pump gain Crosstalk board Noise pins Violating operating close sensitivity specification Noisy Narrow loop bandwidth that allows noise crop Crosstalk from side Dual Noisy crystal reference source. Part does lock performs worse than expected. Possible problems shown below: Programming Problem Ensure that there programming related problems. Make sure that stream correct. also possible toggle functions such power down functions order current changes responding programming all. most National's PLLs, check bias level high frequency input pins, should volts when part powered volts when part powered down. also look divider outputs part responding programming. Sensitivity/Impedance Mismatch Problem Ensure power level high frequency input pins well input crystal reference within acceptable limits. These limits temperature, voltage, frequency dependent. also aware that impedance mismatching issues occur. possible, look outputs dividers part dividing properly.
Layout Problem Ensure that pins connected properly aware that layout issues cause noisy spectrum. Layout easily introduce spurs. Problem VCOs typically have very limited tuning range. Ensure that being programmed outside operating limits. Some VCOs produce large harmonics also have problems running when tuning voltage volts. loop filter parameters designed what obtained actual design. Here some things that throw design off: value comparison frequency different that what designed for. charge pump gain different than what designed for. input capacitance large enough interact with component values loop filter. gain different than what designed for. Note that many VCOs have gain that perfectly constant, also that sometimes manufactures give minimum gain specification, which different than typical gain VCO.
Miscellaneous Questions Related EasyPLL
lock detect pin? parts with digital lock detect easiest since they produce logic output. other type lock detect usually high puts narrow pulses when charge pump comes necessary integrate this output determine average value order construct lock detect circuit. output open drain, adding diode greatly increases sensitivity circuit. typical circuit shown below:
Input
Output
about programming part? Aside from getting instructions from databook, software programming PLLs available web. This software useful because only does actually send bits necessary program PLL, also shows bits that being sent. This facilitates figuring what bits send.
National PLLs? Below several value added features National PLLs support Excellent Phase Noise Performance (-169 dbc/Hz) AN-1052 details leakage many parts) well balanced charge pump. This National's PLLs have such reference spurs such good phase noise. Added features like fastlock, lock detect, powerdown. Extensive portfolio ones cost/performance needs. Good packaging options current consumption Quality service excellent technical support. Where additional help? National Support www.national.com/feedback Send your questions email. National Customer Support Group 1-800-272-9959
This group handles technical non-technical questions requests. What's available National's wireless website where Wireless Website http://WIRELESS.NATIONAL.COM This site EasyPLL selection/design/simulation tools, test data, driver software, availability, pricing, other related products much more information targeted National's wireless products. National's Main Website http://www.national.com/ This site datasheets, test data, availability, pricing, sample ordering, plethora other things about general National Semiconductor products.

What terms circuit associated with EasyPLL? below terms circuit.

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