TriCore Family Unified 32-Bit Microcontroller-DSP User's Man
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TC10GP
TriCore Family
Unified 32-Bit Microcontroller-DSP
User's Manual
2000-01
1.01
TC10GP Revision History: Previous Versions: Page 13-69 14-25, 14-47 19-7 several several several Subjects
2000-01 1.01) 1999-10 (V1.0)
feature description chip-select outputs enhanced. Figure enhanced. General-Purpose Timer Units feature description enhanced. Address decoding corrected. Syntax 32-bit Compare Instruction corrected. Full duplex configuration diagram, Figure 19-4, enhanced. Default values control register bits mentioned explictly note "(default)" convenience. Typo errors corrected. Register names updated with module name prefixes consistency between register definition implementation tables each module.
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Edition 2000-01 Published Infineon Technologies St.-Martin-Strasse D-81541 Infineon Technologies 2000. Rights Reserved. Attention please! information herein given describe certain components shall considered warranted characteristics. Terms delivery rights technical change reserved. hereby disclaim warranties, including limited warranties non-infringement, regarding circuits, descriptions charts stated herein. Infineon Technologies approved CECC manufacturer. Information further information technology, delivery terms conditions prices please contact your nearest Infineon Technologies Office Germany Infineon Technologies Representatives worldwide (see address list). Warnings technical requirements components contain dangerous substances. information types question please contact your nearest Infineon Technologies Office. Infineon Technologies Components only used life-support devices systems with express written approval Infineon Technologies, failure such components reasonably expected cause failure that life-support device system, affect safety effectiveness that device system. Life support devices systems intended implanted human body, support and/or maintain sustain and/or protect human life. they fail, reasonable assume that health user other persons endangered.
TC10GP Unified 32-bit µC-DSP
Table Contents
1.2.1 1.2.2 1.2.3 1.2.3.1 1.2.3.2 1.2.4 1.2.5 1.2.5.1 1.2.5.2 1.2.6 2.1.1 2.1.2 2.1.3 2.1.4 2.1.5 2.1.5.1 2.1.5.2 2.1.5.3 2.1.6 2.1.7 2.1.8 2.1.8.1 2.1.8.2 2.1.8.3 2.1.9 2.1.10 2.1.10.1 2.1.10.2 2.1.10.3 2.1.10.4 2.1.10.5 2.1.10.6 2.1.10.7 2.1.10.8 2.1.10.9
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Introduction About Infineon TriCore Architecture About This Document Intended audience. Related Documentation Textual conventions Radix Fields Ranges Units Reserved, Undefined, Unimplemented Terminology Unimplemented Undefined Register Access Modes Detailed TC10GP Features TC10GP Architectural Overview
Processor Architecture TC10GP Processor Architecture Overview Program State Registers Data Types Addressing Modes Instruction Formats Tasks Contexts Upper Lower Contexts Context Save Areas Fast Context Switching Interrupt System Trap System Protection System Permission Levels Memory Protection Model Watchdog Timer ENDINIT Protection Reset System Processor Registers Core Special Function Registers General-Purpose Registers 2-10 Program State Information 2-11 Context Management Registers 2-11 Stack Management 2-11 Interrupt Trap Control 2-12 System Control Register 2-12 Memory Protection Registers 2-12 Debug Registers 2-12 TC10GP Central Processing Unit 2-13 Instruction Fetch Unit 2-13 Execution Unit 2-14 General-Purpose Register File 2-15 2000-01
User's Manual
TC10GP Unified 32-bit µC-DSP
Table Contents
2.6.1 2.6.2 2.6.3 2.6.4 2.6.5 2.6.6 2.6.7 2.6.8 2.6.9 3.2.1 3.2.2 3.2.3 3.2.4 3.2.5 5.2.1 5.2.2 5.2.3 5.2.3.1 5.2.3.2 5.2.3.3 5.2.3.4 5.2.3.5 5.2.4 5.2.4.1 5.2.4.2 5.2.4.3 5.2.5 5.3.1 5.3.2 5.3.3 5.3.3.1
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2-16 2-16 2-17 2-20 2-21 2-22 2-22 2-23 2-24 2-24 2-25
Core Special Function Register Descriptions Program Counter PSW, Program Status Word PCXI, Previous Context Information Register FCX, Free Context List Pointer LCX, Context List Limit Pointer ISP, Interrupt Stack Pointer. BIV, Interrupt Vector Table Pointer BTV, Trap Vector Table Pointer SYSCON, System Control Register CSFR Address Table
Coprocessor Instructions Coprocessor Overview Coprocessor Instructions PARITY Instruction BSPLIT Instruction BMERGE Instruction UNPACK Instruction PACK Instruction TC10GP Pipelines Pipeline Overview Integer Load/Store Pipelines Loop Pipeline Context Operations
On-Chip Local Memory Units Local Memory Unit Overview PMU, Program Memory Unit Configuration Options CSRAM, Code Scratch-Pad ICACHE, Instruction Cache Cache Size Bypass Control Cache Organization Cache Refill Instruction Streaming Cache Coherency, Cache Invalidation Control Registers PMUID, Identification Register PMU_CON0, Control Register PMU_CON1, Control Register 5-10 Implementation TC10GP 5-11 DMU, Data Memory Unit 5-13 Configuration Options 5-13 DSRAM, Data Scratch-Pad 5-15 DCACHE, Data Cache 5-17 Cache Enable/Disable Control 5-17
User's Manual
2000-01
TC10GP Unified 32-bit µC-DSP
Table Contents
5.3.3.2 5.3.3.3 5.3.3.4 5.3.3.5 5.3.3.6 5.3.4 5.3.4.1 5.3.4.2 5.3.4.3 5.3.4.4 5.3.4.5 5.3.4.6 5.3.4.7 5.3.5 5.3.5.1 5.3.5.2 5.3.5.3 5.3.5.4 5.3.6 6.4.1 6.4.2 6.4.3 6.4.4 6.4.5 6.4.6 6.4.7 6.5.1 6.5.2 6.5.3 6.5.4 6.5.5 6.5.6 6.7.1 6.7.2 6.10 6.11
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5-17 5-17 5-18 5-18 5-18 5-18 5-19 5-19 5-20 5-20 5-20 5-20 5-21 5-21 5-22 5-22 5-23 5-24 5-25
Cache Organization Cache Write-Back Refill Cache Flush Instruction Cache Invalid Instruction Cache Flush Invalidate Instruction Trap Generation FPI-Bus Error Range Error Register Access Error Cache Refill Error Cache Write-Back Error Cache Flush Error Cache Management Error Control Registers DMUID, Identification Register DMU_CON, Configuration Register DMU_STR, Synchronous Trap Flag Register DMU_ATR, Asynchronous Trap Flag Register Implementation TC10GP
Interrupt System Interrupt System Overview Service Request Sources External Interrupts Service Request Nodes Service Request Control Registers Service Request SETR, CLRR, Request Flag Clear Bits SRE, Enable SRR, Service Request Flag TOS, Type-of-Service Control SRPN, Service Request Priority Number Interrupt Control Units ICR, Interrupt Control Register CCPN, Current Priority Number 6-10 Global Interrupt Enable 6-10 PIPN, Pending Interrupt Priority Number 6-10 ARBCYC, Number Arbitration Cycle Control 6-11 ONECYC, Clocks Arbitration Cycle Control 6-11 Operation Interrupt Control Unit 6-11 TC10GP Arbitration Process 6-12 Controlling Number Arbitration Cycles 6-13 Controlling Duration Arbitration Cycles 6-13 Entering Interrupt Service Routine 6-13 Exiting Interrupt Service Routine 6-15 Interrupt Vector Table 6-15 Usage TC10GP Interrupt System 6-17 2000-01
User's Manual
TC10GP Unified 32-bit µC-DSP
Table Contents
6.11.1 6.11.2 6.11.3 6.11.4 6.11.5 6.11.6 6.11.7 6.12 6.13 6.14 6.14.1 6.14.2 6.14.3 6.14.4 6.14.5 7.2.1 7.2.2 7.2.3 7.2.4 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.3.6 7.3.7 7.3.8 7.3.9 7.3.10 7.3.11 7.3.12 7.3.13 7.3.14 7.3.15 7.3.16 7.3.17 7.3.18 7.3.19 7.3.20 7.3.21 7.3.22 7.3.23
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6-17 6-18 6-18 6-20 6-21 6-21 6-21 6-22 6-23 6-24 6-24 6-25 6-25 6-25 6-25
Spanning Interrupt Service Routines Across Vector Entries Configuring Ordinary Interrupt Service Routines Interrupt Priority Groups Splitting Interrupt Service Across Different Priority Levels Using Different Priorities Same Interrupt Source Software-Posted Interrupts Interrupt Priority Service Request Nodes Interrupt Control Unit PCP_ICR, PICU Interrupt Control Register CPPN, Current Priority Number Global Interrupt Enable PIPN, Pending Interrupt Priority Number ARBCYC, Number Arbitration Cycles Control ONECYC, Clocks Arbitration Cycle Control
Trap System Trap System Overview Trap Classes Synchronous Traps Asynchronous Traps Hardware Traps Software Traps Trap descriptions RESET Trap PRIV Trap Trap Trap Trap Trap Trap GRWP Trap IOPC Trap Trap Trap Trap Trap Trap Trap Trap CTYP Trap NEST Trap Trap Trap Trap Trap SOVF Trap
User's Manual
2000-01
TC10GP Unified 32-bit µC-DSP
Table Contents
7.3.24 7.3.25 7.4.1 7.5.1 7.5.2 7.5.3 7.5.4 8.2.1 8.2.2 8.2.3 8.2.4 9.2.1 9.2.2 9.3.1 9.3.2 9.3.3 9.3.4 9.3.4.1 9.3.5 9.3.6 9.4.1 9.4.2 9.4.3 9.4.4 9.4.5 10.1 10.1.1 10.1.2 10.1.3 10.1.4 10.1.4.1 10.1.4.2 10.1.4.3
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Trap Trap Trap Vector Table Entering Trap Service Routine Non-Maskable Interrupt 7-10 NMI_SR, Status Register 7-10 External Input 7-11 7-11 Watchdog Timer 7-11 Memory Protection Memory Protection Overview Memory Protection Registers DPRx_n, Data Range Protection Register Pairs DPMx_n, Data Range Mode Registers CPRx_n, Code Range Protection Register Pairs CPMx_n, Code Range Mode Registers Memory Protection Register Table
Reset Boot Reset Boot Overview Reset Status Control Registers RST_SR, Reset Status Register RST_REQ, Reset Request Register Reset Operations Power-On Reset External Hard Reset Soft Reset Watchdog Timer Reset Watchdog Timer Reset Lock Deep-Sleep Wake-Up Reset State TC10GP after Reset Booting Scheme 9-10 Hardware Booting Scheme 9-10 Software Booting Scheme 9-10 Boot Options 9-10 Normal Boot Options 9-11 Debug Boot Options 9-11 Clock System TC10GP Clock System Overview Power Management Clock Gating Clock Domains Clock Control Clock Generation Unit Oscillator Circuit Phase-Locked Loop (PLL) N-Divider 10-2 10-2 10-2 10-3 10-4 10-5 10-6 10-7 10-7
User's Manual
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TC10GP Unified 32-bit µC-DSP
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10.1.4.4 10.1.4.5 10.1.4.6 10.1.4.7 10.1.4.8 10.1.5 10.1.5.1 10.1.5.2 10.1.5.3 10.1.6 10.1.7 10.2 10.3 10.3.1 10.3.2 10.3.3 10.3.4 10.3.5 11.1 11.2 11.2.1 11.2.2 11.3 11.3.1 11.3.2 11.3.2.1 11.3.2.2 11.3.2.3 11.3.3 11.3.3.1 11.3.3.2 11.3.3.3 11.3.3.4 11.3.3.5 11.3.4 12.1 12.2 12.2.1 12.2.1.1 12.2.1.2 12.2.2 12.2.2.1 12.2.3 12.2.4
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Frequency Ranges 10-7 Lock Detection 10-7 K-Divider 10-8 Clock Source Control 10-8 Enable/Disable Control 10-9 Determining System Clock Frequency 10-9 Bypass Operation 10-9 Bypass Operation 10-9 Operation 10-9 Startup Operation 10-11 Loss-of-clock Operation 10-12 PLL_CLC, Clock Control Status Register 10-12 CLC, Module Clock Control Registers 10-13 Enable/Disable Control 10-14 Sleep Mode Control 10-15 Debug Suspend Mode Control 10-15 Entering Disabled Mode 10-15 Clock Divider Control 10-17 Power Management Power Management Overview Power Management Control Registers PMG_CSR, Power Management Control Status Register PMG_CON, Power Management Control Register Power Management Modes Idle Mode Sleep Mode Entering Sleep Mode TC10GP State During Sleep Mode Exiting Sleep Mode Deep Sleep Mode Entering Deep Sleep Mode TC10GP State During Deep Sleep Mode Exiting Deep Sleep Mode Exiting Deep Sleep Mode With Power-On Reset Signal Exiting Deep Sleep Mode With Signal Summary TC10GP Power Management States 11-2 11-2 11-3 11-4 11-5 11-5 11-5 11-6 11-6 11-6 11-7 11-7 11-7 11-7 11-8 11-8 11-8 11-9
FPI-Bus Control Unit 12-2 FPI-Bus Overview 12-2 Control Unit (BCU) 12-5 FPI-Bus Arbitration 12-6 Arbitration Priority 12-6 Starvation Protection 12-7 Error Handling 12-7 Interpreting Error Information 12-8 Power Saving Mode 12-10 Registers 12-11 2000-01
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TC10GP Unified 32-bit µC-DSP
Table Contents
12.2.4.1 12.2.4.2 12.2.4.3 12.2.4.4 12.2.5 12.2.5.1 13.1 13.2 13.3 13.3.1 13.3.2 13.4 13.4.1 13.4.2 13.4.3 13.4.4 13.4.5 13.4.6 13.4.7 13.4.8 13.4.9 13.4.10 13.4.11 13.4.12 13.4.13 13.5 13.5.1 13.5.1.1 13.5.1.2 13.5.2 13.5.2.1 13.5.2.2 13.5.3 13.5.4 13.5.5 13.5.5.1 13.5.5.2 13.5.5.3 13.5.5.4 13.6 13.6.1 13.6.2 13.6.3 13.6.4 13.7 BCU_ID, Identification Register BCU_CON, Control Register BCECON, BCEADD, BCEDAT Debug Registers BCU_SRC, Service Request Control Register Implementation TC10GP Register Table
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12-11 12-12 12-12 12-14 12-15 12-15
External Controller 13-2 External Controller Overview 13-2 Features 13-2 Basic Operation 13-3 Internal External Operation 13-5 External Internal Operation 13-5 Signal Description 13-6 Output Clock, EBUCLK 13-7 Address Bus, A[23:0] 13-7 Address/Data Bus, AD[31:0] 13-7 Read/Write Strobes, RD/WR 13-7 Address Latch Enable, 13-8 SDRAM Address Strobes, 13-8 Byte Control Signals, 13-8 Variable Waitstate Control, WAIT 13-9 Chip Select Lines, 13-10 Arbitration Signals, HOLD, HLDA BREQ 13-11 Chip Select, CSEBU 13-11 Instruction Fetch Indication Signal, CODE 13-11 Emulation Support Signals, CSEMU CSOVL 13-12 Detailed Internal External Operation 13-12 Address Regions 13-12 Address Region Selection 13-12 Address Region Parameters 13-15 SDRAM Support 13-16 SDRAM Addressing 13-16 SDRAM Memory Types 13-17 Driver Turn-Around Waitstates 13-19 Data Width External Devices 13-20 Basic Access Timing 13-21 Access Non-Multiplexed Devices 13-21 Access Multiplexed Devices 13-23 Access SDRAMs 13-27 SDRAM Read Write Burst Sequences 13-30 Detailed External Internal Operation 13-36 Signal Direction 13-37 Address Translation 13-38 External Internal Access Controls 13-40 Basic Access Timing 13-40 Arbitration 13-42 2000-01
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TC10GP Unified 32-bit µC-DSP
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13.7.1 13.7.1.1 13.7.1.2 13.7.1.3 13.7.2 13.7.3 13.7.4 13.7.4.1 13.7.4.2 13.8 13.9 13.9.1 13.9.2 13.10 13.10.1 13.10.2 13.10.3 13.10.4 13.10.5 13.10.6 13.10.7 13.10.8 13.10.9 13.10.10 13.10.11 13.11 13.12 13.12.1 14.1 14.2 14.2.1 14.2.2 14.2.3 14.2.4 14.2.5 14.3 14.3.1 14.3.1.1 14.3.1.2 14.3.1.3 14.3.1.4 14.3.1.5 14.3.2 14.3.2.1 14.3.2.2 External Arbitration Arbitration Modes Arbitration Signals Arbitration Sequence Internal Request External Requests Atomic Read-Modify-Write Accesses Internal External Read-Modify-Write Access External Internal Read-Modify-Write Access Boot Process Emulation Support Emulation Boot Overlay Memory Registers EBU_CLC, Clock Control Register EBU_ID, Identification Register EBU_CON, Global Control Register EBU_DRMCON0, SDRAM Control Register EBU_DRMCON1, SDRAM Control Register EBU_DRMSTAT, SDRAM Status Register EBU_ADDSELx, Address Select Registers EBU_BUSCONx, Control Registers EBU_EMUCON, Emulator Configuration Register EBU_EMUAS, Emulator Region Address Select Register EBU_EMUBC, Emulator Configuration Register EXTCON, External Access Configuration Register Implementation Register Address Table
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13-43 13-43 13-44 13-45 13-46 13-47 13-48 13-48 13-48 13-49 13-51 13-52 13-52 13-54 13-55 13-56 13-57 13-58 13-60 13-61 13-62 13-63 13-65 13-66 13-67 13-68 13-69 13-69
Peripheral Control Processor 14-2 Overview 14-2 Architecture 14-2 Processor 14-3 Code Memory (PCODE) 14-4 Parameter (PRAM) 14-4 FPI-Bus Interface 14-5 Interrupt Control Unit (PICU) Service Request Nodes (PSRNs) 14-5 Programming Model 14-5 General Purpose Register 14-5 Register 14-6 Registers 14-6 Registers 14-6 Register 14-7 Register 14-7 Contexts Context Models 14-8 Context Models 14-9 Context Save Area 14-10 2000-01
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TC10GP Unified 32-bit µC-DSP
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14.3.2.3 14.3.2.4 14.3.3 14.3.3.1 14.3.3.2 14.4 14.4.1 14.4.2 14.4.3 14.4.3.1 14.4.3.2 14.4.3.3 14.5 14.5.1 14.5.2 14.5.3 14.5.4 14.5.4.1 14.5.4.2 14.5.5 14.6 14.6.1 14.6.2 14.6.3 14.6.4 14.6.5 14.6.6 14.6.6.1 14.6.6.2 14.6.6.3 14.6.6.4 14.7 14.7.1 14.7.2 14.7.3 14.8 14.9 14.9.1 14.9.2 14.9.3 14.9.4 14.9.5 14.9.6 14.9.7 14.9.8 14.9.9 Context Save Restore Operation Initialization Contexts Channel Programs Channel Restart Mode Channel Resume Mode Operation Initialization Channel Invocation Context Restore Operation Channel Exit Context Save Operation Normal Exit Error-Condition Channel Exit Debug Exit Interrupt Operation Issuing Service Requests PICU, Interrupt Control Unit Service Request Nodes Issuing Service Requests Service Request EXIT Instruction Service Request Error Queue Full Operation Instruction Overview Primitives Load Store Arithmetic/Logical Instructions Manipulation Flow Control Addressing Modes FPI-Bus Addressing PRAM Addressing Addressing Flow Control Destination Addressing Accessing Resources from FPI-Bus Access Control Registers Access PRAM Access PCODE Debugging Control Status Registers PCP_CLC, Clock Control Register PCP_ID, Module Register PCP_CS, Control Status Register PCP_ES, Error/Debug Status Register PCP_ICR, Interrupt Control Register PCP_SRC0, Service Request Control Register (TOS PCP_SRC1, Service Request Control Register (TOS PCP_SRC2, Service Request Control Register (TOS PCP_SRC3, Service Request Control Register (TOS
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14-13 14-13 14-14 14-15 14-15 14-16 14-17 14-17 14-17 14-18 14-18 14-19 14-19 14-20 14-20 14-21 14-22 14-22 14-22 14-22 14-23 14-23 14-24 14-24 14-26 14-27 14-27 14-27 14-29 14-29 14-29 14-30 14-30 14-30 14-31 14-31 14-32 14-33 14-34 14-35 14-36 14-37 14-38 14-39 14-39 14-40
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14.10 Instruction Details 14-41 14.10.1 Instruction Codes Fields 14-41 14.10.1.1 Conditional Codes. 14-41 14.10.1.2 Instruction Fields 14-42 14.10.2 Counter Operation COPY Instruction. 14-44 14.10.3 ADD, 32-bit Addition 14-45 14.10.4 AND, 32-bit Logical 14-45 14.10.5 CHKB, Check Bit. 14-46 14.10.6 CLR, Clear 14-46 14.10.7 COMP, 32-bit Compare 14-47 14.10.8 COPY, Instruction 14-48 14.10.9 DEBUG, Debug Instruction 14-48 14.10.10 EXIT, Exit Instruction 14-49 14.10.11 INB, Insert 14-49 14.10.12 Jump Conditionally 14-50 14.10.13 Jump Long Unconditional 14-50 14.10.14 Load 14-51 14.10.15 LDL, Load 16-bit Value 14-52 14.10.16 MOV, Move Register Register 14-52 14.10.17 NEG, Negate 14-52 14.10.18 NOP, Operation 14-53 14.10.19 NOT, Logical 14-53 14.10.20 Logical 14-53 14.10.21 PRI, Prioritize 14-54 14.10.22 Rotate Left 14-54 14.10.23 Rotate Right 14-55 14.10.24 SET, 14-55 14.10.25 SHL, Shift Left 14-55 14.10.26 SHR, Shift Right 14-56 14.10.27 Store 14-56 14.10.28 SUB, 32-bit Subtract 14-57 14.10.29 XOR, 32-bit Logical Exclusive 14-58 14.10.30 Flag Updates Instructions 14-58 14.11 Programming 14-60 14.11.1 Initial Channel Program 14-60 14.11.1.1 Channel Entry Table 14-60 14.11.1.2 Channel Resume 14-60 14.11.2 Channel Management Small Minimum Contexts 14-61 14.11.2.1 Unused Registers Globals Constants 14-62 14.11.3 Dispatch Priority Tasks 14-62 14.11.4 Code Reuse Across Channels (Call Return) 14-62 14.11.5 Case-like Code Switches (Computed Go-To) 14-63 14.11.6 Simple operation 14-63 14.12 Programming Notes Tips 14-64 14.12.1 Notes Configuration 14-64 14.12.2 General Purpose Register 14-64
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14.13 14.13.1 14.13.2 15.1 15.2 15.3 15.4 15.4.1 15.4.2 15.4.2.1 15.4.2.2 15.4.2.3 15.4.2.4 15.4.3 15.4.4 15.4.5 15.4.6 15.4.6.1 15.4.6.2 15.4.6.3 15.4.6.4 15.4.6.5 15.4.6.6 15.4.7 15.4.8 15.4.8.1 15.4.8.2 15.4.8.3 15.5 15.5.1 15.5.2 15.5.3 15.5.4 15.5.5 15.6 15.6.1 15.6.2 15.6.3 15.7 16.1 16.2 16.3 16.3.1 16.3.2
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Implementation 14-65 Register Table 14-65 Memories 14-65 Watchdog Timer 15-2 Watchdog Timer Overview 15-2 Features Watchdog Timer 15-2 EndInit Function 15-3 Watchdog Timer Operation 15-4 Register Overview 15-5 Modes Watchdog Timer 15-6 Time-Out Mode 15-7 Normal Mode. 15-7 Disable Mode 15-8 Prewarning Mode 15-8 Password Access WDT_CON0 15-8 Modify Access WDT_CON0 15-9 Term Definitions WDT_CON0 Accesses 15-10 Detailed Descriptions Modes 15-11 Time-Out Mode Details 15-11 Normal Mode Details 15-12 Disable Mode Details 15-12 Prewarning Mode Details 15-13 Operation During Power-Saving Modes 15-14 Operation OCDS Suspend Mode 15-15 Double Watchdog Error. 15-15 Determining Periods 15-15 Time-out Period 15-16 Normal Period 15-17 Period During Power-Saving Modes 15-18 Handling Watchdog Timer. 15-18 System Initialization 15-18 Re-opening Access Critical System Registers 15-19 Servicing Watchdog Timer 15-19 Handling User-Definable Password Field, WDTPW 15-20 Determining Required Values Access 15-22 Watchdog Timer Registers 15-23 WDT_CON0, Watchdog Control Register 15-24 WDT_CON1, Watchdog Control Register 15-25 WDT_SR, Watchdog Status Register 15-26 Register Table 15-28 System Timer System Timer Overview SKernel Functions SKernel Registers STM_ID, System Timer Module Identification Register STM_TIM0, System Timer Register 16-2 16-2 16-2 16-4 16-5 16-5
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16.3.3 16.3.4 16.4 16.4.1 16.4.2 16.4.3 17.1 17.2 17.3 17.3.1 17.3.1.1 17.3.2 17.3.3 17.3.4 17.4 17.5 17.6 17.6.1 17.6.2 17.7 17.7.1 17.7.1.1 17.7.1.2
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16-6 16-7 16-8 16-8 16-8 16-9
TIMx, System Timer Registers through STM_CAP, System Timer Capture Register System Timer Implementation External SRegisters STM_CLC, System Timer Clock Control Register SRegister Table
General Purpose Timer Units 17-2 Overview General Purpose Timer Units 17-2 GPTU Kernel Functions 17-3 Timer 17-4 Input Selection 17-5 Access Timer Count Reload Registers. 17-6 Reload Selection 17-7 Service Requests, Output Signals, Trigger Signals 17-8 Timers Configuration Limitations 17-9 Timer 17-10 Quadrature Counting Mode 17-17 Global GPTU Controls 17-17 Output Control 17-17 Service Request Control 17-18 Kernel Registers 17-20 Timer T0/T1 Register Descriptions 17-21 GPTUx_T01IRS, Timer Input Reload Source Selection Register 17-21 GPTUx_T01OTS, Timer Output, Trigger, Service Request Selection Register 17-23 17.7.1.3 GPTUx_T0DCBA, Timer Count Register (parts 17-24 17.7.1.4 GPTUx_T0CBA, Timer Count Register (parts 17-24 17.7.1.5 GPTUx_T0RDCBA, Timer Reload Register (parts 17-25 17.7.1.6 GPTUx_T0RCBA, Timer Reload Register (parts 17-25 17.7.1.7 GPTUx_T1DCBA, Timer Count Register (parts 17-25 17.7.1.8 GPTUx_T1CBA, Timer Count Register (parts 17-25 17.7.1.9 GPTUx_T1RDCBA, Timer Reload Register (parts 17-26 17.7.1.10 GPTUx_T1RCBA, Timer Reload Register (parts 17-26 17.7.2 Timer Registers 17-27 17.7.2.1 GPTUx_T2AIS, Timer T2/T2A External Input Selection Register 17-27 17.7.2.2 GPTUx_T2BIS, Timer External Input Selection Register 17-28 17.7.2.3 GPTUx_T2ES, Timer External Input Edge Selection Register 17-29 17.7.2.4 GPTUx_T2CON, Timer Mode Control Status Register 17-31 17.7.2.5 GPTUx_T2RCCON, Reload/Capture Mode Control Register 17-34 17.7.2.6 GPTUx_T2, Timer Count Register. 17-35 17.7.2.7 GPTUx_T2RC0, Timer Reload/Capture Register 17-35 17.7.2.8 GPTUx_T2RC1, Timer Reload/Capture Register 17-36 17.7.3 Global Control Registers 17-36 17.7.3.1 GPTUx_T012RUN, Timer Control 17-36 17.7.3.2 GPTUx_OSEL, Output Source Selection Register 17-38 17.7.3.3 GPTUx_OUT, GPTU Output Register. 17-39 User's Manual 2000-01
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17.7.3.4 17.7.3.5 17.8 17.8.1 17.8.2 17.8.2.1 17.8.2.2 17.8.3 18.1 18.2 18.3 18.4 18.4.1 18.4.1.1 18.4.1.2 18.4.1.3 18.4.2 18.4.3 18.4.4 18.5 18.5.1 18.5.2 18.5.3 18.6 18.6.1 18.6.1.1 18.6.1.2 18.6.2 18.7 18.8 18.9 18.9.1 18.9.2 18.9.3 18.9.4 18.9.5 18.9.6 18.9.7 18.10 18.10.1 18.10.2 18.10.3 18.10.4 18.10.5 GPTUx_SRSEL, Service Request Source Selection Register GPTUx_ID, Identification Register GPTU Implementation Peripheral Input Output Selection External GPTU Registers GPTUx_CLC, GPTU Clock Control Register GPTUx_SRC0.7, Service Request Control Registers GPTU Register Table
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17-41 17-43 17-44 17-44 17-44 17-45 17-46 17-47
Asynchronous/Synchronous Serial Interface 18-2 Asynchronous/Synchronous Serial Interface Overview 18-2 Interface Overview 18-2 Kernel Functions 18-3 Asynchronous Operation 18-5 Asynchronous Data Frames 18-6 Eight-Bit Data Frames 18-7 Nine-Bit Data Frames 18-7 Infrared Data Association (IrDA) Frames 18-8 Asynchronous Transmission 18-9 Asynchronous Reception 18-9 IrDA Mode 18-10 Synchronous Operation 18-11 Synchronous Transmission. 18-12 Synchronous Reception 18-13 Synchronous Timing 18-13 Baud Rate Generation 18-14 Baud Rates Asynchronous Mode 18-15 Using Fixed Input Clock Divider 18-16 Using Fractional Divider 18-17 Baud Rates Synchronous Mode 18-17 Hardware Error Detection Capabilities 18-18 Interrupts 18-19 Kernel Registers 18-20 ASCx_ID, Identification Register. 18-21 ASCx_CON, Control Register 18-22 ASCx_BG, Baud Rate Timer Reload Register 18-24 ASCx_FDV, Fractional Divider Register 18-25 ASCx_PMW, IrDA Pulse Mode Width Register 18-25 ASCx_TBUF, Transmit Buffer Register 18-26 ASCx_RBUF, Receive Buffer Register 18-27 Implementation 18-27 External Registers 18-27 ASCx_CLC, Clock Control Register 18-28 ASCx_PISEL, Peripheral Input Selection Register 18-29 Service Request Control Registers 18-30 ASCx Register Table 18-31 High-Speed Synchronous Serial Interface 19-2 2000-01
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19.1 19.1.1 19.2 19.3 19.3.1 19.3.2 19.3.3 19.3.4 19.3.5 19.3.6 19.3.7 19.3.8 19.4 19.4.1 19.4.2 19.4.2.1 19.4.2.2 19.4.3 19.4.4 19.4.5 19.5 19.5.1 19.5.2 19.5.3 19.5.4 19.5.5 20.1 20.2 20.2.1 20.2.2 20.3 20.3.1 20.3.2 20.3.3 20.3.4 20.3.5 20.3.6 20.4 20.4.1 20.4.1.1 20.4.1.2 20.4.1.3 20.4.1.4 20.4.1.5 20.4.2
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High-Speed Synchronous Serial Interface Overview 19-2 Features 19-2 Interface Overview 19-3 Kernel Description 19-3 General Operation 19-4 Operating Mode Selection 19-4 Full-Duplex Operation 19-6 Half-Duplex Operation 19-8 Continuous Transfers 19-9 Port Control 19-10 Baud-rate Generation 19-10 Error Detection Mechanisms 19-11 Kernel Registers 19-13 SSCx_ID, Identification Register 19-14 SSCx_CON, Control Register 19-14 Register SSCx_CON Programming Mode 19-15 Register SSCx_CON Operating Mode 19-16 SSCx_BR, Baud Rate Timer Reload Register 19-17 SSCx_TB, Transmit Buffer Register 19-18 SSCx_RB, Receive Buffer Register 19-18 Implementation 19-19 External Registers 19-19 SSCx_CLC, Clock Control Register 19-20 SSCx_PISEL, Peripheral Input Select Register 19-20 Service Request Control Registers 19-21 SSCx Register Table 19-23 Parallel Ports 20-2 Overview Parallel Ports 20-2 Port Kernel Functions 20-3 Features 20-3 Port operation 20-3 Port Kernel Registers 20-6 Px_OUT, General Purpose Output Data Register 20-7 Px_IN, General Purpose Input Data Register 20-7 Px_DIR, Port Direction Control 20-8 Px_OD, Open Drain Output Control 20-8 Px_PUDSEL Px_PUDEN, Port Pull Device Control 20-9 Px_ALTSEL0 Px_ALTSEL1, Alternate Function Selection Registers 20-10 Port Implementation 20-11 Peripheral Interconnections 20-12 Detailed GPTU0 Interconnection 20-13 Detailed GPTU1 Interconnection 20-14 Detailed ASC0 Interconnection 20-17 Detailed ASC1 Interconnection 20-17 Detailed SSC0 Interconnection 20-17 Register Addresses 20-20 2000-01
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Appendix TC10GP Address 21-2 Index 21-2
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Introduction
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Introduction
Introduction
This User's Manual describes Infineon TC10GP, industry's first single-chip 32-bit microcontroller-DSP, based Infineon TriCore Architecture. TC10GP designed meet needs most demanding embedded control systems applications where competing issues price/performance, real-time responsiveness, computational power, data bandwidth, power consumption design elements. TC10GP combines three powerful technologies within silicon die, achieving levels power, speed, economy embedded applications: Reduced Instruction Computing (RISC) processor architecture Digital signal processing (DSP) operations addressing modes On-chip memory peripherals operations addressing modes provide computational power necessary efficiently analyze complex real-world signals. RISC load/store architecture provides high computational bandwidth with system cost. On-chip memory peripherals designed support even most demanding high-bandwidth real-time embedded control-systems tasks. Additional high-level features TC10GP include: Program Memory Unit-instruction memory instruction cache Data Memory Unit-data memory data cache Serial communication interfaces-flexible synchronous asynchronous modes Peripheral Control Processor-DMA operations interrupt servicing General-purpose timers On-chip debugging emulation facilities Flexible interconnections external components Flexible power-management
Please section titled Detailed TC10GP Features more information about TC10GP features. About Infineon TriCore Architecture
Infineon TriCore Architecture specifies family compatible semiconductor components means combine them variety ways produce many different products. Infineon TC10GP embodiment Infineon TriCore Architecture. complete description TriCore architecture found document titled TriCore µC-DSP Architecture Manual. This TC10GP User's Manual manual describes features TC10GP with respect TriCore Architecture. Where TC10GP directly implements TriCore architectural functions, this manual simply refers those functions features TC10GP. cases where this manual describes TC10GP feature without referring TriCore Architecture, this means that TC10GP direct embodiment TriCore Architecture. Where TC10GP implements subset TriCore architectural features, this manual describes TC10GP implementation, then describes differs from TriCore Architecture. example, where TriCore Architecture specifies up-to four Memory Protection Register Sets, TC10GP implements two. Such differences between TC10GP TriCore Architecture documented text covering each such subject. User's Manual 2000-01
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1.2.1 About This Document Intended audience
This document designed read primarily design engineers software engineers need detailed description interactions TC10GP functional units, registers, instructions, exceptions. 1.2.2 Related Documentation
complete description TriCore architecture found document titled TriCore µC-DSP Architecture Manual. architecture TC10GP described separately this because configurable nature TriCore specification: different versions architecture contain different systems components. TriCore architecture, however, remains constant across derivative designs order preserve compatability. implementation-specific details TC10GP found Infineon TC10GP Data Sheet. 1.2.3 Textual conventions
This document uses following textual conventions named components TC10GP. Functional units TC10GP given plain UPPER CASE. example, "The provides interface external peripherals." Register names, bit-field names, code examples appear UPPER-CASE CONSTANT-WIDTH FONT. example, "The mnemonic Interrupt Control Register ICR." names also appear UPPER-CASE CONSTANT-WIDTH FONT. Pins using negative logic indicated overbar. example, "The BYPASS latched with rising edge pin." Bit-fields registers given Registername_Bitfield example, "The Current Priority Number bit-field register called ICR_CCPN." Variables used describe sets processing units registers appear mixed-case constant-width italic font. example, CPRx_nL refers registers CPR0_0L through CPR1_3L. bounds variables always given where register expression first used, repeated needed rest text. Variables expressions (such "Interrupt where range 0.3") appear regular italic font. 1.2.3.1 Radix
default radix decimal. Hexidecimal constants prefixed with "0x" programming language, they suffixed with subscript letter "H", Binary constants suffixed with subscript letter "B", 111B. 1.2.3.2 Fields Ranges
When extent register fields, groups signals, groups pins collectively named body document, they given NAME[U:L], which defines range named group from inclusive. Individual bits, signals, pins given NAME[n] where range variable
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given text. example: CLKSEL[2:0], TOS[0]. range field written U:L,
without brackets. range number given U.L, some specified range values 1.2.4 Units
Units abbreviated follows: kbaud Mbaud Kbyte megaherz microseconds 1000 characters second 1,000,000 characters second 1024 bytes memory
general, prefix scales unit 1000 whereas prefix scales unit 1024. Hence, Kbyte unit scales expression preceding 1024. kbaud unit scales expression preceding 1000. prefix scales 1,000,000, scales .000001. example, Kbyte 1024 bytes, kbaud 1000 characters second, 1,000,000 1.2.5 Reserved, Undefined, Unimplemented Terminology
tables where register bit-fields defined, following conventions used indicate undefined unimplemented functions. 1.2.5.1 Unimplemented
Register bit-fields named indicate unimplemented functions with following behavior. Reading these bit-fields returns Writing these fields effect. These bit-fields reserved. When writing, software should always such bit-fields order preserve compatibility with future products. 1.2.5.2 Undefined
Certain combinations bit-field labeled Undefined, indicating that behavior TC10GP undefined that combination bits. Setting register undefined combinations lead unpredictable results. Such combinations reserved. When writing, software should always such bit-fields legal values given tables. 1.2.6 Register Access Modes
Read write access registers bit-fields registers sometimes restricted. memory register access tables, following terms used. U-User Mode: Processor mode non-privileged tasks. Restricts access certain registers functions. User's Manual 2000-01
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SV-Supervisor Mode: Processor mode reserved operating system routines privileged tasks. Grants access registers functions. NC-No change: indicated register bit-field does change when read written. E-ENDINIT protected: special password access procedure must invoked access indicated register, address, bit-field. BE-Bus Error: Indicates address address range that will generate Error accessed. bitfield read written. bitfield only read (read-only). bitfield only write (write-only). bitfield also modified hardware (such status bit). This symbol found connection with `rw' `r'. information User Supervisor Mode, section titled Permission Levels. information about ENDINIT protection, chapter titled Watchdog Timer.
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Detailed TC10GP Features
Detailed features Infineon TC10GP include: High-performance 32-bit micro-controller-DSP Processor registers managed using explicit Load/Store instructions 16-bit multiply-accumulate operations (MAC) execute simultaneously Processor addressing modes support algorithms Super-scalar processor design uses three instruction pipelines GByte address range (232) General-purpose register Core Special Function Registers (CSFR) provide processor control status 16-bit 32-bit instruction formats freely intermixed reduced code size Fast context switching interrupt latency Separate co-processor Executes specialized instructions such parity generation Seamless instruction integration-uses same instruction issue hardware On-chip memory Zero Kbyte instruction SRAM Kbyte instruction cache Kbyte data SRAM Zero Kbyte data cache Internal components connected Flexible Peripheral Interconnect (FPI) Peripheral Control Processor off-loads direct memory access (DMA) operations from used data transfers peripheral control Includes Kbyte parameter SRAM Kbyte code SRAM On-chip serial interfaces on-chip Universal Synchronous/Asynchronous Serial Interfaces (USARTs) communication other micro-controllers, microprocessors, external peripherals High-Speed Synchronous Serial Interface (SSC0) provides serial communication between TC10GP other microcontrollers, microprocessors, external peripherals Timers Three configurable General-Purpose Timers, plus dedicated pins function control Watchdog Timer System Timer with 56-bit precision On-chip Power Management Low-power operation each TC10GP component customized each application Power management includes running, idle, sleep, deep-sleep modes External Interface (EBU) connects TC10GP external components 32-bit data 24-bit address Demultiplexed multiplexed operation IntelTM-style peripheral interface Synchronous DRAM interface Four decoded chip-select Emulator chip-select outputs External master access internal separate chip-select input Emulation memory support
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Three General Purpose 8-bit Ports On-chip emulation debug support Several types reset: external power-up reset, external hard reset, software reset, watchdog timer reset, wake-up reset from power-down mode. TC10GP Architectural Overview
Figure provides simplified high-level view TC10GP on-chip components. These summarized following paragraphs.
System Components
Program Memory Unit Data Memory Unit External Pins
Control Unit
Watchdog Timer
Power Management Unit
TriCore
System Clock (Osc. PLL)
OCDS JTAG
System Timer
Peripheral Control Processor Memory
Synchronous Serial Interface
External Interface
Async/Sync Serial Interface Async/Sync Serial Interface
GeneralPurpose
GeneralPurpose Timer Unit GeneralPurpose Timer Unit
Peripheral Components
External Pins
Figure TC10GP Block Diagram
TriCore Central Processing Unit (CPU) TC10GP based TriCore Architecture. 32-bit micro-controller-DSP, optimized real-time embedded systems. TriCore processor architecture based Harvard architecture, which separates address data buses
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program data memories. three pipelines, each arithmetic instructions, load/store instructions, loop-control instructions. Program Memory Unit Data Memory Unit TC10GP contains separate program data memory units (PMU DMU). These units each consist on-chip local memory, cache, interface bus. configured either Kbyte instruction SRAM Kbyte instruction cache, Kbyte instruction cache. cache two-way set-associative. configured either Kbyte data SRAM Kbyte data cache, Kbyte data SRAM. cache two-way set-associative. Control Unit high-speed internal interconnects internal peripherals. Control Unit (BCU) arbitrates access bus, granting access handling errors. External Unit External Unit (EBU), provides external interface between TC10GP external devices. This interface demultiplexed 24-bit address 32-bit data bus. connects various types memories and/or peripherals without additional external logic components, including Intel TM-style peripherals (those having separate read data write data signals), ROM, EPROM, Static RAM, synchronous DRAM. sometimes called External Interface. Peripheral Control Processor Peripheral Control Processor (PCP) associated memory performs most tasks that normally done combination controller interrupt service routines. off-loads most time-critical interrupt-driven tasks, thereby reducing contextswitching overhead these tasks. This approach also eases implementation real-time functions applications based non-real-time operating systems. need kernel task management, efficiently supports DMA-type transactions between peripheral devices memory. programmable memory. Watchdog Timer Watchdog Timer (WDT) provides reliability verification recovery from software hardware failure. System Timer System Timer (STM) high-precision, long-range 56-bit timer that provides global system time. General-Purpose Timer Units General-Purpose Timer Units (GPTU0 GPTU1) each contain three 32-bit timers (T0, timing events, counting events, recording events. They stand-alone connected together solve more complex tasks. configured four 8-bit timers concantenated form wider timers (16, 32-bit timers). configured 16-bit timers concatenated form 32-bit timer. Asynchronous/Synchronous Serial Interfaces Asynchronous/Synchronous Serial Interfaces (ASC0 ASC1) provide serial communication between TC10GP other microcontrollers, microprocessors, external peripherals. They identical, operate either asynchronous synchronous mode. Synchronous Serial Interface high-speed Synchronous Serial Interface (SSC0) supports full-duplex half-duplex synchronous communication between TC10GP other microcontrollers, 2000-01
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microprocessors, external peripherals. serial clock signal generated SSC0 itself master mode) driven external master slave mode). Data width, shift direction, clock polarity phase programmable, enabling communication with SPIcompatible devices. System Clock, Oscillator, Phase-Locked Loop TC10GP contains on-chip oscillator well phase-locked loop (PLL) circuit allow TC10GP synchronize external clocks. This permits TC10GP operate lowfrequency external clock while still providing maximum performance. monitors frequency deviations detect external clock failure, cause execution emergency recovery actions. TC10GP's flexible clocking system minimizes power consumption reduces EMI. Power Management System power management functions TC10GP accommodate battery-powered applications requiring careful power conservation. These functions provide long battery life manage power loss. They also limit peak power consumption during turn-on reset TC10GP order avoid unnecessary power fault conditions. There four power-management modes: Run, Idle, Sleep, Deep Sleep. On-Chip Debugging System JTAG Module TC10GP provides robust on-chip debugging (OCDS), JTAG interface conforms IEEE Standard 1149.1. Parallel Ports on-chip GPTU0 GPTU1, ASC0, ASC1 SSC0 peripherals connected three 8bit wide ports with flexible programming options general-purpose peripheral input/output functions.
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Processor Architecture
Central Processing Unit (CPU) TC10GP based Infineon TriCore 32-bit microcontroller-DSP processor architecture. optimized real-time embedded systems, combines following features. Reduced Instruction Computing (RISC) architecture Digital signal processing (DSP) operations data structures Real-time processing using CISC instructions RISC load/store architecture provides high computational bandwidth with system cost. superscalar design three pipelines. TC10GP Harvard-style architecture, with separate address data buses program data memories. There special instructions common operations hardware-assisted data structure index generation circular buffers (useful filters) bitreversed indexing (useful Fast Fourier Transforms). These features make possible efficiently analyze complex real-world signals. CPU's interrupt-processing architecture combines quick responsiveness associated with microcontrollers with high degree interrupt-service flexibility. architecture minimizes interrupt latency having uninterruptable multi-cycle instructions, supporting fast context switching, supporting task-based memory protection. combination interruptprocessing capabilities Peripheral Control Processor (PCP) provide system designer with tools meet even most demanding hard-deadline real-time scheduling requirements simply efficiently. While TriCore architecture employs 32-bit instruction formats, frequently-used instructions have optional 16-bit instruction format. This results smaller code size, faster code bandwidth. Additional benefits this approach include lowered program memory requirements, lower system cost, less power consumption. TC10GP Processor Architecture Overview
This section provides overview TC10GP Central Processing Unit (CPU) architecture. basic features include following. Data paths: bits throughout Address space: Gigabytes, unified, data, program, Instruction formats: mixed 32-bit 16-bit formats interrupt latency flexible interrupt prioritization scheme Fast automatic context switching Separate multiply-accumulate unit Saturating integer arithmetic Bit-handling operations Packed-data operations Zero-overhead looping Flexible power management Byte addressing Little-endian byte ordering Precise exceptions 2000-01
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2.1.1 Program State Registers
state entire processor represented Program State Registers (PSR). register consists General-Purpose Registers (GPRs), 32-bit registers containing program status information (PCXI PSW), 32-bit program counter (PC). PCXI, PSW, part Core Special Function Registers (CSFRs). shown Figure 2-1, General-Purpose Registers divided into sixteen 32-bit data registers through D15) sixteen 32-bit address registers through A15).
General-Purpose Registers Address Registers Data Registers
Program Status Information PCXI
Figure Program State Registers 2.1.2 Data Types
TriCore instruction supports operations Booleans, bit-strings, characters, signed fractions, addresses, signed unsigned integers, single-precision floating-point numbers. While most instructions designed specific data type, some useful manipulating several data types. 2.1.3 Addressing Modes
Addressing modes enable load store instructions access data elements within data structures efficiently. Examples include records, randomly- sequentially-accessed arrays, stacks, circular buffers. Data elements bits wide. Addressing modes provide efficient compilation programs written programming language, easy access peripheral registers, efficient implementation typical data User's Manual 2000-01
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structures. Hardware-assisted data structures include circular buffers filters, bitreversed indexing FFTs. following seven addressing modes supported TriCore architecture: Absolute Base Short Offset Base Long Offset Pre-increment pre-decrement Post-increment post-decrement Circular (modulo) Bit-Reverse Instruction Formats
2.1.4
architecture supports both 32-bit instruction formats. instructions have 32-bit format. 16-bit instructions subset 32-bit instructions, chosen because their frequency use, included reduce code space. 2.1.5 Tasks Contexts
Throughout this document, term task refers independent thread control. There types tasks: Software Managed Tasks (SMTs) Interrupt Service Routines (ISRs). Software-managed tasks created through services real-time kernel operating system, dispatched under control scheduling software. Interrupt Service Routines dispatched hardware response interrupt. Interrupt Service Routine code that invoked processor directly receipt interrupt. Software-managed tasks sometimes referred User Tasks, assuming that they will execute User Mode. Each task allocated permission level. individual permissions enabled disabled primarily mode bits Program Status Word (PSW). processor state associated with task called task's context. context includes everything processor needs order define current state task. system saves current task's context when another task about run, restores task's context when task resumed. context includes Program State Registers. efficiently manages maintains tasks' contexts through hardware. 2.1.5.1 Upper Lower Contexts
task's context subdivided into Upper Context Lower Context, illustrated Figure 2-2. Upper Context consists upper address registers, A15, upper data registers, D15. These registers designated non-volatile, purposes function calling. Upper Context also includes PCXI registers. Lower Context consists lower address registers, through lower data registers, through saved again PCXI register. Both Upper Lower Contexts include Link Word contained register PCXI. Contexts saved fixed-size areas memory described section titled Context Save Areas; they linked together Link Word.
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Upper Context, registers used special purpose. holds return address (RA), while holds stack pointer value (SP). Four General-Purpose Address Registers part Upper Lower Context. regarded global registers which shared among tasks which saved restored. Upper Context saved automatically interrupts. also saved CALL instructions restored RETURN instructions. Lower Context must saved restored Interrupt Service Routine (ISR) needs more registers than available Upper Context. Note With exception registers A11, upper context registers interrupted calling function inherited. Only Stack Pointer (SP) register, A10, Return Address (RA) register, A11, start with defined values interrupt handler called function.
Lower Context saved PCXI
Upper Context (RA) (SP) PCXI
Figure Upper Lower Contexts 2.1.5.2 Context Save Areas
accommodate systems with multiple interacting threads control, uses linked lists fixed-size Context Save Areas (CSAs). words on-chip memory storage, aligned 16-word boundary. single hold exactly Upper Lower Context. Unused CSAs linked together free list. They allocated from free list needed, returned when longer needed. Allocation freeing handled transparently processor.
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Typically, only system initialization code certain operating system exception-handling routines need access CSAs their lists explicitly. number CSAs which used only limited size available data memory. Note TC10, Context Save Areas only located either local data scratch-pad (DSRAM) external memory cacheable segment data cache disabled, CSAs only reside DSRAM. 2.1.5.3 Fast Context Switching
TC10GP uses uniform context-switching method function calls, interrupts, traps. cases, task's Upper Context automatically saved restored hardware. Saving restoring Lower Context left option task. explanation manages contexts found section titled Context Management Registers. 2.1.6 Interrupt System
interrupt request generated TC10GP on-chip peripheral units generated external events. Requests either targeted CPU, Peripheral Control Processor (PCP). order better differentiate programmable stages interrupt processing available TC10GP, this document refers interrupt-triggering event interrupt service request. TC10GP interrupt system evaluates service requests priority which unit (the PCP) should receive request. highest-priority service request then presented PCP) interrupt. specific contexts where above level formality required, term interrupt used generally mean event directed CPU, while term service request describes event that directed either PCP. interrupt, entry code Interrupt Service Routine (ISR) contained Interrupt Vector Table. Each entry this table corresponds fixed-size code block. requires more code than fits entry, must include jump instruction vector rest elsewhere memory.) Each interrupt source assigned interrupt priority number. priority numbers programmable. uses priority number determine location entry code block. prioritization service routines enables nested interrupts interrupt priority groups. chapter titled Interrupt System more information. 2.1.7 Trap System
Trap events break normal execution code much like interrupts. traps different from interrupts these ways: Trap Service Routines (TSR) reside Trap Vector Table, separate from Interrupt Vector Table. trap does change CPU's interrupt priority. Traps cannot disabled software, always active.
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trap occurs result exception within following classes events. Internal Protection Instruction Errors Context Management Internal Peripheral Errors Assertion System Call Non-Maskable Interrupt
Each entry Trap Vector Table corresponds fixed-size code block. requires more code than fits entry, must include jump instruction vector rest elsewhere memory.) When trap taken, Trap Identification Number (TIN) placed data register D15. trap handler uses identify cause trap. During trap arbitration, pending trap with lowest will chosen execute. 2.1.8 Protection System
There protection systems TC10GP. memory-access protection system protects code data memory regions, described sections titled Permission Levels Memory Protection Model. Access sensitive system registers protected hardware against system malfunctions, described chapter titled Watchdog Timer ENDINIT Protection. 2.1.8.1 Permission Levels
Each task assigned specific permission level. Individual permissions enabled through mode bits Program Status Word (PSW). three permission levels are, decreasing order restrictveness, shown below. User-0 Mode assigned unprivileged user tasks. Tasks this level have permission access peripherals enable disable interrupts. User-1 Mode assigned tasks that access common, unprotected peripherals. This typically includes read access serial ports, read access timers, read access most status registers. Tasks this level disable interrupts. Supervisor Mode assigned tasks that must able access system resources. 2.1.8.2 Memory Protection Model
memory protection model based address ranges, where each address range associated permission setting. Address ranges their associated permissions specified identical sets tables residing Core Special Function Register (CSFR) space. Each referred Protection Register (PRS). TC10GP incorporates sets Protection Register Sets each code data memory. number sets implementation-specific: other TriCore products implement different number Protection Register Sets. When protection system enabled, checks every load/store instruction fetch address before performing access. Legal addresses must fall within ranges specified currently selected PRS, permission that type access must present matching range. User's Manual 2000-01
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2.1.8.3 Watchdog Timer ENDINIT Protection
Registers which control basic TC10GP configuration operation protected special End-of-Initialization (ENDINIT) bit. ENDINIT globally protects those TC10GP registers which control basic system configuration against unintentional modification. Write accesses registers protected this ENDINIT-bit prohibited long this clear enable access these registers again, special password-protected access sequence Watchdog Timer registers performed. again within defined time-out period, otherwise system malfunction assumed have occurred, Watchdog Timer triggers reset TC10GP. Watchdog Timer chapter more details. 2.1.9 Reset System
Several events will cause TC10GP system reset: Power-On Reset: activated through external when power device turned (also called cold reset) Hard Reset: activated through external during time (also called warm reset) Soft Reset: activated through software write reset-request register, this register special protection mechanism prevent accidental access Watchdog Timer Reset: activated through error condition detected Watchdog Timer Wake-up Reset: activated through external wake device from powermanagement mode reset status register informs which kind event caused reset. 2.1.10 Processor Registers processor contains general-purpose registers store instruction operands. specialpurpose registers managing state processor itself. 2.1.10.1 Core Special Function Registers CPU's operations controlled Core Special Function Registers (CSFRs). These registers also provide status information about operation. CSFRs split into following groups: Program State Information Context Management Stack Management Interrupt Trap Control System Control Memory Protection Debug Control
following sections summarize these registers. CSFRs complemented General-Purpose Registers (GPRs). Table shows CSFRs GPRs.
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Table Processor Register Register Name PCXI SYSCON DPRx_0 DPRx_3 CPRx_0 CPRx_1 DPMx_0 DPMx_3 CPMx_0 CPMx_1 DBGSR EXEVT SWEVT CREVT TRnEVT Description General-Purpose Data Registers General-Purpose Address Registers Program Status Word Previous Context Information Register Program Counter Free Context List Head Pointer Free Context List Limit Pointer Interrupt Stack Pointer Interrupt Control Register Base Address Interrupt Vector Table Base Address Trap Vector Table System Configuration Register Data Range Protection Registers Code Range Protection Registers Data Protection Mode Registers Code Protection Mode Registers Debug Status Register External Break Input Event Specifier Software Break Event Specifier Core Access Event Specifier Trigger Event Specifier
accesses CSFRs through instructions: MFCR MTCR. MFCR instruction (Move From Core Register) moves contents addressed CSFR into data register. MFCR executed privilege level. MTCR instruction (Move Core Register) moves contents data register addressed CSFR. prevent unauthorized writes CSFRs, MTCR instruction only executed Supervisor privilege level. CSFRs also mapped into segment memory address space. This mapping makes complete architectural state visible address map. This feature provides efficient debug emulator support. Note allowed access CSFRs through this mechanism-it must MFCR MTCR instructions. Trying access CSFRs through normal load store instructions results trap. instruction provides single-bit, bit-field, load-modify-store accesses CSFRs. only other instruction, affecting CSFR, RSTV instruction (Reset Overflow Flags), which User's Manual 2000-01
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resets only overflow flags PSW, without modifying other bits. This instruction executed privilege level. Note Access Core SFRs through their mapped addresses segment implemented primarily debug purposes. Special attention needs paid when accessing these registers. strongly advised write CSFRs while core executing. Reading registers while core running does guarantee coherent status information. high range emulator external fast route internal FPIBus. However, certain restrictions placed this mode operation regarding access CSFRs GPRs: external used access state core (GPRs CSFRs) while core running (i.e. halted) configured perform accesses external bus. 2.1.10.2 General-Purpose Registers Figure shows General-Purpose Registers (GPRs). 32-bit wide GPRs split evenly into data registers, DGPRs, D15) address registers, AGPRs, A15). Separation data address registers facilitates efficient performance arithmetic memory operations parallel. Several instructions interchange information between data address registers order, example, create derive table indexes. 64-bit values represented concatenating consecutive double-word-aligned data registers. Eight such extended-size registers (E0, E10, E12, E14) available.
General-Purpose Address Registers (AGPR) (implicit address) (return address) (stack pointer) (global address) (global address) (global address) (global address)
General-Purpose Data Registers (DGPR) (implicit data) 64-Bit Extended Data Registers
Figure General-Purpose Registers (GPRs) shown Figure 2-3, registers defined System Global Registers. Their contents saved restored across calls, traps, interrupts. Register used stack pointer (SP) register. used store return address (RA) calls linked jumps
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store return program counter (PC) value interrupts traps part Upper Context. 32-bit instructions have unlimited GPRs. However, many 16-bit instructions implicitly their address register their data register make encoding these instructions into bits possible. There separate floating-point registers-the data registers used perform floating-point operations. Floating-point data saved restored automatically using fast context-switching capabilities TC10GP. GPRs essential part task's context. When saving restoring task's context from memory, context split into Upper Context Lower Context shown Figure Registers through through part Lower Context. Registers through through part Upper Context. 2.1.10.3 Program State Information PSW, PCXI registers hold reflect Program State Information. When saving restoring task's context, contents these registers saved restored modified during this process. five most-significant bits contain status flags that cleared arithmetic instructions. remaining bits control permission levels, protection register sets, call depth counter.
PCXI contains linkage information previous execution context, supporting fast interrupts
automatic context switching. 2.1.10.4 Context Management Registers Context Management Registers (CMR) comprised three pointer registers, FCX, PCX, LCX. These pointers handle context management used during context save/restore operations. Each pointer register consists fields: 16-bit offset 4-bit segment specifier. ContextSave Area (CSA) address range containing word locations bytes). Each save Upper Context Lower Context. Incrementing pointer offset value points that word locations above previous one. pointer register points head free list. previous context pointer (PCX) points previous task. part previous context information register PCXI. pointer register used recognize impending list underflows. value used interrupt CALL instruction matches limit value, context-save operation completes, target address forced trap vector address that handles list depletion. 2.1.10.5 Stack Management General-purpose address register designated Stack Pointer (SP). initial contents this register usually RTOS instruction when task created, which allows private stack area assigned individual tasks.
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When entering Interrupt Service Routines (ISRs), Stack Pointer loaded with contents separate register, Interrupt Stack Pointer (ISP), after saving previous contents with Upper Context. This helps prevent interrupt service routines from accessing private stack areas possibly interfering with software-managed task's context. 2.1.10.6 Interrupt Trap Control Three CSFRs support interrupt trap handling: Interrupt Control Register (ICR), Interrupt Vector Table Pointer (BIV), Trap Vector Table Pointer (BTV). holds current priority number (CCPN), enable/disable interrupt system, pending interrupt priority number, implementation-specific control interrupt arbitration scheme. other registers hold base addresses interrupt BIV) trap vector tables (BTV). 2.1.10.7 System Control Register System Configuration Control Register (SYSCON) provides enable/disable memory protection system status flag Free Context List Depletion condition. 2.1.10.8 Memory Protection Registers described Protection System, specified memory ranges protected from unauthorized read-, write-, instruction-fetch accesses. addition, protection hardware used generate signals Debug Unit.The TC10GP contains register sets that specify addresses access permissions number memory ranges. There separate register sets code data memory. two-bit field register enables selection four such register sets (four data four code). TC10GP incorporates sets each data code memory protection. Data Range Protection Register Sets Code Range Protection Register Sets, DPRx_n CPRx_n, specify lower upper boundary address associated memory range. upper- lower-boundary addresses, TC10GP implements four register pairs each data memory protection set, register pairs each code memory protection set. Please refer chapter titled Memory Protection. These registers also used store individual addresses that cause program break-points when debugging. 8-bit field Data Code Protection Mode Registers DPMx_n CPMx_n) determines access permissions debug signal conditions ranges specified their corresponding Range Protection Registers. 2.1.10.9 Debug Registers registers implemented support debugging. These registers define conditions under which debug event generated, actions taken assertion debug event, status information supplied debug functions.
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TC10GP Central Processing Unit
Figure illustrates architecture TC10GP's Central Processing Unit (CPU). comprised Instruction Fetch Unit, Execution Unit, General-Purpose Register File, several peripheral interfaces.
Program Memory Unit (PMU) TriCore Processor, TC10GP System Control Interrupts Core Register Access Debug/ Emulation Test
Instruction Fetch Unit
Integer Pipeline
Loop Pipeline Execution Unit
Load/Store Pipeline
General-Purpose Register File (GPR)
Data Memory (DMU) Figure Central Processing Unit (CPU) Block Diagram Instruction Fetch Unit
Figure shows Instruction Fetch Unit. prefetches aligns incoming instructions from 64-bit wide Program Memory Unit (PMU). Issue Unit directs instruction appropriate pipeline. Instruction Protection Unit checks validity accesses also checks instruction breakpoint conditions. Unit responsible updating issue prefetch program counters.
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Program Memory Unit
Instruction Protection Unit
Prefetch Align Injection
Debug
Issue Unit
Integer Pipeline
Loop Load/Store Pipeline Pipeline
Figure Instruction Fetch Unit Execution Unit
shown Figure 2-6, Execution Unit contains Integer Pipeline, Loop Pipeline, Load/Store Pipeline. Integer Pipeline Load/Store Pipeline have four stages: Fetch, Decode, Execute, Writeback. Execute stage extend beyond cycle accommodate multicycle operations such load instructions. Loop Pipeline stages, Decode Write-back. three pipelines operate parallel, permitting three instructions execute cycle.
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Integer Pipeline
Loop Pipeline
Load/Store Pipeline
Decode
Decode
Load/Store Decode
Execute
Processor Loop Exec. Address
Register File
Figure Execution Unit Figure introduces following acronyms abbreviations: Decode-Instruction Prefetch Decode MAC-Multiply-Accumulate Unit ALU-Arithmetic/logic Unit Loop Exec.-Loop Execution Unit EA-Effective Address General-Purpose Register File
General-Purpose Register (GPR) file, divided into Address Register File (registers through A15) Data Register File (registers through D15). data flow instructions issued to/from Load/Store Pipeline steered through Address Register File. data flow instructions issued to/from Integer Pipeline data load/store instructions issued to/from Load/Store Pipeline steered through Data Register File.
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Pipelines
Data Register File General-purpose Register File
Address Register File
Data Alignment Data Memory Unit
Figure General-Purpose Register File
Core Special Function Register Descriptions
Core Special Function Registers (CSFRs) which closely related CPU's operation described detail following sections. description remaining registers found respective chapters which detail operation controlled through these registers. memory protection registers handled chapter Memory Protection, Interrupt Unit Control register, ICR, described chapter Interrupt System. debug functions asscociated control registers discussed current version this document. 2.6.1 Program Counter
program Counter (PC) holds address instruction which currently fetched forwarded pipelines. handles updates automatically. Software current value example, perform code address calculations. Reading through software executed must only done with MFCR instruction. Explicit writes through MTCR instruction must done possible unexpected behavior CPU. Note must perform Load/Store instructions mapped address segment trap will generated such case. Note Reading while Core executing, either through MFCR instruction mapped address segment (see below), will return value which representative where code currently executed from, however, guaranteed that value returned will always correspond instruction which been will executed. example, possible that points target predicted branch which User's Manual 2000-01
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Processor Architecture
subsequently resolved mispredicted. Thus, branch target instruction will executed. however, should possible implement statistical profile/coverage report with some degree error sampling value while running. debug mode, explicit read write operations performed using mapped address segment This must only done through FPI-Bus master other than itself (through DMU). Several restrictions apply this operation: Writing while Core executing non-deterministic user strongly advised correct sequence which user should adopt halt Core, modify remove Core from Halt mode. Reading while Core halted will return first instruction executed once Core released from Halt mode. only exception this interrupt asynchronous trap received Core immediately after removed from Halt mode prior first instruction being executed. Writing while Core halted will modify deterministic way. value will first instruction executed once Core released from Halt mode. only exception this interrupt asynchronous trap received Core immediately after removed from Halt mode prior first instruction being executed.
Program Counter (BAddr FE08H)
Reset Value A000 0000H External Boot 8000 0000H Internal Boot BE00 0000H Emulator Boot
PC[31:16]
PC[15:1]
Field
31:1
Type
Value Function Program Counter Value. Reserved
Note that register read-only bit, hard-wired This ensures that only half-word aligned addresses placed into (instructions only aligned half-word addresses). 2.6.2 PSW, Program Status Word
Program Status Word (PSW) register holds instruction flags control bits number options overall protection system. User's Manual 2000-01
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special instruction available which affects only overflow flag bits register PSW. RSTV (Reset Overflow Flags) instruction clears bits without modifying other bit. PSW. Program Status Word (BAddr FE04H)
Reset Value 0000 0B80H
Field Bits
Type Value
Description Protection Register Control. Selects active Data Code Memory Protection Register Set. Select Memory Protection Register Select Memory Protection Register Undefined, reserved. Undefined, reserved. Access Privilege Control. User-0 Mode: peripheral access. Access segments prohibited will result trap. This access level given tasks that need directly access peripheral devices. Tasks this level have permission enable disable interrupts. User-1 Mode: regular peripheral access. This access level enables access common peripheral devices that specially protected, including read/write access serial ports, read access timers, access most status registers. Tasks this level disable interrupts. Supervisor Mode. This access level enables access peripheral devices. enables read/write access core registers protected peripheral devices. Tasks this level disable interrupts. Undefined, reserved.
13:12
11:10
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Field Bits Type Value Description Interrupt Stack Control. Determines whether current execution thread using shared global (interrupt) stack user stack. User Stack. interrupt taken when then stack pointer register loaded from register before execution starts first instruction Interrupt Service Routine. Shared Global Stack. interrupt taken when then current value stack pointer register used Interrupt Service Routine. Global Address Register Write Control. Determines whether current execution thread permission modify global address registers. Modification global address registers prohibited. Modification global address registers permitted. Most tasks ISRs will only read global address registers, which point global memory pool data structures. However, task designated manage modify particular global address register. Note: system designer must determine which global address variables used with sufficient frequency and/or sufficiently time-critical code justify allocation global address registers. Call Depth Counter Enable. enables call-depth counting, provided that mask field 1's. default, should cleared SYSCALL instruction Trap Service Routine allow trapped SYSCALL instruction execute without producing another trap upon return from trap handler. then again when next SYSCALL instruction executed. Call depth counter disabled. Call depth counter enabled.
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Field Bits Type Value Description Call Depth Counter Field. field consists variable-width fields. first mask field, consisting string zero more initial bits, terminated first bit. remaining bits field then interpreted call-depth counter. When call depth counter overflows, trap generated. Depending width mask field, call depth counter overflow power-of-two boundary from (20) (26). Setting mask field 1111110B leaves bits counter, causes every call trapped. This used call tracing. Setting field mask field 1111111B disables call depth counting altogether. 6-bit counter; trap overflow 5-bit counter; trap overflow 4-bit counter; trap overflow 3-bit counter; trap overflow 2-bit counter; trap overflow 1-bit counter; trap overflow trap every call (call trace mode) disable call depth counting Unimplemented, reserved.
0ccccccB 10cccccB 110ccccB 1110cccB 11110ccB 111110cB 1111110B 1111111B
2.6.3
PCXI, Previous Context Information Register
This register holds information about previous task's context, saved restored together with both, upper lower context. also contains Previous Context Pointer (PCX), which holds address previous task's context save area (CSA). PCXI Previous Context Information Register (BAddr FE00H)
Reset Value 0000 0000H
PCPN
PCXS
PCXO
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Field PCPN Type Value Function Previous Priority Number. This field contains priority level number interrupted task. Previous Interrupt Enable. This indicates state interrupt enable (ICR_IE) interrupted task. Upper/Lower Context Tag. This identifies type context saved. Lower context. Upper context. type does match type expected when context restore operation performed, trap generated. Previous Context Pointer Segment Address. This field contains segment address portion PCX. Previous Context Pointer Offset Field. PCXO PCXS fields form pointer PCX, which points previous context. Reserved
31:24
PCXS
19:16
PCXO
15:0
2.6.4
FCX, Free Context List Pointer
register points address next available context save area (CSA) linked list CSAs. automatically updated context save operation point next available CSA. Free List Head Pointer (BAddr FE38H)
Reset Value 0000 0000H
FCXS
FCXO
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Field FCXS FCXO Type Value Function Segment Address Field. This field used conjunction with FCXO field. Offset Address Field. FCXO FCXS fields together form pointer, which points next available CSA. Reserved
19:16 15:0
2.6.5
LCX, Context List Limit Pointer
register points last context save area (CSA) linked list free CSAs. value used context save operation detect usage last entry, trigger trap allow proper software reaction. Free List Limit Pointer (BAddr FE3CH)
Reset Value 0000 0000H
LCXS
LCXO
Field LCXS LCXO
Type
Value Function Segment Address. This field used conjunction with LCXO field. Offset Field. LCXO LCXS fields form pointer LCX, which points last available CSA. Reserved
19:16 15:0
2.6.6
ISP, Interrupt Stack Pointer
separet private stack software managed tasks from stack used interrupt service routines (ISRs), automatic switch implemented TC10GP Interrupt Stack Pointer (ISP) when entering ISRs. After saving upper context, with register A10, used stack pointer, register loaded with contents register ISP. When returning from ISR, previous value stack pointer restored through upper context restore operation.
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Note Register EndInit-protected Interrupt Stack Pointer (BAddr FE28H)
Reset Value 0000 0100H
ISP[31:16]
ISP[15:1]
Field
31:1
Type
Value Function Interrupt Stack Pointer. Reserved
2.6.7
BIV, Interrupt Vector Table Pointer
register points start address Interrupt Vector Table code memory. More detailled information functions associated with this register Interrupt Vector Table found chapter Interrupt System. Note Register EndInit-protected Interrupt Vector Table Pointer (BAddr FE20H)
Reset Value 0000 0000H
BIV[31:16]
BIV[15:1]
Field
31:1
Type
Value Function Interrupt Vetor Table Pointer. Reserved
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2.6.8 BTV, Trap Vector Table Pointer
register points start address Trap Vector Table code memory. More detailled information functions associated with this register Trap Vector Table found chapter Trap System. Note Register EndInit-protected Trap Vector Table Pointer (BAddr FE24H)
Reset Value A000 0100H
BTV[31:16]
BTV[15:1]
Field
31:1
Type
Value Function Trap Vetor Table Pointer. Reserved
2.6.9
SYSCON, System Control Register
SYSCON register holds enable/disable memory protection system status flag context list depletion condition. SYSCON System Control Register (BAddr FE14H)
Reset Value 0000 0000H
PROT
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Field PROTEN Type Value Function Memory Protection Enable. This enables memory protection system. Memory protection controlled through memory protection register sets. Note that required initialize protection register sets prior setting PROTEN one. Memory Protection disabled. Memory Protection enabled. Free Context List Depletion Sticky Flag. This sticky indicates that trap occured since last cleared software. trap occured since last clear. trap occured since last clear. Reserved
FCDSF
CSFR Address Table
following Table lists CSFRs TC10GP their physical addresses. Except General-Purpose Registers (GPRs), addresses given each CSFRs. 32-bit address represents mapped address register segment Access these mapped locations performed through CPU's Slave Interface (CPS) FPI-Bus master other than itself. 16-bit address given register associated address when performing access through MTCR MFCR instructions. Access modes CSFRs described following notes therefore contained Table 2-2. Note General-Purpose Registers (GPRs) accessed through MTCR MFCR instructions. Therefore, they have 16-bit address. Note Write accesses CSFRs through interface FPI-Bus master while running might lead unexpected behavior. strongly advised only write these registers when halted. Note Read write accesses from FPI-Bus must only made with word-aligned word accesses. access following this rule will flagged with error. read write operation will performed. Note Read accesses from FPI-Bus performed User Supervisor Mode. Write accesses from FPI-Bus must performed Supervisor Mode. write attempt User Mode will flagged with error. write operation will performed. Note Registers ISP, EndInit-protected. order successfully write these registers, ENDINIT register WDT_CON0 Watchdog Timer must cleared. chapter titled Watchdog Timer detailled information EndInit-protection.
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Table CSFR Register Table Name Description Address Register (AGPR) Address Register (AGPR) Address Register (AGPR) Address Register (AGPR) Address Register (AGPR) Address Register (AGPR) Address Register (AGPR) Address Register (AGPR) Address Register (AGPR) Address Register (AGPR) Address Register (AGPR) Address Register (AGPR) Address Register (AGPR) Address Register (AGPR) Address Register (AGPR) Address Register (AGPR) Data Register (DGPR) Data Register (DGPR) Data Register (DGPR) Data Register (DGPR) Data Register (DGPR) Data Register (DGPR) Data Register (DGPR) Data Register (DGPR) Data Register (DGPR) Data Register (DGPR) Data Register (DGPR) Data Register (DGPR) Data Register (DGPR) Data Register (DGPR) Data Register (DGPR) Address FFFF FFBCH FFFF FFB8H FFFF FFB4H FFFF FFB0H FFFF FFACH FFFF FFA8H FFFF FFA4H FFFF FFA0H FFFF FF9CH FFFF FF98H FFFF FF94H FFFF FF90H FFFF FF8CH FFFF FF88H FFFF FF84H FFFF FF80H FFFF FF3CH FFFF FF38H FFFF FF34H FFFF FF30H FFFF FF2CH FFFF FF28H FFFF FF24H FFFF FF20H FFFF FF1CH FFFF FF18H FFFF FF14H FFFF FF10H FFFF FF0CH FFFF FF08H FFFF FF04H Reset Value undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined undefined 2000-01
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Table CSFR Register Table (cont'd) Name SYSCON Description Data Register (DGPR) Free List Limit Pointer Free List Head Pointer Interrupt Unit Control Register Interrupt Stack Pointer Base Address Trap Vector Table Base Address Interrupt Vector Table System Configuration Register Program Counter (reset values depending selected boot option) Program Status Word Previous Context Information Register Trigger Event Specifier Trigger Event Specifier Software Break Event Specifier External Break Input Event Specifier Debug Status Register Code Protection Mode Registers, bytes) Code Protection Mode Registers, bytes) Data Protection Mode Registers, bytes) Data Protection Mode Registers, bytes) Code Range Protection Register Upper Boundary Code Range Protection Register Lower Boundary Code Range Protection Register Upper Boundary Address FFFF FF00H Reset Value undefined
FFFF FE3CH FE3CH 0000 0000H FFFF FE38H FE38H 0000 0000H FFFF FE2CH FE2CH 0000 0000H FFFF FE28H FE28H 0000 0100H FFFF FE24H FE24H A000 0100H FFFF FE20H FE20H 0000 0000H FFFF FE14H FE14H 0000 0000H FFFF FE08H FE08H A000 0000H 8000 0000H BE00 0000H FFFF FE04H FE04H 0000 0B80H FFFF FE00H FE00H 0000 0000H FFFF FD24H FD24H 0000 0000H FFFF FD20H FD20H 0000 0000H FFFF FD10H FD10H 0000 0000H FFFF FD08H FD08H 0000 0000H FFFF FD00H FD00H 0000 000XH FFFF E280H E280H FFFF E200H E200H FFFF E080H E080H FFFF E000H E000H 0000 0000H 0000 0000H 0000 0000H 0000 0000H
PCXI TR1EVT TR0EVT SWEVT CREVT EXEVT DBGSR CPM1_0 CPM1_1 CPM0_0 CPM0_1 DPM1_0 DPM1_3 DPM0_0 DPM0_3 CPR1_1U CPR1_1L CPR1_0U
Emulator Resource Protection Event Specifier FFFF FD0CH FD0CH 0000 0000H
FFFF D40CH D40CH 0000 0000H FFFF D408H D408H 0000 0000H FFFF D404H D404H 0000 0000H
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Table CSFR Register Table (cont'd) Name CPR1_0L CPR0_1U CPR0_1L CPR0_0U CPR0_0L DPR1_3U DPR1_3L DPR1_2U DPR1_2L DPR1_1U DPR1_1L DPR1_0U DPR1_0L DPR0_3U DPR0_3L DPR0_2U DPR0_2L Description Code Range Protection Register Lower Boundary Code Range Protection Register Upper Boundary Code Range Protection Register Lower Boundary Code Range Protection Register Upper Boundary Code Range Protection Register Lower Boundary Data Range Protection Register Upper Boundary Data Range Protection Register Lower Boundary Data Range Protection Register Upper Boundary Data Range Protection Register Lower Boundary Data Range Protection Register Upper Boundary Data Range Protection Register Lower Boundary Data Range Protection Register Upper Boundary Data Range Protection Register Lower Boundary Data Range Protection Register Upper Boundary Data Range Protection Register Lower Boundary Data Range Protection Register Upper Boundary Data Range Protection Register Lower Boundary Address Reset Value
FFFF D400H D400H 0000 0000H FFFF D00CH D00CH 0000 0000H FFFF D008H D008H 0000 0000H FFFF D004H D004H 0000 0000H FFFF D000H D000H 0000 0000H FFFF C41CH C41CH 0000 0000H FFFF C418H C418H 0000 0000H FFFF C414H C414H 0000 0000H FFFF C410H C410H 0000 0000H FFFF C40CH C40CH 0000 0000H FFFF C408H C408H 0000 0000H FFFF C404H C404H 0000 0000H FFFF C400H C400H 0000 0000H FFFF C01CH C01CH 0000 0000H FFFF C018H C018H 0000 0000H FFFF C014H C014H 0000 0000H FFFF C010H C010H 0000 0000H
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Table CSFR Register Table (cont'd) Name DPR0_1U DPR0_1L DPR0_0U DPR0_0L Description Data Range Protection Register Upper Boundary Data Range Protection Register Lower Boundary Data Range Protection Register Upper Boundary Data Range Protection Register Lower Boundary Address Reset Value
FFFF C00CH C00CH 0000 0000H FFFF C008H C008H 0000 0000H FFFF C004H C004H 0000 0000H FFFF C000H C000H 0000 0000H
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Coprocessor Instructions
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Coprocessor Instructions
Coprocessor Instructions
This chapter describes TC10GP Coprocessor instructions. Coprocessor Overview
TriCore architecture defines interface implementation-specific coprocessors designed handle application-specific instructions. TC10GP Coprocessor implements special instructions, described this section. execution Coprocessor instructions appear applications though they were regular instructions. special steps need taken programmer. Coprocessor Instructions
This section describes specialized instructions that performed TC10GP Coprocessor. 3.2.1 PARITY Instruction
PARITY instruction computes parity byte 32-bit input operand. parity number source operand number. byte parity result stored into every output register. remaining bits that register zero-filled. Figure illustrates operation PARITY instruction. Syntax:
PARITY (RR)
Operation:
D[c][(n] Even_Parity(D[a][(n+7):n]);
D[a]
Parity Logic
Parity Logic
Parity Logic
Parity Logic
D[c]
Figure PARITY Operation User's Manual 2000-01
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3.2.2 BSPLIT Instruction
BSPLIT instruction takes 32-bit input operand splits into double-word output register such that even bits input operand lower half-word lower word output register, bits input operand lower half-word upper word output register. upper half-words words output operand zero-filled. Figure illustrates this operation. Syntax:
BSPLIT (RR)
Operation:
D[c][31:16] D[c+1][31:16] D[c][n/2] D[a][n]; D[c+1][(n-1)/2] D[a][n];
D[a]
bits D[a]
even bits D[a]
D[c+1] Figure BSPLIT Operation
E[c]
D[c]
3.2.3
BMERGE Instruction
BMERGE instruction performs reverse operation BSPLIT. takes 32-bit input operands merges bits each input operands into 32-bit output register such that bits lower half-word first input operand moved positions, bits lower half-word second input operand moved even positions output operand. bits upper half-word input operands used this instruction. Figure illustrates this operation. Syntax:
BMERGE (RR)
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Operation:
D[c][n] D[a][n/2] D[b][n/2]); 0.31
D[a]
used fill bits slots D[a] used
D[b]
fill even bits slots D[a]
D[c] Figure BMERGE Operation
3.2.4
UNPACK Instruction
UNPACK instruction takes IEEE-754 single-precision floating point number splits into parts such that easily processed through regular instructions. Register D[a] holds IEEE-754 single precision floating point number. exponent mantissa input number unpacked placed register pair E[c]. bias removed from exponent unpacking, result placed D[c+1]; D[c] receives mantissa. compute mantissa, input number first checked IEEE floating point value zero; input number zero, then unpacked mantissa zero. Otherwise, bits 22:0 D[a] copied bits 29:7 D[c], with bits D[c] cleared implicit high order normalized mantissa. becomes since unpacked mantissa always positive. resulting mantissa positive number 2Q30 format. sign-bit floatingpoint number itself remains available sign input operand register D[a]. special provision made dealing with IEEE infinities, denormals, NaNs. Syntax:
UNPACK (RR)
Operation:
D[c][6:0] D[c]29:7] D[a][22:0]; D[c][30] D[c][31]
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D[c+1][31:8] D[c+1][7:0] D[a][30:23] 127;
exponent mantissa
D[a]
D[c]
mantissa
exponent mantissa
D[a]
subtract bias (127)
D[c+1]
exponent
Figure UNPACK Operation
3.2.5
PACK Instruction
PACK instruction performs opposite UNPACK instruction. Register pair E[d] holds unbiased exponent normalized mantissa unpacked floating point number. exponent register D[d+1], while mantissa register D[d]. register D[a] holds sign unpacked number. PACK instruction first computes biased exponent packed result adding unpacked exponent. bias offset from standard IEEE exponent bias 127, because mantissa input register D[d] taken have been normalized using instruction derive left shift count. That puts high-order fraction position D[d], position left where UNPACK places biased exponent negative, mantissa zero, biased exponent zero. result inserted into bits 30:23 D[c]. Bits 30:8 D[d] inserted into bits 22:0 D[c]. from D[a] copied into D[c].
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rounding done, special provision made generating IEEE denormal values infinities exponent overflow underflow. Syntax:
PACK (RRR)
Operation:
D[c][30:23] D[d+1][7:0] D[c][22:0] D[d][30:8] D[c][31] D[a][31]
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TC10GP Pipelines
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TC10GP Pipelines
TC10GP Pipelines
This chapter describes TC10GP pipelines including integer load/store pipelines, loop pipeline. Pipeline Overview
specified TriCore architecture, TC10GP implements pipelined, superscalar processor architecture that allows execution instructions parallel. processor pipeline design reduces branch latency, data dependencies, overall system complexity. major pipelines perform integer operations load/store operations. Each these four stages: Fetch (common both), Decode, Execute, Write-back. third minor pipeline optimizes loops. three pipelines illustrated Figure 4-1. Integer Load/Store Pipelines
Integer Pipeline executes following operation types. Integer arithmetic logical operations Bit-wise logical operations Multiply-accumulate (MAC) operations Integer division Conditional data jumps
Load/Store Pipeline executes following operation types. Load Store operations Context-switch operations System operations Address arithmetic calculations Unconditional conditional branch target calculations
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Exe. Integer Decode Integer Execute Fetch Load/Store Decode
Exe. Write-back Integer Pipeline
Load/Store Execute
Write-back
Load/Store Pipeline
Loop Execute
Write-back
Loop Pipeline
Figure Pipeline Architecture pipelines share common fetch stage that issue instruction each pipeline cycle. Certain issue constraints apply. instance, when instructions issued parallel, first instruction must integer pipeline instruction. integer followed load instruction issued parallel, load followed pair integer cannot. example, following code sequence takes four cycles.
ld.w st.w ld.a [a0]0 [a1]0, [a5]4
Cycle
Integer
Load/Store ld.w st.w ld.a
Note third cycle instruction dependent store dual-issued. result from forwarded store instruction without stall penalty. general, required User's Manual 2000-01
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forwarding paths implemented that dependent instructions executed without stall penalties. simple integer operations, operations, address arithmetic instructions execute single cycle. Divide instructions, such DVSTEP, take eight uninterruptable cycles execute. multiply-accumulate (MAC) instructions executed special two-stage pipeline. first stage contains 16x16-bit multipliers. second stage contains accumulation, rounding saturation logic. pipeline perform 32x32-bit multiply every cycles with latency three cycles, 16x16-bit multiplies every cycle with latency cycles. Loop Pipeline
Loop Pipeline optimizes execution loops, such those typically found applications. This pipeline driven Loop Cache Buffer (LCB), which stores location, target, other required information. loop instruction executed Load/Store Pipeline first iteration, loop pipeline afterwards. loop single-issued, then updated when detected decode stage pipeline. subsequent iterations loop, when detects loop, automatically fetches start loop body. Unlike normal Branch Target Buffer hit, loop instruction itself fetched. injected from into Loop Pipeline during last execute cycle. example, following code will execute shown below:
mov.a loop_start: ld.w loop number_of_iterations [a0+]4 loop_start
Cycle
Integer
Load/Store mov.a ld.w loop ld.w ld.w ld.w ld.w
Loop loop loop loop loop
seen, after first pass through loop, each subsequent iteration will take only clock cycle, thereby providing zero overhead loop capability.
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Context Operations
Context save context restore operations associated with calls, returns, interrupts, 128-bit data between register file local on-chip data memory. contains dedicated hardware optimize context switching, resulting context-save time on-chip local memory between four cycles.
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On-Chip Local Memory Units
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On-Chip Local Memory Units
On-Chip Local Memory Units
This chapter describes TC10GP local memory units, including Program Memory Unit Data Memory Unit. Local Memory Unit Overview
TC10GP Harvard-style architecture, with separate address data buses program data memories. TC10GP incorporates on-chip program data memories caches. Program Memory Unit (PMU) Data Memory Unit (DMU) connect directly CPU. this chapter, term ICache refers CPU's instruction cache, term DCache refers CPU's data cache. PMU, Program Memory Unit
Program Memory Unit (PMU), shown Figure 5-1, contains: 8-Kbyte SRAM that configured either: on-chip local code scratch-pad memory (CSRAM) instruction cache extension normal instruction cache 8-Kbyte instruction cache (ICACHE), extendable Kbytes Control block interface Instruction Fetch Unit interface
FPI-Bus
FPI-Bus Interface
ICACHE
CSRAM
Control
Interface Instruction Fetch Unit
Figure Block Diagram Program Memory Unit (PMU)
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5.2.1 Configuration Options
instruction cache (ICACHE) scratch-pad code SRAM (CSRAM) programmed configurations. Depending application needs, either have 8-Kbyte ICACHE 8-Kbyte CSRAM, CSRAM used extend ICACHE total Kbyte. selection made Cache Size control CCSIZ register PMU_CON0. Figure shows configured combination Kbytes scratch-pad code SRAM (CSRAM) Kbytes instruction cache (ICACHE), while Figure shows cache-only configuration.
FPI-Bus Interface Slave Master
ICACHE Kbyte
Cache Bypass
CSRAM Kbyte SRAM Non-Cached
Interface
Figure Configuration with Scratch-Pad SRAM Instruction Cache Note that FPI-Bus interface master/slave interface. master part interface used when needs access resources which located FPI-Bus module connected FPI-Bus, such External Control Unit, EBU). slave part interface used when another FPI-Bus master needs access resources such CSRAM. Note also that only external FPI-Bus master write CSRAM. Fetch Unit only data read access resources.
User's Manual
2000-01
TC10GP Unified 32-bit µC-DSP
On-Chip Local Memory Units
FPI-Bus Interface Slave Master Cache Bypass
ICACHE Kbyte
Interface
Figure Configuration Cache-Only Operation 5.2.2 CSRAM, Code Scratch-Pad
Code Scratch-Pad (CSRAM) 8-Kbyte static (SRAM). designed such that either used standard memory extension instruction cache (ICACHE). options controlled Code Cache Size control bit, CCSIZ, register PMU_CON0. fetch accesses address range CSRAM never cached ICACHE, they always directly targeted RAM. fetch access from CSRAM performed clock cycle, data width such access bits. Note that Fetch Unit only read from CSRAM, never write CSRAM accessed from FPI-Bus side another master, such Data Memory Unit, DMU. read access from FPI-Bus, data width bits (byte, halfword, word). natural alignment accessed data must obeyed, that bytes aligned byte boundary, halfwords must aligned halfword (even byte) boundaries, word accesses must aligned word boundaries. Accesses following this rule will flagged with FPI-Bus error PMU. write access from FPI-Bus, data width bits. Byte accesses allowed will flagged with error. natural alignment accessed data must obeyed, that halfwords must aligned halfword (even byte) boundaries, word accesses User's Manual 2000-01
TC10GP Unified 32-bit µC-DSP
On-Chip Local Memory Units
must aligned word boundaries. Accesses following this rule will flagged with FPI-Bus error PMU. Read write accesses from FPI-Bus CSRAM performed with waitstate ICACHE controller idle, with waitstates there pending cache refill operation. CSRAM mapped twice into overall address space, into lower half segment into upper half segment This shown Table 5-1. rightmost columns indicate limitations error modes accesses given address range Error). Table CSRAM Address Segment Address Name Description Fetch Access Read 0xC7FF FEFF -0xC000 2000 0xC000 1FFF CSRAM 0xC000 0000 Trap reserved Local Code Scratch Kbyte) Trap cacheonly operation Trap reserved Local Code Scratch Kbyte) Trap cacheonly operation Note Note FPI-Bus Access Read Error (BE) Note Write
Note
0x8FFF FEFF -0x8800 2000 0x8800 1FFF 0x8800 0000 CSRAM
Note Cache/SRAM configuration, read accesses from FPI-Bus performed User Supervisor Mode. Access width bits, with data aligned natural boundary. Misaligned accesses will result error. Cache-only configuration, accesses this range will result error. Note Cache/SRAM configuration, write accesses from FPI-Bus performed User Supervisor Mode. Access width bits, with data aligned natural boundary. Misaligned accesses byte accesses will result error. Cache-only configuration, accesses this range will result error. Segment non-cacheable segment, while segment cacheable segment TC10GP. Although CSRAM mapped cacheable segment Fetch accesses allowed. CPU's Fetch Unit, this address range reserved range, fetch accesses this range will lead trap.
User's Manual
2000-01
TC10GP Unified 32-bit µC-DSP
On-Chip Local Memory Units
Mapping CSRAM into this address range cacheable segment done allow access data (constants) CSRAM cache into DMU's data cache (DCACHE). Thus, choice either caching caching data CSRAM DCACHE depending address access. address ranges marked reserved Table implemented TC10GP. instruction fetch address this range will return Program Synchronous Trap (PSE) CPU. FPI-Bus access these ranges will flagged with error PMU. programmed cache-only configuration, instruction fetch CSRAM ranges will also return trap, FPI-Bus access CSRAM will flagged with error. placement CSRAM into lower half segment facilitates absolute addressing mode load store operations, supporting fast access constants stored CSRAM code memory absolute addressing mode, address lower Kbyte each segments specified immediate address load/store instruction; such address does have first loaded into address register). 5.2.3 ICACHE, Instruction Cache
Instruction Cache (ICACHE) two-way set-associative cache with LeastRecently-Used (LRU) replacement algorithm. 5.2.3.1 Cache Size Bypass Control
size ICACHE selected either Kbyte Kbyte (see Figure Figure 5-3). selection made with Code Cache control CCSIZ register PMU_CON0. default after reset which selects Kbyte option (with Kbyte code scratch-pad RAM, CSRAM). When setting CCSIZ CSRAM used extension ICACHE enlarge Kbyte longer available scratch-pad RAM. ICACHE bypassed (disabled) control CCBYP (Code Cache Bypass) register PMU_CON0. default value CCBYP after reset thus bypassing ICACHE. enable ICACHE, CCBYP during initialization. Since these cache controls critical operations, register PMU_CON0 been implemented EndInit-protected register. order successfully write PMU_CON0, ENDINIT register WDT_CON0 first cleared (default after reset) through sophisticated password mechanism. chapter titled Watchdog Timer detailed description EndInit-protection. 5.2.3.2 Cache Organization
organization ICACHE (8-Kbyte ICACHE) (16-Kbyte ICACHE) cache lines, with bits line. Each cache line divided into double-words (DW, bits), with valid each Alignment cache line results four-double-word address (address bits A[4:0] With 32/16-bit mixed instruction formats TriCore, full cache line hold minimum eight 32-bit instructions maximum sixteen 16-bit instructions. cache enabled, then instruction fetch accesses address ranges segments will first targeted ICACHE. address associated instruction found User's Manual 2000-01
TC10GP Unified 32-bit µC-DSP
On-Chip Local Memory Units
cache (Cache Hit), instruction passed CPU's Fetch Unit. address found cache (Cache Miss), PMU's cache controller issues cache refill sequence. 5.2.3.3 Cache Refill
Cache refill performed with Critical Word First strategy, meaning refill sequence starts with instruction actually requested (the critical word) Fetch Unit until cache line. refill will always done 64-bit quantities. critical word maps onto first 64-bit entry cache line, refill entire cache line, four double-words, will performed. critical word maps onto last 64-bit entry cache line, only this double-word will refilled. However, case valid bits refilled cache line cleared. Thus, depending location critical word, refill sequence will always double-words without wrap-around (the instructions mapping refilled cache line which addresses lower than that critical word fetched, except instructions located within double-word containing critical word). refill sequence will always only affect cache line. There prefetching next cache line crossing cache lines). refill done from FPI-Bus resource (mainly external memory connected External Controller, EBU), burst refill with words performed (the FPI-Bus does support burst words; refill request double-words will performed 8-word burst). single words then assembled double-words. 5.2.3.4 Instruction Streaming
ICACHE supports instruction streaming, meaning that during refill sequence, already deliver critical word CPU's Fetch Unit (after having assembled double-word) before sequence completed. ICACHE bypassed (CCBYP access cacheable address space performed such that cache controller issues refill sequence without updating cache contents (cache data valid bits). 5.2.3.5 Cache Coherency, Cache Invalidation
does have automatic cache coherence support. Changes contents memory areas external which have already been cached ICACHE detected. Software provide cache coherency such case. supports this cache invalidation function. ICACHE contents invalidated through setting invalidate control CCINV register PMU_CON1. While this cache accesses will treated Cache Miss operations, cache refill performed. 5.2.4 Control Registers
control registers identification register, shown Figure 5-4, implemented Program Memory Unit (PMU). Since first control register, PMU_CON0, holds critical configuration bits usually only written during initialization routine, this register EndInit-protected minimize chance unintentional changes configuration (see chapter titled Watchdog
User's Manual
2000-01
TC10GP Unified 32-bit µC-DSP
On-Chip Local Memory Units
Timer details EndInit-protection). registers their bits described following.
System Registers
Control Registers
PMU_ID
PMU_CON0 PMU_CON1
PMU_ID PMU_CON0 PMU_CON1 Figure Registers
Identification Register Control Register (EndInit-protected) Control Register
5.2.4.1
PMUID, Identification Register
PMUID register identifies module number revision number PMU. PMU_ID Identification Register (BAddr 08H)
Reset Value: 0000 71XXH
Field
Bits 15:8
Type Value Function Identification Number. Revision Number. Please refer TC10GP Data Sheet actual revision number. Unimplemented, reserved
User's Manual
2000-01
TC10GP Unified 32-bit µC-DSP
On-Chip Local Memory Units
5.2.4.2 PMU_CON0, Control Register
PMU_CON0 register controls code cache PMU. PMU_CON0 Control Register (BAddr 10H)
Reset Value: 0000 0006H
Field CCBYP
Bits Type Value Function This must cleared software after reset. Must write instructions this register. Code Cache Bypass Control. Cache enabled. Cache bypassed (default after reset). Code Cache Size Control. Controls configuration scratchpad SRAM. Kbyte cache. CSRAM used scratchpad code (default). Kbyte cache. SRAM used cache extension. Unimplemented, reserved
CCSIZ
User's Manual
2000-01
TC10GP Unified 32-bit µC-DSP
On-Chip Local Memory Units
5.2.4.3 PMU_CON1, Control Register
PMU_CON1 register performs code cache invalidate control PMU. PMU_CON1 Control Register (BAddr 14H)
Reset Value: 0000 0000H
Field CCINV
Bits
Type Value Function Code Cache Invalidate Control. Normal operation. Invalidates cache lines. long CCINV set, instruction fetch accesses generate cache refill. advised keep CCINV until ICACHE coherency guaranteed. Unimplemented, reserved
User's Manual
2000-01
TC10GP Unified 32-bit µC-DSP
On-Chip Local Memory Units
5.2.5 Implementation TC10GP
Table shows address assignments resources non-cacheable segment while Table shows address assignments cacheable segment Please note that access control registers must only made with word accesses, otherwise error (BE) will generated. Access from CPU's Fetch Unit register address range allowed will lead Program Synchronous Error (PSE) trap. Access allowed User Mode. Access allowed Supervisor Mode. EndInit-protected location. change contents. FPI-Bus Error. Word access only. Table Address Map, Non-Cacheable Segment Address Name Description Fetch Access Read 0xCFFF FFFF -0xC800 0000 0xC7FF FFFF -0xC7FF FF18 reserved Trap FPI-Bus Access Read Error (BE) Write
reserved
Trap Trap Trap Trap Trap
0xC7FF FF14 PMU_CON1 Control Register 0xC7FF FF10 PMU_CON0 Control Register 0xC7FF FF0C -0xC7FF FF08 PMU_ID 0xC7FF FF07 -0xC7FF FF00 0xC7FF FEFF -0xC000 2000 0xC000 1FFF CSRAM 0xC000 0000 reserved Identification Register (read-only) reserved
Trap
Trap reserved Local Code Scratch Kbyte) Trap cache-only operation
Error (BE)
Note Note
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2000-01
TC10GP Unified 32-bit µC-DSP
On-Chip Local Memory Units
Table Address Map, Cacheable Segment Address Name Description Fetch Access Read 0x8FFF FEFF -0x8800 2000 0x8800 1FFF 0x8800 0000 CSRAM reserved Local Code Scratch Kbyte) reserved Trap Note Note Trap FPI-Bus Access Read Write
Trap
0x87FF FFFF -0x8000 0000
Note Cache/SRAM configuration, read accesses from FPI-Bus performed User Supervisor Mode. Access width bits, with data aligned natural boundary. Misaligned accesses will result error. Cache-only configuration, accesses this range will result error. Note Cache/SRAM configuration, write accesses from FPI-Bus performed User Supervisor Mode. Access width bits, with data aligned natural boundary. Misaligned accesses byte accesses will result error. Cache-only configuration, accesses this range will result error.
User's Manual
2000-01
TC10GP Unified 32-bit µC-DSP
On-Chip Local Memory Units
DMU, Data Memory Unit
Data Memory Unit (DMU), shown Figure 5-5, contains: 32-Kbyte SRAM block that configured either: 32-Kbyte on-chip local data scratch-pad memory (DSRAM) 16-Kbyte scratch-pad memory (DSRAM) 16-Kbyte Data Cache (DCACHE) Control block interface Instruction Fetch Unit interface
FPI-Bus
FPI-Bus Interface
DCACHE
DSRAM
Control
Interface 2*64 Load/Store Unit
Figure Block Diagram Data Memory Unit (DMU) 5.3.1 Configuration Options
32-Kbyte static programmed configurations. Depending application needs, either have full 32-Kbyte scratch-pad Data SRAM (DSRAM) without data cache, 16-Kbyte Data SRAM (DSRAM) with 16-Kbyte Data Cache (DCACHE). selection made Cache On/Off control DCAON register DMU
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