Field-Programmable Microcontroller Peripherals with Embedded MicroCell

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

Field-Programmable Microcontroller Peripherals with Embedded MicroCell

Datasheet Thumbnail

Top Searches for this datasheet

PSD6XX Family
Field-Programmable Microcontroller Peripherals with Embedded MicroCells
PSD6XX series complete family Field Programmable Microcontroller Peripherals with Embedded MicroCellsTM. devices used rapidly implement highly integrated embedded control systems. device family offers variety functions including PLDs with embedded MicroCells, dynamically reconfigurable Ports, programmable power management, EPROM, SRAM other functions. Drawing from WSI's years experience with microcontroller (MCU) applications, PSD6XX product family radically simplifies addition programmable logic embedded system designs. innovative "microcontroller-macrocells", called MicroCells, bring inexpensive programmable logic MCU-based embedded system designs. Because MicroCells directly connected system address/data bus, their NVM-based programmable logic tightly coupled software programs running system MCU. MCU's ability communicate directly with MicroCells flip-flop level makes PSD6XX devices ideal implementing functions most frequently needed embedded systems. Communicating with Microcontrollers Regardless function they perform, microcontroller peripherals must communicate MCU. MCUs require clock, data bus, chip select, read write signals. implement these signals using current industry standard PLDs required valuable product terms macrocells each chip. case most embedded system designs, this left remaining usable resources implement peripheral function that designers dismissed expensive. MicroCell directly connects logic MCU. then sees PSD6XXE1 decoded location address map. Direct read write operations easily simply performed. Functions like counters serial ports constructed with programmable logic without design time resources lost interfacing MCU. When compared industry standard CPLD implementations this architecture save CPLD product term macrocell resources.
Features
simple, programmable interface microcontrollers using either multiplexed
non-multiplexed busses. interface logic directly decodes microcontroller control signals. Microcontroller families supported include Intel 8031, 80196, 80186, 80C251 80386EX; Motorola 68HC11, 68HC16, 68HC12 683XX; Philips 8031 8051XA; National 16000; Zilog Neuron 3150.
Three PLDs with Output MicroCells Input MicroCells, inputs
product terms. PSD6XX PLDs used efficiently implement variety logic functions including state machines address decoders internal external control. also provides seven external chip select outputs.
Embedded Input Output MicroCells that enable efficient implementation user
defined system logic functions that require both microcontroller software hardware interaction.
Power Management Unit that reduces device standby current typical.
lower power operation refer ZPSD6XX product family.
Return Main Menu
PSD6XX Family
Features
(cont.)
Twenty individually configurable Port pins. Ports used I/Os,
I/Os, latched address outputs special function I/Os. Fifteen port pins configured open drain outputs.
Internal EPROM densities Kbit, Kbit Mbit, configurable eight
sixteen-bit widths. EPROM divided into eight equal-size blocks, accessible user-specified addresses. access time includes address latching decoding. EPROM includes power option.
Internal Kbit SRAM that configured eight sixteen-bit data widths.
SRAM retains data power lost automatically switching standby power.
page register expands microcontroller address space factor sixteen. security prevents copying PSD6XX configuration logic well
EPROM contents device programmers.
programmable Power Management Unit (PMU) supports separate, low-power
modes allowing operations with little VCC). device automatically detect lack microcontroller activity into power down mode.
devices available EPROM versions. They ideal prototyping
low-volume production, versions high-volume, low-cost applications.
Package choices include plastic ceramic chip carriers. PSD6XX family development supported WSI's based PSDsoftsoftware
system. software MS-Windows® Windows compatible. suite includes PSDabel(ABEL® specify logic, efficient fitter. tool also includes PSDsilosIII simulator from SIMUCADTM. MagicPro® programmer engineering development tool program device.
General Information
PSD6XX series Field Programmable Microcontroller Peripherals combine innovative architecture with advanced technology provide user-programmable, high-performance, low-power solution microcontroller system design. embedded input output MicroCells enable efficient implementation user defined logic functions that require both software hardware interaction. devices eliminate need discrete `glue' logic allow development entire systems using only highly integrated devices.
Development System
PSD6XX family supported Windows-based PSDsoft Development System. PSDsoft design flow shown Figure design entry done using PSDabel, which creates minimized logic implementation, provides logic simulation PLDs. PSD6XX Interface Port configuration entered PSDconfiguration. PSDcompiler, comprised fitter address translator, generates object file from PSDabel, PSDconfiguration code files. object file then down loaded programmer (MagicPro III, Data I/O, other third party programmer device programming) PSDsimulator (PSDsilos Logic simulator) device-level simulation.
Please refer revision block this document updated information.
PSD6XX Family
Development System
(cont.)
Figure PSDsoft Development Tools
PSDabel
DESCRIPTION GENERATE ABEL FILE DESIGN TEMPLATE
PSDconfiguration
CONFIGURE INTERFACE
PSDcompiler
FITTER FITTING ADDRESS TRANSLATOR EPROM MAPPING PROGRAM CODE FILE
THIRD PARTY PROGRAMMERS .OBJ FILE
PSDsimulator
PSDsilos CHIP SIMULATION
PSDprogrammer
Magic Pro® PROGRAMMER CHIP PROGRAMMING
Device Versions PSD6XX Family
PSD6XX window package versions ideal general purpose embedded systems development. PSD6XX versions deliver lowest cost PSD6XX solution.
There devices PSD6XX family. part classifications based EPROM size data width. features each part listed Table
Table PSD6XX Product Matrix Part
PSD601E1 PSD611E1 PSD602E1 PSD612E1 PSD603E1 PSD613E1
Width
x8/x16 x8/x16 x8/x16
Pins
EPROM
1024 1024
SRAM
PSD6XX Family
following table describes names functions PSD6XXE1. Pins that have multiple names and/or functions defined configuration.
Table PSD6XXE1 Descriptions
Name
ADIO0-7
30-37
Type
Function Description
Address/Data Port, interface Microcontroller Input pins multiplexed order address/data byte. latches address A0-7. drives data only read active internal functional blocks selected. Address A0-7 inputs non-multiplexed 80C251 mode A4/D0-A11/D7 inputs 80C51XA mode Address latched address) inputs Address/Data Port, interface Microcontroller Address A8-15 inputs 8-bit data mode, multiplexed high order address/data byte inputs 16-bit data mode. latches address A8-15. drives data only read active internal functional blocks selected. Address A8-15 inputs non-multiplexed mode AD8-AD15 inputs 80C251 mode A12-A19 A12/D8 A19/D15 inputs 80C51XA mode Address latched address) inputs Write Input with multiple configurations. Depending interface selected, this active write input read/write pin, write cycle data only, write byte, active Control signal (CNTL0) input Read Data Strobe Input with multiple configurations. Depending interface selected, this active read input clock input. During write cycle, high During read cycle, high high Data Strobe, active Strobe data byte, 16-bit data mode, active PSEN Program Select Enable, active read cycle (80C251 configuration) Control signal (CNTL1) input Read other Control input with multiple configurations. Depending interface selected, this PSEN Program Select enable, active code fetch cycle High byte enable, 16-bit data Strobe high data byte, 16-bit data mode, active SIZ0 Byte enable input Control signal (CNTL2) input general input
ADIO8-15
39-46
CNTL0) (WR, R_W, WRL)
CNTL1 (RD, LDS, PSEN)
CNTL2 (PSEN, BHE, UDS, SIZ0)
PSD6XX Family
Table PSD6XXE1 Descriptions
(cont.)
Name
Reset
Type
Function Description
Active input. Resets Ports, MicroCells some Configuration Registers. Must active power Port This port configurable multiple functions: standard output input port External chip select (ECSPLD) output, input GPLD Latched address outputs (see Table Address A0-3 inputs 80C51XA mode Data Port (D0-3) non-multiplexed configuration Peripheral mode Port This port configurable multiple functions: standard output input port GPLD MicroCell (McellAB) output input Latched address outputs (see Table Data Port non-multiplexed configuration Peripheral mode Port This port configurable multiple functions: standard output input port External chip select (ECSPLD) output, input GPLD Latched address outputs (see Table Data Port (D8-11) non-multiplexed configuration with 16-bit data Port This port configurable multiple functions: standard output input port GPLD MicroCell (McellAB) output input Latched address outputs (see Table Data Port (D12 -15) non-multiplexed configuration with 16-bit data Port PC0, PC1, This port configurable multiple functions: standard output input port GPLD MicroCell (McellC) output input only (WRH), Write strobe input high byte. Active low, 16-bit with
CMOS Open Drain
CMOS Open Drain
(WRH) (Vstby)
CMOS Open Drain
Port PC2. Dedicated SRAM Standby Voltage Input. should grounded Vstby required.
PSD6XX Family
Table PSD6XXE1 Descriptions
(cont.)
Name
(ALE)
Type
Function Description
Port configured input latches addresses ADIO0 pins GPLD input ECSPLD output Port configured GPLD input External chip select (ECSPLD) output CLKIN clock input clock input GPLD MicroCells, power down counter GPLD Array Port configured GPLD input External (ECSPLD) output input When low, enables EPROM/SRAM. When high, EPROM/SRAM disabled conserve power Power pins Ground pins
(CLKIN)
(CSI)
Table Port Latched Address Output Assignments* Microcontroller
8051XA (8-Bit) 80C251 (Page Mode) Other 8-Bit Multiplexed 8051XA (16-Bit) Other 16-Bit Multiplexed 8-bit Non-Multiplexed
Applicable
Port (3:0)
Address [3:0] Address [3:0]
Port (7:4)
Address [7:4] Address [7:4] Address [7:4] Address [7:4]
Port (3:0)
Address [11:8] Address [11:8] Address [3:0] Address [11:8] Address [11:8]
Port (7:4)
Address [15:12] Address [7:4] Address [15:12] Address [15:12]
Address [3:0]
Address [7:4]
Refer Port Section enable Latched Address Output function.
PSD6XX Family
Tables show offset address PSD6XXE1 registers relative CSIOP base address. CSIOP space bytes address that allocated user internal PSD6XXE1 registers. Some Motorola 16-bit microcontrollers, including M68HC16, M68302 M683XX, have different data byte orientation requiring separate address offset maps. Table shows CSIOP address offsets MCUs except those from Motorola 16-bit mode. Table shows address offsets Motorola MCUs 16-bit mode.
PSD6XXE1 Register Description Address Offset
Table Register Address Offset Register Name
Data Control Data
Port Port Port Port Other*
Description
Reads Port input, input mode Selects mode between Address Stores data output Port pins, output mode Configures Port input output Configures Port between CMOS, Open Drain Slew rate Reads Input MicroCell Reads status output enable Port driver Read reads output MicroCells (McellC, McellAB) Write loads Microcell Flip-Flops
Direction Drive
Input MicroCell Enable
Output MicroCell
PMMR0 PMMR1 Page *Other registers that part ports.
Power Management Register Power Management Register Page Register 8031/PIO Configuration Register
PSD6XX Family
PSD6XXE1 Register Description Address Offset
(cont.)
Table Register Address Offset 16-Bit Motorola Microcontrollers 16-Bit Mode Register Name
Data Control Data
Port Port Port Port Other*
Description
Reads Port input, input mode Selects mode between Address Stores data output Port pins, output mode Configures Port input output Configures Port between CMOS, Open Drain Slew rate Reads Input MicroCell Reads status output enable Port driver Read reads output MicroCells (McellC, McellAB) Write loads Microcell Flip-Flops
Direction Drive
Input MicroCell Enable
Output MicroCell
PMMR0 PMMR1 Page *Other registers that part ports.
Power Management Register Power Management Register Page Register 8031/PIO Configuration Register
PSD6XX Family
PSD6XX devices consist several major functional blocks. Figure shows architecture PSD6XX device family. functions each block described briefly following sections. Many blocks perform multiple functions, user configurable.
PSD6XXE1 Architectural Overview
PLDs
device contains three blocks each optimized different function shown Table functional partitioning PLDs reduces power consumption, optimizes cost/performance ease design entry. Decode (DPLD) used decode generate chip selects PSD6XXE1 internal memory, registers peripheral mode. External Chip Select (ECSPLD) optimized generate chip selects devices external PSD6XXE1. General Purpose (GPLD) implement user defined logic functions. DPLD ECSPLD have combinatorial outputs while GPLD Output MicroCells. PSD6XXE1 also Input MicroCells that configured inputs PLD. PLDs receive their inputs from Input differentiated their output destinations, number product terms, MicroCells.
Ports
PSD6XXE1 pins divided among four ports. Each individually configured provide many functions. Ports configured standard ports, I/O, latched address outputs microcontrollers using multiplexed address/data busses. Ports also configured data port microcontrollers with non-multiplexed bus. these modes, Port connected D0-7 Port D8-15.
Table Name
Decode External Chip Select General
Abbreviation
DPLD ECSPLD GPLD
Inputs
Outputs
Product Terms
PSD6XX Family
PSD6XXE1 Architectural Overview
(cont.)
Microcontroller Interface
PSD6XXE1 easily interfaces with most popular eight sixteen-bit microcontrollers with either multiplexed non-multiplexed address/data busses. device configured respond microcontroller control signals which also used inputs PLDs.
Memory
PSD6XXE1 contains EPROM SRAM. EPROM densities available Kbit, Kbit Mbit. space divided into eight equally-sized blocks. Each block located different address space defined user. access time EPROM includes address latching DPLD decoding. Kbit SRAM used scratch memory extension microcontroller SRAM. SRAM data retained event system power down, provided backup battery connected Vstby (PC2). Switching from supply standby power occurs automatically when drops below Vstby voltage.
Page Register
four-bit Page Register expands address range microcontroller sixteen times. paged address used part address space access external memory peripherals internal EPROM, SRAM I/O.
Power Management Unit
Power Management Unit (PMU) PSD6XXE1 enables user control power consumption selected functional blocks based system requirements. includes Automatic Power Down unit (APD) that will turn device functions microcontroller inactivity modes: Power Down mode Sleep mode. Other power saving features, such CMiser PMU, allow EPROM/SRAM operate slower rate conserve power.
PSD6XXE1 Architectural Overview
(cont.)
ADDRESS 16-BIT DATA /CONTROL
EPROM
PAGE EIGHT BLOCKS BATTERY BACK-UP
MBIT EPROM
VSTDBY INCLUDING CMISER FEATURES (PC2)
DECODE SRAM
PERIPHERAL SELECTS DECODE BITS BATTERY BACK
AD0-AD15
INPUT
ADDRESS/DATA
PROGRAMMABLE PORT
Figure PSD6XXE1 Block Diagram
EXTERNAL
EXTERNAL CHIP SELECTS DIRECT MICROCELLS ACCESS FROM DATA
CONTROL CHIP SELECT ALLOCATOR
CONTROL INTERFACE
PROGRAMMABLE PORT
GENERAL
ALLOC.
CLKIN
OUTPUT MICROCELLS
MICROCELL ALLOCATOR INPUT MICROCELLS (PORT A,B,C)
PROGRAMMABLE PORT
PORTS NIBBLE
SECURITY FEATURE
INPUT
PROGRAMMABLE PORT
DIRECT MICROCELL OUTPUT DATA OUTPUT MICROCELL FEEDBACK INPUT MICROCELL INPUT PORTS
PSD6XX Family
PSD6XX Family
PSD6XXE1 consists five major functional blocks:
PSD6XXE1 Functional Blocks
Block Interface Ports Memory Block Power Management Unit
functions each block described following sections. Many blocks perform multiple functions, user configurable.
PLDs
PLDs bring programmable logic functionality PSD6XXE1. After specifying logic PLDs using PSDabel tool PSDsoft suite, logic configuration programmed into device available when power applied. PLDs (DPLD, ECSPLD GPLD) consist array. GPLD architecture includes Output MicroCells addition array. There Input MicroCells that configured inputs PLD. Figure shows organization PLD. array used form product terms specified using PSDabel tool PSDsoft development system. When inputs used term true, output active. GPLD Input consists signals shown Table Both true complement value inputs available array. DPLD ECSPLD Input Busses consists fewer inputs subset inputs.
Table GPLD Inputs Input Source
Address Control Signals Reset Power Down Ports Inputs (Input MicroCells) Port Inputs Page Register Port MicroCell Feedback Port MicroCell Feedback *NOTE:
Input Name
[15:0]* CNTL [2:0] [7:0], [7:0] [7:3], [1:0] [2:0] [3:0] MCELLAB.FB [7:4] MCELLC.FB [7:0]
Number Signals
address inputs A[19:4] 80C51XA mode.
PLDs
(cont.)
DECODE
EPROM SELECTS SRAM SELECT CSIOP SELECT PERIPHERAL SELECTS
Figure Block Diagram
EXTERNAL
CHIP SELECT ALLOCATOR EXTERNAL CHIP SELECTS PORT DIRECT MICRO CELL ACCESS FROM DATA
INPUT
GENERAL
NIBBLE ALLOC.
OUTPUT MICROCELL
MICROCELL ALLOCATOR MCELL
INPUT MICROCELL (PORT A,B,C)
PORT MCELL PORT
DIRECT MICROCELL OUTPUT DATA OUTPUT MICROCELL FEEDBACK, INPUT MICROCELL INPUT PORTS PORT INPUTS
PORTS
PSD6XX Family
PSD6XX Family
Each three PLDs unique characteristics suited applications. They described following sections.
PLDs
(cont.)
Decode
Decode (DPLD), shown Figure used select internal PSD6XXE1 functions: EPROM blocks, SRAM, Registers (CSIOP) Port Peripheral Mode. select signals active high have product term, except which two. CSIOP select line PSD6XXE1 internal registers that occupies bytes memory space. second level decoder selects register based address inputs A[7-0]. Each EPROM block chip select. chip select eighth EPROM block product terms, ES7A ES7B. This allows eighth block reside memory spaces, where ES7B typically select reset vectors configuration bytes that stored address space. PSEL used inputs Port control port's Peripheral mode operation. Usually PSEL defined term address inputs. This mode explained Port section.
Table DPLD Inputs Input Source
Address Ports Port Page Register Control Signal Reset *NOTE:
Input Name
A[15:0]* [7:0], [7:0] [7:3], [1:0] [3:0] CNTL1 (Read)
Number Bits
address inputs [19:4] 80C51XA mode, A[3:0] assigned Port
PLDs
(cont.)
(INPUTS) (16) ES7A (23)
PORTS (PORT A,B,C)
Figure DPLD Logic Array
PGR0 PGR3
A[15:0]
EPROM BLOCK SELECTS
READ
CNTL1
ES7B CSIOP PSEL0 PSEL1 PERIPHERAL MODE SELECT SELECT DECODER SELECT
RESET
*NOTE:
address inputs [19:4] 80C51XA mode, A[3:0] assigned Port
PSD6XX Family
PSD6XX Family
PLDs
(cont.)
External Chip Select
External Chip Select (ECSPLD) provides means select external devices. output buffer ECSPLD configured operate high slew rate writing corresponding Drive Register. slew rate measurement rise fall times output. higher slew rate means faster output response while lower slew rate slower response. Refer Table Section setting Drive Register. Faster transitions more likely cause line reflections system noise than slower rates. Adjusting slew rate allows trade-off between greater speed noise sensitivity. selection should based performance requirements system noise characteristics. corresponding bits Drive Register (for normal speed) (for fast drive). default value zero. ECSPLD inputs shown Table outputs combinatorial, either polarity, have product term each shown Figure
Table ECSPLD Inputs Input Source
Address Control Signals Power Down Signal Page Register
Input Name
A[15:0]* CNTL[2:0] PDN** PGR[3:0]
Number Bits
**In 80C51XA mode, address inputs A[19:4] **APD output. When high, PSD6XXE1 power down mode seven ECSPLD outputs driven device through Ports shown Table MicroCell Allocator. Port selection specified PSDabel file assigned PSDcompiler.
Table ECSPLD Output Port Assignments ECSPLD Output
ECS0 ECS1 ECS2 ECS3 ECS4 ECS5 ECS6
Port Assignments
PA0, PA1, PA2, PA3, PD0* PD1* PD2*
*Port output enable (.oe) product terms ECS4-6 outputs.
PSD6XX Family
PLDs
(cont.)
Figure ECSPLD Logic Array
ECS0 (INPUTS) 15:0] (16) POLARITY ECS1 PGR[ 3:0] POLARITY
CNTRL 2:0] READ/WRITE CONTROL SIGNALS OUTPUT ECS6
POLARITY
80C51XA mode, these address inputs A[19:4].
General
General (GPLD) used implement system logic such loadable counters, system mailboxes handshaking protocols. addition GPLD implement random logic state machine functions. GPLD Output Input MicroCells. GPLD, Output Input MicroCells architectures appear Figure along with Port. MicroCells configured using PSDsoft development system. Like other PLDs, GPLD array which generate product terms, maximum nine product terms each twelve MicroCells. Input Output MicroCells connected PSD6XXE1 internal data directly accessed microcontroller. This enables software load data into Output MicroCells read data from both Input Output MicroCells. This feature allows efficient implementation system logic eliminates need connect data logic array required most standard macrocell architectures.
INPUT
ARRAY
GPLD OUTPUT COMB. SELECT MICRO CELL PORT ALLOCATOR CLEAR INPUT D/T/JK SELECT CLOCK GLOBAL CLOCK SELECT
INPUT
PRODUCT TERMS FROM OTHER MICRO CELLS ADDRESS DATA CONTROL OTHER PORTS
PLDs
(cont.)
PSD6XX Family
GPLD MICROCELLS PORTS
LATCHED ADDRESS DATA RESET PRODUCT TERM ALLOCATOR LOAD DATA WRITE CONTROL
PRODUCT TERMS MICRO CELL
Figure GPLD Port
GPLD OUTPUT
POLARITY SELECT
CLOCK SELECT
OUTPUT ENABLE (OE) MICRO CELL FEEDBACK PORT INPUT INPUT LATCH GATE/CLOCK G/CK
INPUT MICROCELLS
PSD6XX Family
PLDs
(cont.)
Output MicroCell
Eight Output MicroCells connected Port pins (except PC2) named McellC0-7. remaining four Micro-Cells connected Port Port named McellAB4-7. McellAB output assigned specific PSDabel, MicroCell Allocator will assign either Port Table shows MicroCells Port assignment.
Table Output MicroCell Port Data Assignments Native Product Terms
Output Port MicroCell Assignment
McellC0 McellC1 McellC2 McellC3 McellC4 McellC5 McellC6 McellC7 McellAB4 McellAB5 McellAB6 McellAB7 *Internal node only. Port Port
Borrowed Product Terms
Data Data Loading Loading Reading Reading 8-Bit Mode 16-Bit Mode
Port Port Port Port Port Port Port Port Port
Product Term Allocator
MicroCells have same cell architecture except McellC four native product terms McellAB three product terms. GPLD also Product Term Allocator with which PSDcompiler automatically borrow product terms from MicroCell another. McellC borrow five product terms from other MicroCells total nine product terms. McellAB three native product terms borrow product terms. Borrowing allows MicroCell outputs needing more product terms unused product terms others. architecture Output MicroCells, shown Figure consists native product terms borrowed product terms from other MicroCells. polarity product term input controlled gate. MicroCell implement either sequential logic, using Flip-Flop element, combinatorial functions. multiplexor selects combinatorial sequential logic MicroCell output. multiplexor output drive Port also feedback path array inputs.
Micro Cell Flip-Flop Type
Flip-Flop MicroCell configured Toggle, type using PSDabel PSDsoft. flip-flop Clock, Preset Clear inputs driven from product term array. Alternatively, device clock input (CLKIN) used flip-flop. Preset Clear active high inputs; Flip-Flop clocked rising edge clock input.
PLDs
(cont.)
ARRAY
INPUT
MICROCELL INTERNAL DATA 15:8] 7:0] ALLOCATOR DIRECTION REGISTER ENABLE (.OE) PRESET(.PR) POLARITY SELECT PROGRAMMABLE (D/T/JK /SR) CLKIN (NOTE PORT DRIVER CLEAR (.RE) MICROCELL ALLOCATOR (NOTE COMB/REG SELECT
PSD6XX Family
Figure GPLD Output MicroCell
FEEDBACK (.FB) PORT INPUT INPUT MICROCELL
NOTES: MCELL local product terms. MCELL local product terms. Max. total product terms Allocator MCELL only.
PSD6XX Family
PLDs
(cont.)
Loading Reading Micro Cells
GPLD MicroCells occupy memory location address space defined CSIOP (refer section). Flip-Flops each MicroCells loaded from data microcontroller write cycle MicroCell (see Port section MicroCell Addresses). data that associates with MicroCell will load Flip-Flop, data will load Flip-Flop. loading cycle takes priority over other Flip-Flop inputs that include Preset, Clear clock. Table data bits that connected MicroCells. ability load flip-flops read them back useful such applications loadable counters, shift registers, mailboxes handshaking protocols.
Table MicroCell Flip-Flop Loading
Normal Flip-Flop Function
NOTE: when writes MicroCell address
Output Enable
MicroCell connected PSD6XXE1 output. output enable each Port output driver controlled single product term (.oe) from array ORed with Direction Register output. Upon power output enable (.oe) equation defined declared output PSDsoft, enabled. MicroCell output declared internal node Port output PSDabel file, then Port used other functions. internal node feedback routed input array.
Input MicroCell
Input MicroCells shown Figure used latch, register pass incoming Port signals prior driving them onto Input bus. outputs these MicroCells also read microcontroller through internal Data Bus. GPLD Input MicroCells, each Ports (except PC2). Input MicroCells individually configurable. enable/clock latch flip-flop driven multiplexor whose inputs product term from GPLD array address strobe (ALE). Each product term output used latch/clock four Input MicroCells. Port inputs [3:0] controlled product term [7:4] controlled another one. Input MicroCell configurations specified equations written PSDabel. Outputs MicroCells read microcontroller "Input MicroCell" buffer. Port section read MicroCells. Input MicroCells latch higher address bits (A31 A16). latched addresses routed inputs. Input Micro-Cell particularly useful handshaking communication applications where processors wish pass data between each other through commonly accessible storage. Figure shows typical configuration where Master writes Port Data Register that read Slave activation "Slave-Read" output enable product term. Slave write Port Input MicroCells activating "Slave- product term. Master then read Input MicroCells. "Slave-Read" "Slave-Wr" signals product terms that derived from Slave inputs Slave_CS.
PLDs
(cont.)
ARRAY
INPUT
INTERNAL DATA 7:0] INPUT MICROCELL DIRECTION REGISTER ENABLE
PSD6XX Family
Figure Input MicroCell
OUTPUT MICROCELLS MICROCELL
NOTE
PORT DRIVER
FEEDBACK LATCH INPUT MICROCELL
NOTE:
controls input MicroCells. (Input MicroCells [3:0] [7:4]
PLDs
(cont.)
PSD6XXE1
SLAVE SLAVE READ PORT DATA REGISTER MCU-RD MCU-WR GPLD 7:0] PORT
SLAVE
MASTER 7:0]
SLAVE PORT INPUT MICRO CELL
Figure Handshaking Communication Using Input MicroCells
PSD6XX Family
PSD6XX Family
"No-glue Logic" PSD6XXE1 Microcontroller Interface directly connected most popular microcontrollers their control signals. Some these microcontrollers with their types control signals shown Table interface type specified using PSDsoft tools.
Interface
Table 12.Microcontroller Busses Control Signals
8031 68330 80198 68HC11 80C51XA 80C251 80C251 Neuron 3150 80196 80196 68HC12*** 68302 68330 68332 80C51XA 68LC302 80186 80C166
Data
CNTL0
CNTL1
PSEN
CNTL2
PSEN
PD0**
ADIO0
LSTRB A0/BLE A4/D0
PA3-PA0
PSEN
PSEN
SIZ0 PSEN
***Not used CNTL2 configured GPLD input. Other used pins (PC7, PD0, PA3-0) configured other functions. ***ALE/AS input optional microcontrollers with non-multiplexed bus. ***This configuration 68HC12 with non-mux bus. Application Note mux-bus configuration.
Table shows names PSD6XXE1 interface control pins their functions. control pins have multiple functions configured interface many microcontrollers. Depending microcontroller, some control input pins required used GPLD input other functions. Specific examples interfaces different microcontrollers provided following sections. microcontrollers that have more than address lines, Port pins used additional address inputs
PSD6XX Family
Interface
(cont.)
PSD6XXE1 Interface Multiplexed
Figure shows example system using microcontroller with multiplexed PSD6XXE1. ADIO port PSD6XXE1 connected directly microcontroller address/data bus. multiplexed only byte (eight-bit data) both bytes (sixteen-bit data). latches address lines internally; latched addresses brought Port PSD6XXE1 drives ADIO data only when internal resources accessed input active.
Figure Example Typical Multiplexed Interface, 16-Bit Data
(OPTIONAL)
PORT
PORT
(OPTIONAL)
PSD6XXE1
(CNTRL1) (CNTRL2)
(CNTRL0)
PORT
(PD0)
15:8]
15:8]
7:0]
PORT RESET
ADIO PORT
MICRO CONTROLLER
PSD6XX Family
Interface
(cont.)
PSD6XXE1 Interface Non-Multiplexed
Figure shows example system using microcontroller with non-multiplexed PSD6XXE1. address connected ADIO Port, data connected Port (D[7:0]) Ports (D[15:8], 16-bit data only). data Ports tri-state mode when PSD6XXE1 accessed microcontroller. Should system address exceed sixteen bits, Port used additional address inputs.
Figure Example Typical Non-Multiplexed Interface, 16-Bit Data
(16-BIT DATA ONLY)
PORT
PORT
15:8]
7:0]
PSD6XXE1
(CNTRL1) (CNTRL2)
(CNTRL0)
PORT
(OPTIONAL) (PD0)
ADIO PORT
23:16]
15:0]
15:0]
PORT RESET
MICRO CONTROLLER
PSD6XX Family
Interface
(cont.)
Data Byte Enable Reference
Microcontrollers have different data byte orientations. following tables show PSD6XXE1 interprets byte/word operation different write configurations. Even-byte refers locations with address equal zero byte locations with equal one.
Table 8-Bit Data
Even Byte Byte
Table 16-Bit Data With
Byte Byte
Even Byte Even Byte
Table 16-Bit Data With
Byte Byte Even Byte Even Byte
Table 16-Bit Data With SIZ0, (Motorola MCU) SIZ0
Even Byte Even Byte Byte Byte
Table 16-Bit Data With UDS, (Motorola MCU)
Even Byte Even Byte Byte Byte
PSD6XX Family
Interface
(cont.)
Microcontroller Interface Examples
Figures through show examples basic connections between PSD6XXE1 some popular microcontrollers. PSD6XXE1 control input pins labeled microcontroller function which they configured. interface specified using PSDsoft tools. should grounded Vstby used.
80C31
Figure shows interface 80C31 which 8-bit multiplexed address/data bus. lower address byte multiplexed with data bus. microcontroller signals used accessing internal SRAM Ports while PSEN signal used read EPROM. input (Port PD0) latches address. Refer Memory Section additional 80C31 operating modes.
68HC11
Figure shows interface 68HC11 where PSD6XXE1 configured 8-bit multiplexed mode with settings. ECSPLD generate READ signals external board devices. CNTL2 used used input.
80C196
Figure Intel 80C196 microcontroller, which multiplexed sixteen-bit bus, shown connected PSD6XXE1. signal used high data byte selection. Port pins configured PSDabel outputs control READY BUSWIDTH pins 80C196.
MC68331
Figure shows Motorola MC68331 with non-multiplexed sixteen-bit data 24-bit address bus. data from MC68331 connected Port Port -15). SIZ0 inputs determine high/low byte selection.
80C51XA
Philips 80C51XA microcontroller family multiplexed that supports burst cycles. Address bits A[3:0] multiplexed while A[19:4] multiplexed with data bits D[15:0] 16-bit mode. 8-bit mode, A[11:4] multiplexed with data bits D[7:0]. 80C51XA configured operate with PSD6XXE1 eight-bit (shown Figure sixteen-bit (shown Figure data mode. With sixteen-bit data bus, 80C51XA's connected PSD6XXE1. grounded used. 80C51XA improves throughput performance executing Burst cycles fetch codes from memory. Burst cycles, address latched internally PSD6XXE1, while 80C51XA changes lines sequentially fetch bytes code. access time then measured from address valid data valid. PSD6XXE1 timing requirement Burst cycle identical normal cycle except address hold time with respect required.
PSD6XX Family
Interface
(cont.)
80C251
Intel 80C251 microcontroller features user-configurable interface with four possible configurations shown Table
Table 80C251 Configurations Configuration 80C251 Read/Write Pins
PSEN PSEN only PSEN only PSEN
Connecting PSD6XXE1 Pins
CNTL0 CNTL1 CNTL2 CNTL0 CNTL1 CNTL0 CNTL1 CNTL0 CNTL1 CNTL2
Page Mode
Non-Page Mode, 80C31 compatible [7:0] multiplex with [7:0} Non-Page Mode [7:0] multiplex with [7:0} Page Mode [15:8] multiplex with [7:0} Page Mode [15:8] multiplex with [7:0}
Configuration 80C31 compatible. interface PSD6XXE1 identical that shown Figure Configurations have same connection shown Figure There only read input (PSEN) connected CNTL1 PSD6XXE1. connection allows larger address input PSD6XXE1. Configuration shown Figure signal connected CNTL PSEN signal connected CNTL2. 80C251 major operating modes: Page Mode Non-Page Mode. Non-Page Mode, data multiplexed with lower address byte. active every cycle. Page Mode, data D[7:0] multiplexed with address A[15:8]. cycle where there Page hit, signal active only addresses A[7:0] changing. PSD6XXE1 supports both modes. Page Mode, timing identical Non-Page Mode except address hold time setup time with respect required. PSD6XXE1 access time measured from address A[7:0] valid data valid. Upon power 80C251 fetches locations FFF8h FFF9h where configuration bytes reside. After configuration register set, 80C251 starts executing codes from location 0000h. EPROM block PSD6XXE1 chip selects, ES7A ES7B. second chip select, ES7B defined occupy configuration byte locations while ES7A assigned different memory space.
(cont.)
Interface
7:0]
PSD6XX Family
80C31
EA/VP RESET INT0 INT1 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 PSEN PSEN ALE/P ADIO0 ADIO1 ADIO2 ADIO3 ADIO4 ADIO5 ADIO6 ADIO7
PSD6XXE1
RESET
P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 ADIO8 ADIO9 ADIO10 ADIO11 ADIO12 ADIO13 ADIO14 ADIO15
CNTL0 (WR) CNTL1(RD) CNTL2 (PSEN) PD0-ALE RSTIN
Figure Interfacing PSD6XXE1 with 80C31
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7
(Vstby)
RESET
RESET
used, must grounded.
(cont.)
Interface
AD[7:0] AD[7:0]
PSD6XXE1 68HC11
RESET XIRQ MODB ADIO8 ADIO9 ADIO10 ADIO11 AD1012 AD1013 ADIO14 ADIO15 ADIO0 ADIO1 ADIO2 ADIO3 AD104 AD105 ADIO6 ADIO7
RESET
CNTL0 CNTL1(E) CNTL RSTIN
Figure Interfacing PSD6XXE1 with 68HC11
MODA
(Vstby)
used, must grounded.
RESET
PSD6XX Family
(cont.)
Interface
[15:0] [15:0]
PSD6XX Family
80196 PSD6XXE1
ADIO8 ADIO9 ADIO10 ADIO11 AD1012 AD1013 ADIO14 ADIO15 CNTL0 (WR) CNTL1(RD) CNTL 2(BHE) PD0- RSTIN
RESET ACH0/P0.0 ACH1/P0.1 ACH2/P0.2 ACH3/P0.3 ACH4/P0.4 ACH5/P0.5 PCS6/P0.6 PCS7/P0.7 INST CLKOUT P4.0/AD P4.1/AD P4.2/AD10 P4.3/AD11 P4.4/AD12 P4.5/AD13 P4.6/AD14 P4.7/AD15 AD10 AD11 AD12 AD13 AD14 AD15
READY BUSWIDTH RESET
P3.0/AD P3.1/AD1 P3.2/AD P3.3/AD P3.4/AD P3.5/AD P3.6/AD P3.7/AD ADIO0 ADIO1 ADIO2 ADIO3 AD104 AD105 ADIO6 ADIO7
Figure Interfacing PSD6XXE1 80C196
P2.0/ P2.1/RXD P2.2/EXINT P2.3/ T2CLK P2.4/ T2RST P2.5/ P2.6/ T2UP-DN P2.7/ T2CAP HSI.0 HSI.1 HSI.2/HSO.4 HSI.3/HSO.5
(Vstby)
VREF ANGND
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 HSO.0 HSO.1 HSO.2 HSO.3
used, must grounded.
RESET
(cont.)
Interface
[15:0] [15:0] A[18:0] A[18:0]
MC68331
ADIO0 ADIO1 ADIO2 ADIO3 AD104 AD105 ADIO6 ADIO7
PSD6XXE1
RESET
DSACK0 DSACK1 A19_CS6 A20_CS7 A21_CS8 A22_CS9 A23_CS10
RESET
ADIO8 ADIO9 ADIO10 ADIO11 AD1012 AD1013 ADIO14 ADIO15
SIZ0
CNTL0 CNTL1( CNTL (SIZ0 PD0-AS
Figure Interfacing PSD6XXE1 MC68331
IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 SIZ0 SIZ1 CLKOUT CSBOOT BR_CS0 BG_CS1 BGACK_CS2 FC0_CS3 FC1_CS4 FC2_CS5
(Vstby) RSTIN
used, must grounded.
RESET
PSD6XX Family
(cont.)
Interface
80C51XA
XTAL1 XTAL2 ADIO0 ADIO1 ADIO2 ADIO3 AD104 AD105 ADIO6 ADIO7 A4D0 A5D1 A6D2 A7D3 A8D4 A9D5 A10D6 A11D7
PSD6XX Family
PSD6XXE1
RXD0 TXD0 RXD1 TXD1
T2EX
RESET
INT0 INT1
A0/WRH A4D0 A5D1 A6D2 A7D3 A8D4 A9D5 A10D6 A11D7 A12D8 A13D9 A14D10 A15D11 A16D12 A17D13 A18D14 A19D15 ADIO8 ADIO9 ADIO10 ADIO11 AD1012 AD1013 ADIO14 ADIO15 PSEN CNTL0 (WR) CNTL1(RD) CNTL 2(PSEN)
A4D0 A5D1 A6D2 A7D3 A8D4 A9D5 A10D6 A11D7
PSEN EA/WAIT BUSW
PD0-ALE RSTIN
Figure Interfacing PSD6XXE1 80C51XA, 8-Bit Data
(Vstby)
RESET
used, must grounded.
(cont.)
Interface
80C51XA
XTAL1 XTAL2 A4D0 A5D1 A6D2 A7D3 A8D4 A9D5 A10D6 A11D7 ADIO0 ADIO1 ADIO2 ADIO3 AD104 AD105 ADIO6 ADIO7
PSD6XXE1
RXD0 TXD0 RXD1 TXD1
T2EX
RESET
INT0 INT1
A0/WRH A4D0 A5D1 A6D2 A7D3 A8D4 A9D5 A10D6 A11D7 A12D9 A13D9 A14D10 A15D11 A16D12 A17D13 A18D14 A19D15 A12D8 A13D9 A14D10 A15D11 A16D12 A17D13 A18D14 A19D15 PSEN
A4D0 A5D1 A6D2 A7D3 A8D4 A9D5 A10D6 A11D7 A12D8 A13D9 A14D10 A15D11 A16D12 A17D13 A18D14 A19D15 ADIO8 ADIO9 ADIO10 ADIO11 AD1012 AD1013 ADIO14 ADIO15
CNTL0 (WR) CNTL1(RD) CNTL (PSEN)
PSEN EA/WAIT BUSW
Figure Interfacing PSD6XXE1 80C51XA, 16-Bit Data
(Vstby) RSTIN
RESET
used, must grounded.
PSD6XX Family
(cont.)
PSD6XX Family
Interface
80C251SB
PSD6XXE1
P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 ADIO0 ADIO1 ADIO2 ADIO3 AD104 AD105 ADIO6 ADIO7
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7
AD10 AD11 AD12 AD13 AD14 AD15
P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7
P3.0/RXD P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 RD/A16 PSEN
AD10 AD11 AD12 AD13 AD14 AD15
ADIO8 ADIO9 ADIO10 ADIO11 AD1012 AD1013 ADIO14 ADIO15
CNTL0 CNTL1( CNTL 2(PSEN)
RESET
PD0-ALE
(Vstby) RSTIN
Figure Interfacing PSD6XXE1 80C251, with READ Input
RESET
RESET
**If used, must grounded. **A16 optional.
(cont.)
Interface
80C251SB
PSD6XXE1
P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7
ADIO0 ADIO1 ADIO2 ADIO3 AD104 AD105 ADIO6 ADIO7
PSEN AD10 AD11 AD12 AD13 AD14 AD15
P3.0/RXD P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 PSEN RD/A16
P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7
AD10 AD11 AD12 AD13 AD14 AD15
ADIO8 ADIO9 ADIO10 ADIO11 AD1012 AD1013 ADIO14 ADIO15
RESET
CNTL0 CNTL1( CNTL (PSEN)
PD0-
(Vstby) RESET
Figure Interfacing PSD6XXE1 80C251, with READ PSEN Input
RESET
RSTIN
used, must grounded.
PSD6XX Family
PSD6XX Family
There four programmable ports: Ports bits, Port seven bits Port three bits. ports configured function different modes operation. Each port individually configurable allowing single port perform multiple functions. configuration defined either using PSDsoft tools microcontroller writing on-chip registers.
Ports
General Port Architecture
general architecture Port shown Figure Individual Port diagrams shown Figures will discussed section below. PSD6XXE1 configured non-multiplexed mode, Port and/or Port connected data available general purpose ports. shown Figure port pins contain output multiplexer whose selects driven configuration defined PSDabel Control Registers. Inputs multiplexer include following: Output data from Data Register output mode Latched address outputs GPLD MicroCell output ECSPLD external chip select output above inputs also connected Port Data Buffer (PDB) feedback Internal Data that read microcontroller. three-state buffer operating like multiplexer that allows only source read time. also inputs from Direction Register, Control Register direct port input (Data Port pin's tri-state output driver enable controlled input gate whose inputs come from GPLD array Enable product term (.oe) Direction Register. enable product term array output defined, then Direction Register sole control buffer. Refer Tables direction port configured.
Table Port Direction Control, Output Enable P.T. Defined Direction Register Port Mode
Input Output
Table Port Direction Control, Output Enable P.T. Defined Direction Register
*Port does have output enable P.T. register contents altered microcontroller. feedback path allows microcontroller check contents registers. Ports have embedded Input MicroCells which configured latch, register direct input GPLD. latch register clocked address strobe product term from GPLD array. output from Input MicroCell drives input read microcontroller. Refer Input MicroCell description section. Port additional logic (not shown Figure that enables operate Peripheral mode when Register set.
Output Enable P.T.*
Port Mode
Input Output Output Output
(cont.)
Ports
DATA REG. DATA ADDRESS OUTPUT ADDRESS MICRO CELL OUTPUTS EXT.CS READ DATA OUTPUT SELECT
Figure General Port Architecture
PORT
INTERNAL DATA
CONTROL REG. REG. ENABLE PRODUCT TERM (.OE) INPUT MICRO CELL GPLD INPUT ENABLE
PSD6XX Family
PSD6XX Family
Ports
(cont.)
Port Operating Modes
Ports have several modes operation shown Table mode selected using PSDabel tool programmed into device using Non-Volatile Memory (NVM) that active when power applied cannot altered unless device reprogrammed. mode defined PSDsoft, then other modes microcontroller writing Port configuration registers. I/O, Data Port Address Input modes configurations. other modes initiated microcontroller. modes selected, port altered dynamically between Address modes writing Control Register. Each eight-bit Control Register store "1", setting respective port I/O, "0", setting Address Out. Direction Register output enable product term determine input output. Table summarizes operating modes ports. functions available every port. Table shows where different modes configured.
Table Port Operating Modes Port Mode
McellAB Outputs McellC Outputs ECSPLD Outputs ZPLD Inputs Address Address Data Port Open Drain Slew Rate Peripheral
Port
PA7- (PA7 (PA3
Port
(A7- (D15 (PB7 (PB3
Port
PC7-3,
Port
PSD6XX Family
Ports
(cont.)
Port Operating Modes (cont.) Table Port Operating Mode Settings Defined PSDabel
Declare pins only
Mode
Control Direction Defined Register Register Register PSDconfiguration Setting Setting Setting
output, input (Note (Note (Note
Data Port (Port A,B) Address (Port A,B) Address (Port A,B,C)
Logic equations Declare pins only Logic equation Input MicroCells
Specify type
Peripheral Logic equations (Port (PSEL0 Applicable
NOTE direction Port pins controlled Direction Register ORed with individual output enable product term (.oe) from GPLD array.
Mode
mode uses port input GPLD Input MicroCell, and/or output from GPLD, ECSPLD. Port assignments shown Tables output tri-stated with control signal defined product term (.oe) from PLD, setting zero Direction Register. Direction Register must defined input pin. mode specified PSDabel declaring port pins, then writing equation assigning port.
Mode
Mode microcontroller uses PSD6XXE1 ports expand ports. ports PSD6XXE1 mapped into microcontroller address space. addresses ports listed Table port will into mode writing zero corresponding Control Register. direction changed writing Direction Register port where makes output input. output enable product term also change direction (see Table 20). When configured output, content Data Register drives pins. input mode, microcontroller reads port input through Data buffer Ports have Control Register mode default pins that configured I/O.
Address Mode
microcontrollers with multiplexed address/data bus, ports Address mode drive latched addresses external devices. Address [7:0] always assigned Port Table address output assignments Ports Direction Register Control Register must port pins using Address mode. non-multiplexed mode, address[7:0] available Port Address Mode.
PSD6XX Family
Ports
(cont.)
Port Operating Modes (cont.) Address Mode
microcontrollers that have more than address lines, higher addresses connected Port address input latched Input MicroCell ALE. input that included DPLD equations EPROM SRAM considered address input.
Data Port Mode
Port used data ports microcontroller with non-multiplexed address/data bus. Data Port connected data microcontroller. general functions disabled Port port configured Data Port.
Peripheral Mode
Only Port supports Peripheral mode whereby Port serves tri-stateable bi-directional data buffer microcontroller's data bus. Peripheral mode enabled setting Register "1". Figure shows that when Peripheral mode enabled either PSEL0 PSEL1 from DPLD active, Port acts bi-directional buffer microcontroller D[7:0] data bus. buffer tri-stated when PSEL active. Peripheral mode used interface with external peripherals.
Open Drain/Slew Rate Mode
Ports (pins PA7-4) (pins PB7-4) (except PC2) configured open drain instead CMOS outputs. Open Drain configuration useful sinking large currents operate LEDs, example. Open Drain mode enabled writing corresponding Drive Register. Port (PA3-0), Port (PB3-0) Port configured ECSPLD outputs that have high slew rate. high slew rate enabled writing corresponding Drive Register.
Figure Port Peripheral Mode
PSEL0
PSEL1 DATA
REGISTER
PSD6XX Family
Ports
(cont.)
Port Registers
Each port registers used configuration (PCR, Port Configuration Registers) data transfers (PDR, Port Data Registers). contents registers accessed microcontroller through normal read/write cycles addresses given Tables address registers comprised that CSIOP output from DPLD plus address offset listed tables. pins port individually configurable each register controls respective pin. example, register refers port. three Port Configuration Registers, shown Table used setting port configuration. Each register zero power
Table Port Configuration Registers Register Name
Control Direction Drive*
Port
A,B,C,D A,B,C,D
Access
Write/Read Write/Read Write/Read
*Note: Table Drive Register definition.
Control Register
zero Control Register sets Port Port sets Port Address mode. default mode I/O.
Direction Register
Controls direction data flow Ports. configures port output, input. configuration read from Direction Register. default mode input. shown Port Architecture diagram, direction data flow Port pins also controlled output enable (.oe) product term from GPLD array. product term active, Direction Register sole control direction. example configuration port with three least significant bits output remainder input shown Table Port register only three least significant bits active.
Table Port Direction Assignment Example
PSD6XX Family
Ports
(cont.)
Port Registers (cont.) Drive Register
Drive Register configures driver Open Drain, case ECSPLD outputs, sets operate high slew rate. external pull-up resistor required when slew rate mode. Ports register sets different functions lower higher nibbles. four upper bits corresponding bits CMOS ("0") Open Drain ("1") driver. four lower bits used slew rate control. slew rate measurement rise fall times output. higher slew rate means faster output response while lower slew rate slower, lower slope, response. operates high slew rate when corresponding Drive Register "1". Table shows Drive Registers Port which Open Drain Slew Rate configuration.
Table Drive Register Assignment
Drive Register Port Port Port Port Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Slew Rate Slew Rate Open Drain Slew Rate Slew Rate Slew Rate Slew Rate Slew Rate Open Drain Slew Rate Slew Rate Slew Rate Open Drain Slew Rate
NOTE: Applicable, should "0".
PSD6XX Family
Ports
(cont.)
Port Data Registers
Port Data Registers, shown Table used microcontroller write read data from ports. Table shows register name, ports having each register type microcontroller access each register. registers described below.
Table Port Data Registers Register Name
Data Data Output MicroCell Input MicroCell Enable
Port
A,B,C,D A,B,C,D A,B,C A,B,C A,B,C Write/Read
Access
Read input
Read outputs MicroCells Write loading MicroCells Flip-Flop Read outputs Input MicroCells Read output enable control port driver
Data
Port pins connected directly Data buffer. input mode, input read through Data buffer.
Data Register
Stores output data written output mode. contents Register driven pins Direction Register product term "1". contents register also read back microcontroller.
Output MicroCell
GPLD Output MicroCells occupy location microcontroller's address space. microcontroller read output MicroCells. Writing MicroCell loads data MicroCell Flip-Flops. Refer section more detail.
Input MicroCell
Input MicroCells used latch store external inputs. outputs Input MicroCells routed input also read microcontroller. Refer section detail description.
Enable
Enable buffer allows microcontroller read outputs "OR" gate that enable input port output driver. indicates driver output mode, indicates driver tri-state input mode.
PSD6XX Family
Ports
(cont.)
Port Data Registers (cont.) Register Address Offset
base address Registers defined CSIOP equation that occupies bytes address space defined user PSDsoft. lower address byte A[7:0], address offset, selects register. Table shows address offset MCUs except those Motorola microcontrollers with 16-bit data bus. Table shows address offset Motorola MCUs 16-bit mode. example, when CSIOP defined occupy address range 1000h 10FFh PSDabel, address Port Control Register then 1002h.
Table Register Address Offset (relative CSIOP) Register Name
Data Control Data Direction Drive Input MicroCell Enable Output MicroCell
Port
Port
Port
Port
Table 27A. Register Address Offset 16-Bit Motorola Microcontrollers 16-Bit Mode (relative CSIOP) Register Name
Data Control Data Direction Drive Input MicroCell Enable Output MicroCell
Port
Port
Port
Port
PSD6XX Family
Ports
(cont.)
Port Functionality Structure
Port have similar functionality structure shown Figure ports configured perform more following functions: Mode GPLD Output MicroCells McellAB[7:4] connected Port PA[7:4} Port PB[7:4]. ECSPLD Output External chip select output connected either Port PA[3:0] Port PB[3:0]. Latched Address output Provide latched address output Table Address Additional high address inputs using Input MicroCells. Open Drain/Slew Rate pins PA[3:0] PB[3:0] configured Open Drain Mode pins PA[7:4] PB[7:4] configured fast slew rate Data Port Port D[7:0} non-multiplexed Port D[15:8] 16-bit non-multiplexed Peripheral Mode Port only
Table Port Latched Address Output Assignments Microcontroller
8051XA (8-Bit) 80C251 (Page Mode) Other 8-Bit Multiplexed 8051XA (16-Bit) Other 16-Bit Multiplexed 8-Bit Non-Multiplexed
Applicable.
Port (3:0)
N/A* Address (3:0) Address (3:0)
Port (7:4)
Address (7:4) Address (7:4) Address (7:4) Address (7:4)
Port (3:0)
Address (11:8) Address (11:8) Address (3:0) Address (11:8) Address (11:8) Address (3:0)
Port (7:4)
Address (15:12) Address (7:4) Address (15:12) Address (15:12) Address (7:4)
INTERNAL DATA
DATA REG. DATA ADDRESS OUTPUT ADDRESS 7:0] A[15:8] PORT MCELL 7:4] ECS[3:0] READ DATA CONTROL REG. REG. ENABLE PRODUCT TERM (.OE) INPUT MICRO CELL ENABLE OUTPUT SELECT
(cont.)
Ports
Figure Port Structure
PSD6XX Family
GPLD- INPUT
PSD6XX Family
Ports
(cont.)
Port Functionality Structure
Port does support Address mode Control Register required. Port configured perform more following functions: Mode GPLD Output McellC outputs connected Port pins GPLD Input eight Input MicroCells Address Additional high address inputs using Input MicroCells. Open Drain Port pins configured Open Drain Mode Port dedicated Vstby SRAM battery backup used other functions. configured input certain microcontroller interface designs.
Port Functionality Structure
Port only three pins, does support Address mode, Control Register required. Port configured perform more following functions: Mode ECSPLD Output External chip select output Input direct input PLD, Input MicroCells Slew rate pins fast slew rate Port pins configured PSDsoft input pins other dedicated functions: ALE, address strobe input CLKIN, clock input MicroCells Flip-Flops counter CSI, active chip select input. high input will disable EPROM/SRAM.
INTERNAL DATA
DATA REG. DATA PORT OUTPUT MCELL 7:0] READ
(cont.)
Ports
Figure Port Structure
PSD6XX Family
DATA
OUTPUT SELECT
ENABLE
REG. ENABLE PRODUCT TERM (.OE) INPUT MICRO CELL
GPLD INPUT
(cont.)
Ports
DATA REG. DATA PORT OUTPUT ECS[ 6:4] READ
Figure Port Structure
DATA
INTERNAL DATA
OUTPUT SELECT
REG. GPLD-INPUT
PSD6XX Family
PSD6XX Family
PSD6XXE1 internal EPROM SRAM memory blocks. memory select signals come from DPLD user-defined PSDsoft Software.
Memory Blocks
EPROM
PSD6XXE1 provides three EPROM densities: 256K bit, 512K bit. EPROM divided into eight blocks. EPROM configured 128K eight-bit data busses sixteen-bit data buses. Each block EPROM select. Blocks zero have select (ES0-ES6) block selects, ES7A ES7B, either which enables Block dual selects allow Block reside separate memory spaces. typical application would store reset vector residing memory space accessed ES7B. rest Block memory space would accessed ES7A. same technique also used store Configuration bytes Intel 80251 microcontroller which resides high memory space.
SRAM
SRAM bits memory that configured SRAM enabled from output DPLD. SRAM battery back-up mode which invoked when supply voltage drops under standby voltage.
Memory Select
EPROM SRAM select outputs from DPLD whose equations defined using PSDabel. following rules apply memory space definitions: EPROM block select space should larger than physical block size EPROM block select space must overlap SRAM, Peripheral spaces cannot overlap SRAM, Peripheral spaces overlap EPROM with priority given SRAM I/O. This allows SRAM utilize EPROM space that used.
PSD6XX Family
Memory Blocks
(cont.)
Memory Select 8031 Microcontrollers
8031 family microcontrollers, including 80C251 80C51XA, separate address space code memory (enabled PSEN) data memory (enabled RD). PSD6XXE1 allows EPROM SRAM reside program space, data space both. Three different configurations possible:
Separate Space Mode
Code memory space separated from data memory space. PSEN signal used access program code from EPROM, signal used access data from SRAM Ports. This default configuration.
Combined Space Mode
program data memory spaces combined into 64KB block space that allows EPROM SRAM accessed either PSEN EPROM SRAM blocks address space must overlap. This mode enabled microcontroller setting bits Register shown Table "1", either PSEN access SRAM. "1", either PSEN access EPROM. Figure shows memory select logic Combined Space Mode.
Mixed Mode
Allows individual EPROM blocks configured either Data Space Program Space. EPROM block chip selects must qualified with 8031 input -ES7 equations. active will select EPROM blocks data space disable blocks that program space. EPROM blocks that reside data space, access time calculated from valid data valid. This mode automatically PSDsoft whenever signal included EPROM chip select equations.
Table Register
PIO_EN disable mode enable mode *Bit used, "0".
Bits after reset.
RD_EN access SRAM, access EPROM, SRAM,
PSEN_EN PSEN access EPROM only PSEN access EPROM, SRAM,
PSD6XX Family
Memory Blocks
(cont.)
Figure 8031 Memory Modes Separate Space Mode
EPROM ES0-ES7 DPLD
SRAM
PSEN
Figure 80C31 Memory Mode Combined Space Mode
DPLD
ES0-ES7
EPROM
SRAM
PSEN
PSD6XX Family
PSD6XXE1 offers number configurable power saving options which include Automatic Power Down (APD) Logic Power Management Mode Registers (PMMR0 PMMR1). Logic allows PSD6XXE1 enter into either Power Down Sleep Mode automatically, while PMMRs configured time microcontroller selectively reduce power consumption functional blocks.
Power Management Unit
Logic Power Down Mode
Automatic Power Down (APD) logic puts PSD6XXE1 into power savings mode monitoring activity address strobe (ALE/AS). unit enabled, four-bit counter starts counting whenever address strobe inactive. strobe remains inactive fifteen CLKIN clock periods, power down (PDN) signal will become active PSD6XXE1 enter into either Power Down Sleep Mode. Immediately after starts pulsing PSD6XXE1 will return normal operation. counter clock source comes from CLKIN which Port order guarantee that counter will overflow when enabled, there should less than clocks between successive pulses. Usually, microcontrollers entering power down mode will freeze their logic high level. programming PMMR0, knows when power down mode. detects level power down state CLKIN periods, then PSD6XXE1 will enter power down mode. enable operation, PMMR0 should "1". When address strobe starts pulsing again, input switches from high low, PSD6XXE1 will return normal activity. When signal (active state) Power Down Sleep Mode), PSD6XXE1 interface disabled inputs (address, data control signals) blocked from entering device. clock input needed Power Down mode, should blocked save power setting PMMR0 "1".
Sleep Mode
Sleep Mode activated Sleep mode bit, Polarity PMMRs set, Counter overflowed after CLKIN clocks (see Figure 27). Sleep Mode PSD6XXE1 consumes less power than Power Down Mode, with typical reduced 25µA. this mode, still monitors inputs responds them. soon starts pulsing input switches from high low, PSD6XXE1 exits Sleep Mode. PSD6XXE1 access time from Sleep Mode specified tLVDV1. response time input transition specified tLVDV2.
Table Power Down Effect Ports Port Function
Address Data Port Peripheral
Level
Change Change Undefined Three-State Three-State
PSD6XX Family
Power Management Unit
(cont.)
Table Summary PSD6XXE1 Timing Standby Current During Power Down Sleep Mode
Propagation Delay
Normal (Note tLVDV2 (Note
Mode
Power Down Sleep
Recovery Time Normal Operation
tLVDV3 (Note
Access Time
Access Access
Access Recovery Time Normal Access
tLVDV tLVDV1
Typical Standby Current
50µA (Note 25µA (Note
NOTES: Power Down does affect operation PLD. Sleep Mode input will have propagation delay tLVDV2. recovery time normal operation after existing Sleep Mode. input during transition will have propagation delay tLVDV3. Typical current consumption assuming CLKIN disabled.
Figure Logic Block
PMMR0 POLARITY PMMR0 CLEAR LOGIC
SLEEP-EN PMMR1
SLEEP MODE EPROM SELECT
COUNTER EDGE DETECT POWER DOWN (PD) ZPLD SRAM SELECT
CLKIN
SELECT DISABLE EPROM/SRAM DISABLE INTERFACE
PSD6XX Family
Power Management Unit
(cont.)
Figure Enable Power Down Flow Chart
RESET
DISABLED
POLARITY PMMR0
NEED SLEEP MODE
ENABLE SLEEP MODE PMMR1
ENABLE PMMR0
ENABLE PMMR0
DISABLE CLKIN PMMR0
DISABLE CLKIN PMMR0
IDLE CLKIN CLOCK PSD6XXE1 POWER DOWN MODE
IDLE CLKIN CLOCK PSD6XXE1 SLEEP MODE
PSD6XX Family
Power Management Unit
(cont.)
Table Power Management Mode Registers (PMMR0, PMMR1)**
PMMR0
ZPLD Mcell ZPLD Array CMiser Enable Polarity high
**Bits used, should **Both PMMR0 PMMR1 register bits clear zero following power
Subsequent reset pulses will clear registers.
power down polarity power down polarity high Automatic Power Down (APD) disabled Automatic Power Down (APD) enabled EPROM/SRAM CMiser EPROM/SRAM CMiser CLKIN input array connected Every CLKIN change will power when Turbo CLKIN input array disconnected CLKIN input MicroCells connected CLKIN input MicroCells disconnected
PMMR1
Sleep Mode Enable *Unused bits should Sleep Mode Disabled Sleep Mode Enabled
Table Counter Operation Enable
Polarity
Level
Pulsing Counting Counting
Counter
Counting (Generates after Clocks) Counting (Generates after Clocks)
PSD6XX Family
Power Management Unit
(cont.)
Other Power Saving Options
PSD6XXE1 offers other reduced power saving options that independent Power Down Sleep Mode. Except SRAM Standby input features, they enabled setting bits PMMR register.
CMiser
CMiser resides PMMR0. This controls power consumption access time EPROM SRAM. When CMiser when data mode, PSD6XXE1 will consume lowest level power. However, access time will slower (see CMiser adder timing parameters). When CMiser off, power higher PSD6XXE1 will return standard access time.
SRAM Standby Mode
SRAM dedicated Vstby (PC2) that connected battery. When becomes lower than Vstby then PSD6XXE1 will automatically connect Vstby power source SRAM. SRAM Standby Current (Istby) typically 0.5µA. SRAM data retention voltage minimum.
Input
Port configured PSDsoft input When low, signal selects enables internal EPROM SRAM read write operations PSD6XXE1. high will disable EPROM SRAM reduce power consumption. However, remains operational when high.
Input Clock
PSD6XXE1 provides option turn CLKIN input save power consumption. CLKIN input array Output MicroCells. During power down CLKIN input being used part logic equation, clock should disabled save power. CLKIN will disconnected from array MicroCells setting PMMR0.
PSD6XX Family
Power Management Unit
(cont.)
Page Register
four-bit Page Register increases addressing capability microcontroller factor contents Register also read microcontroller. outputs Page Register (PGR0-PGR3) inputs included EPROM SRAM chip select equations. Figure shows Page Register. four Flip-Flops Register connected internal data microcontroller write read from Page Register. Register operate independent register microcontroller page mode implemented.
Figure Page Register
RESET
PGR0 PGR1 PGR2 PGR3 GPLD ECSPLD DPLD
PAGE REG.
Reset Input
PSD6XXE1 active reset input which loads internal configurations clear some registers. Figure shows reset timing requirement. active range minimum tNLNH duration. After rising edge reset, PSD6XXE1 remains reset state during tOPR range. device must reset power-up prior use. While reset input active, active outputs determined PSDabel equations. chip status during reset power down shown Table
PSD6XX Family
Power Management Unit
(cont.)
Table Chip Status During Reset Power Down Mode Port Configuration
Output Address Data Port Peripheral Input Active Tri-stated Tri-stated Tri-stated
Reset
Power Down Mode
Unchanged Depends inputs defined Tri-stated Tri-stated
Register
PMMR0 MicroCells Flip-Flop other registers
Reset
Cleared (power reset) Unchanged (warm reset) Unchanged* Cleared
Power Down Mode
Unchanged Unchanged* Unchanged
*The MicroCell Flip-Flop cleared reset input (Power Down) signal, depending
equations that defined PSDabel file.
Battery Backup
PSD6XXE1 supports battery backup operation that retains contents SRAM event power loss. Port dedicated input external power source. supply voltage falls below reference voltage (Vstby), internal power-switch occurs that provides power internal SRAM. SRAM contents retained down level
Security Protection
PSD6XXE1 programmable security which acts duplication barrier. When set, contents EPROM, non-volatile configuration bits, cannot read device programmers. security through PSDsoft Software embedded compiled output file. security erasable secured windowed part erased re-programmed.
PSD6XX Family
Absolute Maximum Ratings
Symbol
TSTG
Parameter
Storage Temperature
Condition
CLDCC PLDCC Commercial Industrial Military With Respect With Respect With Respect
Unit
Operating Temperature Voltage Programming Supply Voltage Supply Voltage Protection
>2000
NOTE: Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure Absolute Maximum Rating conditions extended periods time affect device reliability.
Operating Range
Range
Commercial Industrial
Temperature
+70°C -40° +85°C
Tolerance
Recommended Operating Conditions
Symbol
Parameter
Supply Voltage
Condition
Speeds
Unit
PSD6XX Family
following tables describe AD/DC parameters PSD6XX family: Electrical Specification Timing Specification Timing Combinatorial Timing Synchronous Clock Mode Asynchronous Clock Mode Input MicroCell Timing Microcontroller Timing Read Timing Write Timing Peripheral Mode Timing Power Down Reset Timing Following some issues concerning parameters presented: specification Supply Current given different modes operation. Before calculating total power consumption, determine percentage time that PSD6XX each mode. Also supply power considerably different EPROM_CMISER "ON". power component gives PLD, EPROM, SRAM mA/MHz specification. timing specification required time delay when EPROM_CMISER "ON".
AC/DC Parameters
Typical Power Calculation
Example PSD6XX Typical Power Calculation Conditions
Highest input frequency (Freq PLD) frequency (Freq ALE) EPROM Access SRAM access access Operational Modes Normal Sleep Number product terms used (from fitter report) total product terms CMiser 8-bit mode additional power above base) 32/129 24.8%
Calculation (typical numbers used)
total Isleep %sleep %normal (ICC (ac) (dc)) Isleep %sleep normal (%EPROM mA/MHz Freq %SRAM mA/MHz Freq %PLD mA/MHz Freq µA/PT) 0.90 (0.8 mA/MHz 0.15 mA/MHz 0.95 mA/MHz mA/PT) 22.5 (2.56 0.84 15.2 12.8 22.5 31.4 22.5 3.14 3.16 Standby current consumption handled similarly sleep mode shown above.
PSD6XX Family
Versions)
Characteristics
Symbol
VIH1 VIL1 VHYS
Parameter
Supply Voltage High Level Input Voltage Level Input Voltage Reset High Level Input Voltage Reset Level Input Voltage Reset Hysteresis Output Voltage
Conditions
Speeds (Note (Note
-0.5 -0.5
+0.5 -0.1
Unit
0.01 0.15
0.45
VSBY ISBY IIDLE (DC) (Note
Output High Voltage SRAM Standby Voltage SRAM Standby Current Idle Current (VSTBY Pin) SRAM Data Retention Voltage Standby Supply Current Power Down Mode Sleep Mode
VSBY Only VSTBY >VCC -0.3 (Note >VCC (Note 0.45
-0.1 ±0.1
µA/PT
Input Leakage Current Output Leakage Current ZPLD Adder Operating Supply Current EPROM Adder SRAM Adder ZPLD Adder
mA/MHz mA/MHz mA/MHz mA/MHz mA/MHz mA/MHz
EPROM Adder (AC) (Note
CMiser (8-bit mode) other cases CMiser (8-bit mode)
SRAM Adder
CMiser (16-bit mode) CMiser
NOTES:
Reset input hysteresis. VIL1 valid below 0.2VCC -0.1. VIH1 valid above 0.8VCC. high internal Power Down active. Sleep mode internal Power Down active. ZPLD ICC/Frequency Power Consumption graph details.
PSD6XX Family
Versions)
PSD6XXE1 AC/DC Parameters GPLD ECSPLD Timing
GPLD ECSPLD Combinatorial Timing 10%)
Symbol
-90**
Parameter
ECSPLD Input ECSPLD Combinatorial Output GPLD Input Pin/Feedback GPLD Combinatorial Output Port GPLD Input Pin/Feedback GPLD Combinatorial Output Port GPLD Input ECSPLD Output Enable GPLD Input GPLD Output Enable GPLD Input ECSPLD Output Disable GPLD Input GPLD Output Disable
Conditions
(Notes
Aloc
Slew Rate Unit
(Note
(Note
(Notes (Notes (Notes (Notes (Notes (Notes MicroCell
ARPW
GPLD Register Clear Preset Delay GPLD Register Clear Preset Pulse Width GPLD Array Delay
NOTES: ECSPLD Input pins A(0:15), PGR(0:3), CNTL(0:2), PDN. ECSPLD Outputs PA(0:3), PB(0:3), PD(0:2). GPLD Inputs A(0:15), PGR(0:3), CNTL(0:2), PA(0:7), PB(0:7), PC(0:7), PD(0:2), ALE, PDN. 25ns propagation delay from RSTin pin. GPLD Outputs PA(4:7), PB(4:7), PC(0:7).
**-90 speed available only Industrial Operating Temperature Range product.
PSD6XX Family
Versions)
PSD6XXE1 AC/DC Parameters GPLD ECSPLD Timing
GPLD MicroCell Synchronous Clock Mode Timing
Symbol Parameter
Maximum Frequency External Feedback fMAX Maximum Frequency Internal Feedback CNT) Maximum Frequency Pipelined Data Input Setup Time Input Hold Time Clock High Time Clock Time Clock Output Delay GPLD Array Delay Minimum Clock Period
-90**
27.03 37.04 41.67
25.00 31.25 35.71
Conditions
1/(tS tCO) 1/(tS -10) 1/(tCH tCL) (Note (Note Clock Input Clock Input Clock Input MicroCell
30.30 43.48 50.00
Aloc
Slew Rate
Unit
GPLD MicroCell Asynchronous Clock Mode Timing 10%)
Symbol Parameter
Maximum Frequency External Feedback fMAXA Maximum Frequency Internal Feedback CNTA) Maximum Frequency Pipelined Data MINA Input Setup Time Input Hold Time Clock Input High Time Clock Input Time Clock Output Delay GPLD Array Delay Minimum Clock Period
-90**
25.00 33.33 41.67
21.74 27.78 35.71
Conditions
1/(tSA tCOA 1/(tSA tCOA-10) 1/(tCH tCL) (Note (Note (Note (Note (Note MicroCell fCNTA
26.32 35.71 41.67
Aloc
Slew Rate
Unit
NOTE: GPLD Inputs A(0:15), PGR(0:3), CNTL(0:2), PA(0:7), PB(0:7), PC(0:7), PD(0:2), ALE, PDN. 25ns propagation delay from RSTin pin.
**-90 speed available only Industrial Operating Temperature Range product.
PSD6XX Family
Versions)
PSD6XXE1 AC/DC Parameters GPLD ECSPLD Timing
Input MicroCell Timing 10%)
Symbol
-90**
Parameter
Input Setup Time Input Hold Time Input High Time Input Time Input Combinatorial Output Delay
Conditions
(Note (Note (Note (Note (Note
Aloc
Unit
NOTES: Inputs from Port relative register/latch clock from PLD. latch timings refer tAVLX tLXAX.
**-90 speed available only Industrial Operating Temperature Range product.
PSD6XX Family
Microcontroller Interface AC/DC Parameters
Versions)
Explanation Symbols Timing. Example:
AVLX Time from Address Valid Invalid.
Signal Letters
Address Input CEout Output Input Data Input Internal WDOG_ON signal Interrupt Input Input Reset Input Output Port Signal Output Output Data UDS, LDS, IORD, PSEN Inputs Chip Select Input Input Internal Signal Vstby Output Output MicroCell
Signal Behavior
Time Logic Level Logic Level High Valid Longer Valid Logic Level Float Pulse Width
PSD6XX Family
Microcontroller Interface AC/DC Parameters
Read Timing
Symbol
LVLX AVLX LXAX AVQV SLQV
-90**
Parameter
Pulse Width Address Setup Time Address Hold Time Address Valid Data Valid Valid Data Valid Data Valid 8/16-Bit Data Valid 8-Bit Bus, 8031, 80251 Separate Mode Data Hold Time Pulse Width Data High-Z Pulse Width Setup Time Enable Hold Time After Enable Address Input Valid Address Output Delay
Conditions
CMiser Unit
(Note (Note (Note
(Note (Note (Note (Note (Note 16-Bit Mode (Note 8-Bit Mode (Note
RLQV
RHQX RLRH RHQZ EHEL THEH ELTL
AVPV
NOTES:
timing same timing LDS, UDS, PSEN 8031 combined mode) signals. PSEN have same timing 8031 separate mode. input used select internal PSD6XXE1 function. multiplexed mode latched address generated from ADIO delay address output Port.
**-90 speed available only Industrial Operating Temperature Range product.
PSD6XX Family
Microcontroller Interface AC/DC Parameters
Write Timing
Symbol
LVLX AVLX LXAX AVWL SLWL DVWH WHDX WLWH WHAX WHPV WLMV DVMV
-90**
Unit
Parameter
Pulse Width Address Setup Time Address Hold Time Address Valid Leading Edge Valid Leading Edge Data Setup Time Data Hold Time Pulse Width Trailing Edge Address Invalid Trailing Edge Port Output Valid Using Port Data Register Valid Port Output Valid Using MicroCell Register Load Data Valid Port Output Valid Using MicroCell Register Data Address Input Valid Address Output Delay
Conditions
(Note (Note (Notes (Note (Note (Note (Note (Note (Note (Note (Note 16-Bit Mode (Note 8-Bit Mode (Note
AVPV
NOTE: timing same timing LDS, UDS, WRL, signals. Assuming data stable before active write signal. Assuming write active before data becomes valid.
**-90 speed available only Industrial Operating Temperature Range product.
PSD6XX Family
Microcontroller Interface AC/DC Parameters
Port Peripheral Data Mode Read Timing
Symbol
AVQV (PA) SLQV (PA) RLQV (PA) DVQV (PA) QXRH (PA) RLRH (PA) RHQZ (PA)
-90**
Parameter
Address Valid Data Valid Valid Data Valid Data Valid Data Valid 8031 Mode Data Data Valid Data Hold Time Pulse Width Data High-Z
Conditions
(Note
Unit
(Notes
(Note (Note (Note
Port Peripheral Data Mode Write Timing
Symbol
WLQV (PA) DVQV (PA) WHQZ (PA)
-90**
Parameter
Data Propagation Delay Data Port Data Propagation Delay Invalid Port Tri-state
Conditions
(Note (Note (Note
Unit
NOTES: input used select Port Data Peripheral Mode. Data already stable Port Data stable ADIO pins data Port
**-90 speed available only Industrial Operating Temperature Range product.
PSD6XX Family
Microcontroller Interface AC/DC Parameters
Power Down Timing
Symbol
LVDV LVDV1
-90**
Parameter
Access Time from Power Down Access Time from Sleep GPLD ECSPLD Propagation Delay Sleep Mode GPLD ECSPLD Recovery Time After Sleep Mode Maximum Delay from Enable Internal Valid Signal
Conditions
Unit
CLWH
Using CLKIN Input
(µs)
**-90 speed available only Industrial Operating Temperature Range product.
Reset Timing
Symbol
Parameter
RESET Active Time RESET High Operational Device
Conditions
Unit
PSD6XX Family
Figure Read Timing
tAVLX ALE/AS tLVLX (BHE) MULTIPLEXED ADDRESS (BHE/SIZ0) NON-MULTIPLEXED DATA NON-MULTIPLEXED
tLXAX
ADDRESS VALID tAVQV ADDRESS VALID
DATA VALID
DATA VALID tSLQV
tRLQV (PSEN, (LDS, UDS) tRLRH tRHQZ tRHQX
tEHEL tTHEH tELTL
tAVPV ADDRESS
*tAVLX tLXAX required 80C251 Page Mode 80C51XA Burst Mode.
PSD6XX Family
Figure Write Timing
tAVLX ALE/AS
LXAX
LVLX (BHE) MULTIPLEXED ADDRESS VALID tAVWL ADDRESS (BHE, SIZ0) NON-MULTIPLEXED DATA NON-MULTIPLEXED tSLWL tDVWH (WRH, WRL) (LDS, UDS) (DS) WLWH WHDX WHAX ADDRESS VALID DATA VALID DATA VALID
EHEL THEH WLMV tAVPV ADDRESS WHPV STANDARD ELTL
PSD6XX Family
Figure Peripheral Read Timing
ALE/AS
ADDRESS
DATA VALID
tAVQV (PA) tSLQV (PA) tRLQV (PA) tRLRH (PA) tQXRH (PA) tRHQZ (PA)
tDVQV (PA) DATA PORT
Figure Peripheral Write Timing
ALE/AS
ADDRESS
DATA
tWLQV
(PA)
tWHQZ (PA)
tDVQV (PA) PORT DATA
PSD6XX Family
Figure Combinatorial Timing
ECSPLD INPUT tPD1 EXTERNAL OUTPUT
GPLD INPUT tPD2 tPD3 GPLD OUTPUT
Figure Synchronous Clock Mode Timing
CLKIN
INPUT
REGISTERED OUTPUT
PSD6XX Family
Figure Asynchronous Clock Mode Timing (Product-Term Clock)
tCHA
tCLA
CLOCK
INPUT tCOA REGISTERED OUTPUT
Figure Input MicroCell Timing (Product-Term Clock)
CLOCK
INPUT
OUTPUT
PSD6XX Family
Figure Input Output Disable/Enable
INPUT
INPUT OUTPUT ENABLE/DISABLE
Figure Asynchronous Reset/Preset
tARPW
RESET/PRESET INPUT tARP REGISTER OUTPUT
PSD6XX Family
Figure Reset Timing
Figure Switching Waveforms
WAVEFORMS
INPUTS
OUTPUTS
STEADY INPUT
STEADY OUTPUT
CHANGE FROM CHANGE FROM
WILL CHANGING FROM WILL CHANGING
DON'T CARE
CHANGING, STATE UNKNOWN
OUTPUTS ONLY
CENTER LINE TRI-STATE
PSD6XX Family
Preliminary
Capacitance
Symbol
COUT CVPP
Parameter
Capacitance (for input pins only) Capacitance (for input/output pins) Capacitance (for WR/VPP R/W/VPP)
Conditions Typical Unit
VOUT
NOTES: These parameters only sampled 100% tested. Typical values 25°C nominal supply voltages.
Figure Testing Input/Output Waveform
3.0V TEST POINT 1.5V
Figure Testing Load Circuit
DEVICE UNDER TEST
2.01
(INCLUDING SCOPE CAPACITANCE)
Erasure Programming
clear locations their programmed contents, expose window packaged device ultra-violet light source. dosage second/cm required. This dosage obtained with exposure wavelength 2537 intensity 12000 µW/cm minutes. device should about inch from source, filters should removed from light source prior erasure. PSD6XX similar devices will erase with light sources having wavelengths shorter than 4000 Although erasure times will much longer than with sources 2537 exposure fluorescent light sunlight eventually erases device. maximum system reliability, these sources should avoided. used such environment, package windows should covered opaque substance. Upon delivery from WSI, after each erasure, PSD6XX device bits EPROM high state. configuration bits state. code, configuration, data loaded through procedure programming Information programming device available directly from WSI. Please contact your local sales representative.
PSD6XX Family
PSD6XXE1 Assignments
52-Pin PLDCC/ CLDCC
Assignment
52-Pin PLDCC/CLDCC/ MQFP/PQFP
(Vstby)
52-Pin PLDCC/ CLDCC
Assignment
52-Pin PLDCC/CLDCC/ MQFP/PQFP
AD10 AD11 AD12 AD13 AD14 AD15 CNTL0 RESET CNTL2 CNTL1
52-Pin MQFP/ PQFP
52-Pin MQFP/ PQFP
PSD6XX Family
PSD6XX Package Information
Figure Drawing 52-Pin Plastic Leaded Chip Carrier (PLDCC) (Package Type
CNTL2 CNTL1 CNTL0
(VSTBY)
AD15 AD14 AD13 AD12 AD11 AD10
CNTL2
Figure Drawing 52-Pin Ceramic Leaded Chip Carrier (CLDCC) with Window (Package Type
CNTL1 CNTL0
(VSTBY)
AD15 AD14 AD13 AD12 AD11 AD10
PSD6XX Family
RESET
CNTL1
CNTL2
(cont.)
(VSTBY)
CNTL0
PSD6XX Package Information
Figure Drawing 52-Pin Metric Quad Flatpack (MQFP) (Package Type
AD15 AD14 AD13 AD12 AD11 AD10
Figure Drawing 52-Pin Plastic Quad Flatpack (PQFP) (Package Type
CNTL1 CNTL2 CNTL0
(VSTBY)
AD15 AD14 AD13 AD12 AD11 AD10
PSD6XX Family
Product Revisions
Date
January, 1997 May, 1998
Revision Reason
Initial release
Data Sheet Changes
Table changed Characteristics table updated; Microcontroller Interface Write Timing twlmv changed package added; product errata removed; Power Calculation chart added.
Return Main Menu

Field-Programmable Microcontroller Peripherals with Embedded MicroCell

Top Searches for this datasheet

Other recent searches