(NEASCOT-S20TM) 155M AINTEGRATED CONTROLLER Document S14628E

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

(NEASCOT-S20TM) 155M AINTEGRATED CONTROLLER Document S14628E

Datasheet Thumbnail

Top Searches for this datasheet

µPD98405
(NEASCOT-S20TM)
155M AINTEGRATED CONTROLLER
Document S14628EJ1V0IFJ1 (1st edition) Date Published October 2000 CP(K)
Printed Japan
2000
[MEMO]
Information S14628EJ1V0IF00
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices HANDLING UNUSED INPUT PINS CMOS Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices. STATUS BEFORE INITIALIZATION DEVICES Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
Information S14628EJ1V0IF00
NEASCOT-S20 EEPROM trademarks Corporation.
information this document current February, 2000. information subject change without notice. actual design-in, refer latest publications NEC's data sheets data books, etc., most up-to-date specifications semiconductor products. products and/or types available every country. Please check with sales representative availability additional information. part this document copied reproduced form means without prior written consent NEC. assumes responsibility errors that appear this document. does assume liability infringement patents, copyrights other intellectual property rights third parties arising from semiconductor products listed this document other liability arising from such products. license, express, implied otherwise, granted under patents, copyrights other intellectual property rights others. Descriptions circuits, software other related information this document provided illustrative purposes semiconductor product operation application examples. incorporation these circuits, software information design customer's equipment shall done under full responsibility customer. assumes responsibility losses incurred customers third parties arising from these circuits, software information. While endeavours enhance quality, reliability safety semiconductor products, customers agree acknowledge that possibility defects thereof cannot eliminated entirely. minimize risks damage property injury (including death) persons arising from defects semiconductor products, customers must incorporate sufficient safety measures their design, such redundancy, fire-containment, anti-failure features. semiconductor products classified into following three quality grades: "Standard", "Special" "Specific". "Specific" quality grade applies only semiconductor products developed based customer-designated "quality assurance program" specific application. recommended applications semiconductor product depend quality grade, indicated below. Customers must check quality grade each semiconductor product before using particular application. "Standard": Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade semiconductor products "Standard" unless otherwise expressly specified NEC's data sheets data books, etc. customers wish semiconductor products applications intended NEC, they must contact sales representative advance determine NEC's willingness support given application. (Note) "NEC" used this statement means Corporation also includes majority-owned subsidiaries. "NEC semiconductor products" means semiconductor product developed manufactured defined above).
Information S14628EJ1V0IF00
INTRODUCTION
Readers
This manual intended engineers wish understand functions
µPD98405 design application systems using
Purpose purpose this manual answer questions asked users this product. prepared purpose reference cases where there points that unclear users. Read This Manual Refer table contents item that unclear. When reading this information, must have general knowledge logic circuits microcomputers. When using this manual, sure refer latest user's manual data sheet. Related Documents Data sheet S12689E
User's manual S12250E Conventions Data significance Active Memory address Numeric notation Left: high-order digit, right: low-order digit xxx_B following signal name) Top: high-order, bottom: low-order Binary .XXXX XXXXB Decimal .XXXX Hexadecimal.XXXXh
Information S14628EJ1V0IF00
[MEMO]
Information S14628EJ1V0IF00
CONTENTS
CHAPTER PINS
Q.1.1 Q.1.2 Q.1.3 operation PHRST_B performed? PHRST_B valid during internal mode? necessary supply high-quality power such power supply pins AVDD3, HVDD3, RVDD3 when using internal PHY?.
CHAPTER INTERFACE.
Q.2.1 Q.2.2 Q.2.3 Q.2.4 Q.2.5 Q.2.6 Q.2.7 Q.2.8 Q.2.9 cache line size configuration register should set? Which command issued µPD98405 during master?. should latency timer configuration register set?. What function retry timer configuration register?. What results when µPD98405 receives invalid command during target? registers µPD98405 mapped space memory space?. Does µPD98405 support master operation arbitration parking such line driving selected arbiter when there master request transfer bus? When using 32-bit PCI, should ACK64_B REQ64_B pins processed? possible endian mode?
Q.2.10 What value Revision configuration register?. Q.2.11 possible write status bits through configuration register? Q.2.12 What settings related burst size when µPD98405 performs transfer master? Q.2.13 long does take check EEPROMconnection automatic loading?. Q.2.14 64-bit recognized? Q.2.15 setting performed when using 64-bit PCI? Q.2.16 What count Fast back-to-back?
CHAPTER UTOPIA INTERFACE
Q.3.1 Q.3.2 Q.3.3 Q.3.4 Q.3.5 Q.3.6 Q.3.7 Q.3.8 When should TCLAV signal deasserted? What phase difference between TCLK RCLK? What frequencies TCLK RCLK what their delay from SCLK? clocks (TCLK RCLK) UTOPIA output clock same timing SCLK input. other clocks used? RCLAV signal deasserted middle transferring cell during cell-level handshaking? Does RENBL_B signal perform same operation Drop mode (GMR register octet- cell-level handshake mode? What status through pins while TENBL_B signal inactive (high level)? external device connected UTOPIA interface controlled external interface. this time, necessary control interface µPD98405?.
Information S14628EJ1V0IF00
CHAPTER CONTROL MEMORY.
Q.4.1 Q.4.2 Q.4.3 Q.4.4 Q.4.5 Q.4.6 control memory automatically initialized without problems even maximum size control memory mounted? only used, possible reduce capacity control memory? What conditions SRAM used control memory? host access control memory? long does take initialize control memory after reset? contents control memory cleared when control memory automatically initialized after reset?
CHAPTER MAILBOX
Q.5.1 Q.5.2 mailbox straddling over 64K-byte area? When does mailbox become full transmission/reception stopped?.
CHAPTER TRANSMISSION SCHEDULER
Q.6.1 Q.6.2 Q.6.3 Q.6.4 Q.6.5 Q.6.6 Q.6.7 Q.6.8 What relation between setting scheduler register parameters) actual transmission rate? same cell scheduling operation performed 1/10 10/100?. possible make priorities more shapers same?. possible control band between (for example, widen cell transmission interval between VC2)?. What band each linked shaper aggregate mode? long cell time cell transmission scheduling?. What relation between cell transmission scheduling operation? Does host have scheduler register?
CHAPTER TRANSMISSION
Q.7.1 Q.7.2 Q.7.3 Q.7.4 possible transmit FIFO overflow cells discarded? size transmit queue each consisting transmit packet descriptor limited? transmission performed transmit packet descriptor AAL5 that SIZE transmit queue consists sequence valid packet descriptor link pointer blank packet descriptor, what does queue read pointer transmit table point completion transmission? Q.7.5 Q.7.6 Q.7.7 Q.7.8 Q.7.9 packet added during transmission when transmit active?. When contents packet descriptor Word0 stored transmit table Word0? number linked shaper limited?. there problem value vacant field (Word1, Word2 bits through transmit packet descriptor values system memory rewritten?. there problem value vacant field (Word0, bits through transmit buffer descriptor values system memory rewritten? Q.7.10 What does Packet queue pointer field transmission indication indicate?. Q.7.11 cell transmitted?.
Information S14628EJ1V0IF00
CHAPTER RECEPTION
Q.8.1 Q.8.2 Q.8.3 Q.8.4 Q.8.5 Q.8.6 Q.8.7 Q.8.8 Q.8.9 What will happen cell VPI/VCI value enabled receive lookup table been received, indicated? CRC-10 error reported when cell received? possible disable error check? number batches receive pool limited?. possible temporarily stop reception each there case which receive batch consumed even receive indication including error information reported? only user data AAL5 CPCS-PDU stored receive buffer when AAL5 packet received? should time register (T1R) detect error?. receive pool cell shared with receive pool AAL5?. Pools allocated receive pool cell. pools through used receiving cells? only pools through used?. Q.8.10 What Alert level receive pool descriptor? setting interrupt Alert level valid cell pool? Q.8.11 can't register accessed? Q.8.12 receive cell discarded when VPI/VCI filtering function (VFM enabled using register? Q.8.13 should UINFO field receive table receive indication used?. Q.8.14 What Packet size field receive indication?
CHAPTER TRANSMISSION/RECEPTION.
Q.9.1 Q.9.2 Q.9.3 Q.9.4 contents transmit/receive table changed during transmission reception? many bits VPI/VCI support?. what part CRC-32 operation applied?. receive indication issued even when cell received?
CHAPTER COMMAND
Q.10.1 What will happen Tx_Ready command issued that transmitting packet (active VC)? Q.10.2 What will happen Close_Channel command issued with incorrect setting transmit receive specified command? Q.10.3 When accessing control memory using Indirect_Access command, more addresses accessed issuing command only once?. Q.10.4 What should setting field when internal register external device accessed using Indirect_Access command? Q.10.5 command used?.
CHAPTER LOOPBACK.
Q.11.1 counter valid even loopback mode? Q.11.2 valid data output side (UTOPIA interface) loopback mode? Q.11.3 Does status UTOPIA interface affect transmit/receive operation µPD98405 loopback mode?
Information S14628EJ1V0IF00
Q.11.4 loopback mode RPLP mode loopback used same time? Q.11.5 loopback operation affected data received from receive line side optical cable connected) TPLP mode loopback? optical cable connected, does circuit fault, such LOS, occur?.
CHAPTER
Q.12.1 receive clock extracted receive clock recovery used reference clock transmission side? network synchronization supported?
CHAPTER REGISTER
Q.13.1 What function ADDR register? Q.13.2 should ECCR ERDR register initialized? Q.13.3 corresponding bits PCPR1 PCPR2 registers automatically reset each time each window register been read. low-order bits counter read writing, example, each PCPR1 PCPR2 registers? Q.13.4 area lookup table eliminated setting register register when function used?. Q.13.5 clearing condition register related setting interrupt mode (MDR2 register)? Q.13.6 transmission/reception temporarily halted clearing register during transmission/reception?. Q.13.7 What value register? Q.13.8 Should registers even when used, does this setting affect entire band VBR?
CHAPTER JTAG
Q.14.1 JTAG function reset when JTAG used?
CHAPTER AC/DC CHARACTERISTICS.
Q.15.1 much current consumption internal function used? Q.15.2 When supplied VDD5 pin, much current consumption power supply? Q.15.3 device directly connected control memory UTOPIA interface? that time, does processing VDD5 influence this connection?.
CHAPTER OTHERS.
Q.16.1 Access prohibited clocks (SCLK input) after reset. Does this mean that access prohibited only after hardware reset? Q.16.2 there differences initialization device between hardware reset (input level RST_B pin) software reset (writing register)?
Information S14628EJ1V0IF00
CHAPTER PINS
Q.1.1
operation PHRST_B performed?
A.1.1
PHRST_B goes same time RST_B goes low, holds level min. clock (SCLK input) period after RST_B gone high.
Q.1.2
PHRST_B valid during internal mode?
A.1.2
Yes. PHRST_B outputs level when level input RST_B when software reset applied.
Q.1.3
necessary supply high-quality power such power supply pins AVDD3, HVDD3, RVDD3 when using internal PHY?
A.1.3
Supply +3.3 power same manner supplyed digital block (VDD3).
Information S14628EJ1V0IF00
CHAPTER INTERFACE
Q.2.1
cache line size configuration register should set?
A.2.1
µPD98405 supports words only cache line size. Therefore, setting valid cache line size. other values set, µPD98405 does consider cache boundary when performing transfer.
Q.2.2
Which command issued µPD98405 during master?
A.2.2
Refer µPD98405 user's manual section 4.2.4 Master transactions. Regarding read command, however, which command issued differs follows depending settings cache line size. When cache line size Commands described µPD98405 user's manual section 4.2.4 Read transactions issued. When cache line size value other than µPD98405 always issues memory read command. command. Exercise caution when using system that performs processing identifying type read
Q.2.3
should latency timer configuration register set?
A.2.3
Setting latency timer becomes valid when low-order bits value masked. That setting latency timer should 248.
Q.2.4
What function retry timer configuration register?
A.2.4
µPD98405 counts retry timeout, disconnect timeout, latency timeout retry timer count. these transfer abort counts exceed retry timer value, FERR register operation stopped.
Information S14628EJ1V0IF00
CHAPTER INTERFACE
Q.2.5
What results when µPD98405 receives invalid command during target?
A.2.5
µPD98405 does respond transfer (does assert DEVSEL_B active). Invalid commands those listed below: Memory Read Memory Read Line Memory Read Multiple Memory Write Memory Write Invalidate Read Write Configuration Read Configuration Write
Q.2.6
registers µPD98405 mapped space memory space?
A.2.6
Both space memory space used. They also used simultaneously.
Q.2.7
Does µPD98405 support master operation arbitration parking such line driving selected arbiter when there master request transfer bus?
A.2.7
Yes.
Q.2.8
When using 32-bit PCI, should ACK64_B REQ64_B pins processed?
A.2.8
Pull ACK64_B REQ64_B pins externally.
Information S14628EJ1V0IF00
CHAPTER INTERFACE
Q.2.9
possible endian mode?
A.2.9
Only little endian used mode. little endian selected general-purpose mode.
Q.2.10
What value Revision configuration register?
A.2.10
Revision 01h, which common versions. values register, µPD98405 internal register, differ depending version. version device recognized using register.
Q.2.11
possible write status bits through configuration register?
A.2.11
Write operation Status register conforms standard. When written bit, holds value, when written bit, cleared
Q.2.12
What settings related burst size when µPD98405 performs transfer master?
A.2.12
Settings register, cache line size latency timer configuration register related.
Information S14628EJ1V0IF00
CHAPTER INTERFACE
Q.2.13
long does take check EEPROMconnection automatic loading?
A.2.13
Connection check takes about clocks (CLK input) automatic loading takes about 2400 clocks (CLK input).
Q.2.14
64-bit recognized?
A.2.14
µPD98405 samples REQ64_B signal reset (rise RST_B). When REQ64_B low,
µPD98405 recognizes 64-bit PCI, performs 64-bit transfer.
RST_R
Sampling
REQ64_B
Q.2.15
setting performed when using 64-bit PCI?
A.2.15
described A.2.14, 64-bit transfer enabled when 64-bit recognized register 64-bit addressing, PBAH register value other than
Q.2.16
What count Fast back-to-back?
A.2.16
maximum count Fast back-to-back field register. When maximum count Fast back-to-back one, transfers executed Fast back-to-back. maximum number seven. When transfer disabled Fast back-to-back executed.
Information S14628EJ1V0IF00
CHAPTER UTOPIA INTERFACE
Q.3.1
When should TCLAV signal deasserted?
A.3.1
Deassert between (second byte cell header) (44th byte payload). deassert
TCLK
TENBL_B
TxCLAV
Tx7-Tx0 TSOC
Q.3.2
What phase difference between TCLK RCLK?
A.3.2
phase difference between TCLK RCLK officially specified.
Q.3.3
What frequencies TCLK RCLK what their delay from SCLK?
A.3.3
TCLK RCLK output clock same timing SCLK input. this time, delay follows: SCLK TCLK delay: MAX. SCLK RCLK delay: MAX.
Information S14628EJ1V0IF00
CHAPTER UTOPIA INTERFACE
Q.3.4
clocks (TCLK RCLK) UTOPIA output clock same timing SCLK input. other clocks used?
A.3.4
Q.3.5
RCLAV signal deasserted middle transferring cell during cell-level handshaking?
A.3.5
Yes. µPD98405 does load data through while RCALV signal deasserted. RCLAV signal deasserted again, starts loading through valid data.
Q.3.6
Does RENBL_B signal perform same operation Drop mode (GMR register octet- cell-level handshake mode?
A.3.6
Yes. details operation, refer 4.3.1 UTOPIA interface µPD98405 User's Manual.
Q.3.7
What status through pins while TENBL_B signal inactive (high level)?
A.3.7
through pins output
Q.3.8
external device connected UTOPIA interface controlled external interface. this time, necessary control interface µPD98405?
A.3.8
right control interface µPD98405 used. this case, PHINT_B must externally pulled other pins opened.
Information S14628EJ1V0IF00
CHAPTER CONTROL MEMORY
Q.4.1
control memory automatically initialized without problems even maximum size control memory mounted?
A.4.1
Yes. details automatic initialization, refer Setting Control Memory µPD98405 User's Manual.
Q.4.2
only used, possible reduce capacity control memory?
A.4.2
capacity control memory reduced accordance with number used. determined capacity, refer Setting Control Memory µPD98405 User's Manual.
Q.4.3
What conditions SRAM used control memory?
A.4.3
SRAM that satisfies following conditions used: +3.3 product Operating speed: (when SCLK MHz); operating speed dependent SCLK input. total bits wide; enabling control 8-bit units necessary.
Q.4.4
host access control memory?
A.4.4
host access control memory µPD98405. host read write control memory issuing Indirect_Access command.
Information S14628EJ1V0IF00
CHAPTER CONTROL MEMORY
Q.4.5
long does take initialize control memory after reset?
A.4.5
takes clocks (SCLK input). time required automatically initialize control memory dependent size control memory fixed clocks.
Q.4.6
contents control memory cleared when control memory automatically initialized after reset?
A.4.6
µPD98405 only writes block numbers when control memory automatically initialized. Other areas cleared initialize control memory, therefore, execute software reset after host cleared areas that automatic initialization (writing block numbers) executed.
Information S14628EJ1V0IF00
CHAPTER MAILBOX
Q.5.1
mailbox straddling over 64K-byte area?
A.5.1
cannot. mailbox must into area bytes that register (the high-order bits mailbox start address). mailbox used maximum size (about bytes), register must cleared
System memory
System memory
XXX10000h
64K-byte boundary
XXX10000h
64K-byte boundary
Mailbox
Mailbox
XXX20000h
64K-byte boundary
XXX20000h
64K-byte boundary
Q.5.2
When does mailbox become full transmission/reception stopped?
A.5.2
mailbox becomes full (including notification) when corresponding indication been correctly written mailbox. Transmission/reception stopped when attempt made write next indication mailbox that full.
Information S14628EJ1V0IF00
CHAPTER TRANSMISSION SCHEDULER
Q.6.1
What relation between setting scheduler register parameters) actual transmission rate?
A.6.1
scheduler register parameters) cell units. average rate valid cell transmission cells cell. peak rate, valid cell interval cell interval. actual transmission rate scheduler register dependent speed (line speed) device connected line side. relation between line speed transmission rate expressed follows: Average rate Line speed Peak rate Line speed/(P Here example setting where line speed 155.52 Mbps. Example Line speed: 155.52 Mbps, Average rate: 38.88 Mbps, Peak rate: 51.84 Mbps 38.88/155.52 (155.52/51.84)
Q.6.2
same cell scheduling operation performed 1/10 10/100?
A.6.2
Yes.
Q.6.3
possible make priorities more shapers same?
A.6.3
Yes. priorities shapers made same setting same value PRIORITY field scheduler register each shaper. cell transmission timing conflict between shapers same priority occurs, cells sequentially transmitted shapers using round-robin algorithm.
Information S14628EJ1V0IF00
CHAPTER TRANSMISSION SCHEDULER
Q.6.4
possible control band between (for example, widen cell transmission interval between VC2)?
A.6.4
Yes. Forcibly narrow band using unassigned cell generator. priority unassigned cell generator highest level, data cell intervals extended band used unassigned cell generator. Example transmitting cell: VC1, VC2, shaper Setting shaper 1/9, Normal cell transmission VC1, Data cell Unassigned cell
Cell transmission when unassigned cell generator used Shaper unassigned cell generator. Setting shaper 2/3,
Unassingned cell transmitted unassigned cell generator.
Q.6.5
What band each linked shaper aggregate mode?
A.6.5
Each active that transmitting cell equally divides band shaper uses divided band. example, (VC1, VC2, VC3) registered shaper aggregate mode (setting shaper: 11/1, while transmitting cell, band each shaper setting. 1/3, 1/3, While transmitting cell, band each follows: 1/2, 1/2,
Information S14628EJ1V0IF00
CHAPTER TRANSMISSION SCHEDULER
Q.6.6
long cell time cell transmission scheduling?
A.6.6
µPD98405 performs cell transmission scheduling using SCLK input clocks unit. Therefore, determines next cell transmitted every clocks.
Q.6.7
What relation between cell transmission scheduling operation?
A.6.7
µPD98405 determines cell transmitted every clocks using scheduler. After cell transmitted been determined, operation read cell data executed. transmit FIFO become full, operation read cell data stopped.
Q.6.8
Does host have scheduler register?
A.6.8
scheduler register managed changed µPD98405. necessary host rewrite this bit. host must only when shaper used unassigned cell generator.
Information S14628EJ1V0IF00
CHAPTER TRANSMISSION
Q.7.1
possible transmit FIFO overflow cells discarded?
A.7.1
transmit FIFO become full because UTOPIA interface cannot transmit cells more, cell data read. transmit FIFO vacancy, reading data resumed.
Q.7.2
size transmit queue each consisting transmit packet descriptor limited?
A.7.2
Q.7.3
transmission performed transmit packet descriptor AAL5 that SIZE
A.7.3
Transmission performed normally. Only last cell padding trailer transmitted. Because length field trailer this cell last cell aborted user.
Trailer Padding "AII bytes bytes CPCSUU byte Length "AII bytes
Header
CRC-32
bytes
byte
bytes
Information S14628EJ1V0IF00
CHAPTER TRANSMISSION
Q.7.4
transmit queue consists sequence valid packet descriptor link pointer blank packet descriptor, what does queue read pointer transmit table point completion transmission?
A.7.4
queue pointer points position link pointer. start transmission adding packet this case, issue additional Tx_Ready command position blank packet descriptor.
Transmit queue Valid
Link pointer
queue read pointer completion transmission
Blank
packet added this position.
Q.7.5
packet added during transmission when transmit active?
A.7.5
Yes. packet position blank packet descriptor that transmit queue issue Tx_Ready command.
Information S14628EJ1V0IF00
CHAPTER TRANSMISSION
Q.7.6
When contents packet descriptor Word0 stored transmit table Word0?
A.7.6
After Tx_Ready command been issued, µPD98405 reads packet descriptor stores contents packet descriptor Word0 transmit table Word0, then reads data.
Q.7.7
number linked shaper limited?
A.7.7
also possible link used shaper.
Q.7.8
there problem value vacant field (Word1, Word2 bits through transmit packet descriptor values system memory rewritten?
A.7.8
vacant field (Word1, Word2 bits through value other than µPD98405 reads four words packet descriptors internally ignores information vacant field. values system memory rewritten.
Word0
CLPM
CPCS-UU
Word1
SIZE ADDRESS
Word2
Word3
Information S14628EJ1V0IF00
CHAPTER TRANSMISSION
Q.7.9
there problem value vacant field (Word0, bits through transmit buffer descriptor values system memory rewritten?
A.7.9
vacant field (Word0, bits through value other than µPD98405 reads words buffer descriptors internally ignores information vacant field. values system memory rewritten.
LAST
ADDRESS
SIZE
Q.7.10
What does Packet queue pointer field transmission indication indicate?
A.7.10
Packet queue pointer field indicates address packet descriptor packet next which transmission been completed. Note that does indicate packet descriptor address packet which transmission been completed. Only low-order bits address reported.
Information S14628EJ1V0IF00
CHAPTER TRANSMISSION
Q.7.11
cell transmitted?
A.7.11
transmitted following ways: Open transmit same VPI/VCI values them. These transmitted same time with AAL5 packet other cell. this time, cell scheduling determined depending setting shaper which each linked. transmit packet descriptor transmit queue AAL5 packet cell. this case, AAL5 packet cell alternately transmitted.
AAL5 transmit queue Transmit buffer
AAL5 packet AAL5 table
AAL5 packet
transmit queue
Transmit buffer
cell table
cell
AAL5 transmit queue AAL5 Common table Transmit buffer
AAL5 packet
cell
Information S14628EJ1V0IF00
CHAPTER RECEPTION
Q.8.1
What will happen cell VPI/VCI value enabled receive lookup table been received, indicated?
A.8.1
cell VPI/VCI value enabled received received, that cell internally discarded. this time, indication, such interrupt, made. invalid VPI/VCI cell counter (RUEC register) incremented.
Q.8.2
CRC-10 error reported when cell received? possible disable error check?
A.8.2
CRC-10 error reported cell data when cell received. this time, indication, such interrupt, made. CRC-10 error check always enabled. When CRC-10 error check used, ignore cell data.
Word0 Word11
BYTE
BYTE
Word12
UINFO
Word13
TIME STAMP
Word14
CELL HEADER
Word15
NUMBER
Information S14628EJ1V0IF00
CHAPTER RECEPTION
Q.8.3
number batches receive pool limited?
A.8.3
Yes. 64K, equal number bits Remaining number batches field receive pool descriptor.
Q.8.4
possible temporarily stop reception each
A.8.4
Yes. stop reception, clear enable receive lookup table each resume reception, enable bit.
Q.8.5
there case which receive batch consumed even receive indication including error information reported?
A.8.5
Yes. batches consumed until error occurs recognized from Packet size Packet start address fields receive indication. receive FIFO overrun error occurs while first cell packet received, cells that packet internally discarded receive batch consumed this time. This reported Packet size
Q.8.6
only user data AAL5 CPCS-PDU stored receive buffer when AAL5 packet received?
A.8.6
entire AAL5 CPCS-PDU including user data, padding, trailer stored receive buffer.
Information S14628EJ1V0IF00
CHAPTER RECEPTION
Q.8.7
should time register (T1R) detect error?
A.8.7
setting register should system clock time (SCLK input) 64K. example, where time required detect error 320K clocks (about 13.1 where SCLK MHz).
Q.8.8
receive pool cell shared with receive pool AAL5?
A.8.8
Separately receive pools cell ALL5.
Q.8.9
Pools allocated receive pool cell. pools through used receiving cells? only pools through used?
A.8.9
pools through used receiving cells.
Q.8.10
What Alert level receive pool descriptor? setting interrupt Alert level valid cell pool?
A.8.10
setting interrupt Alert level valid cell pool. With µPD98401A, they invalid cell pool.
Information S14628EJ1V0IF00
CHAPTER RECEPTION
Q.8.11
can't register accessed?
A.8.11
newly provided version above (VER register 0103h) µPD98405. This provided version below (VER register 0102h) register read-only value With version 3.0, function this always enable VPI/VCI filtering function.
Q.8.12
receive cell discarded when VPI/VCI filtering function (VFM enabled using register?
A.8.12
field that made invalid SHIFT received cell having VPI/VCI value other than µPD98405 discards that cell, increments RUEC register. Even field that made invalid MASK received cell having VPI/VCI value other than µPD98405 does discard that cell. Area that made invalid SHIFT (when SHIFT
8-bit High-order Low-order High-order
16-bit Low-order
SHIFT 4-bit High-order Low-order Low-order
Area that made invalid SHIFT
Area that made invalid MASK (when MASK 00FFh)
SHIFT 4-bit Low-order
MASK 00FFh Low-order
Area that made invalid MASK
Information S14628EJ1V0IF00
CHAPTER RECEPTION
Q.8.13
should UINFO field receive table receive indication used?
A.8.13
value UINFO field receive table stored UINFO field receive indication user UINFO field application user information.
Q.8.14
What Packet size field receive indication?
A.8.14
Packet size field indicates size receive packet. packet size specified cell units byte units. error occurs, however, receive indication always reports Packet size field cell units. this time, packet size number cells received stored receive buffer until error occurs.
Information S14628EJ1V0IF00
CHAPTER TRANSMISSION/RECEPTION
Q.9.1
contents transmit/receive table changed during transmission reception?
A.9.1
contents table cannot changed during transmission reception, except Word12 receive table.
Q.9.2
many bits VPI/VCI support?
A.9.2
transmission side transmit 24-bit VPI/VCI value. reception side reduces 24-bit VPI/VCI value bits. This reduction done follows: shifted side using SHIFT value register 16-bit VPI/VCI value generated. SHIFT 16-bit value supported. VPI/VCI reduction SHIFT
8-bit High-order Low-order High-order
16-bit Low-order
SHIFT 4-bit High-order Low-order Low-order
Area that made invalid result reduction
Q.9.3
what part CRC-32 operation applied?
A.9.3
CRC-32 operation applied entire CPCS-PDU frame User data, Padding, CPCS-UU, CPI, Length.
Information S14628EJ1V0IF00
CHAPTER TRANSMISSION/RECEPTION
Q.9.4
receive indication issued even when cell received?
A.9.4
receive indication issued when cell received. When cell received, stored receive buffer cell data reported only cell receive interrupt (RCR7 through RCR0 bits register). transmission side, transmit indication issued even when cell transmitted.
Information S14628EJ1V0IF00
CHAPTER COMMAND
Q.10.1
What will happen Tx_Ready command issued that transmitting packet (active VC)?
A.10.1
Tx_Ready command ignored. However, command accepted and, command FIFO used, Busy register specified time.
Q.10.2
What will happen Close_Channel command issued with incorrect setting transmit receive specified command?
A.10.2
µPD98405 malfunction setting incorrect because performs close processing corresponding transmit receive
Q.10.3
When accessing control memory using Indirect_Access command, more addresses accessed issuing command only once?
A.10.3
When command issued once, only address read written.
Q.10.4
What should setting field when internal register external device accessed using Indirect_Access command?
A.10.4
internal register external device accessed regardless whether "11" "10". This does mean that internal register accessed only when "11" that external device accessed only when "10".
Information S14628EJ1V0IF00
CHAPTER COMMAND
Q.10.5
command used?
A.10.5
command issued times close receive after receive lookup table been disabled, following sequence: Disable receive lookup table. Issue command times. Issue receive Deactivate_Channel command. Issue receive Close_Channel command.
Information S14628EJ1V0IF00
CHAPTER LOOPBACK
Q.11.1
counter valid even loopback mode?
A.11.1
Yes. counter counts number transmit cells number cells received loopback.
Q.11.2
valid data output side (UTOPIA interface) loopback mode?
A.11.2
data invalid TENBL_B UTOPIA interface deasserted (high level).
Q.11.3
Does status UTOPIA interface affect transmit/receive operation µPD98405 loopback mode?
A.11.3
Even TCALV/RCLAV UTOPIA interface invalid, example, µPD98405 correctly executes transmission/reception.
Information S14628EJ1V0IF00
CHAPTER LOOPBACK
Q.11.4
loopback mode RPLP mode loopback used same time?
A.11.4
Yes. loopback mode TPLP mode loopback cannot used same time.
HOST TPLP SARLP
Line
RPLP
Q.11.5
loopback operation affected data received from receive line side optical cable connected) TPLP mode loopback? optical cable connected, does line fault, such LOS, occur?
A.11.5
data received from receive line side affected TPLP mode. line fault does occur regardless whether receive line connected disconnected.
Information S14628EJ1V0IF00
CHAPTER
Q.12.1
receive clock extracted receive clock recovery used reference clock transmission side? network synchronization supported?
A.12.1
reference clock transmit synthesizer only REFCLK input (19.44 MHz). synchronizing transmission side with receive clock cannot supported. Network synchronization
Information S14628EJ1V0IF00
CHAPTER REGISTER
Q.13.1
What function ADDR register?
A.13.1
This test register that stores address last transfer executed general-purpose mode. This register invalid mode.
Q.13.2
should ECCR ERDR register initialized?
A.13.2
ECCR ERDR registers initialized after software reset. They initialized after hardware reset, their default values are: ECCR ERDR undefined.
Q.13.3
corresponding bits PCPR1 PCPR2 registers automatically reset each time each window register been read. low-order bits counter read writing, example, each PCPR1 PCPR2 registers?
A.13.3
Yes. desired bits counter read forcibly writing corresponding PCPR1 PCPR2 registers.
Q.13.4
area lookup table eliminated setting register register when function used?
A.13.4
Yes. lookup table area necessary when function used.
Information S14628EJ1V0IF00
CHAPTER REGISTER
Q.13.5
clearing condition register related setting interrupt mode (MDR2 register)?
A.13.5
register always cleared when read.
Q.13.6
transmission/reception temporarily halted clearing register during transmission/reception?
A.13.6
Yes. bits again, transmission/reception resumed. While bits cleared, however, transmission stopped. While transmission stopped, rate cannot adjusted set. reception side, cells received during this time internally discarded.
Q.13.7
What value register?
A.13.7
Ver. 3.0: 0102h Ver. 3.1: 0103h other versions, consult NEC.
Q.13.8
Should registers even when used, does this setting affect entire band VBR?
A.13.8
registers have when used. This setting does affect entire band VBR.
Information S14628EJ1V0IF00
CHAPTER JTAG
Q.14.1
JTAG function reset when JTAG used?
A.14.1
JTAG reset using using JRST_B pin. When using JRST_B pin: JTAG function reset using pins while JRST_B pulled Input clock five times while pulled When using JRST_B pin: JTAG function reset inputting level JRST_B while JRST_B pins pulled this time, low-level width must clock cycle SCLK input more. JRST_B kept (pull down, etc.), JTAG function reset, regardless status pin.
Information S14628EJ1V0IF00
CHAPTER AC/DC CHARACTERISTICS
Q.15.1
much current consumption internal function used?
A.15.1
current consumption specified under special conditions such when internal function used. Only current consumption during normal operation shown µPD98405 Data Sheet. current consumption when internal function used almost same under normal condition.
Q.15.2
When supplied VDD5 pin, much current consumption power supply?
A.15.2
power supply used only supply interface does affect internal operation. Therefore, even supplied VDD5 pin, power consumption normal current consumption (refer µPD98405 Data Sheet)
Q.15.3
device directly connected control memory UTOPIA interface? that time, does processing VDD5 influence this connection?
A.15.3
device directly connected control memory UTOPIA Interface. power supplied VDD5 this time nothing with device. Supply VDD5 only when interface used.
Information S14628EJ1V0IF00
CHAPTER OTHERS
Q.16.1
Access prohibited clocks (SCLK input) after reset. Does this mean that access prohibited only after hardware reset?
A.16.1
Access prohibited clocks after both hardware software reset.
Q.16.2
there differences initialization device between hardware reset (input level RST_B pin) software reset (writing register)?
A.16.2
Basically, initialization operation same there following difference. After software reset, configuration register, ECCR ERDR registers initialized. addition, EEPROM connection checked.
Information S14628EJ1V0IF00
[MEMO]
Information S14628EJ1V0IF00
Facsimile Message
From:
Name Company
Although taken possible steps ensure that documentation supplied customers complete, free up-to-date, readily accept that errors occur. Despite care precautions we've taken, encounter problems documentation. Please complete this form whenever you'd like report errors suggest improvements
Tel.
Address
Thank your kind support.
North America Hong Kong, Philippines, Oceania Electronics Inc. Electronics Hong Kong Ltd. Corporate Communications Dept. Fax: +852-2886-9022/9044 Fax: 1-800-729-9288 1-408-588-6130 Korea Europe Electronics Hong Kong Ltd. Electronics (Europe) GmbH Seoul Branch Technical Documentation Dept. Fax: 02-528-4411 Fax: +49-211-6503-274 South America Brasil S.A. Fax: +55-11-6462-6829 Taiwan Electronics Taiwan Ltd. Fax: 02-2719-5951 Asian Nations except Philippines Electronics Singapore Pte. Ltd. Fax: +65-250-3583
Japan Semiconductor Technical Hotline Fax: 044-435-9608
would like report following error/make following suggestion: Document title: Document number: Page number:
possible, please referenced page drawing. Document Rating Clarity Technical Accuracy Organization
00.6
Excellent
Good
Acceptable
Poor

(NEASCOT-S20TM) 155M AINTEGRATED CONTROLLER Document S14628E

Top Searches for this datasheet

Other recent searches