Description Features AS-i Complete Specification V2.11 compl

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Description Features AS-i Complete Specification V2.11 compl

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Advanced AS-Interface
Description
Features
AS-i Complete Specification V2.11 compliant Integrated EEPROM Additional addressing channel using optoelectronic interface Extended address mode operation programmable option slaves) High impedance AS-i line input, additional pins further impedance optimizations voltage output, approximately volts, stabilized volt voltage output, stabilized, CMOS logic supplied directly (e.g. status indicator output (compliant standard indication recommendation) Integrated watchdog
monolithic CMOS integrated circuit designed AS-i (Actuator Sensor-interface) networks. AS-i networks intended industrial automation. main advantage AS-i solutions that actuators sensors connected using twowire unshielded cable that easy install. This cable transports both power information/data. AS-i network communication based masterslave principle. network extended cable lengths greater than 100m) using repeater mode configuration. AS-i standard automation industry based 62026-2 50295. device available 28-pin SSOP package.
Block Diagram
U5RD OSC1/2
A2SIPOWERFAIL DETECTION
ELECTRONIC INDUCTOR
POWER SUPPLY
OSCILLATOR
RECEIVE TRANSMIT
ASI+
ASIP
DIGITAL LOGIC
ASI-
ASIN
THERMAL PROTECTION
GND2
GND1
Figure Block Diagram
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Advanced AS-Interface
Description
Table Description NAME ASIP ASIN OSC2 OSC1 U5RD UOUT TYPE INOUT INOUT DESCRIPTION connected AS-i-line ASI+ reverse polarity protection diode connected AS-i-line ASI-
SUPPLY Common ports except ASIP/ASIN connected ASI- line) INOUT Addressing channel input Input peripheral fault indication Crystal oscillator x-tal) Crystal oscillator external clock input Output data Output data Output data Output data
SUPPLY Digital ground, must connected Input/output parameter Input/output parameter receive strobe "Master Mode" Input/output parameter power fail "Master Mode" Input/output parameter data clock "Master Mode" Input data Input data Input data Input data Parameter strobe output Data strobe output/reset input
SUPPLY Digital supply input, should connected IN/OUT Output "AS-i-Diagnosis" addressing channel output connection external components Internal supply that might used supply external circuits well Supply external circuitry (e.g. sensor, actuator, etc.), approx. VUIN minus volt
SUPPLY Input power supply block (usually connected AS-i-line ASI+ reverse polarity protection diode)
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Configuration
ASIP ASIN OSC2 OSC1 UOUT U5RD
Receiver
receiver detects signals AS-i line delivers appropriate pulses digital logic. value input signal removed signal band-pass filtered. digital output signals extracted from -shaped input pulses comparators. maximum voltage first negative pulse determines threshold level following pulses. maximum value digitally filtered guarantee stable conditions (burst spikes have effect). This approach combines fast adaptation changing signal amplitudes with high detection safety. receiver delivers positive (P-PULSE) negative (N-PULSE) pulses IC's logic. logic resets comparators after receiving REC-RESET signal. When receiver turned transmitter turned reduce power consumption.
A2SI
Figure Configuration, 28-Pin SSOP
Transmitter
Functional Block Description
Power Supply
on-chip electronic inductor provides de-coupled voltage power supply regulates internal operating voltage. de-coupling circuit (electronic coil) connected between UOUT pins guarantees high impedance seen external capacitor resistor required allow low-pass filter with very high time constant. This high time-constant value necessary maximize input impedance. de-coupling circuit limits current that drawn from UOUT. power supply will shut down de-coupling circuit case overload condition prevent total malfunction complete AS-i line. regulated volt supply voltage connected U5R. external capacitors necessary cope with fast internal external load changes (spikes). Current drawn from subtracted from total load current. power supply circuit dissipates major amount power. total power dissipation shall exceed specified values Figure ground reference voltage both defined pin. This must connected ASI- (ref. Figure
transmitter draws modulated current between ASIP ASIN pins generate communication signals. shape current corresponds integral -function. transmitter uses current high current driver. order activate high current drive capability, small current will turned automatically prior each transmission (slave mode only). current will ramped slowly avoid false voltage pulses AS-I line. amount circuitry between ASI+ ASI- pins minimized allow high impedance values. When transmitter turned receiver turned reduce power consumption.
Digital Logic
digital logic block performs analysis received signal, controls reaction transmits slave response, switches I/O-ports, controls internal EEPROM. principal unction described detail section
Protection Circuitry
device several protection cells that prevent disruption malfunction complete AS-i line. thermal detection shuts down power supply case over-heating condition (temperature 140°C typically more than seconds) when UOUT shorted more than seconds.
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device only reactivated power-on reset. over-heating condition occur overloading output pin. Therefore, circuit monitors operating conditions power supply (effectively monitors UOUT) measures temperature silicon.
mode (master/repeater mode only), input signals have CMOS levels between VU5R
Power-Fail Detection
Infrared Diode Input
photo current input used alternative communication slave mode. circuitry will turned when communication been switched AS-i line. Slave mode logic sets input photo-detector mode disables CMOS mode. this photo-detector mode, signals external photo diode amplified. CMOS
UOUT
power-fail detector consists comparator that generates logic signal case power supply drops below (Power-Fail) time more than tLoff (0.8 ms). power fail signal will presented master mode only. Power-fail detection monitors value ASIP voltage. will activate logic signal power fails more than 1ms. device then buffered external capacitor internal circuitry will reset when supply voltage fails.
U5RD OSC1/2
SIPOWERFAIL DETECTION
ELECTRONIC INDUCTOR
POWER-ON
POWER SUPPLY
SHUT-DOWN
OSCILLATOR
DATA-OUT
OUTPUT STAGE
DO(3:0)
RESET
POWER-FAIL
P-PULSE
DATA-IN
INPUT STAGE
DI(3:0)
RECEIVE ASIP
N-PULSE
RESET
STAGE
REC-RESET
DIGITAL LOGIC
DATA-STRB
PARAM STRB PARAM
SEND-D
OUTPUT STAGE
ASIN
TRANSMIT
SEND-SBY
Logic
PARAM
THERMAL PROTECTION
OVER-HEAT
FAULT
INPUT STAGE P(3:0) OUTPUT STAGE
CMOS INPUT Current STAGE INPUT
OUTPUT STAGE
INPUT STAGE
GND2
GND1
Figure Functional Block Diagram
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Description Digital Logic
STATE MACHINE, reaction
which
controls
digital logic structured parts (see Figure
PORTS, which contain registers digital I/O's; finally which contains non2 volatile data SIcircuit.
UART, which analyses incoming signal from AS-i line ensures correct timing output signals;
Digital Logic
P-PULSE N-PULSE P-Pulse -REG -REG -REG -REG -REG SEND-D SEND-SBY -REG -REG -REG -REG -REG -REG REC-S SEND EG-0 SEND EG-1 SEND EG-2 SEND EG-3 PI-0 PI-1 PI-2 PI-3 DO-R DO-R DO-R DO-R DATA-OUT-0 DATA-OUT-1 DATA-OUT-2 DATA-OUT-3
STATE MACHINE
DI-REG DI-REG DI-REG DI-REG PO-REG PO-REG PO-REG PO-REG
DATA-STRB RESET DATA-IN-0 DATA-IN-1 DATA-IN-2 DATA-IN-3
REC-RESET
UART
PORTS
PARAM-OUT-0 PARAM-OUT-1 PARAM-OUT-2 PARAM-OUT-3 PARAM-STRB PARAM-IN-0 PARAM-IN-1
E2PROM
ADD-CLK ADD-OUT ADD-IN POWER-FAIL POWER-ON RESET
PARAM-IN-2 PARAM-IN-3 IRD-IN FAULT-IN LED-OUT OVER-HEAT HOUTDOWN
Figure Digital Logic
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7.1.1
7.1.1.1
UART Operational Modes Master/Repeater Mode
Input (CMOS Input)
sends signal retrieved from AS-i line AS-i telegram. input signal Manchester-coded active low. falling edge signal, which conducted ADD-IN, starts receiving process triggers ActivityChecker. Receive-Muxer selects input receive data.
signal connected with Send-Muxer SEND-D ADD-IN. signal latched every long there activity input pin. there high level input longer then Activity-Checker will recognize this activity Receive-Muxer returning idle state. information transported SEND-D with delay sender always non-standby mode. SENDSBY signal constant there generation ADD-CLK.
P-PULSE N-PULSE ADD-IN
PULSE ENCODER
UART
-REG
RECEIVE MUXER ACTIVITY CHECKER CODE CHECKER
-REG -REG -REG -REG
RECEIVE REGISTER
-REG -REG -REG -REG -REG
-REG -REG -REG -REG
SEND REGISTER
EC-R
SEND-D
STROBE UNIT CONTROL UNIT
SEND MUXER
ADD-OUT REC-STRB ADD-CLK SEND-SBY REC-RESET
SEND-STRB
Figure UART Block Diagram
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7.1.1.2
AS-i Input
7.1.1.3
Ports
signal AS-i-line generates signals receiver output that pulse coded with minimal pulse width pulse AS-i line starts receiver triggers ActivityChecker through N-PULSE P-PULSE. Receive-Muxer selects AS-i-line pins input receive data. N-PULSE P-PULSE signals latched every long there activity input pins. there pulse distance AS-i-line inputs longer then receiver will recognize this activity Receive-Muxer going idle state. Pulse-Encoder used convert active high pulse-coded signal active Manchester-IIcoded (MAN) signal. will also check pulse stream timing pulse errors (e.g. alternation error). Master/Repeater mode Pulse-Encoder additionally resynchronizes error-free telegram into proper time base. This eliminate pulse jitter transformed AS-i telegram. synchronized signal sent ADD-OUT through Send-Muxer. ADD-OUT connected LED-OUT higher hierarchy level. all, information AS-i-line pins transported LED-OUT with delay Master/Repeater mode sender never standby mode, hence SEND-SBY signal always low. generation ADD-CLK provided simplify external processing Manchester-coded data. rising edge ADD-CLK signal middle second half Manchester data assuring that correct binary data clocked into shift register. ADD-CLK starts with rising edge after falling edge start ADD-OUT with period ratio 1:1. last rising edge ADD-CLK signal occurs after falling edge ADD-OUT. received signal Master Mode valid slave answer with start bit, four data bits, parity, pause following with length greater than UART generates active high REC-STRB signal with pulse width REC-STRB signal connected Parameter Output this mode. appears 10.0 10.5 after rising edge AS-iline.
Functional assignments some ports depend operational mode Thus, these ports perform multiple functions that related particular mode Master Mode, following signals ports connected: Slave Function Parameter output port Parameter output port Parameter output port output/addressing channel output Fault indicator input/addressing channel input Master REC-CLK POWERFAIL REC-STRB MAN-OUT Repeater REC-CLK MAN-OUT
MAN-IN
MAN-IN
7.1.2
Slave Mode
After IC-reset, Receive-Muxer watching input channels (AS-i-line pin) depending multiplex select signal MPX. frequency about kHz. low, Receive-Muxer selects AS-i-line vice versa high, selects data input. channel, from which valid master call received first, will locked until next IC-reset occurs.
7.1.2.1 Input Mode (Photo Diode Input)
photo diode current input Manchester-coded active (ref. 8.2.2 Addressing Channel Input IRD). level signal starts receiver triggers Activity-Checker. Control-Unit enabling Receive-Register received information clocked every into Receive-Register. there high level input longer then Control-Unit will recognize this activity Receive-Register will disabled. received information correct master call with Start-Bit, eleven Data-Bits, Parity-Bit, End-Bit, following pause either greater than (Synchronous Mode) 18.0 (Asynchronous Mode), UART generates internal active high REC-STRB signal with pulse width
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received telegram contained error, Control-Unit will generate REC-STRB signal asynchronous state waiting pause input. After pause detected, UART ready receive next telegram from input. REC-STRB signal generated, occurs 10.0 (Synchronous Mode) 21.0 21.5 (Asynchronous Mode), respectively, after rising edge End-Bit signal. slave asynchronous state, transforms synchronous state. Rec-Muxer locked input until next IC-reset. After generation REC-STRB signal Control-Unit waiting about SEND-STRB generated Main-State-Machine. Control-Unit receives active high SENDSTRB signal, starts transmission SendRegister data. Therefore, Send-Register data will converted active Manchester II-coded (MAN) signal which sent LED-OUT ADD-OUT. first falling edge signal occurs 11.75 (Synchronous Mode) 12.25 (Asynchronous Mode) after rising edge REC-STRB signal. Hence, delay from rising edge End-Bit master call (IRD input) first falling edge slave response (LED output) 21.25 21.75 (Synchronous Mode) 33.25 33.75 (Asynchronous Mode). After pause detected, UART ready receive next telegram from input. case Control-Unit will receive SENDSTRB signal within given time frame (for instance, this slave addressed), will check activity input. Otherwise, will just wait response time µs). both cases Control-Unit stays synchronous. Once slave pause detected, UART ready receive next telegram from input.
7.1.2.2 AS-i Input Mode
Pulse-Encoder used convert active high pulse coded signal active Manchester-IIcoded (MAN) signal. will also check pulse stream timing pulse errors (e.g. alternation error). Control-Unit enables Receive-Register that received information clocked every there pulse distance AS-iline input longer than Control-Unit recognizes this activity disables Receive-Register. received information correct master call with Start-Bit, eleven (11) Data-Bits, Parity-Bit, EndBit, following pause either greater than (Synchronous Mode) 18.0 (Asynchronous Mode), UART generates internal active high REC-STRB signal. received telegram contained error, Control-Unit will generate RECSTRB signal asynchronous state waiting pause AS-i line input. After pause detected UART ready receive next telegram from AS-i line input. REC-STRB signal generated, occurs 10.0 10.5 (Synchronous Mode) 21.5 (Asynchronous Mode), respectively, after rising edge (receiver comparator switching point) End-Bit AS-i line input. slave asynchronous state, transforms synchronous state. Rec-Muxer locked AS-i line input until next IC-reset. After generation REC-STRB signal Control-Unit waiting about SEND-STRB generated Main-State-Machine. Control-Unit receives active high SENDSTRB signal (pulse width ns), starts transmission Send-Register data. Therefore, Send-Register data will converted active Manchester II-coded (MAN) signal which sent AS-i line transmitter SEND-D. first falling edge signal occurs 11.75 (Synchronous Mode) 12.25 (Asynchronous Mode) after rising edge REC-STRB signal. Hence, delay from rising edge End-Bit master call (AS-i input) first falling edge slave response (AS-i output) 21.75 22.25 (Synchronous Mode) 33.75 34.25 (Asynchronous Mode).
signal AS-i-line generates pulse-coded signals (N-PULSE, P-PULSE) receiver output with minimum pulse width pulse AS-i line starts receiver triggers Activity-Checker through N-PULSE P-PULSE.
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SEND-SBY will always after rising edge REC-STRB. This turn transmitter settle operation point. small offset current, hich required operate transmitter, will ramped slowly avoid false voltage pulses AS-i line. data sent, Control-Unit sets sender standby mode (SEND-SBY high) checks slave pause AS-i line input. After pause detected, UART ready receive next telegram from AS-i line input. case Control-Unit will receive SENDSTRB signal within given time frame (for instance, this slave addressed), will check activity AS-i line. activity detected time frame about (another slave transmitting data), Control-Unit will wait next pause (slave pause). Otherwise, will just wait response time µs). both cases Control-Unit stays synchronous. Once slave pause detected, UART ready receive next telegram from AS-i line input.
7.1.2.3 Ports
active (logic high) signal shall cause flashing status (frequency approx. 2Hz) Status-Register (S1) shall well. active (logic low), cleared. that case status operation depends DataExchange-Disable flag. Data-Exchange-Disable flag data exchange allowed) steady-on shall indicate that communication off. Note: active priority will cause flashing even Data-Exchange-Disable flag set. UART selected input channel, output should toggle. this mode does operate indicator output. Hence, periphery failures status information will signaled. OVER-HEAT TRUE will into shutdown stay there until next power-on reset occurs. INVERT-DATA-IN TRUE, input data inverted. This feature will simplify circuitry NPN-inputs.
7.1.2.4 State Machine
Slave Mode necessary decode IO-Configuration; Data-Out Data-In signals directly connected respective port. Multiplex-Flag-nvmem TRUE, output ports will switch high impedance state certain period time following rising edge DataStrobe. contrast master mode, parameter port performs parameter input output function according AS-i Complete Specification. Also compliant AS-I Complete Specification, contains independent watchdog which activated setting Watchdog-active-Flag-nvmem TRUE. Watchdog-Flag TRUE data exchange more than Watchdog-active-Flag-nvmem TRUE, reset (INIT) will performed.
so-called Main-State-Machine performs central control SIIC concerning mode control, access EEPROM; processing master requests; control ports. There register interface (receive send register) between Main-State-Machine UART (controls serial data communication channels). This register interface used exchange communication data between UART Main-StateMachine. avoid situation which single slave accidentally locked allowed state thereby could jeopardize entire system, prohibited states state machine will lead RESET. This means that will execute reset procedure performing instruction "Reset Slave (RES)".
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Summary Master Calls
following diagram Master Calls that will decoded SIare listed. "Enter Program Mode" call intended factory programming only.
order achieve EEPROM firmware protection comply complete AS-i specification, call "Enter Program Mode" will deactivated before shipment slave. Please refer SIApplication Note details programming process.
Table Master Calls Related Slave Responses
Master Request Slave Response
Instruction Data Exchange Write Parameter
DEXG WPAR
~Sel ~Sel
Address Assignment ADRA Write Extented Code-1 Delete Address Reset Slave Read Configuration Read Code Read Code-1 Read Code-2 Read Status Broadcast (Reset) WID1 DELA RDIO RDID RID1 RID2 RDST BR01
~Sel ~Sel
slave response slave response
Enter Program Mode PRGM
Note: extended address mode "Select Bit" defines whether A-Slave B-Slave being addressed. Dependent type master call carries select information (Sel) inverted select information (~Sel).
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Electrical Specification
Absolute Maximum Ratings
Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. These conditions represent stress rating only, functional operation device these other conditions above operational limits noted this specification implied. Exposure maximum rating conditions extended conditions effect device performance, functionality, reliability.
Table Absolute Maximum Ratings SYMBOL ,VGND VASIP VASIN VASIP-ASIN VASIPP VUIN VUINPV Vinputs1 Vinputs2 VHBM1 VHBM2 VEDM Ptot PARAMETER Voltage reference Positive AS-i supply voltage Negative AS-i supply voltage Voltage difference from ASIP ASIN ASIP VASIN) AS-i supply pulse voltage, voltage difference between pins ASIP ASIN (from ASIP ASIN) Aux. power supply input voltage Aux. power supply input voltage pulse Voltage pins DI0, DO0, DSR, PST, LED, FID, UOUT Voltage pins OSC1, OSC2, IRD, CAP, U5R, U5RD Input current into except supply pins Humidity non-condensing Electrostatic discharge human body model (HBM1) Electrostatic discharge human body model (HBM2) Electrostatic discharge equipment discharge model (EDM) Storage temperature Total power dissipation 4000 2000 0.85
MIN. -0.3 -0.3 -0.3
MAX.
UNITS
NOTE
-0.3
-0.3 -0.3
VUIN
Vinputs1
ASIN-pin shall shorted 0V-pin PCB. Reverse polarity protection performed externally. Pulse with 50µs, repetition rate Defined 40040 cond. HBM1: 100pF charged HBM1 with resistor 1.5k series, valid ASIP-ASIN only. HBM2: 100pF charged HBM2 with resistor 1.5k series, valid pins except ASIP-ASIN. EDM: 200pF charged with resistor series, valid ASIP-ASIN only. maximum operating temperature, allowed total power dissipation depends additional thermal resistance from case ambient operation ambient temperature (see Figure
CAUTION: ELECTROSTATIC SENSITIVE DEVICE
Permanent damage resulting loss functionality performance occur this device subjected high-energy electrostatic discharge.
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Ptot (Ta); layer layer
Ptot (2L) Ptot (1L)
Figure Maximum Power Dissipation, PTOT f(Ambient Temperature) Table Operating Conditions SYMBOL VUIN VASIN V0V, VGND IASI ICL1 ICL2 PARAMETER Positive supply voltage Negative AS-i supply voltage Negative supply voltage Supply current VASI Max. output sink current pins DO0, Max. output sink current pins Ambient temperature range, operating range MIN. MAX. 33.1 UNITS
NOTE
voltage ASIN shall shorted with ensure proper functionality transmitter circuit. 8.000 MHz, load without reaction circuit, ASIP short-cut ASIN respectively.
Characteristics
parameters valid recommended range VASIP VASIN, VUIN V0V, amb. devices tested within recommended range VASIP VASIN, V0V, +25°C 85°C 25°C sample base only) unless otherwise stated. Unused input pins shall connected suitable potential within application circuit because there internal pull-up/down resistors. recommended connect these pins either resistor UOUT respectively. With external signal data strobe (pull-down open drain driver) more than 44µs, will execute reset procedure. During power procedure data parameter ports will stay highimpedance state. been initialization procedure external reset DSR, should toggled externally avoid that control logic transfers test mode.
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8.2.1
Digital Input Output Pins
Table Input/Output Voltage Current SYMBOL PARAMETER MIN. MAX. UNITS NOTE
Pins DI3, DSR, FID, VHYST IIHV Voltage range input "low" level, Voltage range input "low" level, only Voltage range input "high" level Hysteresis switching level Current range input "low" level Current range input "high" level Current range high voltage input 0.25 VUOUT
Pins DO3, DSR, VOL1 VOL2 Voltage range output "low" level Output leakage current IOL1 10mA
Voltage range output "low" level Voltage range output "low" level Output leakage current Capacitance
IOL1 10mA IOL2 4.5V
Switching level approximately i.e. VHYST. higher capacitive load external pull-up resistor connected UOUT necessary reach VICH 3.5V less than after beginning pulse, otherwise reset will executed. output driver sends "low" (LED on). output driver sends "high" (equivalent tri-state, off).
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Table Timing Parameter Port SYMBOL tsetup tPST tPI-latch tCYCLE PARAMETER Valid output data; PST-H/L pulse width PST-H/L parameter input latch Next cycle MIN. MAX. 13.5 UNITS
NOTE Figure
parameter input data must stable within period that defined minimum maximum tPI-latch.
tCYCLE
tsetup
tPST
keep stable
PO0-PO3
Parameter port output data
tPI-latch
parameter input value (PIx) parameter output value (POx) wired with external signal source value
Figure Timing Diagram Parameter Port
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Table Timing Data Port Outputs SYMBOL tsetup thold tDSTR tDI-latch tCYCLE PARAMETER Valid output data; DSR-H/L Valid output data; DSR-L/H pulse width DSR-H/L data input latch Next cycle MIN. MAX. 13.5 UNITS
NOTE Figure
data input must stable within period that defined minimum maximum tDI-latch.
tCYCLE
tsetup
tDSR
data remains, multiplex flag hi-z, multiplex flag
DO0-DO3
Data port output data
keep stable
thold
DI0-DI3
Data port input data
tDI-latch Figure Timing Diagram Data Port
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Table Timing Reset Signal SYMBOL tALM1 tALM2 tRESET1 PARAMETER Ext. reset) Ext. Hi-Z Reset time after external transition MIN. MAX. UNITS NOTE
tRESET1
hi-z
DO0-DO3 PO0-PO3
Data port output data
hi-z
Parameter port output data
tALM1 tALM2
Figure Timing Diagram External Reset
8.2.2
Addressing Channel Input
addressing channel input dedicated photo-diode input. photo-diode connected pins directly. input current input. valid signal current input have certain amplitude (range) should exceed certain offset value (see Figure Table logic "low" input will detected, present signal value drops below IIRDO, "high" will detected, present value greater than IIRDO IIRDA.
input current IIRDA
IRDA
IRDO time
Figure Photo Current Waveforms
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Table Current Amplitude Diode Input Slave Mode SYMBOL IIRDO IIRDA PARAMETER Input current offset Input current amplitude MIN. MAX. UNITS NOTE
Table Digital Input Master/Repeater Mode SYMBOL PARAMETER Voltage range input "low" level Voltage range input "high" level Rise/fall time MIN. MAX. VU5R UNITS
NOTE
order avoid jittery AS-i line, rise/fall time input signal should possible.
8.2.3
Fault Indication Input,
fault indication input digital input dedicated periphery fault messaging signal (for properties Table status equivalent input signal. transition will occur with certain delay, because synchronizer circuit between.
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8.2.4
Voltage Outputs
Table Properties Voltage Output Pins UOUT SYMBOL VUOUT VUOUTp tUOUTp VDROP VU5R IUOUT IUOUTS CLUOUT CL5V PARAMETER UOUT output supply voltage UOUT output voltage pulse devi ation UOUT output voltage pulse devi ation width Voltage drop from UOUT supply voltage UOUT output supply current output supply current Total voltage output current IUOUT Short circuit output current Load capacitance UOUT Load capacitance MIN. MAX. UNITS IU5R
NOTE IUOUT 30mA
VUIN VUIN VDROPmax VDROPmin
VUIN
IUOUT
COUT output current switches from vice versa. 11.0V VOUT 27.6V.
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8.2.5
AS-i Load
following parameters determined with short-cut between pins ASIP pins ASIN respectively. Table AS-i Interface Properties (Pins ASIP/ASIN UIN) SYMBOL VUIN ILIN VSIG ISIG CZener RIN1 LIN1 CIN1 RIN2 LIN2 CIN2 PARAMETER Input AS-i voltage Input current limit Input signal voltage difference between ASIP ASIN Modulated output peak current from ASIP ASIN Parasitic capacitance external overvoltage protection diode (zener diode) Equivalent resistor device Equivalent inductor device Equivalent capacitor device Equivalent resistor device Equivalent inductor device Equivalent capacitor device
(L-12mH)*2.5pF/mH
MIN. VUOUTmin+ VDROPmax
MAX. VUOUTmax VDROPmin
UNITS
NOTE
Parameter equivalent circuit slave hich calculated from impedance device paralleled external over-voltage protection diode (zener diode)) satisfy Complete AS-i-Specification v.2.1 concerning requirements extended address range. Subtracting maximum parasitic capacitance external over voltage protection diode (20pF) either triple RIN1, LIN1 CIN1 triple RIN2, LIN2 CIN2 committed device fulfil Complete AS-i-Specification v2.1.
8.2.6
Input Impedance Control
Table SYMBOL RCAP CCAP PARAMETER External filter resistor External filter capacitor MIN. MAX. UNITS NOTE
Recommended values optimal impedance are: RCAP CCAP de-coupling capacitor serial resistor define internal -pass filter time constant; lower values decrease impedance improve turn-on time. Higher values improve impedance increase turn-on time. turn-on time also depends load capacitor UOUT. After connecting slave power capacitor charged with maximum current IUOUT. impedance will increase when voltage allows analog circuitry fully operate.
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8.2.7
Oscillator
Table Oscillator Pins (OSC1 OSC2) SYMBOL COSC PARAMETER External parasitic capacitor oscillator pins OSC1, OSC2 Input "low" voltage Input "high" voltage MIN. MAX. VU5R UNITS
NOTE
external clock applied OSC1 only.
8.2.8
Development Information Data
Table Information Data Conditions: Asynchronous mode, reset default comparator level ,,line pause". SYMBOL VLSIGon PARAMETER Receiver comparator threshold level (see Figure Reset time after Master Call ,,Reset AS-i-Slave" external transition Reset time after power Reset time after power with high capacitive load VASIP voltage detect power fail (master mode only) Power supply break down time (master mode only) VU5R voltage trigger internal reset procedure, falling voltage VU5R voltage trigger INIT procedure, rising voltage Power-on reset pulse width Chip temperature thermal shut down (overheating) 21.5 MIN. MAX. UNITS NOTE Related amplitude pulse
treset1 treset2 treset3 VASIP-PF tLoff VPOR1F VPOR1R tLow TShut
1000 23.5
Guaranteed design only. `Power_on' starts latest VUIN 18V, external capacitor UOUT 10µF. CUOUT 470µF, treset3 guaranteed design only. CUOUT 10µF, power fail generated VASIP VASIP-PF tLoff master mode only).
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level"
VLSIGon (0.45 0.50) VSIG
determines amplitude first negative pulse telegram. This amplitude asserted
VLSIGon VSIG
First negative pulse telegram
Figure Receiver Comparator
MASTER MODE only
VASIP VASIP-PF VUIN
Modes
Loff
VASIN
VU5R VPOR1F VPOR1R tLow
(active low) reset, break down time exceeds tLoff, power-fail signal will generated Power-on Reset will active, VU5R drops below POR1F Reset will initalized
Figure Power-Fail Generation Master Mode) Reset Behavior (All Modes)
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Application Circuits
following figures show typical application cases SIIC. Figure shows application circuit which replacing ASI3+ circuit. Finally, Figure shows SIcircuit used perform analog/digital interface between AS-i-line master electronics. Furthermore this figure shows that used repeater applications well.
Precautions
Precaution must taken avoid radio frequency interference. recommended keep input lines short possible connect unused inputs through pull-up resistor. Furthermore, supply pins should de-coupled with ceramic capacitors addition normal de-coupling capacitors. Also, recommended connect pull-up resistor from (pin order avoid unintentional reset under difficult conditions.
Typical Slave Application
A2SIOSC1
DI_0 DI_1 DI_2 DI_3 DO_0 DO_1 DO_2 DO_3 DS&Reset Fault Input
OSC2
ASI+
39V/1W
ASIP
U5RD ASIN
ASI-
+24V GREEN
RCAP
UOUT
Figure Typical Application, Slave Mode Note: Figure show digital (data parameter) ports without application specific connections. correct function, important consider that output drivers open drain stages hence each port must connected with appropriate pull-up resistor.
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Typical ASI3+ Compatible Application
OSC1
A2SIOSC2
+24V DIO-0 DIO-1 DIO-2 DIO-3 DS&Reset
ASIP
ASI+
39V/1W
ASIN U5RD
ASI-
RCAP
UOUT
Figure Typical ASI3+ Compatible Application Note: Depending I/O-configuration, DI-ports connected Multiplex-Flag set.
Revision January 2001 Pages (total):
Advanced AS-Interface
Typical Master/Repeater Application
ISOLATION
UOUT
A2SI
REC-CLK (optional)
REC-STRB (optional)
OSC1
OSC2
RECEIVE DATA
ASI+
ASIP
/POWER-FAIL
ASIN U5RD
SEND
ASI-
RCAP
CCAP
Figure Master/Repeater Application
further information also Note.
information furnished here AMIS believed correct accurate. However, AMIS shall liable licensee third party damages, including limited personal injury, property damage, loss profits, loss use, interruption business indirect, special, incidental, consequential damages kind connection with arising furnishing, performance, technical data. obligation liability licensee third party shall arise flow AMIS' rendering technical other services.
Revision January 2001 Pages (total):
Advanced AS-Interface
Package Outline
Figure SSOP Package
Figure Package Dimensions Table Package Dimensions (mm) Symbol Nominal Maximum Minimum 1.86 1.99 1.73 0.13 0.21 0.05 1.73 1.78 1.68 0.30 0.38 0.25 0.15 0.20 0.13 10.20 10.33 10.07 5.30 5.38 5.20 0.65 7.80 7.90 7.65 0.75 0.95 0.55
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Advanced AS-Interface
Package Marking
VIEW BOTTOM VIEW
A2SI
R-XXXX
AAAA
Figure Package Marking Marking: AMIS RXXXX AAAA Product name Manufacturer Revision code Date code (year week) Assembly location Traceability Country assembly
Bottom Marking:
yellow indicating pre-programmed Master function printed marking
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Advanced AS-Interface
Ordering Information
12.1 Device Ordering Codes
Ordering Code Description Operating Temperature Package Type Range -25°C 85°C 28-pin SSOP (5.3 10.2) 28-pin SSOP (5.3 10.2) 28-pin SSOP (5.3 10.2) 28-pin SSOP (5.3 10.2) Device Marking Shipping Form
A2SI-ST
Standard version Standard version Pre-programmed master function Pre-programmed master function
Tubes
A2SI-SR
-25°C 85°C
Tape-and-Reel
A2SI-MT
-25°C 85°C
yellow yellow
Tubes
A2SI-MR
-25°C 85°C
Tape-and-Reel
12.2 Demo Ordering Code
Ordering Code Device A2SI-KIT includes: Evaluation board with samples sample Literature (Brochure, Data Sheet, Application Note) Description
Evaluation board dimensions
Revision January 2001 Pages (total):
Advanced AS-Interface
Application Support
13.1 AMIS Partners Application Support
Bihl+Wiedemann Flosswoerthstrasse D-68199 Mannheim, Germany Tel.: 3996 Fax: 3922 Email: mail@bihl-wiedemann.de http://www.bihl-wiedemann.de fieldbus specialists Colchester Road, Kilsyth 3137 Victoria, Australia Tel.: 9761 4653 Fax: 9761 5525 Email: fs_sales@fieldbus.com.au http://www.fieldbus.com.au
13.2 General Information -Interface
AS-International Association Contact Rolf Becker Taubengarten D-63571 Gelnhausen 1103 (63551) Tel: 6051 Fax: 6051 4732 Email: as-interface@t-online.de http://www.as-interface.com
Further Information available http:// www.amis.com/a2si/ Sales Offices http://www.amis.com/sales/
Products sold AMIS covered exclusively warranty, patent indemnification other provisions appearing AMIS standard "Terms Sale" same amended AMIS, sole discretion, from time time). AMIS makes warranty (express, statutory, implied and/or description), including without limitation warranties merchantability and/or fitness particular purpose, regarding information forth Materials pertaining AMIS products, regarding freedom products described Materials from patent and/or other infringement. AMIS reserves right discontinue production change specifications prices products time without notice. AMIS products intended commercial applications. Applications requiring extended temperature range, unusual environmental requirements, high reliability applications, such military, medical life-support life-sustaining equipment, specifically recommended without additional mutually agreed upon processing AMIS such applications. AMIS reserves right change detail specifications required permit improvements design products. trademark Semiconductor, Inc.
Copyright 2000 Semiconductor, Inc. 2300 Buckskin Road Pocatello, Idaho 83201, U.S.A. rights reserved.
Revision January 2001 Pages (total):

Description Features AS-i Complete Specification V2.11 compl

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