AN32502A Power Management Intel PXA250 Application Processor

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AN32502A Power Management Intel PXA250 Application Processor

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AN32502A
Power Management Intel PXA250 Application Processor
This power management developed Intel PXA250 application processor.
Features
AN32502A 2-ch DC-DC converter, 3-ch linear regulator interface circuit power management.
Applications
PDA, Smart phone
Package
HQFN plastic package (HQFN-64)
Type
Silicon monolithic Bi-CMOS
Publication data: November 2002
SDF00034AEB
AN32502A
Ch.5 2.8V 300mA
resistor value limit chrging current exceed limitation coin battery 330k General purpose output 680k
680k
470k 0.01µ FBR1 150k
VREFDET1 FBD1 FBC1 1000p 1000p 1000p
Connect Ch.2 output
REGOUT
LEVEL SHIFT
LEVEL SHIFT
LGND
nRESET
SGND
0.1µ
1000p
1000p
1000p
NDS332P Fairchild NDS335N Fairchild FDC604P Fairchild FDC604P Fairchild FDC604P Fairchild FDC634P Fairchild FDC633P Fairchild FDC604P Fairchild ELL6PM100M Matsushuita Electric Compornents ELL6PM100M Matsushuita Electric Compornents ELJEA151KF Matsushuita Electric Compornents MA2YD23 Matsushuita Electric Industrial
BAT_FLT
Publication data: November 2002
LEVEL SHIFT logic VDD1 DRIVER logic PROM VREF VREF POWER RESET
PGND1
Application circuit example
BACKUP
COIN Voltage Det.
COIN
COIN CHARGE
Ch.1 1.3V 600mA
from logic
150µ
BACKUP circuit
DRIVER
VREFDET2 from control logic logic VREF each channel logic
PROM
(for BACKUP)
Reverse current protection
Note) resistance value constant setting series
PGND2 330k 680k Ch.2 3.2V 300mA
1000p
PWR_EN (Ch.1 On/Off)
decorder
Ch.2 On/Off
VDD1
Ch.3 On/Off
Protection circuit SCPO from ch.1 error amp. from ch.4 output detector logic from control logic VREF VREF 1.6V
Control logic
FBR2
Battery voltage detection
SDF00034AEB
from logic ch.1 ch.4 VREF from control logic logic CONTROL VDD1
Ch.4 On/Off
RGC2
DATA
Ch.3 3.3V 500mA
VDD1
VDD1
PGND3 470k FBR3 0.01µ
TRIG
nRESETOUT
WAKEUP
LEVEL SHIFT
4.7k
Ch.4 3.2V 500mA
PGND4
0.01µ
Stabilized input
AN32502A
Absolute Maximum Ratings
Parameter Storage temperature Operating ambient temperature Operating ambient atmospheric pressure Operating constant gravity Operating shock Supply voltage Symbol Tstg Topr Rating +125 Unit Note
1.013 0.61
Popr
Gopr Sopr
m/s2
m/s2
VBAT
Supply current
Power dissipation
Operating supply voltage range
VDD1 BACKUP
Note) Except storage temperature, operating ambient temperature, supply current power dissipation, ratings Refer page Care should taken when insert this (inverted insertion cause destruction.) Care should taken this IC's surge breakdown voltage.
Publication data: November 2002
SDF00034AEB
AN32502A
Electrical Characteristics
Note) 25°C±2°C unless otherwise specified.
Parameter Ch.1
Symbol
Test circuit
Limits Conditions
Unit
Note
DC-DC converter Output voltage
Vch1d1
1010100B Iout 1000000B Iout 1010100B Iout Output voltage difference Iout Voltage characteristics setting
1.26
1.34
DC-DC converter Output voltage
Vch1d2
1.07
1.13
DC-DC converter output voltage
Vch1dd1
DC-DC converter Supply voltage characteristics Ch.2
Vch1bb
output voltage
Vch2
Iout Iout Output voltage difference Iout Voltage characteristics setting
output voltage
Vch2d
Supply voltage characteristics
Vch2bb
Publication data: November 2002
SDF00034AEB
AN32502A
Electrical Characteristics (continued)
Note) 25°C±2°C unless otherwise specified.
Parameter
Symbol
Test circuit
Limits Conditions Unit Note
Ch.2 backup circuit Backup output voltage Charge voltage Backup battery detection voltage Ch.3 Iout Iout Output voltage difference Iout Voltage characteristics setting Vch2b1 COIN Iout Iout Threshold voltage detection circuit
Vch2c1
Vch2bkd
output voltage
Vch3
output voltage
Vch3d
Supply voltage characteristics
Vch3bb
Ch.4 DC-DC converter output voltage DC-DC converter output voltage Iout Iout Output voltage difference Iout Voltage characteristics setting
Vch4
Vch4d
Supply voltage characteristics
Vch4bb
Publication data: November 2002
SDF00034AEB
AN32502A
Electrical Characteristics (continued)
Note) 25°C±2°C unless otherwise specified.
Parameter
Symbol
Test circuit
Conditions
Limits
Unit
Note
switch Iout I2C: bit: High VIN-V01 3.6V Iout I2C: bit: High VIN-V02
Output voltage
Vsw41
Output voltage
Vsw42
General purpose output VDD1 Iout VDD1 Iout
Output high level voltage
Vpoh
-0.3
Output level voltage
Vpol
Ch.5 Output voltage Output voltage Iout Iout Output voltage difference Iout Voltage characteristics setting
Vch5
2.716
2.884
Vch5d
Supply voltage characteristics
Vch5bb
Publication data: November 2002
SDF00034AEB
AN32502A
Electrical Characteristics (continued)
Note) 25°C±2°C unless otherwise specified.
Parameter Input/ output
Symbol
Test circuit
Conditions
Limits Unit Note
BAT_FLT detection voltage BAT_FLT return hysteresis BAT_FLT level output voltage BAT_FLT high level output voltage Reset detection voltage Reset return hysteresis nRESET level output voltage nRESET high level output voltage WAKEUP level output voltage WAKEUP high level output voltage ChSW level input voltage ChSW high level input voltage nRESETOUT level input voltage nRESETOUT high level input voltage
Bflt
detection voltage detection reset voltage
-2.5% Bflt VDD1 -0.3
Bflt VDD1 Bflt
2.5% Bflt VDD1 2.5% Bflt
Bflth Bflt1 Bflt2 Rset Rseth Rsetv1 Rsetv2 Rwkv1 Rwkv2 Rswv1 Rswv2 Rrsv1 Rrsv2
Reset detection voltage Reset detection reset voltage
-2.5% Bflt
load (pulled down VDD1 only resistor internally) -0.3 VDD1 -0.3 VDD1 -0.3 -0.3
VDD1 VDD1
VDD1 VDD1
VDD1 VDD1
Publication data: November 2002
SDF00034AEB
AN32502A
Electrical Characteristics (continued)
Note) 25°C±2°C unless otherwise specified.
Parameter Serial interface
Symbol
Test circuit
Conditions
Limits Unit
Note
DATA input high level DATA input level input high level input level frequency drive capability
Datah Datal Vack
Pull-up Ch.2 only operation Charge circuit stopping load Ch.2 only operation Charge circuit operation load PWR_EN: High Ch.1 only operation load High Ch.3 only operation load High Ch.4 only operation load Serial High Ch.5 only operation load channels operating load
SDF00034AEB
VDD1 -0.3 VDD1 -0.3
VDD1 VDD1
VDD1 VDD1
Operating current
INC1
Operating current
INC2
Operating current
INC3
Operating current
INC5
Operating current
INC6
Operating current
INC7
Operating current
INC8
Publication data: November 2002
AN32502A
Electrical Characteristics (continued)
Note) 25°C±2°C unless otherwise specified.
Parameter Ch.1
Symbol
Test circuit
Limits Conditions Unit Note
DC-DC converter Transient response characteristics
Vch1ex
1000000B Iout: Change Rising time Output voltage difference 1000000B load load from start signal input till output bottom limit PWR_EN: High Oscillator frequency built-in oscillation circuit ch.1
±100
DC-DC converter output ripple voltage
Vch1rr
DC-DC converter startup time
Vch1tr
Oscillator frequency
fdv1
Ch.2 VBpp Iout VBpp Iout Iout: Rising time Output voltage difference load from start signal input till output bottom limit
Ripple rejection Ripple rejection
Vch2rr1
Vch2rr2
Transient response characteristics
Vch2ex
start time
Vch2tr
Note) above values reference values design, guaranteed values.
Publication data: November 2002
SDF00034AEB
AN32502A
Electrical Characteristics (continued)
Note) 25°C±2°C unless otherwise specified.
Parameter Ch.3
Symbol
Test circuit
Limits Conditions Unit Note
ripple rejection ripple rejection transient response characteristics
Vch3rr1
VBpp Iout VBpp Iout Iout: Change Output voltage difference load from start signal input till output bottom limit
Vch3rr2
Vch3ex
start time
Vch3tr
Ch.4 Iout: Change Rising time Output voltage difference load
DC-DC converter transient response characteristics
Vch4ex
±100
DC-DC converter output ripple voltage
Vch4rr
DC-DC converter start time
Vch4tr
load from start signal input till output bottom limit High Oscillator frequency built-in oscillation circuit ch.4
Oscillator frequency
fdv4
Note) above values reference values design guaranteed values.
Publication data: November 2002
SDF00034AEB
AN32502A
Electrical Characteristics (continued)
Note) 25°C±2°C unless otherwise specified.
Parameter Ch.5 ripple rejection
Symbol
Test circuit
Limits Conditions
Unit
Note
Vch5rr1
VBpp Iout VBpp Iout Iout Change Rising time Output voltage difference load from start signal input till output bottom limit
ripple rejection
Vch5rr2
transient response characteristics
Vch5ex
start time
Vch5tr
Note) above values reference values design guaranteed values.
Publication data: November 2002
SDF00034AEB
AN32502A
Descriptions
name nRESET BAT_FLT LGND SGND PGND4 FBR3 PGND3 PGC2 FBR2 PGND2 PGND1 Reset output voltage detection output input/ output part Capacitor connection (internal oscillator) Resistor connection (internal oscillator) (signal system) Capacitor circuit protection switch output Stabilized voltage input switch output Start control (Ch.2) Start control (Ch.3) Soft start (Ch.4) Error amplifier inverted input (Ch.4) Error amplifier output (Ch.4) (Ch.4) side control output (Ch.4 High side control output (Ch.4 Power supply (for ch.4 output circuit) Feedback (Ch.3) (Ch.3) External gate control (Ch.3) Power supply (Ch.3) External gate control (Ch.2 reverse current protection) Feedback (Ch.2) (Ch.2 External gate control (Ch.2) Power supply (Ch.2) (Ch.1) side control output (Ch.1) High side control output (Ch.1) Power supply (for ch.1 output circuit)
SDF00034AEB
Function
Publication data: November 2002
AN32502A
Descriptions (continued)
name FBR1 FBC1 FBD1 VREFDET1 REGOUT BACKUP VREFDET2 PWR_EN DATA VDD1 TRIG nRESETOUT WAKEUP Feedback (Ch.1) Error amplifier output (Ch.1) Error amplifier inverted input (Ch.1) Soft start (Ch.1) External gate control (Ch.5) Feedback (Ch.5) Start control (Ch.5) General purpose output General purpose output General purpose output General purpose output General purpose output Reference voltage filter Power supply (control signal system) Feedback backup charging regulator Output backup regulator Power supply (backup) Through output boost DC-DC backup Through intput boost DC-DC backup Control boost DC-DC backup Reference voltage filter (for backup circuit) Start control input On/off control (Ch.2) On/off control (Ch.3) On/off control (Ch.4) Serial data input Serial clock input Power supply (input/ output) System switch External reset signal input I2C/ hard priority setting Interruption signal
SDF00034AEB
Function
Publication data: November 2002
AN32502A
Technical Data
Circuit diagrams input/ output part function descriptions
Note) characteristics listed below reference values based design guaranteed.
name TRIG (Pin
Function connect power supply voltage (VB).
Inner circuit
nRESETOUT (Pin
External reset signal input: High: (reset) CMOS input
(Pin
On/off switch ch.1: High: VDD1 CMOS input
VDD1
VDD1
VDD1
(Pin
On/off switch ch.2: High: Pulled down resistor internally. setting leads determination which prioritize setting this serial setting.
(Pin
On/off switch ch.3 ch.4: High: VDD1 CMOS input Pulled down resistor internally setting leads determination which prioritize setting these pins serial setting.
VDD1
VDD1
VDD1
(Pin
Determining priority serial external setting ch.2, ch.3 ch.4 on/off. High: take priority over hard setting Hard settings take priority over CMOS input
Publication data: November 2002
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AN32502A
Technical Data (continued)
Circuit diagrams input/output part function descriptions (continued)
Note) characteristics listed below reference values based design guaranteed.
Name DATA (Pin
Function
Inner circuit
VDD1 VDD1 VDD1
data input CMOS input
(Pin
clock input CMOS input
VDD1
VDD1
VDD1
nRESET (Pin
Reset signal output active Pulled down internally
VDD1
VDD1
VDD1
nRESETOUT input
Internal RESET
Publication data: November 2002
SDF00034AEB
AN32502A
Technical Data (continued)
Circuit diagrams input/output part function descriptions (continued)
Note) characteristics listed below reference values based design guaranteed.
Name
Function Output judgment below-threshold voltage (Pin 45). Threshold level: active Pulled down internally
VDD1
Inner circuit
VDD1
BAT_FLT (Pin
VDD1
WAKEUP (Pin
Interrupt signal output mode High active Pulled down internally
VDD1
VDD1
VDD1
(Pin
General purpose output Initial setting: individual control data Output voltage (When output current mA.)
VDD1
VDD1
VDD1
Publication data: November 2002
SDF00034AEB
AN32502A
Technical Data (continued) command
address This IC's address `11100110'. address mark shows initial setting.
CORE_I setting High High change High Ch.2 mode High Ch.3 mode High Ch.4 mode High Ch.5 mode High
CORE
MODE
1=On
Real time Real time
Backup circuit
etc.
Don't input another data except shown this table. When address 01H, possible change output voltage ch.1 shown sequence chart (5). this case, setting data latched when PWR_EN signal changes high. real time mode
Publication data: November 2002
SDF00034AEB
AN32502A
Technical Data (continued)
Serial data transmission
Note) When line data transmitted, start/ stop condition required each time. When address same, repetition DATA allows upgrade settings serial order.
Example: When data four lines transmitted
address
address
Address
Address
Data
Data
Stop
Start
Data first line
Start
Data second line
address
Stop
address
Address
Address
Data
Start
Start
Data
Stop
Data third line
Data fourth line
Publication data: November 2002
SDF00034AEB
Stop
AN32502A
Technical Data (continued)
serial data timing Start condition stop condition
DATA
tBUF
tLOW
tHD: Stop condition Start condition
tSU:
Stop condition
Data recognition condition
Data line Stable state: data effective Data changeable
Data (Pin
tHIGH (Pin
tSU:
tHD:
Recommended operating condition Parameter Time must free before transmission start. Hold time start condition. After this period, first clock pulse generated. period clock. Rise time both lines. Set-up time stop condition. Set-up time data High period clock. Fall time both lines. Hold time data ICs. clock frequency. Symbol tBUF tHD: tLOW tSU: tSU: tHIGH tHD: fSCL 1000 Unit microsec microsec microsec microsec microsec microsec
Publication data: November 2002
SDF00034AEB
AN32502A
Technical Data (continued)
Backup circuit operation
case Ch.2 output
case BACKUP
RGC2
Backup battery
Coin battery detection
Regulator coin battery
Boost DC-DC control
Powered from coin battery
Coin battery detection circuit monitors voltage. When becomes equal less than make switch boost DC-DC converter off.
prevent over-discharge backup battery.)
Output voltage regulator freely between when through adjustment
feedback voltage
Boost DC-DC converter output internally.
Switching ch.2 exercised intra-judging circuit.
Publication data: November 2002
SDF00034AEB
AN32502A
Technical Data (continued)
Backup circuit charging flow
START
DC-DC converter operate
MOSSW (between 51): RGC2:
Coin battery setting: DC-DC converter stop
Charging circuit operate
RGC2: High
Stop charging circuit
Publication data: November 2002
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AN32502A
Technical Data (continued) 6-1. Sequence chart
Power sequence
About Ch.2 PWR_EN
Ch.1
BAT_FLT nRESET
Power reset operation depend about Ch.2 start from this timing after operation.
Power sequence
Ch.1 Ch.5
Output BAT_FLT nRESET
Note) Power supply input/output part supplied from VDD, fall down same time VDD.
Publication data: November 2002
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AN32502A
Technical Data (continued)
6-2. Sequence chart channel operating sequence
3.525 Operating voltage
3.525
About
(Internal reset: initialize)
BAT_FLT
nRESET
(On) fixed
Ch.2 output Coin battery charging circuit Charging circuit operating Charging circuit operating
Operate command
command receipted after VDD1 rise Coin battery voltage 2.2V DC-DC operate DC-DC operate
(Backup DC-DC) Ch.2 output (VDD1) Pulled (PWE_EN)
Ch.1output
(High:
Ch.3/ Ch.4 output
Ch.5
Operate command
Note) When power supply turns ch.2 output charging circuit keep mode until battery voltage (VB) goes 3.525 even though command receipted after power reset operation.
Publication data: November 2002 SDF00034AEB
AN32502A
Technical Data (continued)
6-3. Sequence chart battery detection sequence
Internal
VBAT
BAT_FLT
VBAT
nRESET
VBAT
Ch.1
Output
Ch.2 Output Ch.3
Output
Ch.4
Output
Ch.5
Output
Coin battery voltage
Backup boost output
Coin battery charging circuit
Output
BAT_FLT output changes high when battery voltage becomes over 3.525 When RESET button pressed, make RESET PMIC output only low. Each power supply should kept same.
Publication data: November 2002
SDF00034AEB
AN32502A
Technical Data (continued)
6-4. Sequence chart Ch.1 Sequence case switching ch.1 output voltage (Non real time mode) setting serial data allows judgment which switching mode taken, CORE_I voltage normal on/off.
(I2C) data (I2C) PWR_EN
1010100
1000000 High
Ch.1 data
1000000
1010100
Ch.1 output voltage
µsec
WAKEUP output
µsec waiting time controlled using internal oscillator (500 kHz), counter after PWR_EN changes high low,
wakeup changes high.
Internal resister hold final data.
want operate voltage switching mode normal on/off setting, need sending data.
Publication data: November 2002
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AN32502A
Technical Data (continued)
6-5. Sequence chart PMIC start
START Hard setting take priority over initial setting High Initial setting take priority over hard setting
Ch.2 start
High
High
High
voltage High
Wait control signal from CPU.
Ch.1 start
Ch.2 start
Ch.3 start
Ch.4 start
Hard setting table
Note) Ch.2 only turns with initial setting, when start prioritized. Ch.5 controlled only command. Initial setting:
Ch.1 Ch.2 Ch.3 Ch.4 High High High
High
Publication data: November 2002
SDF00034AEB
AN32502A
Technical Data (continued)
6-6. Sequence chart
nRESETOUT input
nRESET:
When becomes eqaul more than (Internal reset: High)
nRESET: output (for 50msec)
nRESET: return high
nRESET: Each outputs keep current conditions only output.
6-7. Sequence chart operation Output setting change high
DATA
Delay time Equal less than nsec
High
Delay output setting change high same.
Publication data: November 2002
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AN32502A
Technical Data (continued)
7-1. Voltage setting VREF each listed below. VREF (reference value) Ch.1 1.08
Ch.2, Ch.3, Ch.5
Ch.4
1.07
When changing output voltage, find resistance ratio ensuring that feedback voltages become these values.
Example: Ch.3
Ch.3OUT AN32502A
Ch.3OUT VREF
Note) This VREF (reference value) value case design.
Publication data: November 2002
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AN32502A
Technical Data (continued)
7-2. Voltage setting Ch.1 voltage setting from Ch.1 voltage setting possible with 7-bit DAC. Address Ch.1 output voltage Ch.1 VREF (reference value) 0.83
0.92
1.08
Refer sheet No.17 serial setting list. Refer sheet No.25 ch.1 voltage change procedure. These values based premise that feedback resistance values ch.1 identical with ones described block diagram. When this resistance ratio differs, above-listed setting values vary.
Note) This VREF (reference value) value case design.
Power dissipation package HQFN064-P-0808 With radiation board soldered, there other patterns than ones connected from each lands outer PCB. With radiation board soldered, another pattern added rear side
3.500 Mounted standard board(grass epoxy 50mm 50mm With radiation board soldering Rth(j-a) 41.2°C/W Mounted standard board (grass epoxy 50mm 50mm 0.8mm) With radiation board soldering Rth(j-a) 66.7°C/W
3.000
Power dissipation
2.500
2.427
2.000
1.500
1.499
1.000 0.460 Package itself Rth(j-a) 217.1°C/W
0.500
0.000
Ambient temperature (°C)
Publication data: November 2002
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AN32502A
Package schematics (Unit: HQFN064-P-0808
8.20 0.10 (8.00) 8.00 0.10 (1.10) 4-C0.50
0.20 0.10
0.85max
0.10 0.60 0.10 (1.10) (7.00) 2.00) (Depth 0.07) (4.00)
Seating plane
(0.65) (0.65) 0.16 0.06 0.08
(3.35)
(3.35) Area resin flash
0.40
(4.00)
(8.00)
Publication data: November 2002
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AN32502A
Application Notes
Overview This power management developed Intel PXA250/ features follows: single chip onto which integrate ch.2 DC-DC converter, ch.3 interface circuit PXA250/210 Charging circuit backup battery, boost DC-DC converter back-up switch built Built-in ch.5 general-use output input/2 outputs analog switch built high efficient synchronous rectifier circuit employed DC-DC converter. Power supply PXA250/ core controlled software (I2C interface). (Intel Reference Number: 278530-001 Core voltage changing sequence described document available.) Small-size high leadless package adopted (HQFN-64) Function overview Ch.1 (Step-down DC-DC converter core) Output voltage range: with (I2C) Synchronous rectifier type Maximum current Operating frequency: Ch.4 (Step-down DC-DC converter) Output voltage range: Synchronous rectifier type 100% duty operation guaranteed Maximum current Operating frequency: Ch.2, Ch.3, Ch.5 (LDO) Output voltage range: Maximum current
Note) Maximum current conforms test circuit condition described specification.
DC-DC converter backup (Boost circuit) Output voltage: Output current: (typical) (maximum) Built-in output switch (Automatic on/off main power supply) Built-in charger circuit backup battery built Input/ output-related items Input interface Output PWR_EN TRIG External reset input Analog switch input
nRESET BAT_FLT WAKEUP General purpose output (Ch.5 control) Analog switch output
Publication data: November 2002
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AN32502A
Application Notes (continued)
System block diagram block diagram this shown figure Output-stage MOSFETs ch.1 ch.5 externally nature general purpose. Output current each channel typical value evaluation board. Therefore, select external MOSFET meet conditions needed application. Output voltages ch.2 ch.5 available range more with constant setting external feedback circuit.
Ch.1 Control Logic Protection circuit Battery adapter Ch.3 Li-IOn 0.85 Buck converter Ch.2
Buck converter
Ch.4 Ch.5 Backup 500mA
Backup battery charging circuit
Boost General purpose Analog switch outputs
Coin battery
Figure
Output voltage setting Output voltage each channel determined following equation. VREF internal reference voltage differs from every each channel differs values. Refer table Ch.1 reference voltage controlled DAC. 1.08 initial setting value (DAC data `1010100'). reference voltage with 8.36 step range 0.38 1.45 Output voltage change multiplied (R1+R2)/R2. example, when output output able adjusted step about VREF
Publication data: November 2002
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AN32502A
Application Notes (continued)
Output voltage setting (continued)
VREF
Table VREF Ch.1 Ch.2, Ch.3, Ch.5 Ch.4 1.08 1.07
AN32502A
Figure On/off control
Ch.1 controlled hard (Pin only. Ch.2, ch.3 ch.4 controlled both hard command.
(Pin setting allows which prioritize. High: take priority over hard pin. Low: Hard priority over Ch.5 controlled only. Initial setting time applying supply voltage turns off. Table control Ch.1 Ch.2 Ch.3 Ch.4 Ch.5 control
Publication data: November 2002
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AN32502A
Application Notes (continued)
Explanation operation Ch.1
comparator PGND1 FBR1 VREFH 1.95 Error amplifier Output stage R103 Buffer OUTPUT
7bit
SSWC R101 R102 335k 640k
SGND
Figure Ch.1 step-down DC-DC converter. Figure shows internal block configuration. Output setting Built-in 7-bit converter, allows reference voltage step about 8.36 comparison between this reference voltage FBR1 input voltage, feedback control functions. Therefore, output voltage determined following equation: VOUT VREF
VREF 1.08 initial setting. (DAC data `1010100') voltage variable range 0.38 1.45 allowing setting with 8.36 step (value case design). Refer figure linearity DAC. When high precision required output voltage, high precision resistor R12, respectively. influenced absolute precision, relative precision. Therefore, when using resistor ±0.5% precision resistor, output voltage varies maximum ±1%. comparison block comparator controls period output pulse depending input voltage. output voltage "High" power N-channel output while triangular wave oscillation voltage lower than (SS1) (error amplifier output) voltages. Maximum duty determined maximum voltage triangular oscillation voltage (SS1). This about 88%. Insertion capacitor between allows soft start operation enabling gradual elongation period output pulse making overshoot undershoot smaller time startup. constant soft start determined internal R101 external capacitor
Publication data: November 2002
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AN32502A
Application Notes (continued)
Explanation operation (continued) Ch.1 (continued) Output voltage Output voltage from applied with dead time nsec that simultaneous cause through-current flow. Refer figure timing.
output
output
nsec
nsec
Figure Error amplifier Error amplifier response characteristics determined feedback built-in R103 between R13: C11: 0.01 recommended above actual pattern layout, recommended make lines short possible reduce effect noise. On/off control Ch.1 controlled only Control serial data unavailable. Power supply Power supplied from (VB2) only output drive stage from (VB1) other parts. connected (PGND1) only output drive stage. Other parts connected signal system (SGND). Connect source, anode, C13GND with thick wires near possible. Peripheral parts characteristics output capacitor effect output transient response characteristics. recommended high capacitor like SPCAP. also recommended select constant inductor supply voltage range this (2.8 considering efficiency degradation caused size resistance.
Publication data: November 2002
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AN32502A
Application Notes (continued)
Explanation operation (continued) Ch.1 (continued) linearity (Ch.1)
12.0
11.5
11.0
Delta output voltage
10.5
10.0
Measure conditions: data Output voltage: setting data `1010100' 100d 120d 140d
Figure Soft start timing chart
Supply voltage (VB) internal oscillation output min. voltage Output voltage min.
gate voltage
Figure Oscillation frequency internal oscillation circuit determined capacitor between resistor between GND. Oscillation frequency capacitor resistor (estimated constant).
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AN32502A
Application Notes (continued)
Explanation operation (continued) Ch.2
R201 Gate control VREF R202
RGC2
PGND2 FBR2
Figure Ch.2 linear regulator. Figure shows ch.2 internal block configuration. runs feedback control comparing internal VREF with voltage. Output voltage determined following equation. Vout R21+R22 VREF
Internal VREF Ch.2 intended used memory circuit automatically switched backup power supply circuit when supply voltage lowered. (When gets below ch.2 off, backup power supply circuit on.) functions switch that would prevent current from reverse-flowing from output source when switching backup power supply circuit. When power supply voltage (VB1) equal less than gate control signal becomes "High" gate voltage becomes equal backup supply voltage. (3.1 switched off. Simultaneously, backup power supply circuit actuated keep output voltage constant level. This switching response time determined gate capacitance R201. Output voltage likely drop switching time depending main power supply conditions. this case, connect resistor between pins that R201 resistance kept small equivalently response time able kept short. Rush current power supply input This regulator built-in circuit limiting rush current power supply input. Insertion capacitor between (PR2) allows control rush current approx. supply voltage: On/off control This regulator able on/off control with serial data
Publication data: November 2002
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AN32502A
Application Notes (continued)
Explanation operation (continued) Ch.2 (continued) Power supply Power supply this regulator (VB3) (PGND2). VREF block constituted SGND.
Ch.3
VREF (1.0
PGND3 FBR3
Figure Ch.3 linear regulator circuit that configured identically with ch.2 except backup switching circuit. Figure shows internal block configuration ch.3. Output voltage determined following equation. Vout VREF
Internal VREF External capacitor intended control rush current power supply. On/off control This regulator able on/off control with serial data Power source Power supply this regulator (VB4) (PGND3). VREF block constituted SGND.
Publication data: November 2002
SDF00034AEB
AN32502A
Application Notes (continued)
Explanation operation (continued) Ch.4
VREF 1.07V VREFH 1.95V PGND4 SSWC R401 166K
R402
Figure Ch.4 step-down DC-DC converter synchronous rectifying type. Figure shows internal block configuration ch.4. Output voltage determined following equation. Vout VREF
VREF 1.07 initially. When high precision required output voltage, high precision resistor R42, respectively. influenced absolute precision, relative precision. Therefore, when using resistor ±0.5% precision resistor, output voltage varies maximum ±1%. comparison block comparator controls period output pulse depending input voltage. output voltage "High" power N-channel output while triangular wave oscillation voltage lower than (SS4) (error amplifier output) voltages. This circuit able operation maximum duty 100%. Insertion capacitor between allows soft start operation gradually widening period output pulse startup time that overshoot undershoot startup time. constant time soft start determined internal R401 external capacitor additional components improve transient response characteristics coming when load current suddenly changed. condition this test board, control output voltage sudden load change (changing time µsec) controlled approximately
SGND
Publication data: November 2002
SDF00034AEB
AN32502A
Application Notes (continued)
Explanation operation (continued) Ch.4 (continued) Output voltage Output voltage from applied with dead time nsec that simultaneous cause through-current flow. Refer figure timing.
output
output
nsec
nsec
Figure
On/off control Ch.4 able on/off control serial data. Power supply voltage Power supplied from (VB5) only output drive stage from (VB1) other parts. connected from (PGND4) only output drive stage. Other parts connected signal system (SGND). source, anode C42GND side should connected with wire near possible. Peripheral parts characteristics output capacitor effect output transient response characteristics. recommended high capacitor like SPCAP. also recommended select constant inductor supply voltage range this (2.8 considering efficiency degradation caused size resistance.
Publication data: November 2002
SDF00034AEB
AN32502A
Application Notes (continued)
Explanation operation (continued) Ch.5
VREF 1.0V
FBC1 SGND FBD1
Figure Ch.5 linear regulator circuit that configured identically with ch.2 except backup switching circuit. Figure shows internal block configuration ch.5. Output voltage determined following equation. Vout VREF
Internal VREF External capacitor intended control rush current power supply. On/off control This regulator capable on/off control only with serial data. Initial setting turns startup. Supply voltage Power supply this regulator (VB1) (SGND). VREF block constituted SGND.
Publication data: November 2002
SDF00034AEB
AN32502A
Application Notes (continued)
Backup charging current
VREF
REGOUT
Backup battery
SGND
Figure Figure shows configuration backup battery charging circuit. circuit configuration identical with general linear regulator continues supply charging current until backup battery voltage reaches voltage value shown following equation that balancing condition regulator circuit. Backup voltage VREF
Internal VREF lithium coin battery, above voltage Determine value according battery used, exceed maximum charging current specified. This circuit automatically switched main battery voltage (Pin VB1) becomes equal less than Then, backup boost circuit starts operating. This circuit able setting on/off with serial data. Initial setting turns startup. Power supply this circuit supplied from (VB1).
Publication data: November 2002
SDF00034AEB
AN32502A
Application Notes (continued)
Backup boost converter
BACKUP
VREF
(100 kHz)
CLRQ
switch Ch.2
SGND
FBR2
Ch.2 feedback
Figure backup boost circuit boost circuit burst mode operation. Figure shows internal block configuration. When main battery voltage becomes equal less than this circuit starts operating. Simultaneously, internal switch between becomes this boost circuit output supplied load circuit (memory circuit) behalf ch.2 regulator. internal oscillation circuit starts operating when output voltage becomes below side detection threshold equal less than stops operation when output voltage becomes above high side detection threshold equal more than load current constant, output voltage goes down linearly. when reaches above-stated side detection voltage, oscillating circuit operates again starts charging output capacitor. stops operation when output voltage equal less than Then halting operation when output voltage reaches output wave form this circuit becomes triangular wave variable between thresholds actual wave form, refer figure figure high side detection circuits able detect voltage comparing voltage with internal reference voltage. Since feedback ch.2, judging level varies according ch.2 output voltage setting. above-mentioned thresholds based output setting This circuit automatically becomes when backup battery voltage equal less than prevent backup battery from being over-discharged. On/off control circuit automatically operates when main supply voltage (VB) equal less than backup battery output voltage equal more than Power supply circuit blocks supplied from (backup) GND.
Publication data: November 2002 SDF00034AEB
AN32502A
Application Notes (continued)
Backup boost converter (continued)
Backup boost converter output waveform
Change timing
3.2V Ch.2 output
voltage
nRESET output
voltage
Figure
Switching burst area.
output voltage waveform
output current waveform
Figure
Publication data: November 2002 SDF00034AEB
AN32502A
Application Notes (continued)
General purpose (GPO0 GP05)
Change VDD1 Internal logic Level shift VDD1
LGND
Figure This equipped with 5-system general purpose output pins. Figure shows circuit configuration. output CMOS mode. Initial setting startup every outputs high/ settings carried control. characteristics output MOSFET become output voltage able applied on/off switch external circuits driving LED. care should taken voltage loss above-mentioned resistance output MOSFET actual application. Power supply Power supply voltage this regulator (VDD1) (LGND). Internal logic block preceding level shift SGND.
Analog switch (VO1, VO2)
Control logic
voltage regulator input
output
output
Figure This built-in analog switch input outputs. This input outputs. Figure shows circuit configuration. size between same between P-channel MOSFET connected between between used switch logic control gate. Suppose have supply same stabilized supply voltage both circuit blocks. this analog switch halt block save power while block operating. Initial setting power turns both on/off setting able done control. resistance switching about Care should taken this influence current load fluctuation.
Publication data: November 2002
SDF00034AEB

AN32502A Power Management Intel PXA250 Application Processor

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