Embedded Processor ADSP-TS101S BENEFITS Provides High Performance
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FEATURES MHz, Instruction Cycle Rate Bits Internal-On-Chip-SRAM Memory (484-Ball) (625-Ball) PBGA Package Dual Computation Blocks-Each Containing ALU, Multiplier, Shifter, Register File Dual Integer ALUs, Providing Data Addressing Pointer Manipulation Integrated Includes Channel Controller, External Port, Four Link Ports, SDRAM Controller, Programmable Flag Pins, Timers, Timer Expired System Integration 1149.1 IEEE Compliant JTAG Test Access Port On-Chip Emulation On-Chip Arbitration Glueless Multiprocessing with Eight TigerSHARC Processors
Embedded Processor ADSP-TS101S
BENEFITS Provides High Performance Static Superscalar Operations, Optimized Telecommunications Infrastructure Other Large, Demanding Multiprocessor Applications Performs Exceptionally Well Algorithm Benchmarks (See Benchmarks Table Table Supports Overhead Transfers Between Internal Memory, External Memory, Memory-Mapped Peripherals, Link Ports, Host Processors, Other (Multiprocessor) DSPs Eases Programming Through Extremely Flexible Instruction High Level Language Friendly Architecture Enables Scalable Multiprocessing Systems with Communications Overhead
FUNCTIONAL BLOCK DIAGRAM
COMPUTATIONAL BLOCKS SHIFTER
PROGRAM SEQUENCER
DATA ADDRESS GENERATION INTEGER 32x32 INTEGER 32x32
INTERNAL MEMORY MEMORY 64Kx32 MEMORY 64Kx32 MEMORY 64Kx32 JTAG PORT
MULTIPLIER
ADDR FETCH
SDRAM CONTROLLER
REGISTER FILE 32x32
ADDR DATA
EXTERNAL PORT MULTIPROCESSOR INTERFACE HOST INTERFACE
ADDR DATA INPUT FIFO
ADDR DATA
OUTPUT BUFFER ADDR OUTPUT FIFO DATA ADDRESS PROCESSOR CONTROLLER ADDRESS CONTROL/ STATUS/ TCBs DATA LINK PORT CONTROLLER LINK PORTS CONTROL/ STATUS/ BUFFERS CLUSTER ARBITER
CNTRL
REGISTER FILE 32x32 MULTIPLIER
LINK DATA
SHIFTER
TigerSHARC TigerSHARC logo registered trademarks Analog Devices, Inc.
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ADSP-TS101S
TABLE CONTENTS GENERAL DESCRIPTION
GENERAL DESCRIPTION Dual Compute Blocks Data Alignment Buffer (DAB) Dual Integer ALUs (IALUs) Program Sequencer Interrupt Controller Flexible Instruction On-Chip SRAM Memory External Port (Off-Chip Memory/Peripherals Interface) Host Interface Multiprocessor Interface SDRAM Controller EPROM Interface Controller Link Ports Timer General-Purpose Reset Booting Power Operation Clock Domains Output Drive Strength Control Power Supplies Filtering Reference Voltage Clocks Development Tools Designing Emulator-Compatible Board (Target) Additional Information FUNCTION DESCRIPTIONS States Reset Definitions STRAP FUNCTION DESCRIPTIONS SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS SENSITIVITY TIMING SPECIFICATIONS General Timing Link Ports Data Transfer Token Switch Timing Output Drive Currents Test Conditions Output Disable Time Output Enable Time Capacitive Loading Environmental Conditions Thermal Characteristics 484-BALL PBGA CONFIGURATIONS 625-BALL PBGA CONFIGURATIONS OUTLINE DIMENSIONS ORDERING GUIDE Revision History
ADSP-TS101S TigerSHARC processor ultra high performance, static superscalar processor optimized large signal processing tasks communications infrastructure. combines very wide memory widths with dual computation blocks-supporting 40-bit floating-point 16-, 32-, 64-bit fixed-point processing-to standard performance digital signal processors. TigerSHARC processor's static superscalar architecture lets processor execute four instructions each cycle, performing twenty-four 16-bit fixed-point operations floating-point operations. Three independent 128-bit wide internal data buses, each connecting three memory banks, enable quad word data, instruction, accesses provide 14.4G bytes second internal memory bandwidth. Operating MHz, ADSP-TS101S processor's core instruction cycle time. Using Single-Instruction, Multiple-Data (SIMD) features, ADSP-TS101S perform billion 40-bit MACs million 80-bit MACs second. Table Table show DSP's performance benchmarks.
Table General-Purpose Algorithm Benchmarks Benchmark Speed Clock Cycles
32-bit Algorithm, million MACs/s peak performance 1024 Point Complex (Radix 32.78 9,835 50-tap 1024 input 91.67 27,500 Single 1.83 0.55 16-bit Algorithm, billion MACs/s peak performance Point Complex (Radix 3.67 1,100 50-tap 1024 input 24.0 7,200 Single 0.47 0.14 Single Complex 0.57 Transfer Rate External port 800M bytes/s Link ports (each) 250M bytes/s n/Table Wireless Algorithm Benchmarks Benchmark Execution (MIPS)1
Turbo Decode MIPS kbps Data Channel 0.86 MIPS Viterbi Decode 12.2 kbps AMR2 Voice Channel 0.27 MIPS Complex Correlation 3.84 Mcps3 with Spreading Factor
Execution Speed Instruction Cycles Second. Adaptive Multi Rate (AMR) Megachips second (Mcps)
ADSP-TS101S code compatible with other TigerSHARC processors. REV.
ADSP-TS101S
Functional Block Diagram Page shows ADSPTS101S processor's architectural blocks. These blocks include: Dual compute blocks, each consisting ALU, multiplier, 64-bit shifter, 32-word register file associated Data Alignment Buffers (DABs) Dual integer ALUs (IALUs), each with 31-word register file data addressing program sequencer with Instruction Alignment Buffer (IAB), Branch Target Buffer (BTB), interrupt controller Three 128-bit internal data buses, each connecting three memory banks On-chip SRAM bit) external port that provides interface host processors, multiprocessing space (DSPs), off-chip memory mapped peripherals, external SRAM SDRAM 14-channel controller Four link ports 64-bit interval timers timer expired 1149.1 IEEE compliant JTAG test access port on-chip emulation Figure shows typical single processor system with external SDRAM. Figure Page shows typical multiprocessor system.
ADSP-TS101S
LCLK_P CLOCK REFERENCE SCLK_P S/LCLK_N VREF BRST LCLKRAT2-0 SCLKFREQ ADDR31-0 IRQ3-0 FLAG3-0 ID2-0 MSSD LDQM HDQM SDWE SDCKE SDA10 FLYBY IOEN LINK DEVICES MAX) (OPTIONAL) LXDAT7-0 LXCLKIN LXCLKOUT LXDIR TMR0E BUSLOCK CONTROLIMP2-0 DS2-0 RESET JTAG BR7-0 BOFF DMAR3-0
DEVICE (OPTIONAL) HOST PROCESSOR INTERFACE (OPTIONAL) BOOT EPROM (OPTIONAL)
TigerSHARC processor uses Static Superscalararchitecture. This architecture superscalar that ADSPTS101S processor's core execute simultaneously from four 32-bit instructions encoded Very Large Instruction Word (VLIW) instruction line using DSP's dual compute blocks. Because does perform instruction reordering runtime-the programmer selects which operations will execute parallel prior runtime-the order instructions static. With exceptions, instruction line, whether contains one, two, three, four 32-bit instructions, executes with throughput cycle eight-deep processor pipeline. optimal program execution, programmers must follow DSP's instruction parallelism rules when encoding instruction line. general, selection instructions that execute parallel each cycle depends instruction line resources each instruction requires source destination registers used instructions. programmer direct control three core components-the IALUs, compute blocks, program sequencer. ADSP-TS101S, most cases, two-cycle arithmetic execution pipeline that fully interlocked, whenever computation result unavailable another operation dependent automatically inserts more stall cycles needed. Efficient programming with dependency-free instructions eliminate most computational memory transfer data dependencies. addition, ADSP-TS101S supports SIMD operations ways-SIMD compute blocks SIMD computations.The programmer direct both compute blocks operate same data (broadcast distribution) different data (merged distribution). addition, each compute block execute four 16-bit eight 8-bit SIMD computations parallel.
Dual Compute Blocks
ADDR DATA
MEMORY (OPTIONAL)
ADDR DATA
SDRAM MEMORY (OPTIONAL)
DATA63-0 WRH/WRL MS1-0
ADDR DATA
ADSP-TS101S compute blocks that execute computations either independently together SIMD engine. issue compute instructions compute block each cycle, instructing ALU, multiplier, shifter perform independent, simultaneous operations. compute blocks referred assembly syntax, each block contains three computational units-an ALU, multiplier, 64-bit shifter-and 32-word register file. Register File-Each compute block multiported 32-word, fully orthogonal register file used transferring data between computation units data buses storing intermediate results. Instructions access registers register file individually (word aligned), sets (dual aligned) four (quad aligned). ALU-The performs standard arithmetic operations both fixed- floating-point formats. also performs logic operations. Multiplier-The multiplier performs both fixed- floating-point multiplication fixed-point multiply accumulate.
ADDR DATA
DATA
CONTROL
ADDRESS
Figure Single Processor System with External SDRAM
Static Superscalar trademark Analog Devices, Inc.
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DATA
ADSP-TS101S
Shifter-The 64-bit shifter performs logical arithmetic shifts, stream manipulation, field deposit extraction operations. Accelerator-128-bit unit Trellis Decoding (for example, Viterbi Turbo decoders) complex correlations communication applications. Using these features, compute blocks can: Provide MACs cycle peak MACs cycle sustained 16-bit performance provide MACs cycle peak MACs cycle sustained 32-bit performance (based FIR) Execute single precision floating-point execute twenty-four 16-bit fixed-point operations cycle, providing 1800 MFLOPS GOPS performance Perform complex 16-bit MACs cycle Execute eight Trellis butterflies cycle
Data Alignment Buffer (DAB) Program Sequencer
ADSP-TS101S processor's program sequencer supports: fully interruptible programming model with flexible programming assembly C/C++ languages; handles hardware interrupts with high throughput aborted instruction cycles. eight-cycle instruction pipeline-three-cycle fetch pipe five-cycle execution pipe-with computation results available cycles after operands available. supply instruction fetch memory addresses; sequencer's Instruction Alignment Buffer (IAB) caches five fetched instruction lines waiting execute; program sequencer extracts instruction line from distributes appropriate core component execution. management program structures determination program flow according JUMP, CALL, RTI, instructions, loop structures, conditions, interrupts, software exceptions. Branch prediction 128-entry branch target buffer (BTB) reduce branch delays efficient execution conditional unconditional branch instructions zero-overhead looping; correctly predicted branches that taken occur with zero-to-two overhead cycles, overcoming three-to-six stage branch penalty. Compact code without requirement align code memory; handles alignment.
Interrupt Controller
quad word FIFO that enables loading quad word data from nonaligned addresses. Normally, load instructions must aligned their data size that quad words loaded from quad aligned address. Using significantly improves efficiency some applications, such filters.
Dual Integer ALUs (IALUs)
ADSP-TS101S IALUs that provide powerful address generation capabilities perform many generalpurpose integer operations. Each IALUs: Provides memory addresses data update pointers Supports circular buffering bit-reverse addressing Performs general-purpose integer operations, increasing programming flexibility Includes 31-word register file each IALU address generators, IALUs perform immediate indirect (pre- post-modify) addressing. They perform modulus bit-reverse operations with constraints placed memory addresses modulus data buffer placement. Each IALU specify either single, dual, quad word access from memory. IALUs have hardware support circular buffers, reverse, zero-overhead looping. Circular buffers facilitate efficient programming delay lines other data structures required digital signal processing, they commonly used digital filters Fourier transforms. Each IALU provides registers four circular buffers, applications total eight circular buffers. IALUs handle address pointer wraparound automatically, reducing overhead, increasing performance, simplifying implementation. Circular buffers start memory location. Because IALU's computational pipeline cycle deep, most cases integer results available next cycle. Hardware (register dependency check) causes stall result unavailable given cycle.
supports nested non-nested interrupts. Each interrupt type register interrupt vector table. Also, each both interrupt latch register interrupt mask register. interrupts fixed either level sensitive edge sensitive, except IRQ3-0 hardware interrupts, which programmable. distinguishes between hardware interrupts software exceptions, handling them differently. When software exception occurs, aborts other instructions instruction pipe. When hardware interrupt occurs, continues execute instructions already instruction pipe.
Flexible Instruction
128-bit instruction line, which contain four 32-bit instructions, accommodates variety parallel operations concise programming. example, instruction line direct conditionally execute multiply, add, subtract both computation blocks while also branches another location program. Some features instruction include: Enhanced instructions communications infrastructure govern Trellis Decoding (for example, Viterbi Turbo decoders) Despreading complex correlations Algebraic assembly language syntax Direct support DSP, imaging, video arithmetic types, eliminating hardware modes REV.
ADSP-TS101S
Branch prediction encoded instruction, enables zerooverhead loops Parallelism encoded instruction line Conditional execution optional instructions User-defined, programmable partitioning between program data memory
On-Chip SRAM Memory
external port supports pipelined, slow, SDRAM protocols. Addressing external memory devices memory mapped peripherals facilitated on-chip decoding high order address lines generate memory bank select signals. ADSP-TS101S provides programmable memory, pipeline depth, idle cycle synchronous accesses, external acknowledge controls support interfacing pipelined slow devices, host processors, other memory-mapped peripherals with variable access, hold, disable time requirements.
Host Interface
ADSP-TS101S bits on-chip SRAM memory, divided into three blocks bits (64K words bits). Each block-M0, M2-can store program, data, both, applications configure memory suit specific needs. Placing program instructions data different memory blocks, however, enables access data while performing instruction fetch. DSP's internal external memory (Figure organized into unified memory map, which defines location (address) elements system. memory divided into four memory areas-host space, external memory, multiprocessor space, internal memory- each memory space, except host memory, subdivided into smaller memory spaces. Each internal memory block connects 128-bit wide internal buses-block MD0, block MD1, block MD2-enabling perform three memory transfers same cycle. DSP's internal architecture provides total memory bandwidth 14.4G bytes second, enabling core access eight 32-bit data words (256 bits) four 32-bit instructions each cycle. DSP's flexible memory structure enables: core access different memory blocks same cycle core access three memory blocks parallel- instruction data accesses Programmable partitioning program data memory Program access memory 32-, 64-, 128-bit words-16-bit words with Complete context switch less than cycles
External Port (Off-Chip Memory/Peripherals Interface)
ADSP-TS101S provides easy configurable interface between external host processors through external port. accommodate variety host processors, host interface supports pipelined slow protocols accesses host slave. Each protocol programmable transmission parameters, such idle cycles, pipe depth, internal wait cycles. host interface supports burst transactions initiated host processor. After host issues starting address burst asserts BRST signal, increments address internally while host continues assert BRST. host interface provides deadlock recovery mechanism that enables host recover from deadlock situations involving DSP. BOFF signal provides deadlock recovery mechanism. When host asserts BOFF, backs current transaction asserts relinquishes external bus. host directly read write internal memory ADSP-TS101S, access most registers, including control (TCB) registers. Vector interrupts support efficient execution host commands.
Multiprocessor Interface
ADSP-TS101S offers powerful features tailored multiprocessing systems through external port link ports. This multiprocessing capability provides highest bandwidth interprocessor communication, including: eight DSPs common On-chip arbitration glueless multiprocessing Link ports point-to-point communication external port link ports provide integrated, glueless multiprocessing support. external port supports unified address space (see Figure that enables direct interprocessor accesses each ADSPTS101S processor's internal memory registers. DSP's on-chip distributed arbitration logic provides simple, glueless connection systems containing eight ADSP-TS101S processors host processor. arbitration rotating priority. lock supports indivisible read-modify-write sequences semaphores. fairness feature prevents from holding external long. DSP's four link ports provide second path interprocessor communications with throughput bytes second. cluster provides 800M bytes second throughput- with total 1.8G bytes second interprocessor bandwidth.
ADSP-TS101S processor's external port provides processor's interface off-chip memory peripherals. word address space included DSP's unified address space. separate on-chip buses-three 128-bit data buses three 32-bit address buses-are multiplexed external port create external system with single 64-bit data single 32-bit address bus. external port supports data transfer rates 800M bytes second over external bus. external configured 64-bit operation. When system configured 64-bit operation, lower bits external data connect even addresses, upper bits connect addresses.
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GLOBAL SPACE 0xFFFFFFFF
HOST (MSH)
INTERNAL SPACE 0x003FFFFF
EXTERNAL MEMORY SPACE
0x10000000 BANK (MS1) 0x0C000000 BANK (MS0) 0x08000000 SDRAM (MSSD) 0x04000000
MULTIPROCESSOR MEMORY SPACE
0x00300000
RESERVED
0x00280000
0x00200000 PROCESSOR PROCESSOR
0x03C00000 0x03800000 PROCESSOR 0x03400000 PROCESSOR 0x03000000 PROCESSOR 0x02C00000 PROCESSOR 0x02800000 PROCESSOR 0x02400000 PROCESSOR 0x02000000 BROADCAST 0x01C00000 EACH COPY INTERNAL SPACE
0x001807FF INTERNAL REGISTERS (UREGS) 0x00180000 RESERVED 0x0010FFFF INTERNAL MEMORY 0x00100000 RESERVED 0x0008FFFF INTERNAL MEMORY 0x00080000
RESERVED RESERVED 0x0000FFFF INTERNAL MEMORY 0x00000000 INTERNAL MEMORY 0x00000000 0x003FFFFF
Figure Memory SDRAM Controller
SDRAM controller controls ADSP-TS101S processor's transfers data from synchronous DRAM (SDRAM). throughput bits SCLK cycle using external port SDRAM control pins. SDRAM interface provides glueless interface with standard SDRAMs-16M bit, bit, 128M bit, 256M bit. directly supports maximum words SDRAM. SDRAM interface mapped external memory DSP's unified memory map.
EPROM Interface
read access. During booting, functions EPROM chip select signal. EPROM boot procedure uses channel which packs bytes into 32-bit instructions. Applications also access EPROM (write flash memories) during normal operation through DMA. EPROM Flash Memory interface mapped DSP's unified memory map. byte address space limited maximum bytes address bits). EPROM Flash Memory interface used after boot DMA.
Controller
ADSP-TS101S configured boot from external 8-bit EPROM reset through external port. automatic process (which follows reset) loads program from EPROM into internal memory. This process uses wait cycles each
ADSP-TS101S processor's on-chip controller, with channels, provides zero-overhead data transfers without processor intervention. controller operates independently invisibly DSP's core, enabling operations
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CONTROL ADDRESS ADDRESS
ADSP-TS101 ID2-0 RESET CLKS/REFS LINK BR7-2,0 ADDR31-0 DATA63-0 CONTROL
CONTROL
RESET
ID2-0 RESET CLKS/REFS
BR7-1 ADDR31-0 DATA63-0 WRH/L MS1-0 BUSLOCK
DATA
ADSP-TS101
DATA
ADSP-TS101 ADSP-TS101 ADSP-TS101 ADSP-TS101 ADSP-TS101 ADSP-TS101
ADDR DATA ADDR DATA GLOBAL MEMORY PERIPHERALS (OPTIONAL)
SCLK_P CLOCK REFERENCE VOLTAGE LCLK_P S/LCLK_N
VREF BOFF LCLKRAT2-0 DMAR3-0 SCLKFREQ BRST IRQ3-0 FLAG3-0 LINK FLYBY IOEN
BOOT EPROM (OPTIONAL)
CLOCK HOST PROCESSOR INTERFACE (OPTIONAL)
ADDR DATA ADDR DATA
LINK DEVICES MAX) (OPTIONAL)
LXDAT7-0 LXCLKIN LXCLKOUT LXDIR
MSSD LDQM HDQM SDWE SDCKE SDA10 CONTROL
SDRAM MEMORY (OPTIONAL)
TMR0E CONTROLIMP2-0 DS2-0
Figure Shared Memory Multiprocessing System
occur while DSP's core continues execute program instructions. controller performs transfers between: Internal memory external memory memorymapped peripherals Internal memory other DSPs common bus, host processor, link port External memory external peripherals link port External master internal memory link port controller provides number additional features.
controller supports Flyby transfers. Flyby operations only occur through external port (DMA channel involve DSP's core. controller acts conduit transfer data from external device another through external memory. During transaction, DSP: Relinquishes external data Outputs addresses, memory selects (MS1-0, MSSD, RAS, CAS, SDWE) FLYBY, IOEN, RD/WR strobes Responds chaining also supported controller. chaining operations enable applications automatically link transfer sequence another continuous transmission. sequences occur over different channels have different transmission attributes.
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ADSP-TS101S
controller also supports two-dimensional transfers. controller access transfer two-dimensional memory arrays transmit receive channel. These transfers implemented with index, count, modify registers both dimensions. controller performs following operations: External port block transfers. Four dedicated bidirectional channels transfer blocks data between DSP's internal memory external memory memory-mapped peripheral external bus. These transfers support master mode handshake mode protocols. Link port transfers. Eight dedicated channels (four transmit four receive) transfer quad word data only between link ports between link port internal external memory. These transfers only handshake mode protocol. priority rotates between four receive channels. AutoDMA transfers. dedicated unidirectional channels transfer data received from external master internal memory link port I/O. These transfers only slave mode protocol, external master must initiate transfer.
Link Ports
Under certain conditions, link port receiver initiate token switch reverse direction transfer; transmitter becomes receiver vice versa.
Timer General-Purpose
ADSP-TS101S timer (TMR0E) that generates output when programmed timer counter expired. Also, four programmable general-purpose pins (FLAG3-0) that function either single input output. outputs, these pins signal peripheral devices; inputs, they provide test conditional branching.
Reset Booting
ADSP-TS101S levels reset (see reset specifications Page 22): Power-up reset-After power-up system, strap options stable, RESET must asserted (low). Normal reset-For resets following power-up reset sequence, RESET must asserted. reset internally (core reset) setting SWRST SQCTL. core reset, external port I/O. After reset, ADSP-TS101S four boot options beginning operation: Boot from EPROM. defaults EPROM booting when strap option low. STRAP FUNCTION DESCRIPTIONS Page Boot external master (host another ADSPTS101S). master cluster boot ADSP-TS101S through writes internal memory through auto DMA. Boot link port. four receive link channels initialized after reset transfer 256-word block internal memory address 255, issue interrupt block (similar DMA). corresponding interrupts address zero (0). boot-Start running from external memory. Using boot' option, ADSP-TS101S must start running from external memory, caused asserting IRQ3-0 interrupt signals. ADSP-TS101S core always exits from reset idle state waits interrupt. Some interrupts interrupt vector table initialized enabled after reset.
Power Operation
DSP's four link ports provide additional 8-bit bidirectional capability. With ability operate double data rate- latching data both rising falling edges clock- running MHz, each link port support 250M bytes second, combined maximum throughput bytes second. link ports provide optional communications channel that useful multiprocessor systems implementing point point interprocessor communications. Applications also link ports booting. Each link port double-buffered input output registers. DSP's core write directly link port's transmit register read from receive register, controller perform transfers through eight (four transmit four receive) dedicated link port channels. Each link port three signals that control operation. LxCLKOUT LxCLKIN implement clock/acknowledge handshaking. LxDIR indicates direction transfer used only when buffering LxDAT signals. example application would using differential low-swing buffers long twisted-pair wires. LxDAT provides 8-bit data input/output. Applications program separate error detection mechanisms transmit receive operations (applications checksum mechanism implement consecutive link port transfers), size data packets, speed which bytes transmitted.
ADSP-TS101S enter power sleep mode which core does execute instructions, reducing power consumption minimum. ADSP-TS101S exits sleep mode when senses falling edge IRQ3-0 interrupt inputs. interrupt, enabled, causes ADSP-TS101S execute corresponding interrupt service routine. This feature useful systems that require power standby mode.
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Clock Domains
shown Figure ADSP-TS101S clock inputs, SCLK (system clock) LCLK (local clock), that drive major clock domains:
SCLK_P LCLK_P LCLKRATx BITS, LCTLx REGISTER EXTERNAL INTERFACE CCLK (INSTRUCTION RATE) LxCLKOUT/LxCLKIN (LINK PORT RATE)
stronger drive strengths useful high frequency switching while lower strengths allow relaxed design methodology. strongest drive strengths have larger di/dt thus require more attention signal integrity issues such ringing, reflections coupling. Also larger di/dt increase external supply rail noise, which impacts power supply power distribution design. drive strengths EMU, CPA, pins controllable fixed maximum level. drive strength calculation, Output Drive Currents Page
Power Supplies
Figure Clock Domains
SCLK (system clock). Provides clock input external interface defines specification reference external signals. external interface runs SCLK frequency. locks internal SCLK SCLK input. LCLK (local clock). Provides clock input internal clock driver, CCLK, which internal clock core, internal buses, memory, link ports. instruction execution rate equal CCLK. from LCLK generates CCLK which phase-locked. LCLKRAT pins define clock multiplication LCLK CCLK (see Table link port clock generated from CCLK software programmable divisor. RESET must asserted until LCLK stable within specification least This applies power-up well dynamic modification LCLK after power-up. Dynamic modification include LCLK going specification long RESET asserted. Connecting SCLK LCLK same clock source requirement device. Using integer clock multiplication value provides predictable cycle-by-cycle operation, requirement fault-tolerant systems some multiprocessing systems. Noninteger values completely functional acceptable applications that require predictable cycle-by-cycle operation.
Output Drive Strength Control
ADSP-TS101S separate power supply connections internal logic (VDD), analog circuits (VDD_A), buffer (VDD_IO) power supply. internal (VDD) analog (VDD_A) supplies must meet requirement. buffer (VDD_IO) supply must meet requirement. analog supply (VDD_A) powers clock generator PLLs. produce stable clock, systems must provide clean power supply power input VDD_A. Designs must critical attention bypassing VDD_A supply. required power-on sequence provide (and VDD_A) before VDD_IO.
Filtering Reference Voltage Clocks
Figure shows possible circuit filtering VREF, SCLK_N, LCLK_N. This circuit provides reference voltage switching voltage, system clock, local clock references.
VDD_IO VREF SCLK_N LCLK_N
SERIES RESISTOR 1.67k SERIES RESISTOR CAPACITOR (SMD) CAPACITOR SMD) PLACED CLOSE DSP'S PINS
Pins CONTROLIMP2-0 DS2-0 work together control output drive strength groups pins, Address/Data/Control group Link group. CONTROLIMP2-0 independently configures groups maximum drive strength digitally controlled drive strength that selectable DS2-0 pins (see Table Page 17). digitally controlled drive strength selected group DS2-0 pins determine eight strength levels that group (see Table Page 17). drive strength selected varies slew rate driver. Drive strength (DS2-0 000) weakest slowest slew rate. Drive strength (DS2-0 111) strongest fastest slew rate.
Figure VREF, SCLK_N, LCLK_N Filter Development Tools
ADSP-TS101S supported with complete CROSSCOREsoftware hardware development tools, including Analog Devices emulators VisualDSP++development environment. same emulator hardware that supports other TigerSHARC processors also fully emulates ADSP-TS101S. VisualDSP++ project management environment lets programmers develop debug application. This environment includes easy assembler (which based algebraic syntax), archiver (librarian/library builder), linker, loader, cycle-accurate instruction-level simulator, C/C++ compiler, C/C++ runtime library that includes mathematical functions. point these tools C/C++ code
CROSSCORE trademark Analog Devices, Inc. VisualDSP++ trademark Analog Devices, Inc.
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efficiency. compiler been developed efficient translation C/C++ code assembly. architectural features that improve efficiency compiled C/C++ code. VisualDSP++ debugger number important features. Data visualization enhanced plotting package that offers significant level flexibility. This graphical representation user data enables programmer quickly determine performance algorithm. algorithms grow complexity, this capability have increasing significance designer's development schedule, increasing productivity. Statistical profiling enables programmer nonintrusively poll processor running program. This feature, unique VisualDSP++, enables software developer passively gather important code execution metrics without interrupting realtime characteristics program. Essentially, developer identify bottlenecks software quickly efficiently. using profiler, programmer focus those areas program that impact performance take corrective action. Debugging both C/C++ assembly programs with VisualDSP++ debugger, programmers can: View mixed C/C++ assembly code (interleaved source object information) Insert breakpoints conditional breakpoints registers, memory, stacks Trace instruction execution Perform linear statistical profiling program execution Fill, dump, graphically plot contents memory Perform source level debugging Create custom debugger windows VisualDSP++ IDDE lets programmers define manage software development. dialog boxes property pages programmers configure manage TigerSHARC development tools, including color syntax highlighting VisualDSP++ editor. This capability permits programmers Control development tools process inputs generate outputs Maintain one-to-one correspondence with tool's command line switches VisualDSP++ Kernel (VDK) incorporates scheduling resource management tailored specifically address memory timing constraints programming. These capabilities enable engineers develop code more effectively, eliminating need start from very beginning, when developing application code. features include Threads, Critical Unscheduled regions, Semaphores, Events, Device flags. also supports Priority-based, Preemptive, Cooperative, Time-Sliced scheduling approaches. addition, designed scalable. application does specific feature, support code that feature excluded from target system. Because library, developer decide whether not. integrated into VisualDSP++ development environment, also used standard command line tools. When used, development environment assists developer with many error-prone tasks assists managing system resources, automating generation various based objects, visualizing system state, when debugging application that uses VDK. VCSE Analog Devices technology creating, using, reusing software components (independent modules substantial functionality) quickly reliably assemble software applications. Download components from drop them into application. Publish component archives from within VisualDSP++. VCSE supports component implementation C/C++ assembly language. Expert Linker visually manipulate placement code data embedded system. View memory utilization color-coded graphical form, easily move code data different areas external memory with drag mouse, examine time stack heap usage. Expert Linker fully compatible with existing Linker Definition File (LDF), allowing developer move between graphical textual environments. Analog Devices emulators IEEE 1149.1 JTAG Test Access Port ADSP-TS101S processor monitor control target board processor during emulation. emulator provides full speed emulation, allowing inspection modification memory, registers, processor stacks. Nonintrusive in-circuit emulation assured processor's JTAG interface-the emulator does affect target system loading timing. addition software hardware development tools available from Analog Devices, third parties provide wide range tools supporting TigerSHARC processor family. Hardware tools include TigerSHARC processor plug-in cards. Third party software tools include libraries, real-time operating systems, block diagram design tools.
Designing Emulator-Compatible Board (Target)
Analog Devices family emulators tools that every developer needs test debug hardware software systems. Analog Devices supplied IEEE 1149.1 JTAG Test Access Port (TAP) each JTAG DSP. emulator uses access internal features DSP, allowing developer load code, breakpoints, observe variables, observe memory, examine registers. must halted send data commands, once operation been completed emulator, system running full speed with impact system timing. these emulators, target board must include header that connects DSP's JTAG port emulator. details target board design issues including mechanical layout, single processor connections, multiprocessor scan chains, signal buffering, signal termination, emulator logic, EE-68: Analog Devices JTAG Emulation Technical Reference
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Analog Devices website (www.analog.com)-use site search "EE-68." This document updated regularly keep pace with improvements emulator support.
Additional Information
synchronization circuit prevents metastability problems. synchronous specification asynchronous signals used only when predictable cycle-by-cycle behavior required. inputs sampled clock reference, therefore input specifications (asynchronous minimum pulsewidths synchronous input setup hold) must guarantee recognition.
States Reset
This data sheet provides general overview ADSP-TS101S processor's architecture functionality. detailed information ADSP-TS101S processor's core architecture instruction set, ADSP-TS101 TigerSHARC Processor Programming Reference ADSP-TS101 TigerSHARC Processor Hardware Reference. detailed information development tools this processor, VisualDSP++ User's Guide TigerSHARC Processors.
FUNCTION DESCRIPTIONS
output pins three-stated during normal operation. three-states outputs during reset, allowing these pins their internal pull-up pull-down state. Some output pins (control signals) have pull-up pull-down that maintains known value during transitions between different drivers.
Definitions
While most ADSP-TS101S processor's input pins normally synchronous-tied specific clock-a asynchronous. these asynchronous signals, on-chip
Type column following definitions tables describes type, when used system. Term (for termination) column describes termination type used system. Note that some pins always used (indicated with symbol).
Table Definitions-Clocks Reset Signal Type Term Description
LCLK_N LCLK_P
LCLKRAT2-01
(pd2)
SCLK_N SCLK_P
SCLKFREQ3 RESET
(pu2)
Local Clock Reference. Connect this VREF shown Figure Local Clock Input. clock input. instruction cycle rate LCLK, where user-programmable 2.5, 3.5, Clock Domains Page LCLK Ratio. DSP's core clock (instruction cycle rate) LCLK, where user-programmable 2.5, 3.5, shown Table These pins must have constant value while powered. System Clock Reference. Connect this VREF shown Figure System Clock Input. DSP's system input clock cluster bus. This must connected same clock source LCLK_P. Clock Domains Page SCLK Frequency. SCLKFREQ required. SCLKFREQ must have constant value while powered. Reset. Sets known state causes program idle state. RESET must asserted specified time according type reset operation. details, Reset Booting Page
Type column symbols: Asynchronous; Ground; Input; Output; Open drain output; Power supply; Internal pull-down approximately Internal pull-up approximately Three-state Term (for termination) column symbols: External pull-down approximately VSS; External pull-up approximately VDD-IO connected; Always used.
internal pull-down sufficient. stronger pull-down necessary. ELECTRICAL CHARACTERISTICS Page maximum minimum current consumption pull-up pull-down resistances. internal pull-up sufficient. stronger pull-up necessary.
Table LCLK Ratio LCLKRAT2-0 Ratio
Table LCLK Ratio (continued) LCLKRAT2-0 Ratio
(default)
Reserved
REV.
-11-
ADSP-TS101S
Table Definitions-External Port Controls Signal Type
Term
Description
ADDR31-0
I/O/T
DATA63-01
I/O/T I/O/T (pu3)
WRL2
I/O/T (pu3)
WRH2
I/O/T (pu3)
I/O/T
BMS2,
(pu/pd3)
Address Bus. issues addresses accessing memory peripherals these pins. multiprocessor system, master drives addresses accessing internal memory processor registers other ADSP-TS101S processors. inputs addresses when host another accesses internal memory processor registers. External Data Bus. Data instructions received, driven DSP, these pins. Memory Read. asserted whenever reads from slave system, excluding SDRAM. When slave, input indicates read transactions that access internal memory universal registers. multiprocessor system, master drives changes concurrently with ADDR pins. Write Low. asserted cases: When ADSP-TS101S writes even address word external memory another external agent; when ADSP-TS101S writes 32-bit zone (host, memory, programmed 32-bit bus). external master (host DSP) asserts writing DSP's word internal memory. multiprocessor system, master drives WRL. changes concurrently with ADDR pins. When slave, input indicates write transactions that access internal memory universal registers. Write High. asserted when ADSP-TS101S writes long word bits) writes address word external memory another external agent 64-bit data bus. external master (host another DSP) must assert writing DSP's high word 64-bit data bus. multiprocessing system, master drives WRH. changes concurrently with ADDR pins. When slave, input indicates write transactions that access internal memory universal registers. Acknowledge. External slave devices deassert wait states external memory accesses. used devices, memory controllers, other peripherals data phase. deassert wait states read accesses internal memory. ADSP-TS101S does drive during slave writes. Therefore, external (approximately pull-up required. Boot Memory Select. chip select boot EPROM flash memory. During reset, uses strap (EBOOT) EPROM boot mode. When configured boot from EPROM, active during boot sequence. Pull-down enabled during RESET (asserted); pull-up enabled after RESET (deasserted). multiprocessor system, master drives BMS. details Reset Booting Page EBOOT signal description Table Page
Type column symbols: Asynchronous; Ground; Input; Output; Open drain output; Power supply; Internal pull-down approximately Internal pull-up approximately Three-state Term (for termination) column symbols: External pull-down approximately VSS; External pull-up approximately VDD-IO connected; Always used.
-12-
REV.
ADSP-TS101S
Table Definitions-External Port Controls (continued) Signal Type
Term
Description
MS1-0
MSH2
(pu3)
BRST2
I/O/T (pu3)
Memory Select. asserted whenever accesses memory banks respectively. MS1-0 decoded memory address pins that change concurrently with ADDR pins. When ADDR31:26 0b000010, asserted. When ADDR31:26 0b000011, asserted. multiprocessor systems, master drives MS1-0. Memory Select Host. asserted whenever accesses host address space (ADDR31:28 0b0000). decoded memory address that changes concurrently with ADDR pins. multiprocessor system, master drives MSH. Burst. current master (DSP host) asserts this indicate that reading writing data associated with consecutive addresses. slave device ignore addresses after first increment internal address counter after each transfer. host-to-DSP burst accesses, increments address automatically while BRST asserted.
Type column symbols: Asynchronous; Ground; Input; Output; Open drain output; Power supply; Internal pull-down approximately Internal pull-up approximately Three-state Term (for termination) column symbols: External pull-down approximately VSS; External pull-up approximately VDD-IO connected; Always used.
address data buses float several cycles during mastership transitions between TigerSHARC processor host. Floating this case means that these inputs driven source that dc-biased terminations present. necessary pull-ups there reliability issues worst-case power consumption these floating inputs negligible. Unconnected address pins require pull-ups pulldowns avoid erroneous slave accesses, depending system. Unconnected data pins left floating. internal pull-up sufficient. stronger pull-up necessary. ELECTRICAL CHARACTERISTICS Page maximum minimum current consumption pull-up pull-down resistances. internal pull-down sufficient. stronger pull-down necessary.
Table Definitions-External Port Arbitration Signal Type Term Description
BR7-0
ID2-01
(pd2)
BOFF
(pd2)
BUSLOCK3
(pu2)
Multiprocessing Request Pins. Used DSPs multiprocessor system arbitrate mastership. Each drives line (corresponding value ID2-0 inputs) monitors others. systems with fewer than eight DSPs, unused pins high. Multiprocessor Indicates DSP's From determines order multiprocessor system. These pins also indicate which request (BR0-BR7) assert when requesting bus: BR0, BR1, BR2, BR3, BR4, BR5, BR6, BR7. ID2-0 must have constant value during system operation change during reset only. Master. current master asserts debugging only. reset this strap pin. more information, Table Page Back Off. deadlock situation occur when host read from each other's same time. When deadlock occurs, host assert BOFF force relinquish before completing outstanding transaction, only outstanding transaction host memory space (MSH). Lock Indication. Provides indication that current master locked bus. Host Request. host must assert request control DSP's external bus. When asserted multiprocessing system, master relinquishes asserts once outstanding transaction finished.
Type column symbols: Asynchronous; Ground; Input; Output; Open drain output; Power supply; Internal pull-down approximately Internal pull-up approximately Three-state Term (for termination) column symbols: External pull-down approximately VSS; External pull-up approximately VDD-IO connected; Always used.
REV.
-13-
ADSP-TS101S
Table Definitions-External Port Arbitration (continued) Signal Type Term Description
I/O/T (pu2)
(o/d)
next col.
(o/d)
next col.
Host Grant. Acknowledges indicates that host take control external bus. When relinquishing bus, master three-states ADDR31-0, DATA63-0, MSH, MSSD, MS1-0, WRL, WRH, BMS, BRST, FLYBY, IOEN, RAS, CAS, SDWE, SDA10, SDCKE, LDQM HDQM pins, puts SDRAM self-refresh mode. asserts until host deasserts HBR. multiprocessor systems, current master drives HBG, slave DSPs monitor HBG. Core Priority Access. Asserted while DSP's core accesses external memory. This enables slave interrupt master DSP's background transfers gain control external core-initiated transactions. open drain output, connected DSPs system. internal pull-up resistor, which only enabled with ID2-0 used, terminate this either ID7-1 used, terminate this epu. Priority Access. Asserted while high priority channel accesses external memory. This enables high priority channel slave interrupt transfers normal priority channel master gain control external DMA-initiated transactions. open drain output, connected DSPs system. internal pull-up resistor, which only enabled with ID2-0 used, terminate this either ID7-1 used, terminate this epu.
Type column symbols: Asynchronous; Ground; Input; Output; Open drain output; Power supply; Internal pull-down approximately Internal pull-up approximately Three-state Term (for termination) column symbols: External pull-down approximately VSS; External pull-up approximately VDD-IO connected; Always used.
internal pull-down sufficient. stronger pull-down necessary. ELECTRICAL CHARACTERISTICS Page maximum minimum current consumption pull-up pull-down resistances. internal pull-up sufficient. stronger pull-up necessary.
Table Definitions-External Port DMA/Flyby Signal Type Term Description
DMAR3-0
FLYBY1
(pu2)
IOEN1
(pu2)
Request Pins. Enable external devices request services from DSP. response DMARx, performs transfers according channel's initialization. ignores requests from uninitialized channels. Flyby Mode. When channel initiated FLYBY mode, generates flyby transactions external bus. During flyby transactions, asserts FLYBY, which signals source destination device latch next data strobe current data, respectively, prepare next data next cycle. Device Output Enable. Enables output buffers external device flyby transactions between device external memory. Active flyby transactions.
Type column symbols: Asynchronous; Ground; Input; Output; Open drain output; Power supply; Internal pull-down approximately Internal pull-up approximately Three-state Term (for termination) column symbols: External pull-down approximately VSS; External pull-up approximately VDD-IO connected; Always used.
internal pull-up sufficient. stronger pull-up necessary. ELECTRICAL CHARACTERISTICS Page maximum minimum current consumption pull-up pull-down resistances.
-14-
REV.
ADSP-TS101S
Table Definitions-External Port SDRAM Controller Signal Type
Term
Description
MSSD
I/O/T (pu2)
RAS1
I/O/T (pu2) I/O/T (pu2)
CAS1
LDQM1
(pu2)
HDQM1
(pu2)
SDA101 SDCKE1,
(pu2) I/O/T (pu/pd2)
SDWE1
I/O/T (pu2)
Memory Select SDRAM. MSSD asserted whenever accesses SDRAM memory space. MSSD decoded memory address that asserted whenever issues SDRAM command cycle (access ADDR31:26 0b000001). MSSD multiprocessor system driven master DSP. Address Select. When sampled low, indicates that address valid read write SDRAM. other SDRAM accesses, defines type operation execute according SDRAM specification. Column Address Select. When sampled low, indicates that column address valid read write SDRAM. other SDRAM accesses, defines type operation execute according SDRAM specification. Word SDRAM Data Mask. When LDQM sampled high, threestates SDRAM buffers. LDQM valid SDRAM transactions when asserted inactive read transactions. write transactions, LDQM active when accessing address word 64-bit memory disable write word. High Word SDRAM Data Mask. When HDQM sampled high, threestates SDRAM buffers. HDQM valid SDRAM transactions when asserted inactive read transactions. write transactions, HDQM active when accessing even address word accesses active when memory configured 32-bit disable write high word. SDRAM Address pin. Separate signals enable SDRAM refresh operation while executes non-SDRAM transactions. SDRAM Clock Enable. Activates SDRAM clock SDRAM self-refresh suspend modes. slave multiprocessor system does have pull-up pull-down. master ID=0 single processor system) pull-up before granting host, except when SDRAM self-refresh mode. self-refresh mode, master pull-down before granting host. SDRAM Write Enable. When sampled while active, SDWE indicates SDRAM write access. When sampled high while active, SDWE indicates SDRAM read access. other SDRAM accesses, SDWE defines type operation execute according SDRAM specification.
Type column symbols: Asynchronous; Ground; Input; Output; Open drain output; Power supply; Internal pull-down approximately Internal pull-up approximately Three-state Term (for termination) column symbols: External pull-down approximately VSS; External pull-up approximately VDD-IO connected; Always used.
internal pull-up sufficient. stronger pull-up necessary. ELECTRICAL CHARACTERISTICS Page maximum minimum current consumption pull-up pull-down resistances. internal pull-down sufficient. stronger pull-down necessary.
Table Definitions-JTAG Port Signal Type Term Description
TDI2
(o/d) (pu3)
Emulation. Connected only DSP's JTAG emulator target board connector. Test Clock (JTAG). Provides asynchronous clock JTAG scan. epu1 Test Data Input (JTAG). serial data input scan path.
Type column symbols: Asynchronous; Ground; Input; Output; Open drain output; Power supply; Internal pull-down approximately Internal pull-up approximately Three-state Term (for termination) column symbols: External pull-down approximately VSS; External pull-up approximately VDD-IO connected; Always used.
REV.
-15-
ADSP-TS101S
Table Definitions-JTAG Port (continued) Signal Type Term Description
TMS2 TRST2
(pu3) (pu3)
Test Data Output (JTAG). serial data output scan path. Test Mode Select (JTAG). Used control test state machine. Test Reset (JTAG). Resets test state machine. TRST must asserted pulsed after power-up proper device operation. more information, Reset Booting Page
Type column symbols: Asynchronous; Ground; Input; Output; Open drain output; Power supply; Internal pull-down approximately Internal pull-up approximately Three-state Term (for termination) column symbols: External pull-down approximately VSS; External pull-up approximately VDD-IO connected; Always used.
reference Page JTAG emulation technical reference EE-68. internal pull-up sufficient. stronger pull-up necessary. ELECTRICAL CHARACTERISTICS Page maximum minimum current consumption pull-up pull-down resistances.
Table Definitions-Flags, Interrupts, Timer Signal Type
Term
Description
FLAG3-0
I/O/A (pd2) (pu2)
IRQ3-03
TMR0E1
(pd2)
FLAG pins. Bidirectional input/output pins used program conditions. Each configured individually input output. FLAG3-0 inputs after power-up reset. Interrupt Request. When asserted, generates interrupt. Each IRQ3-0 pins independently edge triggered level sensitive operation. After reset, these pins disabled unless IRQ3-0 strap option initialized booting. Timer expires. This output pulses four SCLK cycles whenever timer expires. reset this strap pin. additional information, Table Page
Type column symbols: Asynchronous; Ground; Input; Output; Open drain output; Power supply; Internal pull-down approximately Internal pull-up approximately Three-state Term (for termination) column symbols: External pull-down approximately VSS; External pull-up approximately VDD-IO connected; Always used.
internal pull-down sufficient. stronger pull-down necessary. ELECTRICAL CHARACTERISTICS Page maximum minimum current consumption pull-up pull-down resistances. internal pull-up sufficient. stronger pull-up necessary.
Table Definitions-Link Ports Signal Type
Term
Description
L0DAT7-0 L1DAT7-01 L2DAT7-01 L3DAT7-01 L0CLKOUT L1CLKOUT L2CLKOUT L3CLKOUT L0CLKIN L1CLKIN L2CLKIN L3CLKIN L0DIR
Link0 Data Link1 Data Link2 Data Link3 Data Link0 Clock/Acknowledge Output Link1 Clock/Acknowledge Output Link2 Clock/Acknowledge Output Link3 Clock/Acknowledge Output Link0 Clock/Acknowledge Input Link1 Clock/Acknowledge Input Link2 Clock/Acknowledge Input Link3 Clock/Acknowledge Input Link0 Direction. input, output)
Type column symbols: Asynchronous; Ground; Input; Output; Open drain output; Power supply; Internal pull-down approximately Internal pull-up approximately Three-state Term (for termination) column symbols: External pull-down approximately VSS; External pull-up approximately VDD-IO connected; Always used.
-16-
REV.
ADSP-TS101S
Table Definitions-Link Ports (continued) Signal Type Term Description
L1DIR L2DIR2 L3DIR
(pd3) (pd3)
Link1 Direction. input, output) Link2 Direction. input, output) reset this strap pin. more information, Table Page Link3 Direction. input, output)
Type column symbols: Asynchronous; Ground; Input; Output; Open drain output; Power supply; Internal pull-down approximately Internal pull-up approximately Three-state Term (for termination) column symbols: External pull-down approximately VSS; External pull-up approximately VDD-IO connected; Always used.
link port data pins, connected floated extended periods (for example, token slave with token master), require pull-ups pull-downs there reliability issues worst-case power consumption these floating inputs negligible. Floating this case means that these inputs driven source that dc-biased terminations present. internal pull-down sufficient. stronger pull-down necessary. ELECTRICAL CHARACTERISTICS Page maximum minimum current consumption pull-up pull-down resistances.
Table Definitions-Impedance Drive Strength Control Signal Type
Term
Description
CONTROLIMP2-1 CONTROLIMP02
(pd3)
DS2-01
(pu3)
Impedance Control. (Address/Data/Controls) LINK (all link port outputs) signals, CONTROLIMP2-0 pins control impedance shown Table These pins enable disable dig_ctrl mode. When dig_ctrl: Disabled (maximum drive strength) Enabled (use DS2-0 drive strength selection) Digital Drive Strength Selection. Selected shown Table drive strength calculation, Output Drive Currents Page drive strength some pins preset, controlled DS2-0 pins. pins that always drive strength (100%) are: CPA, DPA, EMU.
Type column symbols: Asynchronous; Ground; Input; Output; Open drain output; Power supply; Internal pull-down approximately Internal pull-up approximately Three-state Term (for termination) column symbols: External pull-down approximately VSS; External pull-up approximately VDD-IO connected; Always used.
internal pull-up sufficient. stronger pull-up necessary. internal pull-down sufficient. stronger pull-down necessary. ELECTRICAL CHARACTERISTICS Page maximum minimum current consumption pull-up pull-down resistances.
Table Control Impedance Selection CONTROLIMP2-0 dig_ctrl LINK dig_ctrl
Table Drive Strength Selection DS2-0 Drive Strength
(default)
reserved reserved reserved
reserved reserved reserved
(default)
Strength Strength Strength Strength Strength Strength Strength Strength
REV.
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ADSP-TS101S
Table Definitions-Power, Ground, Reference Signal Type Term Description
VDD_A VDD_IO VREF
pins internal logic. pins analog circuits. critical attention bypassing this supply. pins buffers. Reference voltage defines trip point input buffers, except RESET, IRQ3-0, DMAR3-0, ID2-0, CONTROLIMP2-0, TCK, TDI, TMS, TRST. value (which trip point). VREF connected power supply voltage divider circuit. voltage divider should have decoupling capacitor SMD) connected VSS. decoupling capacitor between VREF input VSS, close DSP's pins possible. Filtering Reference Voltage Clocks Page Ground pins. Ground pins analog circuits. connect. connect these pins anything (not supply, signal, each other), because they reserved must left unconnected.
VSS_A
Type column symbols: Asynchronous; Ground; Input; Output; Open drain output; Power supply; Internal pull-down approximately Internal pull-up approximately Three-state Term (for termination) column symbols: External pull-down approximately VSS; External pull-up approximately VDD-IO connected; Always used.
STRAP FUNCTION DESCRIPTIONS
Some pins have alternate functions reset. Strap options operating modes. During reset, samples strap option pins. Strap pins have approximately pull-down default value. strap connected external pull-up logic load, samples default value during reset. strap pins connected logic inputs, stronger external pull-down required ensure default value
Table Definitions-I/O Strap Pins Signal Pin. Description
depending leakage and/or level input current logic load. mode other than default mode, connect strap sufficiently stronger external pull-up. multiprocessor system, eight DSPs connected cluster bus, resulting parallel combination strap pulldown resistors. Table lists describes each DSP's strap pins.
EBOOT
IRQEN
L2DIR
TMR0E
EPROM boot. boot from EPROM immediately after reset (default) idle after reset wait external device boot through external port link port Interrupt Enable. disable IRQ3-0 interrupts level sensitive after reset (default) enable IRQ3-0 interrupts edge sensitive immediately after reset Test Mode required setting during reset. reserved. Test Mode required setting during reset. reserved.
-18-
REV.
ADSP-TS101S
SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
Parameter Test Conditions Unit
VDD_A VDD_IO TCASE IDDIDLELP IDD_IO VREF
Internal Supply Voltage Analog Supply Voltage Supply Voltage Case Operating Temperature High Level Input Voltage1 Level Input Voltage1 Supply Current Typical Activity2 Supply Current Typical Activity2 Supply Current IDLELP Instruction Execution VDD_IO Supply Current Typical Activity2 Voltage Reference
VDD, VDD_IO VDD, VDD_IO CCLK MHz, 1.25 TCASE CCLK MHz, 1.25 TCASE CCLK MHz, 1.20 TCASE SCLK MHz, VDD_IO TCASE
1.14 1.14 3.15 -0.5
1.26 1.26 3.45 VDD_IO +0.8
Specifications subject change without notice. Applies input bidirectional pins. details internal external power estimation, including: power vector definitions, current usage descriptions, formulas, EE-169, Estimating Power ADSP-TS101S Analog Devices website-use site search "EE-169" (www.analog.com). This document updated regularly keep pace with silicon revisions.
ELECTRICAL CHARACTERISTICS
Parameter Test Conditions
Unit
IIHP IILP IOZH IOZHP IOZL IOZLP IOZLO
High Level Output Voltage Level Output Voltage1 High Level Input Current2 High Level Input Current (pd)2 Level Input Current3 Level Input Current (pu)4 Three-State Leakage Current High5, Three-State Leakage Current High (pd)7 Three-State Leakage Current Low8 Three-State Leakage Current (pu)9 Three-State Leakage Current (od)7 Input Capacitance10,
@VDD_IO min, @VDD_IO min, @VDD_IO max, VDD_IO @VDD_IO max, VDD_IO @VDD_IO max, @VDD_IO max, @VDD_IO max, VDD_IO @VDD_IO max, VDD_IO @VDD_IO max, @VDD_IO max, @VDD_IO max, @fIN MHz, TCASE
44.5 44.5 -4.6
17.2 17.2 -9.8
Specifications subject change without notice.
Applies output bidirectional pins. Applies input pins with internal pull-downs (pd). Applies input pins without internal pull-ups (pu). Applies input pins with internal pull-ups (pu). Applies three-stateable pins without internal pull-downs (pd). Applies open drain (od) pins with pull-ups (pu). Applies three-stateable pins with internal pull-downs (pd). Applies three-stateable pins without internal pull-ups (pu). Applies three-stateable pins with internal pull-ups (pu). Applies signals. Guaranteed tested.
REV.
-19-
ADSP-TS101S
ABSOLUTE MAXIMUM RATINGS
Internal (Core) Supply Voltage (VDD)1 -0.3 +1.40 Analog (PLL) Supply Voltage (VDD_A)1 -0.3 +1.40 External (I/O) Supply Voltage (VDD_IO)1 -0.3 +4.6 Input Voltage1 -0.5 VDD_IO +0.5 Output Voltage Swing1 -0.5 VDD_IO +0.5 Storage Temperature Range1
Stresses greater than those listed above cause permanent damage device. These stress ratings only; functional operation device these other conditions greater than those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
SENSITIVITY
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although ADSP-TS101S features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
-20-
REV.
ADSP-TS101S TIMING SPECIFICATIONS
With exception Link Port, IRQ3-0, DMAR3-0, TMR0E, FLAG3-0 (input), TRST pins, timing ADSPTS101S relative reference clock edge. Because input setup/hold, output valid/hold, output enable/disable times relative clock edge, timing data ADSP-TS101S calculated (formula-based) values. information timing, General Timing. information link port transfer timing, Link Ports Data Transfer Token Switch Timing Page
General Timing
asynchronous timing data IRQ3-0, DMAR3-0, TMR0E, FLAG3-0 (input), TRST pins appears Table general timing data appears Table Table Table specifications measured with load specified Figure Page with output drive strength strength order calculate output valid hold times different load conditions and/or output drive strengths, refer Figure Page through Figure Page (Rise Fall Time Load Capacitance) Figure Page (Output Valid Load Capacitance Drive Strength).
Timing measured signals when they cross level described Figure Page delays nanoseconds) measured between point that first signal reaches point that second signal reaches
Table Asynchronous Signal Specifications-All values this table nanoseconds Name Description Pulsewidth (min) Pulsewidth High (min)
IRQ3-01 DMAR3-01 TMR0E FLAG3-01, TRST
Interrupt request input request input Timer expired output Flag pins input JTAG test reset input
tCCLK tCCLK tCCLK
tCCLK tSCLK tCCLK
These input pins need synchronized clock reference. output specifications, Table Table
Table Reference Clocks Input Clock Clock Jitter1 Tolerance High (ns) (ns) (ps)
Signal
Type
Description
Speed Grade (MHz)
Clock Cycle (ns)
Clock Cycle (ns)
CCLK CCLK2, LCLK_P4, LCLK_P4, 5,6,7 SCLK_P5,7, TCK10
Core Clock Core Clock Input Local Clock Input Local Clock Input System Clock, SCLKFREQ Input Test Clock (JTAG)
Greater Greater (10÷3) Greater CCLK Greater CCLK
12.5 12.5 12.5 12.5
{40% Duty Cycle} {40% Duty Cycle} {40% Duty Cycle} 12.5 12.5
Actual input jitter should combined with specifications accurate timing analysis. CCLK internal clock instruction cycle time. period this clock equal Local Clock (LCLK_P) period divided Local Clock Ratio (LCLKRAT2-0). information available internal clock rates, ORDERING GUIDE Page period CCLK tCCLK. Core Clock Ratio (CR) 2.5, 3.5, LCLKRAT2-0 pins. more information, Table Page Clock Domains Page period LCLK tLCLK. LCLK_P SCLK_P must connected same source. more information, Table Page period SCLK tSCLK. period tTCK.
REV.
-21-
ADSP-TS101S
Power-Up Sequencing, Power-Up Reset, Normal Reset (Hot) Timing Requirements
power-up sequencing, power-up reset, normal reset (hot reset) timing requirements, refer respectively Table Figure Table Figure Table Figure
Table Power-Up Sequencing Timing Parameter Unit
Timing Requirement VDD_IO Stable Within Specification After tVDD VDD_A Stable Within Specification
VDD_A
tVDD
VDD_IO
Figure Power-Up Sequencing Timing Table Power-Up Reset Timing Parameter Unit
Timing Requirements tSTART_LO RESET Deasserted After VDD, VDD_A, VDD_IO, SCLK/LCLK, Static/Strap Pins Stable Within Specification RESET Deasserted First Pulse tPULSE1_HI tPULSE2_LO RESET Asserted Second Pulse tTRST_PWR1 TRST Asserted During Power-Up Reset
tSCLK tSCLK tSCLK
tSCLK
Applies after VDD, VDD_A, VDD_IO, SCLK/LCLK Static/Strap Pins stable within specification, before RESET deasserted.
RESET
TRST
D_IO K/LCLK, STAT IC/STR PINS
Figure Power-Up Reset Timing
-22-
REV.
ADSP-TS101S
Table Normal Reset (Hot Reset) Timing Parameter Unit
Timing Requirements tRST_IN RESET Asserted RESET Deasserted After Strap Pins Stable tSTRAP
tSCLK
tRST_IN
RESET
tSTRAP
STRAP PINS
Figure Normal Reset (Hot Reset) Timing
REV.
-23-
ADSP-TS101S
Table Signal Specifications (for SCLK <16.7 ns)-All values this table nanoseconds Output Disable (max)2 Output Enable (min)2 Output Valid (max)1
Output Hold (min)
Input Setup (min)
Input Hold (min)
Name
Description
ADDR31-0 DATA63-0 MSSD MS1-0 SDCKE SDWE LDQM HDQM SDA10 BOFF BUSLOCK BRST BR7-0 FLYBY IOEN BMS5 FLAG3-06 TMR0E5 RESET4, TMS4 TDI4 TRST4, EMU10 JTAG_SYS_IN11 JTAG_SYS_OUT12 ID2-09
External Address External Data Memory Select HOST Line Memory Select SDRAM Line Memory Select Static Blocks Memory Read Write Word Write High Word Acknowledge Data SDRAM Clock Enable Address Select Column Address Select SDRAM Write Enable Word SDRAM Data Mask High Word SDRAM Data Mask SDRAM ADDR10 Host Request Host Grant Back Request Lock Burst Multiprocessing Request pins FLYBY FLYBY Core Priority Access Priority Access Boot Memory Select FLAG pins Timer Expired Global Reset Test Mode Select (JTAG) Test Data Input (JTAG) Test Data Output (JTAG) Test Reset (JTAG) Master Debug only Emulation System input System output Chip must constant
11.0 16.0
SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK TCK_FE8 SCLK LCLK TCK_FE8
-24-
Reference Clock
REV.
ADSP-TS101S
Table Signal Specifications (for SCLK <16.7 ns)-All values this table nanoseconds (continued) Output Disable (max)2 Output Enable (min)2 Output Valid (max)1
Output Hold (min)
Input Setup (min)
Input Hold (min)
Name
Description
CONTROLIMP2-09 DS2-09 LCLKRAT2-09 SCLKFREQ9
Static pins must constant Static pins must constant Static pins must constant Static pins must constant
output valid (max) value this column applies standard capacitive load used testing. output valid varies with capacitive loading, Figure Page external port protocols employ IDLE cycles mastership transitions well slave address boundary crossings avoid potential contention. apparent driver overlap, output disables being larger than output enables, actual. pins open drains have internal pull-ups. These input pins have Schmitt triggers therefore need synchronized clock reference. These synchronous specifications only apply recognition current clock reference cycle. This strap option. During reset, internal resistor pulls low. input specifications, Table additional requirement details, Reset Booting Page TCK_FE indicates falling edge. These pins change only during reset; recommend connecting VDD_IO/VSS. Reference clock depends function. System inputs are: IRQ3-0, BMS, LCLKRAT2-0, SCLKFREQ, TMR0E, FLAG3-0, ID2-0, BRST, WRH, WRL, MSSD, SDCKE, SDWE, CAS, RAS, ADDR31-0, DATA63-0, DPA, CPA, HBG, BOFF, HBR, ACK, BR7-0, L0CLKIN, L0DAT7-0, L1CLKIN, L1DAT7-0, L2CLKIN, L2DAT7-0, L2DIR, L3CLKIN, L3DAT7-0, DS2-0, CONTROLIMP2-0, RESET, DMAR3-0. System outputs are: BMS, BUSLOCK, TMR0E, FLAG3-0, FLYBY, IOEN, MSH, BRST, WRH, WRL, MS1-0, HDQM, LDQM, MSSD, SDCKE, SDWE, CAS, RAS, ADDR31-0, DATA63-0, DPA, CPA, HBG, ACK, BR7-0, L0CLKOUT, L0DAT7-0, L0DIR, L1CLKOUT, L1DAT7-0, L1DIR, L2CLKOUT, L2DAT7-0, L2DIR, L3CLKOUT, L3DAT7-0, L3DIR, EMU.
Table Signal Specifications (for 16.7 <SCLK ns)-All values this table nanoseconds Output Disable (max)2
Output Enable (min)2
Output Valid (max)1
Output Hold (min)
Input Setup (min)
Input Hold (min)
Name
Description
ADDR31-0 DATA63-0 MSSD MS1-0 SDCKE
External Address External Data Memory Select HOST Line Memory Select SDRAM Line Memory Select Static Blocks Memory Read Write Word Write High Word Acknowledge Data SDRAM Clock Enable Address Select
SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK
REV.
-25-
Reference Clock
Reference Clock
ADSP-TS101S
Table Signal Specifications (for 16.7 <SCLK ns)-All values this table nanoseconds (continued) Output Disable (max)2 Output Enable (min)2 Output Valid (max)1
Output Hold (min)
Input Setup (min)
Input Hold (min)
Name
Description
SDWE LDQM HDQM SDA10 BOFF BUSLOCK BRST BR7-0 FLYBY IOEN BMS5 FLAG3-06 TMR0E5 RESET4, TMS4 TDI4 TRST4, EMU10 JTAG_SYS_IN11 JTAG_SYS_OUT12 ID2-09 CONTROLIMP2-09 DS2-09 LCLKRAT2-09 SCLKFREQ9
Column Address Select SDRAM Write Enable Word SDRAM Data Mask High Word SDRAM Data Mask SDRAM ADDR10 Host Request Host Grant Back Request Lock Burst Multiprocessing Request pins FLYBY FLYBY Core Priority Access Priority Access Boot Memory Select FLAG pins Timer Expired Global Reset Test Mode Select (JTAG) Test Data Input (JTAG) Test Data Output (JTAG) Test Reset (JTAG) Master Debug only Emulation System input System output Chip must constant Static pins must constant Static pins must constant Static pins must constant Static pins must constant
11.0 16.0
SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK TCK_FE8 SCLK LCLK TCK_FE8
output valid (max) value this column applies standard capacitive load used testing. output valid varies with capacitive loading, Figure Page external port protocols employ IDLE cycles mastership transitions well slave address boundary crossings avoid potential contention. apparent driver overlap, output disables being larger than output enables, actual. pins open drains have internal pull-ups. These input pins have Schmitt triggers therefore need synchronized clock reference. These synchronous specifications only apply recognition current clock reference cycle. This strap option. During reset, internal resistor pulls low. input specifications, Table
-26-
Reference Clock
REV.
ADSP-TS101S
additional requirement details, Reset Booting Page TCK_FE indicates falling edge. These pins change only during reset; recommend connecting VDD_IO/VSS. Reference clock depends function. System inputs are: IRQ3-0, BMS, LCLKRAT2-0, SCLKFREQ, TMR0E, FLAG3-0, ID2-0, BRST, WRH, WRL, MSSD, SDCKE, SDWE, CAS, RAS, ADDR31-0, DATA63-0, DPA, CPA, HBG, BOFF, HBR, ACK, BR7-0, L0CLKIN, L0DAT7-0, L1CLKIN, L1DAT7-0, L2CLKIN, L2DAT7-0, L2DIR, L3CLKIN, L3DAT7-0, DS2-0, CONTROLIMP2-0, RESET, DMAR3-0. System outputs are: BMS, BUSLOCK, TMR0E, FLAG3-0, FLYBY, IOEN, MSH, BRST, WRH, WRL, MS1-0, HDQM, LDQM, MSSD, SDCKE, SDWE, CAS, RAS, ADDR31-0, DATA63-0, DPA, CPA, HBG, ACK, BR7-0, L0CLKOUT, L0DAT7-0, L0DIR, L1CLKOUT, L1DAT7-0, L1DIR, L2CLKOUT, L2DAT7-0, L2DIR, L3CLKOUT, L3DAT7-0, L3DIR, EMU.
REFERENCE CLOCK 1.5V
INPUT SIGNAL 1.5V INPUT SETUP INPUT HOLD
OUTPUT SIGNAL OUTPUT VALID 1.5V OUTPUT HOLD
THREE-STATE OUTPUT DISABLE OUTPUT ENABLE
ASYNCHRONOUS INPUT OUTPUT SIGNAL 1.5V PULSEWIDTH
Figure General Parameters Timing
REV.
-27-
ADSP-TS101S
Link Ports Data Transfer Token Switch Timing
Table Table Table Table with Figure Figure Figure Figure provide timing specifications link ports data transfer token switch.
Table Link Ports-Transmit Parameter Unit
Timing Requirements tCONNS1 Connectivity Pulse Setup tCONNS2 Connectivity Pulse Setup Connectivity Pulse Input Width tCONNIW3 tACKS Acknowledge Setup Switching Characteristics tLXCLK_TX4 Transmit Link Clock Period
tCCLK tLXCLK_TX tLXCLK_TX tCCLK, whichever larger 0.33 tLXCLK_TX tLXCLK_TX 0.33 tLXCLK_TX tLXCLK_TX tLXCLK_TX tLXCLK_TX 0.25 tLXCLK_TX 0.25 tLXCLK_TX 0.17 tLXCLK_TX 0.17 tLXCLK_TX tCCLK
tLXCLKH_TX1 tLXCLKH_TX2 tLXCLKL_TX1 tLXCLKL_TX2 tDIRS tDIRH tDOS1 tDOH1 tDOS2 tDOH2 tLDOE tLDOD5
Transmit Link Clock Width High Transmit Link Clock Width High Transmit Link Clock Width Transmit Link Clock Width LxDIR Transmit Setup LxDIR Transmit Hold LxDAT7-0 Output Setup LxDAT7-0 Output Hold LxDAT7-0 Output Setup LxDAT7-0 Output Hold LxDAT7-0 Output Enable LxDAT7-0 Output Disable
0.66 tLXCLK_TX tLXCLK_TX 0.66 tLXCLK_TX tLXCLK_TX tLXCLK_TX tLXCLK_TX
formula this parameter applies when MHz, ADSP-TS101S does maximum LxCLK MHz. formula this parameter applies when LxCLKIN shows connectivity pulse with each three possible transitions "Acknowledge." After connectivity pulse minimum, LxCLKIN return high remain high "Acknowledge," return high subsequently (meeting tACKS) "Not Acknowledge," remain "Not Acknowledge." Link clock Ratio (LR) bits LCTLx register. This specification applies last data byte "Dummy" byte that follows verification byte enabled. more information, ADSPTS101 TigerSHARC Processor Hardware Reference.
tCONNS tDIRS tLxCLKH_Tx
LxCLKOUT
tLxCLK_Tx tDOH tLxCLKL_Tx tDOS
tACKS tDOH tDOS
tDIRH
tCONNIW
LxCLKIN
tLDOE
LxDAT7-0
tLDOD
LxDIR
Figure Link Ports-Transmit
-28-
REV.
ADSP-TS101S
Table Link Ports-Receive Parameter Unit
Timing Requirements Receive Link Clock Period tLXCLK_RX1
tLXCLKH_RX2 tLXCLKH_RX3 tLXCLKL_RX2 tLXCLKL_RX3 tDIS tDIH
Receive Link Clock Width High Receive Link Clock Width High Receive Link Clock Width Receive Link Clock Width LxDAT7-0 Input Setup LxDAT7-0 Input Hold
tCCLK, whichever larger 0.33 tLXCLK_RX tLXCLK_RX 0.33 tLXCLK_RX tLXCLK_RX tLXCLK_RX
tCCLK
0.66 tLXCLK_RX tLXCLK_RX 0.66 tLXCLK_RX tLXCLK_RX
Switching Characteristics tCONNV Connectivity Pulse Valid Connectivity Pulse Output Width tCONNOW
tLXCLK_RX
link clock ratio (LR) bits LCTLx register. formula this parameter applies when formula this parameter applies when
tLxCLK_Rx tCONNV
LxCLKIN
tLxCLKH_Rx tLxCLKL_Rx
tDIH tDIS
tDIH tDIS
tCONNOW
LxCLKOUT
LxDAT7-0
LxDIR
Figure Link Ports-Receive
REV.
-29-
ADSP-TS101S
Table Link Ports-Token Switch, Token Master Parameter Unit
Timing Requirements Token Request Input Width tREQI tTKRQ Token Request from Token Enable1 Switching Characteristics Token Switch Enable Output tTKENO tREQO Token Request Output Width2
tLXCLK_RX tLXCLK_TX tLXCLK_TX tLXCLK_TX
guaranteeing token switch during token enable. LxCLKOUT shows both possible responses token request: "Token Grant" (LxCLKOUT remains high), "Token Regret" (LxCLKOUT goes low).
tTKENO
LxCLKOUT
tREQO
tTKRQ
LxCLKIN
tREQI
Figure Link Ports-Token Switch, Token Master Table Link Ports-Token Switch, Token Requester Parameter Unit
Timing Requirements tTKENI1 Token Switch Enable Input Switching Characteristics Token Request Output Width2 tREQO
tLXCLK_RX tLXCLK_RX
Required whenever there break transmission. LxCLKOUT shows both possible responses token request: "Token Grant" (LxCLKOUT remains high), "Token Regret" (LxCLKOUT goes low).
tTKENI
LxCLKIN token regret
tREQO
tTKRQ tREQO
LxCLKOUT token regret
tTKENI
LxCLKIN token grant
tTKRQ
tREQO
LxCLKOUT token grant
Figure Link Ports-Token Switch, Token Requester
-30-
REV.
ADSP-TS101S
Output Drive Currents
OUTPUT CURRENT
Figure through Figure show typical characteristics output drivers ADSP-TS101S. curves these diagrams represent current drive capability output drivers function output voltage over range drive strengths. complete output driver characteristics, refer IBIS models, available Analog Devices website, www.analog.com.
STRENGTH -100 OUTPUT VOLTAGE VDD_IO 3.15V, +85°C VDD_IO 3.15V, +85°C VDD_IO 3.45V, -40°C VDD_IO 3.45V, -40°C VDD_IO 3.3V, +25°C
VDD_IO 3.3V, +25°C
STRENGTH
OUTPUT CURRENT
VDD_IO 3.45V, -40°C VDD_IO 3.3V, +25°C VDD_IO 3.45V, -40°C
VDD_IO 3.15V, +85°C
VDD_IO 3.3V, +25°C VDD_IO 3.15V, +85°C
Figure Typical Drive Currents Strength
STRENGTH
OUTPUT CURRENT
OUTPUT VOLTAGE
VDD_IO 3.3V, +25°C VDD_IO 3.15V, +85°C VDD_IO 3.15V, +85°C VDD_IO 3.45V, -40°C VDD_IO 3.45V, -40°C
Figure Typical Drive Currents Strength
VDD_IO 3.3V, +25°C
STRENGTH
OUTPUT CURRENT
DD_IO 3.15V, +85°C VDD_IO 3.15V, +85°C VDD_IO 3.3V, +25°C
VDD_IO 3.45V, -40°C
-100 -125
VDD_IO 3.45V, -40°C
OUTPUT VOLTAGE
VDD_IO 3.3V, +25°C
Figure Typical Drive Currents Strength
STRENGTH
OUTPUT VOLTAGE
OUTPUT CURRENT
VDD_IO 3.45V, -40°C VDD_IO 3.3V, +25°C VDD_IO 3.45V, -40°C
-100 -120 -140 -160
Figure Typical Drive Currents Strength
VDD_IO 3.15V, +85°C
VDD_IO 3.3V, +25°C VDD_IO 3.15V, +85°C
OUTPUT VOLTAGE
Figure Typical Drive Currents Strength
REV.
-31-
ADSP-TS101S
Test Conditions
STRENGTH -100 -120 -140 -160 -180 OUTPUT VOLTAGE VDD_IO 3.45V, -40°C VDD_IO 3.3V, +25°C
OUTPUT CURRENT
test conditions timing parameters appearing Table Page Table Page include output disable time, output enable time, capacitive loading. timing specifications apply voltage reference levels Figure
VDD_IO 3.15V, +85°C
VDD_IO 3.45V, -40°C
INPUT OUTPUT 1.5V 1.5V
VDD_IO 3.3V, +25°C VDD_IO 3.15V, +85°C
Figure Voltage Reference Levels Measurements (Except Output Enable/Disable)
REFERENCE SIGNAL
Figure Typical Drive Currents Strength
tDIS
STRENGTH -100 -120 -140 -160 -180 -200 -220
tMEASURED_DIS tENA
(MEASURED) (MEASURED)
tMEASURED_ENA
(MEASURED)
2.0V 1.0V
(MEASURED)
VDD_IO 3.45V, -40°C VDD_IO 3.3V, +25°C VDD_IO 3.45V, -40°C
OUTPUT CURRENT
tDECAY
OUTPUT STOPS DRIVING
tRAMP
OUTPUT STARTS DRIVING
VDD_IO 3.15V, +85°C
VDD_IO 3.3V, +25°C VDD_IO 3.15V, +85°C
HIGH IMPEDANCE STATE. TEST CONDITIONS CAUSE THIS VOLTAGE APPROXIMATELY 1.5V.
Figure Output Enable/Disable
Output Disable Time
OUTPUT VOLTAGE
Figure Typical Drive Currents Strength
Output pins considered disabled when they stop driving, into high impedance state, start decay from their output high voltage. time voltage decay dependent capacitive load, load current, This decay time approximated following equation:
DECAY
STRENGTH -100 -120 -140 -160 -180 -200 -220
VDD_IO 3.45V, -40°C VDD_IO 3.3V, +25°C VDD_IO 3.45V, -40°C
OUTPUT CURRENT
VDD_IO 3.15V, +85°C
output disable time tDIS difference between tMEASURED_DIS tDECAY shown Figure time tMEASURED_DIS interval from when reference signal switches when output voltage decays from measured output high output voltage. tDECAY value calculated with test loads with equal
Output Enable Time
VDD_IO 3.3V, +25°C VDD_IO 3.15V, +85°C
OUTPUT VOLTAGE
Output pins considered enabled when they have made transition from high impedance state when they start driving. time voltage ramp dependent capacitive load, drive current, This ramp time approximated following equation:
RAMP
Figure Typical Drive Currents Strength
-32-
REV.
ADSP-TS101S
output enable time tENA difference between tMEASURED_ENA tRAMP shown Figure time tMEASURED_ENA interval from when reference signal switches when output voltage ramps from measured three-stated output level. tRAMP value calculated with test load drive current with equal
Capacitive Loading
RISE FALL TIMES
STRENGTH (VDD_IO 3.3V)
Output valid hold based standard capacitive loads: pins (see Figure 24). delay hold specifications given should derated drive strength related factor loads other than nominal value Figure through Figure show output rise time varies with capacitance. Figure graphically shows output valid varies with load capacitance. (Note that this graph derating does apply output disable delays; Output Disable Time Page 32.) graphs Figure through Figure linear outside ranges shown.
RISE TIME 0.1349x 1.9955
FALL TIME 0.1163x 1.4058
LOAD CAPACITANCE
Figure Typical Output Rise Fall Time (10%-90%, VDD_IO Load Capacitance Strength
OUTPUT
1.5V 30pF
STRENGTH (VDD_IO 3.3V)
Figure Equivalent Device Loading Measurements (Includes Fixtures)
RISE FALL TIMES
STRENGTH (VDD_IO 3.3V)
RISE TIME 0.1304x 0.8427
FALL TIME 0.1144x 0.7025
RISE FALL TIMES
RISE TIME
0.2015x 3.8869
FALL TIME 0.174x 2.6931
LOAD CAPACITANCE
Figure Typical Output Rise Fall Time (10%-90%, VDD_IO Load Capacitance Strength
STRENGTH (VDD_IO 3.3V)
LOAD CAPACITANCE
Figure Typical Output Rise Fall Time (10%-90%, VDD_IO Load Capacitance Strength
RISE FALL TIMES
RISE TIME 0.1082x 1.3123
FALL TIME 0.0912x 1.2048
LOAD CAPACITANCE
Figure Typical Output Rise Fall Time (10%-90%, VDD_IO Load Capacitance Strength
REV.
-33-
ADSP-TS101S
STRENGTH (VDD_IO 3.3V)
RISE FALL TIMES
STRENGTH (VDD_IO 3.3V)
RISE FALL TIMES
RISE TIME 0.1071x 0.9877
RISE TIME 0.0907x 1.0071
FALL TIME 0.0798x 1.0743
FALL TIME 0.09x 0.3134
LOAD CAPACITANCE
LOAD CAPACITANCE
Figure Typical Output Rise Fall Time (10%-90%, VDD_IO Load Capacitance Strength
Figure Typical Output Rise Fall Time (10%-90%, VDD_IO Load Capacitance Strength
STRENGTH (VDD_IO 3.3V)
STRENGTH (VDD_IO 3.3V)
RISE FALL TIMES
OUTPUT VALID
RISE TIME 0.1001x 0.7763
FALL TIME 0.0793x 0.8691
LOAD CAPACITANCE
LOAD CAPACITANCE
Figure Typical Output Rise Fall Time (10%-90%, VDD_IO Load Capacitance Strength
Figure Typical Output Valid (VDD_IO Load Capacitance Case Temperature Strength 0-71
line equations output valid versus load capacitance are: Strength 0.0956x 3.5662 Strength 0.0523x 3.2144 Strength 0.0433x 3.1319 Strength 0.0391x 2.9675 Strength 0.0393x 2.7653 Strength 0.0373x 2.6515 Strength 0.0379x 2.1206 Strength 0.0399x 1.9080
STRENGTH (VDD_IO 3.3V)
RISE FALL TIMES
RISE TIME 0.0946x 1.2187
FALL TIME 0.0906x 0.4597
LOAD CAPACITANCE
Figure Typical Output Rise Fall Time (10%-90%, VDD_IO Load Capacitance Strength
-34-
REV.
ADSP-TS101S
Environmental Conditions
ADSP-TS101S rated performance over extended commercial temperature range, TCASE -40°C +85°C.
Thermal Characteristics
ADSP-TS101S packaged Plastic Ball Grid Array (PBGA). ADSPTS101S specified case temperature (TCASE). ensure that TCASE data sheet specification exceeded, heat sink and/or flow source used. Table Table thermal data.
Table Thermal Characteristics Package Parameter Condition Typical Unit
Airflow Airflow3 Airflow3
16.6 14.0 12.9
°C/W °C/W °C/W °C/W °C/W
Determination parameter system dependent based number factors, including device power dissipation, package thermal resistance, board thermal characteristics, ambient temperature, flow. JEDEC JESD51-2 procedure using four layer board (compliant with JEDEC JESD51-9). SEMI Test Method G38-87 using four layer board (compliant with JEDEC JESD51-9).
Table Thermal Characteristics Package Parameter Condition Typical Unit
Airflow2 Airflow3 Airflow3
13.8 11.7 10.8
°C/W °C/W °C/W °C/W °C/W
Determination parameter system dependent based number factors, including device power dissipation, package thermal resistance, board thermal characteristics, ambient temperature, flow. JEDEC JESD51-2 procedure using four layer board (compliant with JEDEC JESD51-9). SEMI Test Method G38-87 using four layer board (compliant with JEDEC JESD51-9).
REV.
-35-
ADSP-TS101S
484-BALL PBGA CONFIGURATIONS Table 484-Ball PBGA Assignments Mnemonic Mnemonic Mnemonic Mnemonic Mnemonic
DATA14 DATA11 DATA8 DATA4 DATA1 L0DIR L0CLKIN L0DAT6 L0DAT3 L0DAT1 LCLK_N VSS_A SCLK_N SCLK_P CONTROLIMP2 CONTROLIMP1 RESET DMAR1 DATA29 DATA30 DATA26 VDD_IO VDD_IO VDD_IO VDD_IO LCLKRAT0 SCLKFREQ TMR0E
DATA21 DATA18 DATA12 DATA13 DATA7 DATA5 DATA2 L0DAT7 L0DAT4 L0DAT0 VDD_A VSS_A CONTROLIMP0 DMAR2 DMAR0 IRQ1 L3DAT1 DATA28 DATA27 VDD_IO FLAG3 BUSLOCK FLAG0
DATA23 DATA17 DATA15 DATA9 DATA10 DATA6 DATA3 DATA0 L0CLKOUT L0DAT5 L0DAT2 LCLK_P VDD_A VREF TRST DMAR3 IRQ3 IRQ0 L3DAT2 L3DAT0 DATA31 VDD_IO VDD_IO FLAG1 FLAG2
DATA24 DATA19 DATA16 VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO IRQ2 LCLKRAT1 L3DAT5 L3DAT3 L3DAT4 VDD_IO VDD_IO VDD_IO
DATA25 DATA22 DATA20 VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO LCLKRAT2 L3CLKOUT L3DAT7 L3DAT6 VDD_IO VDD_IO VDD_IO IOEN FLYBY
-36-
REV.
ADSP-TS101S
Table 484-Ball PBGA Assignments (continued) Mnemonic Mnemonic Mnemonic Mnemonic Mnemonic
L3CLKIN L3DIR VDD_IO VDD_IO VDD_IO BRST L1DIR DATA36 DATA37 VDD_IO VDD_IO ADDR23 ADDR25 ADDR27
L1DAT0 L1DAT2 L1DAT1 VDD_IO VDD_IO HDQM DATA38 DATA39 VDD_IO VDD_IO ADDR30 ADDR22 ADDR26
L1DAT3 L1DAT5 L1DAT7 VDD_IO VDD_IO VDD_IO SDWE MSSD LDQM DATA34 DATA41 DATA35 VDD_IO VDD_IO VDD_IO VDD_IO ADDR14 ADDR19 ADDR24
L1DAT4 L1CLKOUT L1CLKIN VDD_IO VDD_IO VDD_IO ADDR31 SDCKE DATA40 DATA43 DATA46 VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO ADDR12 ADDR17 ADDR20
L1DAT6 DATA32 DATA33 VDD_IO VDD_IO ADDR28 ADDR29 DATA42 DATA45 L2DAT5 DATA48 DATA52 DATA58 DATA60 DATA63 L2DAT4 L2CLKOUT ADDR0 ADDR1 ADDR11 ADDR21 ADDR18 ADDR16
REV.
-37-
ADSP-TS101S
Table 484-Ball PBGA Assignments (continued) Mnemonic Mnemonic Mnemonic Mnemonic Mnemonic
AA10 AA11
DATA44 DATA50 DATA47 DATA49 DATA51 DATA54 DATA57 DATA61 L2DAT0 L2DAT3 L2DAT7
AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22
ADDR2 ADDR5 ADDR8 SDA10 ADDR10 ADDR13 ADDR15
AB10 AB11
DATA53 DATA55 DATA56 DATA59 DATA62 L2DAT1 L2DAT2 L2DAT6 L2CLKIN L2DIR
AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22
BOFF ADDR3 ADDR4 ADDR6 ADDR7 ADDR9
484-Ball PBGA Configurations (Top View, Summary)
VDD_A VSS_A KEY: VDD_IO SIGNAL
VIEW
-38-
REV.
ADSP-TS101S
625-BALL PBGA CONFIGURATIONS Table 625-Ball PBGA Assignments Mnemonic Mnemonic Mnemonic Mnemonic Mnemonic
DATA17 DATA14 DATA11 DATA9 DATA7 DATA4 DATA1 L0DIR L0DAT7 L0DAT4 L0DAT1 LCLK_N LCLK_P VDD_A SCLK_N VREF CONTROLIMP2 RESET DMAR2 TRST DATA26 DATA25 DATA24 VDD_IO VDD_IO VDD_IO BUSLOCK TMR0E
DATA16 DATA13 DATA12 DATA10 DATA5 DATA2 L0CLKOUT L0DAT5 L0DAT2 VSS_A SCLK_P CONTROLIMP1 DMAR3 DMAR0 IRQ3 IRQ1 DATA29 DATA28 DATA27 VDD_IO VDD_IO FLAG3 FLAG2 FLAG1
DATA20 DATA21 DATA18 DATA15 DATA8 DATA6 DATA3 DATA0 L0CLKIN L0DAT6 L0DAT3 L0DAT0 VSS_A VDD_A CONTROLIMP0 DMAR1 IRQ2 LCLKRAT0 LCLKRAT1 IRQ0 L3DAT0 DATA31 DATA30 VDD_IO VDD_IO VDD_IO FLAG0
DATA19 VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO L3DAT3 L3DAT2 L3DAT1 VDD_IO VDD_IO VDD_IO VDD_IO
DATA23 DATA22 VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO SCLKFREQ LCLKRAT2 L3DAT6 L3DAT5 L3DAT4 VDD_IO VDD_IO VDD_IO
REV.
-39-
ADSP-TS101S
Table 625-Ball PBGA Assignments (continued) Mnemonic Mnemonic Mnemonic Mnemonic Mnemonic
L3CLKIN L3CLKOUT L3DAT7 VDD_IO VDD_IO FLYBY L1DIR L1CLKIN VDD_IO VDD_IO VDD_IO SDCKE SDWE
L1DAT0 L3DIR VDD_IO VDD_IO VDD_IO IOEN BRST DATA34 DATA33 DATA32 VDD_IO VDD_IO VDD_IO VDD_IO
L1DAT2 L1DAT1 VDD_IO VDD_IO VDD_IO VDD_IO DATA37 DATA36 DATA35 VDD_IO VDD_IO VDD_IO ADDR31 ADDR30 ADDR29
L1DAT5 L1DAT4 L1DAT3 VDD_IO VDD_IO VDD_IO HDQM DATA40 DATA39 DATA38 VDD_IO VDD_IO ADDR28 ADDR27
L1CLKOUT L1DAT7 L1DAT6 VDD_IO VDD_IO LDQM MSSD DATA43 DATA42 DATA41 VDD_IO VDD_IO VDD_IO ADDR26 ADDR25 ADDR24
-40-
REV.
ADSP-TS101S
Table 625-Ball PBGA Assignments (continued) Mnemonic Mnemonic Mnemonic Mnemonic Mnemonic
AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25
DATA46 DATA45 DATA44 VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO ADDR23 ADDR22 ADDR21
AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25
DATA49 DATA48 DATA47 VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO ADDR20 ADDR19 ADDR18
AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25
DATA50 DATA51 DATA54 DATA57 DATA60 DATA63 L2DAT2 L2DAT5 L2CLKOUT ADDR0 ADDR3 ADDR6 ADDR9 ADDR11 ADDR14 ADDR17 ADDR16
AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25
DATA52 DATA55 DATA58 DATA61 L2DAT0 L2DAT3 L2DAT6 L2CLKIN ADDR1 ADDR4 ADDR7 SDA10 ADDR12 ADDR15
AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25
DATA53 DATA56 DATA59 DATA62 L2DAT1 L2DAT4 L2DAT7 L2DIR BOFF ADDR2 ADDR5 ADDR8 ADDR10 ADDR13
625-Ball PBGA Configurations (Top View, Summary)
VIEW VSS_A KEY: VDD_IO SIGNAL VDD_A
REV.
-41-
ADSP-TS101S
OUTLINE DIMENSIONS
ADSP-TS101S available 484-ball PBGA package with rows balls (B-484); also available 625-ball PBGA package with rows balls (B-625).
484-Ball PBGA (B-484)
19.10 19.00 18.90 1.10
19.10 19.00 18.90 BOTTOM VIEW DETAIL
17.05 16.95 16.85
19.10 19.00 18.90
16.80
0.80 BALL PITCH 1.10
17.05 16.95 16.85 VIEW
2.50
0.65 0.55 0.45 SEATING PLANE BALL DIAMETER 0.55 0.50 0.45 DETAIL
1.30
NOTES: DIMENSIONS MILLIMETERS. ACTUAL POSITION BALL GRID WITHIN 0.25mm IDEAL POSITION RELATIVE PACKAGE EDGES. ACTUAL POSITION EACH BALL WITHIN 0.10mm IDEAL POSITION RELATIVE BALL GRID. CENTER DIMENSIONS NOMINAL.
0.40 0.20
-42-
REV.
ADSP-TS101S
625-Ball PBGA (B-625)
27.20 27.00 26.80
27.20 27.00 26.80 BOTTOM VIEW DETAIL 1.25
1.50 24.00
24.20 24.00 23.80
27.20 27.00 26.80
1.00 BALL PITCH 24.20 24.00 23.80 VIEW 1.50
2.50
0.65 0.55 0.45 SEATING PLANE BALL DIAMETER 0.70 0.60 0.50
NOTES: DIMENSIONS MILLIMETERS. ACTUAL POSITION BALL GRID WITHIN 0.25mm IDEAL POSITION RELATIVE PACKAGE EDGES. ACTUAL POSITION EACH BALL WITHIN 0.10mm IDEAL POSITION RELATIVE BALL GRID. CENTER DIMENSIONS NOMINAL. THIS PACKAGE COMPLIES WITH JEDEC MS-034 SPECIFICATION, USES TIGHTER TOLERANCES THAN MAXIMUMS ALLOWED THAT SPECIFICATION.
0.40 0.20
DETAIL
ORDERING GUIDE Temperature Range (Case) Core Clock (CCLK) Rate5 On-chip SRAM Operating Voltage
Part Number1,
Package
ADSP-TS101SAB1-000 ADSP-TS101SAB2-000 ADSP-TS101SAB1-100 ADSP-TS101SAB2-100
-40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C
VDD_IO VDD_IO VDD_IO VDD_IO
(B-625)6 (B-484)7 (B-625)6 (B-484)7
indicates supplies. indicates -40°C +85°C temperature. B-625, Plastic Ball Grid Array (PBGA); B-484, Plastic Ball Grid Array (PBGA). indicates speed grade; indicates speed grade. instruction rate runs internal clock (CCLK) rate. B-625 package measures B-484 package measures
REV.
-43-
ADSP-TS101S Revision History
Location Page
-44-
REV.
PRINTED U.S.A.
C03164-0-2/03(A)
2/03-Data Sheet changed from REV. REV. Edits FEATURES section Edits GENERAL DESCRIPTION section Edits FUNCTION DESCRIPTIONS section Edits SPECIFICATIONS section Edits ORDERING GUIDE. Changes formatting Global
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